Programming circuit for resistive switching element, and semiconductor device.

Abstract

To reduce writing time while suppressing element destruction of a resistance change element upon performing writing operation which changes a resistance state of the resistance change element.SOLUTION: In a write current path 30, a resistance change element R0 and a write transistor M0 are connected in series between a write voltage Vw and a ground voltage VSS, and a write current Iw for performing write operation flows. In a replica current path 20, a drain terminal of a replica write transistor MR0 with substantially the same properties as those of the write transistor M0 is connected to a current source 12, a source terminal of the replica write transistor MR0 is connected to the ground voltage VSS, and a replica current Iwr set based on a current value of the write current Iw flows. In a differential amplifier 11, the write voltage Vw is connected to an inverted input terminal, a voltage of an output terminal of the current source 12 is connected to a non-inverted input terminal, and a control voltage Vb from the output terminal is supplied to each of gate terminals of the write transistor M0 and the replica write transistor MR0.SELECTED DRAWING: Figure 5

Description

Technical Field

[0001] The present invention relates to semiconductor devices such as memories and field programmable gate arrays (FPGAs) using resistance change elements, and more particularly to a writing circuit for a resistance change element for performing a writing operation for changing the resistance state of the resistance change element.

Background Art

[0002] In recent years, memories and field programmable gate arrays using nonvolatile resistance change elements that transition between a low resistance state and a high resistance state according to the direction of an applied voltage and can retain the set resistance state even when no power is supplied are known.

[0003] Patent Document 1, Patent Document 2, and Non-Patent Document 1 disclose programmable logic integrated circuits that enable changes in wiring connections after the manufacture of semiconductor integrated circuits using resistance change elements formed in wiring layers. According to such programmable logic integrated circuits, it is possible to correct circuit defects and change specifications after manufacture, reduce the area of semiconductor integrated circuits, improve the power performance ratio, and further omit the operation of reading circuit configuration information at startup.

[0004] Non-Patent Document 2 discloses a semiconductor memory circuit using a resistance change element formed in a wiring layer. A semiconductor memory circuit using a resistance change element is characterized by a short writing time.

[0005] Here, a verification writing method is known for writing data to memory circuits using resistive switching elements. This method involves repeating the writing operation and the reading operation to confirm that the data has been written correctly until the data is successfully written. When performing such verification writing, a technique is known that allows for stable writing even with respect to variations in element characteristics caused by semiconductor processes, as well as fluctuations in operating voltage and ambient temperature (see, for example, Non-Patent Document 3). [Prior art documents] [Patent Documents]

[0006] [Patent Document 1] Japanese Patent Publication No. 2005-101535 [Patent Document 2] Patent No. 6934258 [Non-patent literature]

[0007] [Non-Patent Document 1] S. Kaeriyama et al., "A Nonvolatile Programmable Solid-Electrolyte Nanometer Switch", IEEE Journal of Solid-State Circuits, Vol. 40(1), pp. 168-176, (2005). [Non-Patent Document 2] M. Tada, "NanoBridge Technology for Embedded Nonvolatile Memory Application", IEEE International Memory Workshop, pp. 101-104., (2022). [Non-Patent Document 3] YY Chen et al., "Tailoring switching and endurance / retention reliability characteristics of HfO2 / Hf RRAM with Ti, Al, Si dopants," 2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers, 2014, pp. 1-2. [Overview of the project] [Problems that the invention aims to solve]

[0008] However, with such resistive switching elements, excessively high writing voltage or current can cause element damage. Therefore, when performing verify writing, it is necessary to start the writing operation under conditions that provide a sufficient margin to prevent element damage caused by excessive writing voltage or current, in response to variations in element characteristics due to semiconductor processes and fluctuations in operating voltage and ambient temperature. This results in the challenge of increasing the number of iterations and thus the writing time.

[0009] The present invention was made to solve the above-mentioned problems, and the object of the present invention is to provide a resistive switching element writing circuit and a semiconductor device that can shorten the writing time while suppressing element damage to the resistive switching element when performing a writing operation that changes the resistance state of the resistive switching element. [Means for solving the problem]

[0010] The resistive switching element writing circuit of the present invention is a resistive switching element writing circuit for which the resistive state changes according to the direction of the voltage applied between two electrodes, and which changes the resistive state from a low-resistance state to a high-resistance state. The resistive element and the writing transistor are connected in series between a writing voltage for performing a writing operation on the resistive element and a ground voltage lower than the writing voltage, and a writing current path through which a writing current flows for performing a writing operation on the resistive element, A current source and The replica current path includes a replica writing transistor having substantially the same characteristics as the writing transistor, the drain terminal of the replica writing transistor being connected to the current source, the source terminal of the replica writing transistor being connected to the ground voltage, and a replica current set based on the current value of the writing current to be passed through the resistance change element. The device includes a differential amplifier to which the writing voltage is connected to an inverting input terminal, the voltage of the output terminal of the current source is connected to a non-inverting input terminal, and the control voltage output from the output terminal is supplied to the gate terminals of the writing transistor and the replica writing transistor, respectively.

[0011] Another resistive switching element writing circuit of the present invention is wherein the resistive switching element is The first electrode is the active electrode, The second electrode is an inert electrode, It is composed of a resistance-changing layer disposed between the first electrode and the second electrode, which contains a solid electrolyte that allows the metal elements constituting the first electrode to diffuse, When the potential of the first electrode becomes higher than that of the second electrode by the amount of the first threshold voltage, the metal elements constituting the first electrode diffuse into the resistance change layer, forming a metal bridge and resulting in a low-resistance state. The element may enter a high-resistance state when the potential of the second electrode becomes higher than that of the first electrode by a second threshold voltage, thereby breaking the metal bridge formed in the resistance-changing layer.

[0012] Furthermore, in the writing circuit for other resistive switching elements of the present invention, the replica current may be set to a current value larger than the writing current, and may also be set according to the resistance value of the resistive switching element in its low-resistance state.

[0013] Further, the write circuit of another resistive change element of the present invention may be configured such that the replica current includes a resistance value at which the amount of heat generated in the resistive change element becomes maximum within the variation range of the resistance value in the low-resistance state of the resistive change element.

[0014] Further, the write circuit of the resistive change element of the present invention may be configured such that the replica current is set to be smaller than the resistance value at which the amount of heat generated in the resistive change element becomes maximum than the variation range of the resistance value in the low-resistance state of the resistive change element.

[0015] Further, the write circuit of another resistive change element of the present invention is such that when the gate width and gate length of the replica write transistor are substantially the same as the gate width and gate length of the write transistor, respectively, the current value of the replica current is Iwr, and when the ratio of the gate width to the gate length of the write transistor is K times the ratio of the gate width to the gate length of the replica write transistor, the current value of the replica current may be set to Iwr / K.

[0016] Furthermore, the write circuit of another resistive change element of the present invention is a write circuit of a resistive change element for performing a write operation for changing the resistance state of the resistive change element from a low-resistance state to a high-resistance state in a storage device in which a plurality of memory cells each including a resistive change element whose resistance state changes according to the direction of a voltage applied between two electrodes and a cell transistor are arranged at intersections of bit line pairs and word lines, a column decoder including a source-side column decoder arranged to apply a predetermined voltage to a bit line pair selected by a column selection signal and connected to a write voltage for performing a write operation on the resistive change element, and a sink-side column decoder connected to a ground voltage lower than the write voltage, and a row decoder arranged to apply a predetermined voltage to a word line selected by a row selection signal. Between the write voltage and the ground voltage, a first transistor in the source-side column decoder, the cell transistor, the resistive change element, a write transistor and a second transistor in the sink-side column decoder are connected in series, and a write current path through which a write current for performing a write operation of the resistive change element flows is formed. Further, a current source, A first replica transistor having substantially the same characteristics as the first transistor, a replica cell transistor having substantially the same characteristics as the cell transistor, a replica write transistor having substantially the same characteristics as the write transistor, and a second replica transistor having substantially the same characteristics as the second transistor are connected in series between the current source and the ground voltage, and a replica current path through which a replica current set based on the current value of the write current to be passed through the resistive change element flows. The write voltage is connected to the inverting input terminal, the voltage of the output terminal of the current source is connected to the non-inverting input terminal, and a differential amplifier that supplies a control voltage output from the output terminal to the gate terminals of the write transistor and the replica write transistor, respectively. A column selection signal of the same voltage for setting the operating state to the on state is applied to the gate terminals of the first transistor and the first replica transistor, a row selection signal of the same voltage for setting the operating state to the on state is applied to the gate terminals of the cell transistor and the replica cell transistor, and a column selection signal of the same voltage for setting the operating state to the on state is applied to the gate terminals of the second transistor and the second replica transistor.

[0017] Also, the write circuit for another resistive change element of the present invention is a storage device in which a plurality of memory cells each including a resistive change element and a cell transistor whose resistance state changes according to the direction of the voltage applied between two electrodes are respectively arranged at intersections of bit line pairs and word lines, and is a write circuit for the resistive change element for performing a write operation for changing the resistance state of the resistive change element from a low resistance state to a high resistance state. A column decoder comprising a source-side column decoder connected to a write voltage for performing a write operation on the resistive change element, and a sink-side column decoder connected to a ground voltage lower than the write voltage, which is arranged to apply a predetermined voltage to the bit line pair selected by the column selection signal, The system comprises a row decoder that applies a predetermined voltage to the word line selected by the row selection signal, Between the writing voltage and the ground voltage, the first transistor in the source-side column decoder, the cell transistor, the resistive element, and the second transistor in the sink-side column decoder are connected in series, forming a writing current path through which a writing current flows for performing the writing operation of the resistive element. Furthermore, a current source and A first replica transistor having substantially the same characteristics as the first transistor, a replica cell transistor having substantially the same characteristics as the cell transistor, and a second replica transistor having substantially the same characteristics as the second transistor are connected in series between the current source and the ground voltage, and a replica current path through which a replica current set based on the current value of the writing current to be passed through the resistance change element flows, The differential amplifier comprises a differential amplifier to which the writing voltage is connected to an inverting input terminal, the voltage of the output terminal of the current source is connected to a non-inverting input terminal, and which supplies the control voltage output from the output terminal to the gate terminal of the replica cell transistor, and also supplies the control voltage to the gate terminal of the cell transistor via the low decoder, A column selection signal of the same voltage is applied to the gate terminal of the first transistor and the gate terminal of the first replica transistor to turn on the operating state, and a column selection signal of the same voltage is applied to the gate terminal of the second transistor and the gate terminal of the second replica transistor to turn on the operating state.

[0018] Furthermore, in other resistive switching element programming circuits of the present invention, the replica current path may be configured by a plurality of subpaths having a replica programming transistor and a selection transistor having substantially the same characteristics as the programming transistor, connected in parallel between the output terminal of the current source and the ground voltage.

[0019] Furthermore, the programming circuit for other resistance-changing elements of the present invention may be configured such that, based on selection signals input to the gate terminals of the plurality of selection transistors, only one of the plurality of selection transistors becomes conductive, and the conductive selection transistor is sequentially switched at preset time intervals.

[0020] In the semiconductor device of the present invention, the writing circuit for any one of the above resistive switching elements is configured as a semiconductor integrated circuit. [Effects of the Invention]

[0021] According to the present invention, when performing a writing operation that changes the resistance state of a resistive switching element, it is possible to shorten the writing time while suppressing element damage to the resistive switching element. [Brief explanation of the drawing]

[0022] [Figure 1] This is a diagram illustrating the structure of the resistive switching element 100. [Figure 2] This diagram illustrates the setting operation performed on the resistive switching element 100. [Figure 3] This diagram illustrates the reset operation performed on the resistive switching element 100. [Figure 4] This graph shows the change in voltage and current characteristics of the resistive switching element 100. [Figure 5] This is a circuit diagram showing the configuration of a programming circuit for a resistive switching element according to the first embodiment of the present invention. [Figure 6]This diagram illustrates the relationship between the drain-source voltage Vds and drain-source current Ids in the replica writing transistor MR0. [Figure 7] This diagram illustrates the relationship between the drain-source voltage Vds and the drain-source current Ids when the writing transistor M0 is operating in the saturation region. [Figure 8] This diagram illustrates the relationship between the drain-source voltage Vds and the drain-source current Ids when the writing transistor M0 operates in the linear region. [Figure 9] This diagram shows the relationship between power P and the resistance R of the resistance changing element R0 when Rpmax is set between resistances Rmin and Rmax. [Figure 10] This figure shows the relationship between power P and the resistance R of the resistance changing element R0 when Rpmax is set to be smaller than the resistance Rmin. [Figure 11] This is a block diagram showing the functional configuration of a semiconductor device according to a second embodiment of the present invention. [Figure 12] This diagram shows only the circuitry used when performing a write operation on a single-row, single-column memory cell 50 in the cell array 44. [Figure 13] This is a circuit diagram showing only the circuit related to the reset operation in a semiconductor device according to a second embodiment of the present invention. [Figure 14] This is a diagram showing the circuit configuration of Comparative Example 1. [Figure 15] This figure shows the circuit configuration of Comparative Example 2. [Figure 16] This diagram shows only the circuitry used when performing a write operation on a single-row, single-column memory cell 50A in a modified example of the second embodiment of the present invention. [Figure 17] This is a circuit diagram showing only the circuit related to the reset operation in a modified example of the second embodiment of the present invention. [Figure 18] This figure shows the variation in the write current Iw during reset operation in Comparative Examples 1 and 2, the writing circuit for the resistive switching element of the second embodiment, and the writing circuit for the resistive switching element of a modified example of the second embodiment. [Figure 19] A programming circuit for a resistive switching element in a semiconductor device according to a third embodiment of the present invention will be described. This is a block diagram of the functional configuration of the semiconductor device of this embodiment. [Figure 20] This diagram shows only the circuitry used when performing a write operation on a single-row, single-column memory cell 50A in the cell array 44. [Figure 21] This is a circuit diagram showing only the circuit related to the reset operation in a semiconductor device according to a third embodiment of the present invention. [Figure 22] This is a circuit diagram showing the configuration of a programming circuit for a resistive switching element in a semiconductor device according to a fourth embodiment of the present invention. [Figure 23] This figure shows an example of the waveform of the selection signal SXB. [Modes for carrying out the invention]

[0023] Next, embodiments of the present invention will be described in detail with reference to the drawings.

[0024] (First Embodiment) First, before describing the programming circuit for the resistive switching element of the first embodiment of the present invention, the structure of the resistive switching element will be described.

[0025] As shown in Figure 1, the resistive switching element 100 has a solid electrolyte 93 in which metal ions can move freely by an electric field, and a first electrode 91 and a second electrode 92 facing each other across the solid electrolyte 93. The first electrode 91 is an active electrode capable of supplying metal ions to the solid electrolyte 93 and is made of, for example, copper (Cu). The second electrode 92 is an inert electrode that cannot supply metal ions to the solid electrolyte 93 and is made of, for example, ruthenium (Ru). The first electrode 91 is connected to the first terminal 101, and the second electrode 92 is connected to the second terminal 102.

[0026] In this resistive switching element 100, as shown in Figure 2, when a positive voltage is applied to the first electrode 91 (first terminal 101) with the second electrode 92 (second terminal 102) at ground potential, the copper in the first electrode 91 ionizes and moves into the solid electrolyte 93, where it is deposited as metal through an electrochemical reaction. The deposited metal forms a metal bridge (also called a filament or conductive path) between the first electrode 91 and the second electrode 92. The voltage at this time is defined as the first threshold voltage or set voltage. As a result, the resistive switching element 100 transitions from a high-resistance state (off state) to a low-resistance state (on state). This transition of the resistive state from a high-resistance state (off state) to a low-resistance state (on state) is called the set operation.

[0027] Conversely, in this resistive switching element 100, as shown in Figure 3, when a positive voltage is applied to the second electrode 92 (second terminal 102) side with the first electrode 91 (first terminal 101) at ground potential, the copper atoms that constituted the metal bridge are collected on the copper electrode side of the first electrode 91, and the metal bridge is broken. As a result, the resistive switching element 100 transitions from a low resistance state (on state) to a high resistance state (off state). This operation of transitioning the resistive state from a low resistance state (on state) to a high / low resistance state (off state) is called a reset operation. Note that even before the electrical connection between the first electrode 91 and the second electrode 92 is completely broken, changes in electrical characteristics occur, such as an increase in resistance or a change in capacitance between the first electrode 91 and the second electrode 92, and finally the electrical connection is broken by the second threshold voltage or the reset voltage. To switch from the off state (high resistance) to the on state (low resistance), the second electrode 92 is grounded again and a positive voltage is applied to the first electrode 91 (reset operation).

[0028] Thus, the resistive switching element 100 is composed of a first electrode 91 which is an active electrode, a second electrode 92 which is an inert electrode, and a resistive switching layer disposed between the first electrode 91 and the second electrode 92, which contains a solid electrolyte 93 that allows the metal elements constituting the first electrode 91 to diffuse. In the resistive switching element 100, when the potential of the first electrode 91 becomes higher than that of the second electrode 92 by a first threshold voltage, the metal elements constituting the first electrode 91 diffuse into the resistive switching layer, forming a metal bridge and resulting in a low-resistance state. Furthermore, when the potential of the second electrode 92 becomes higher than that of the first electrode 91 by a second threshold voltage, the metal bridge formed in the resistive switching layer is broken, resulting in a high-resistance state.

[0029] The change in voltage and current characteristics of the resistive switching element 100 having such bipolar characteristics is shown in the graph in Figure 4.

[0030] As shown in Figure 4, the resistive switching element 100 can repeatedly change its resistance state simply by changing the direction of applied voltage, and it is non-volatile, requiring no power to maintain the on / off state. Furthermore, the resistive switching element 100 has electrical characteristics such as a large on / off resistance difference, with a resistance value of, for example, 1000Ω in the on state and for example, 100MΩ in the off state. Therefore, it is possible to realize a switch element for switching logic signals or a memory circuit for storing data using the resistive switching element 100.

[0031] Next, a programming circuit for a resistive switching element 100 that performs a reset operation to transition the resistive switching element from a low-resistance state to a high-resistance state will be described.

[0032] The resistive switching element programming circuit of this embodiment, as described below, is configured as a semiconductor integrated circuit on a semiconductor device.

[0033] Figure 5 is a circuit diagram showing the configuration of a programming circuit for a resistive switching element according to the first embodiment of the present invention.

[0034] The writing circuit for the resistive switching element in this embodiment is a circuit for performing a writing operation (reset operation) that changes the resistive state of the resistive switching element R0, whose resistive state changes according to the direction of the voltage applied between the two electrodes, from a low-resistance state to a high-resistance state.

[0035] The programming circuit for the resistive switching element in this embodiment, as shown in Figure 5, consists of a differential amplifier 11, a current source 12, a replica current path 20, and a programming current path 30.

[0036] The writing current path 30 is configured such that the resistive switching element R0 and the writing transistor M0 are connected in series between a writing voltage Vw for performing a writing operation on the resistive switching element R0 and a ground voltage VSS which is lower than the writing voltage Vw, and a writing current Iw for performing a writing operation on the resistive switching element R0 flows through it.

[0037] The first terminal of the resistive switching element R0 is connected to the drain terminal of the writing transistor M0, and the writing voltage Vw is applied to the second terminal of the resistive switching element R0. The source terminal of the writing transistor M0 is connected to the ground voltage VSS. The writing current Iw for performing the writing operation on the resistive switching element R0 flows between the second and first terminals of the resistive switching element R0, and also flows between the source and drain terminals of the writing transistor M0.

[0038] The resistive switching element R0 changes the resistance state between the first and second terminals from a low resistance state to a high resistance state, or from a high resistance state to a low resistance state, depending on the polarity of the writing current Iw flowing between the first and second terminals, or the polarity of the voltage applied between the first and second terminals.

[0039] The replica current path 20 has a replica writing transistor MR0 with substantially the same characteristics as the writing transistor M0. The drain terminal of the replica writing transistor MR0 is connected to the current source 12, and the source terminal of the replica writing transistor MR0 is connected to the ground voltage VSS. The replica current Iwr, which is set based on the current value of the writing current Iw to be passed through the resistive switching element R0, flows through the replica current Iwr. The replica current Iwr flows between the source terminal and the drain terminal of the replica writing transistor MR0.

[0040] The differential amplifier 11 is configured such that the write voltage Vw is connected to the inverting input terminal, the voltage at the output terminal of the current source 12 is connected to the non-inverting input terminal, and the control voltage Vb output from the output terminal is supplied to the gate terminals of the write transistor M0 and the replica write transistor MR0, respectively. The input impedance of the differential amplifier 11 can be set high, and the current flowing into the input terminal of the differential amplifier 11 can be kept sufficiently small.

[0041] The current source 12 supplies the replica current Iwr that flows through the replica current path 20.

[0042] The voltage control circuit 10 is configured by the current source 12, the differential amplifier 11, and the replica current path 20.

[0043] Next, the operation of the writing circuit for the resistive element of this embodiment will be described in detail with reference to the drawings.

[0044] First, we will explain the case where a writing voltage Vw is applied to a writing current path 30 in which a resistive switching element R0 and a writing transistor M0 are connected in series, thereby simply turning on the writing transistor M0.

[0045] In this case, the writing current Iw flowing through the resistive switching element R0 fluctuates depending on the resistance value of the resistive switching element R0, the on-resistance value of the writing transistor M0, the voltage value of the writing voltage Vw, etc. These resistance values, voltage values, etc., change due to variations in element characteristics caused by the semiconductor manufacturing process, variations in operating voltage and ambient temperature, etc. Therefore, the writing current Iw also changes due to variations in element characteristics caused by the semiconductor manufacturing process, variations in operating voltage and ambient temperature, etc. If the writing current Iw is too large, there is a possibility that the resistive switching element R0 will be destroyed.

[0046] Therefore, in the resistive switching element writing circuit of this embodiment, by using the circuit configuration described above, the writing current Iw is made a stable current value without being affected by variations in element characteristics caused by the semiconductor manufacturing process, variations in operating voltage and ambient temperature, etc., thereby suppressing element failure of the resistive switching element R0 and shortening the writing time.

[0047] Here, the replica current Iwr is set to a current value larger than the write current Iw that is intended to flow through the resistive switching element R0, and is also set according to the resistance value of the resistive switching element R0 in its low-resistance state.

[0048] For example, if you want the write current Iw to be several hundred μA, you set the current value of the current source 12 to about 1mA. Then, a current close to the current value of the current source 12 flows through the replica current path 20 as the replica current Iwr, and the write current Iw corresponding to the replica current Iwr flows through the write current path 30.

[0049] The following explains why the replica current Iwr remains stable and unaffected by fluctuations in the transistor's device parameters, etc., when using the resistive switching element writing circuit of this embodiment.

[0050] The control voltage Vb is controlled by the differential amplifier 11 to maintain the voltage Vwr applied to the replica current path 20 at the same voltage as the write voltage Vw. Specifically, when the replica write transistor MR0 is flowing the replica current Iwr and the voltage Vwr is higher than the write voltage Vw, the differential amplifier 11 increases the control voltage Vb by ΔVb according to the voltage difference between the voltage Vwr and the write voltage Vw. As a result, the gate-source voltage of the replica write transistor MR0 increases by ΔVb, and the drain-source voltage decreases in order for the replica write transistor MR0 to flow a constant replica current Iwr. Consequently, the voltage Vwr decreases and approaches the write voltage Vw.

[0051] Figure 6 illustrates the relationship between the drain-source voltage Vds and drain-source current Ids in the replica writing transistor MR0. Let gm be the transconductance (transconductance) and ro be the output resistance of the replica writing transistor MR0. First, when the system is in state A on drain-source current characteristic 1 in Figure 6, if the gate-source voltage increases by ΔVb, the system changes to drain-source current characteristic 2, where the current is increased by ΔIw = gm × ΔVb. The replica current Iwr is supplied from the current source 12, and the replica writing transistor MR0 flows the replica current Iwr, so the system transitions to state B, where the drain-source voltage changes by -gm × ΔVb × ro. In other words, the change in voltage Vwr ΔVwr is -gm × ΔVb × ro.

[0052] Conversely, if the voltage Vwr is lower than the write voltage Vw, the same operation occurs, causing the voltage Vwr to increase and approach the write voltage Vw. As is clear from the above explanation of operation, the replica current Iwr and voltage Vwr are stable with respect to fluctuations in the device parameters of the replica write transistor MR0.

[0053] Furthermore, the replica current Iwr is stable with respect to fluctuations in the write voltage Vw. This is because, when the write voltage Vw increases by ΔVw, the differential amplifier 11 decreases the control voltage Vb output from its output terminal by ΔVb in order for the replica writing transistor MR0 to supply a constant replica current Iwr. Conversely, when the voltage Vw decreases by ΔVw, the differential amplifier 11 increases the control voltage Vb output from its output terminal by ΔVb in order for the replica writing transistor MR0 to supply a constant current Iwr.

[0054] Thus, by using the control voltage Vb, the stability of the write current Iw is improved against changes in device parameters due to the manufacturing process and ambient temperature of the write transistor M0. For the sake of explanation, we will assume that the resistance value of the resistive switching element R0 is sufficiently low, that the gate length of the write transistor M0 and the gate length of the replica write transistor MR0 are the same, and that the gate width of the write transistor M0 and the gate width of the replica write transistor MR0 are the same. In this case, the replica current path 20 and the write current path 30 are approximately equivalent. Since the write transistor M0 has the same characteristics as the replica write transistor MR0, it is expected that the changes in device parameters due to global variations and changes in ambient temperature will be approximately the same, except for local variations between transistors. Therefore, the current value of the write current Iw will be approximately the same as the current value of the replica current Iwr. Furthermore, as explained above, the current value of the replica current Iwr is stable against changes in device parameters due to the process and ambient temperature, so the write current Iw will also be stable against changes in device parameters due to the process and ambient temperature.

[0055] Furthermore, the stability of the write current Iw is also improved with respect to the write voltage Vw. For the sake of explanation, we will assume that the resistance of the resistive switching element R0 is sufficiently low, that the gate length of the write transistor M0 and the gate length of the replica write transistor MR0 are the same, and that the gate width of the write transistor M0 and the gate width of the replica write transistor MR0 are the same. In this case, the replica current path 20 and the write current path 30 are almost equivalent. Therefore, the write current Iw is approximately the same value as the replica current Iwr. As mentioned above, since the replica current Iwr is stable with respect to fluctuations in the write voltage Vw, the write current Iw is also stable with respect to fluctuations in the write voltage Vw.

[0056] Furthermore, if the resistance of the resistive switching element R0 is not 0 but a finite value R, the source-drain voltage of the writing transistor M0 decreases from the voltage value of the writing voltage Vw, so the writing current Iw is smaller than the replica current Iwr. Figure 7 illustrates the relationship between the drain-source current Ids and the drain-source voltage Vds when the writing transistor M0 operates in the saturation region and its on-resistance is ro. When the resistance of the resistive switching element R0 is 0, the operating point is state A, and as mentioned above, the drain-source voltage Vds becomes the writing voltage Vw, and the replica current Iwr flows as the drain-source current Ids. In contrast, when the resistance of the resistive switching element R0 is R, the drain-source voltage Vds of the writing transistor M0 changes to state B, which is a decrease of Iw × R compared to point A. The drain-source current Ids decreases by the current ΔIw = (1 / ro) × Iw × R compared to point A. Therefore, it is desirable to set the replica current Iwr to a value that is ΔIw larger than the target write current Iw that you intend to pass through the resistive switching element R0.

[0057] Next, Figure 8 shows the case where the writing transistor M0 operates in the linear region, and the value obtained by subtracting the threshold voltage Vth from the gate-source voltage Vgs is less than the writing voltage Vw. For simplicity of explanation, the on-resistance ro is assumed to be infinite. When the resistance of the resistive switching element R0 is 0, the state is at point A, and as mentioned above, the drain-source voltage Vds becomes the writing voltage Vw, and the drain-source current Ids is the same as the writing current Iw, which is the same current value as the replica current Iwr. When the resistance of the resistive switching element R0 is R, the state changes to point B, where the drain-source voltage Vds decreases by Iw × R compared to point A. The drain-source current Ids decreases by ΔIw = 0.5 × β × ((Vgs - Vth) - (Vw - Iw × R) 2 It decreases by β. β is a coefficient that depends on the process constants and the gate size of the transistor. Therefore, it is desirable to set the replica current Iwr to a current value that is ΔIw larger than the target write current Iw.

[0058] Furthermore, during the reset operation, Joule heat is generated by the power P consumed by the resistive switching element R0, and the replica current Iwr may be set so that this Joule heat can cut a portion of the metal bridge. Figure 9 illustrates the relationship between the power P and the resistance R of the resistive switching element R0. The power P consumed by the resistive switching element R0 is R × Iwr 2 This is expressed as follows. Here, the power P corresponds to the area of ​​the quadrilateral BCDE with vertices B, C, D, and E in Figure 7 or Figure 8. When the resistance of the resistive switching element R0 is sufficiently small, the area of ​​the quadrilateral BCDE is approximately 0. As the resistance of the resistive switching element R0 increases, the area BCDE increases, and eventually the area BCDE begins to decrease. Therefore, the power P consumed by the resistive switching element R0 is equal to R × Iw. 2 The power P reaches its maximum value when the resistance R is Rpmax. Here, if the variation range of multiple resistance changing elements in a semiconductor device has a distribution from resistance Rmin to resistance Rmax, Rpmax is set between resistance Rmin and Rmax as shown in Figure 9. By doing so, even if the resistance value R varies, the variation in power P can be kept low. Also, the maximum value of power P is Rpmax × Iw 2It may be configured so that it can cut a portion of the metal bridge.

[0059] Specifically, the replica current Iwr may be set such that the resistance value that generates the maximum amount of heat (Joule heat) in the resistive switching element R0 is included within the range of variation in the resistance value of the resistive switching element R0 in its low-resistance state.

[0060] Furthermore, as shown in Figure 10, Rpmax may be set to be smaller than the resistance Rmin. Assuming the shape of the metal bridge is a single cylindrical shape, it is presumed that the lower the resistance value, the thicker the metal bridge is, the more thermally stable it is, and the greater the Joule heat required to cut a part of the metal bridge. Therefore, the smaller the resistance R, the smaller the Rpmax should be set to be compared to the resistance Rmin so that higher Joule heat can be obtained. In addition, the resistance Rmin may be determined by including not only the minimum value of the resistance distribution after the set operation, but also the minimum value of the resistance distribution after the reset operation. Patent Document 2 mentioned above discloses that a failure mode during reset occurs in which a resistance-changing element with a low resistance value is generated by the reset operation.

[0061] Specifically, the replica current Iwr may be set such that the resistance value at which the heat generated in the resistive switching element R0 is maximized is smaller than the variation range of the resistance value of the resistive switching element R0 in the low-resistance state.

[0062] Note that the gate length of the writing transistor M0 and the gate length of the replica writing transistor MR0 do not necessarily have to be the same. Also, the gate width of the writing transistor M0 and the gate width of the replica writing transistor MR0 do not necessarily have to be the same. For example, if the ratio of the gate length L0 to the gate width W0 of the writing transistor M0 (W0 / L0) is K times the ratio of the gate length LR0 to the gate width WR0 of the replica writing transistor MR0 (WR0 / LR0), then the replica current Iwr can be set to Iwr(K=1) / K, and the writing current Iw will be Iwr(K=1). Here, Iwr(K=1) is the value of the replica current Iwr when the gate length of the writing transistor M0 and the gate length of the replica writing transistor MR0 are the same, and the gate width of the writing transistor M0 and the gate width of the replica writing transistor MR0 are the same. This makes it possible to reduce the power consumption of the voltage control circuit 10.

[0063] In such cases, the replica current Iwr is set to Iwr / K when the gate width and gate length of the replica writing transistor MR0 are approximately the same as those of the writing transistor M0, respectively. If the ratio of the gate width to the gate length of the writing transistor M0 is K times the ratio of the gate width to the gate length of the replica writing transistor MR0, the replica current Iwr is set to Iwr / K.

[0064] Furthermore, in this embodiment, the maximum voltage applied to the resistive switching element R0 can be limited to the write voltage Vw. Specifically, the write voltage Vw is divided between the resistive switching element R0 and the write transistor M0, but if the resistance value of the resistive switching element R0 is sufficiently large, a voltage approximately equal to the write voltage Vw will be applied to the resistive switching element R0. In particular, because the resistive switching element R0 has a large resistance change ratio, if it transitions to a high-resistance state during reset operation and its resistance value increases, the resistive switching element R0 may be destroyed. Therefore, it is desirable to set the write voltage Vw to a voltage that does not cause element destruction. Since the write voltage Vw can be generated by a general power supply circuit that does not depend on the semiconductor manufacturing process, operating voltage, or ambient temperature, the semiconductor device of this embodiment can stably and easily set the write voltage Vw to a voltage that does not cause element destruction of the resistive switching element R0, regardless of the semiconductor manufacturing process, operating voltage, or ambient temperature.

[0065] In the circuit diagram showing the writing circuit for the resistive switching element of the first embodiment shown in Figure 1, the resistive switching element R0 is connected to the drain terminal of the writing transistor M0, but this configuration is not necessarily required. The resistive switching element R0 may be configured to be connected to the source terminal of the writing transistor M0.

[0066] In the circuit diagram showing the writing circuit for the resistive switching element of the first embodiment shown in Figure 1, the first terminal of the resistive switching element R0 is connected to the drain terminal of the writing transistor M0, and the case where the resistive switching element R0 transitions from a low resistance state to a high resistance state when the writing current Iw flows has been described. However, the circuit configuration may also be such that the second terminal of the resistive switching element is connected to the drain terminal of the writing transistor M0, and the resistive switching element R0 transitions from a high resistance state to a low resistance state when the writing current Iw flows.

[0067] Thus, the resistive switching element writing circuit of this embodiment suppresses element failure of the resistive switching element R0 while achieving a stable writing current Iw regardless of the semiconductor manufacturing process, ambient temperature, and operating voltage. As a result, it is possible to reduce the margin of the writing voltage and current during verify writing when performing a writing operation on the resistive switching element R0, thereby shortening the writing time.

[0068] (Second embodiment) Next, a semiconductor device according to a second embodiment of the present invention will be described.

[0069] The semiconductor device of this embodiment constitutes a memory device in which a plurality of memory cells, each composed of a resistive switching element and a cell transistor as described above, are arranged at the intersection of the bit line pair and the word line. The resistive switching element writing circuit in this embodiment is a circuit for performing a writing operation on the resistive switching element in a memory device of this configuration, changing its resistance state from a low resistance state to a high resistance state.

[0070] First, the functional configuration of the semiconductor device of this embodiment will be described with reference to the block diagram shown in Figure 11.

[0071] As shown in Figure 11, the semiconductor device of this embodiment includes a control circuit 41, a row decoder 42, a column decoder 43, a cell array 44, a readout circuit 45, and a voltage control circuit 46.

[0072] The cell array 44 consists of multiple memory cells and is connected to multiple bit line pairs BL, BLB and multiple word lines WL. Each of the multiple memory cells consists of a resistive switching element and a cell transistor and is connected to the bit line pair and the word line.

[0073] The column decoder 43 is connected to multiple bit line pairs BL and BLB. The column decoder 43 selects the specified bit line pairs BL and BLB according to the column selection signal and applies a predetermined voltage. In other words, the column decoder 43 is positioned to apply a predetermined voltage to the bit line pair BL, BLB selected by the column selection signal.

[0074] The row decoder 42 is connected to multiple word lines WL. The row decoder 42 selects a designated word line WL in response to a row selection signal and applies a predetermined voltage to it. In other words, the row decoder 42 is configured to apply a predetermined voltage to the word line selected by the row selection signal.

[0075] The readout circuit 45 is connected to the bit line pairs BL and BLB via the column decoder 43 and applies a readout voltage to supply a readout current to the resistive switching element. Since the readout current changes according to the resistance state of the resistive switching element, the resistance state of the resistive switching element is determined by comparing it with the reference current. The readout circuit 45 outputs the readout result to the control circuit 41.

[0076] The control circuit 41 receives external control signals such as address signals, write data signals, and command signals, and outputs read data. The control circuit 41 generates row selection signals and column selection signals according to the address signal and outputs them to the row decoder 42 and column decoder 43, respectively. The control circuit 41 generates internal control signals for writing and reading operations according to the external control signals.

[0077] The voltage control circuit 46 generates bias voltages Vb(SET) and Vb(RST) to ensure stable writing.

[0078] Next, Figure 12 shows only the circuit for performing a write operation on a single-row, single-column memory cell 50 in the cell array 44.

[0079] As shown in Figure 12, the cell array 44 consists of bit line pairs BL0 and BLB0 extending in the vertical direction, a word line WL0 extending in the horizontal direction, and memory cells 50 located at the intersections of the bit line pairs BL0 and BLB0 and the word line WL0. The memory cell 50 consists of a resistive switching element R0 and a cell transistor MC. The first terminal of the resistive switching element R0 is connected to the bit line BL0, and the second terminal is connected to either the source terminal or the drain terminal of the cell transistor MC. The other terminal of the source terminal or drain terminal of the cell transistor MC is connected to the other bit line pair BLB0. The gate terminal of the cell transistor MC is connected to the word line WL0.

[0080] The column decoder 43 consists of a source-side column decoder 43A and a sink-side column decoder 43B. The source-side column decoder 43A is connected to the write voltage VSET during set operation and the write voltage VRST during reset operation, which are used to write to the resistive switching element R0. The sink-side column decoder 43B is connected to a ground voltage VSS, which is lower than the write voltages VSET and VRST.

[0081] The source-side column decoder 43A comprises two transistors M1 and M101. The source terminal of transistor M1 is connected to the write voltage VRST during reset operation, the drain terminal is connected to the bit line BLB0, and the gate terminal is connected to the column selection signal C0B(RST). The source terminal of transistor M101 is connected to the write voltage VSET during set operation, the drain terminal is connected to the bit line BL0, and the gate terminal is connected to the column selection signal C0B(SET).

[0082] The sink-side column decoder 43B comprises four transistors: a writing transistor M0 and three transistors M2, M100, and M103. The drain terminal of the writing transistor M0 is connected to the bit line BL0, its source terminal is connected to the drain terminal of transistor M2, and its gate terminal is connected to the bias voltage Vb(RST). The source terminal of transistor M2 is connected to the ground voltage VSS, and its gate terminal is connected to the column selection signal C0(RST). The drain terminal of transistor M100 is connected to the bit line BLB0, its source terminal is connected to the drain terminal of transistor M102, and its gate terminal is connected to the bias voltage Vb(SET). The source terminal of transistor M102 is connected to the ground voltage VSS, and its gate terminal is connected to the column selection signal C0(SET).

[0083] The row decoder 42 consists of transistors M4 and M5. The source terminal of transistor M4 is connected to the word line voltage VWL, the drain terminal is connected to the word line WL0, and the gate terminal is connected to the row selection signal R0B. The source terminal of transistor M5 is connected to the ground voltage VSS, the drain terminal is connected to the word line WL0, and the gate terminal is connected to the row selection signal R0B.

[0084] In standby mode, column selection signals C0 (SET) and C0 (RST) cause transistors M2 and M102 to conduct, and bit line pairs BL0 and BLB0 to be grounded. Column selection signals C0B (SET) and C0B (RST) cause transistors M1 and M101 to deconduct. Row selection signal R0B causes transistor M5 to conduct, transistor M4 to deconduct, and word line WL0 to be grounded.

[0085] During the set operation, if the resistive element R0 is selected, the column selection signal C0 (SET) causes transistor M102 to conduct and the bit line BLB0 to be grounded. The column selection signal C0B (SET) causes transistor M101 to conduct and the bit line BL0 is connected to the write voltage VSET during the set operation. Then, the column selection signals C0 (RST) and C0B (RST) cause transistors M2 and M1 to become non-conductive. Then, the row selection signal R0B causes transistor M5 to become non-conductive and transistor M4 to conduct, and the word line WL0 is connected to the word line voltage VWL. As a result, the write current flows from the bit line BL0 through the resistive element R0 and the cell transistor MC to the bit line BLB0.

[0086] During a reset operation, if the resistive element R0 is selected, the column selection signal C0(RST) causes transistor M2 to conduct and the bit line BL0 is grounded. Then, the column selection signal C0B(RST) causes transistor M1 to conduct, and the bit line BLB0 is connected to the write voltage VRST during the reset operation. Then, the column selection signals C0(SET) and C0B(SET) cause transistors M102 and M101 to become non-conductive. Then, the row selection signal R0B causes transistor M5 to become non-conductive and transistor M4 to conduct, and the word line WL0 is connected to the word line voltage VWL. As a result, the write current flows from the bit line BLB0 through the resistive element R0 and the cell transistor MC to the bit line BL0.

[0087] Figure 13 is a circuit diagram showing only the circuits related to the reset operation in a semiconductor device according to a second embodiment of the present invention. The semiconductor device of this embodiment includes a write current path 70 through which a write current Iw flows, and a voltage control circuit 46.

[0088] As described above, the write current path 70 comprises a resistive switching element R0, a transistor M1 in the source-side column decoder 43A, a cell transistor MC in the memory cell 50, and write transistors M0 and M2 in the sink-side column decoder 43B. The first terminal of the resistive switching element R0 is connected to the drain terminal of the write transistor M0. The source terminal of the write transistor M0 is connected to the drain terminal of the transistor M2. The source terminal of the transistor M2 is connected to the ground voltage VSS. The source terminal of the transistor M1 is connected to the write voltage VRST during reset operation, and its drain terminal is connected to the drain terminal of the cell transistor MC. The source terminal of the cell transistor MC is connected to the second terminal of the resistive switching element R0. In other words, the write current path 70 is composed of the first and second terminals of the resistive switching element R0, the source and drain terminals of the write transistor M0, the source and drain terminals of the transistor M1, the source and drain terminals of the cell transistor MC, and the source and drain terminals of the transistor M2, all connected in series.

[0089] The voltage control circuit 46 includes a current source 12 that supplies a replica current Iwr, a differential amplifier 11, and a replica current path 60 through which the replica current Iwr flows.

[0090] The replica current path 60 comprises a replica transistor MR1, a replica cell transistor MRC, a replica writing transistor MR0, and a replica transistor MR2. The source terminal of replica transistor MR1 is connected to the first terminal of the replica current path 60, and its drain terminal is connected to the drain terminal of replica cell transistor MRC. The source terminal of replica cell transistor MRC is connected to the drain terminal of replica writing transistor MR0. The source terminal of replica writing transistor MR0 is connected to the drain terminal of replica transistor MR2. The source terminal of MR2 is connected to the second terminal of the replica current path 60 and also to the ground voltage VSS. In other words, the source and drain terminals of replica writing transistor MR0, the source and drain terminals of replica transistor MR1, the source and drain terminals of replica cell transistor MR2, and the source and drain terminals of replica transistor MR2 are connected in series.

[0091] If we ignore the resistance change element R0 in the write current path 70 and consider its resistance to be 0, the circuit configuration of the replica current path 60 becomes equivalent to the circuit configuration of the write current path 70. Therefore, the replica transistors on the replica current path 60 have a one-to-one correspondence with the transistors on the write path 70.

[0092] Each replica transistor on the replica current path 60 is a transistor with the same characteristics as the corresponding transistor on the write current path 70. Specifically, the write transistor M0 and the replica write transistor MR0 are transistors with the same characteristics. Also, transistor M1 and the replica transistor MR1 are transistors with the same characteristics. Furthermore, cell transistor MC and the replica cell transistor MRC are transistors with the same characteristics. And transistor M2 and the replica transistor MR2 are transistors with the same characteristics.

[0093] Furthermore, the same voltage is applied to the gate terminal of each replica transistor on the replica current path 60 and the gate terminal of the corresponding transistor on the write current path 70, thereby turning on the operating state of each transistor. Specifically, the gate terminal of the write transistor M0 and the gate terminal of the replica write transistor MR0 are each applied with the bias voltage Vb(RST) output from the output terminal of the differential amplifier 11. In addition, the gate terminal of transistor M1 and the gate terminal of replica transistor MR1 are each applied with the same voltage column selection signal C0B and replica column selection signal CRB, respectively, which turn on the operating state of the transistors. In addition, the gate terminal of cell transistor MC and the gate terminal of replica cell transistor MRC are each applied with the same voltage word line voltage VWL, which turns on the operating state of the transistors. In addition, the gate terminal of transistor M2 and the gate terminal of replica transistor MR2 are each applied with the same voltage column selection signal C0 and replica column selection signal CR, which turn on the operating state of the transistors.

[0094] As described above, in the semiconductor device of this embodiment, the transistor M1, the cell transistor MC, and the resistive switching element R0 in the source-side column decoder 43A, and the writing transistors M0 and M2 in the sink-side column decoder 43B are connected in series between the writing voltage VRST and the ground voltage VSS, forming a writing current path 70 through which the writing current Iw for performing the writing operation of the resistive switching element R0 flows.

[0095] The replica current path 60 is configured such that a replica transistor MR1, which has approximately the same characteristics as transistor M1, a replica cell transistor MRC, which has approximately the same characteristics as cell transistor MC, a replica writing transistor MR0, which has approximately the same characteristics as writing transistor M0, and a replica transistor MR2, which has approximately the same characteristics as second transistor M2, are connected in series between the current source 12 and the ground voltage VSS. The replica current path 60 is configured so that a replica current set based on the current value of the writing current Iw that is to be passed through the resistive switching element R0 flows through it.

[0096] The differential amplifier 11 has the write voltage VRST connected to its inverting input terminal, and the voltage from the output terminal of the current source 12 connected to its non-inverting input terminal. It supplies a bias voltage Vb(RST), which functions as a control voltage output from the output terminal, to the gate terminals of the write transistor M0 and the replica write transistor MR0, respectively.

[0097] The writing circuit for the resistive switching element in the semiconductor device of this embodiment has the same configuration as the first embodiment described above, although the circuit configuration of the writing current path 70 and the replica current path 60 is different. Therefore, a detailed explanation of the connection relationships of the current source 12 and the differential amplifier 11 will be omitted.

[0098] Next, before describing the programming circuit for the resistive switching element in the semiconductor device of this embodiment, we will present two comparative examples, Comparative Example 1 and Comparative Example 2.

[0099] First, Figure 14 shows the circuit configuration of Comparative Example 1. Comparative Example 1 includes a write current path 70. The write current path 70 shown in Figure 14 has the same circuit configuration as the write current path 70 in the second embodiment shown in Figure 13. However, Comparative Example 1 shown in Figure 14 does not include a voltage control circuit 46, and differs in that the bias voltage Vb applied to the gate terminal of the write transistor M0 is a fixed voltage.

[0100] Next, Figure 15 shows the circuit configuration of Comparative Example 2. Comparative Example 2 includes a write current path 70, a replica current path 80, and a current source 12. The write current path 70 shown in Figure 15 has the same circuit configuration as the write current path 70 in the second embodiment shown in Figure 13.

[0101] The replica current path 80 includes a replica write transistor MR0. The drain terminal of the replica write transistor MR0 is connected to the gate terminal, which is connected to the gate terminal of transistor M0 in the write current path, and which is connected to the output terminal of the current source. The source terminal of the replica transistor is connected to the ground voltage VSS. Thus, Comparative Example 2 utilizes a current mirror circuit, and the write current Iw is controlled by the replica current Iwr.

[0102] Next, Figure 16 shows a modified example of this embodiment. In the modified example of this embodiment shown in Figure 16, the memory cell 50 is replaced with a memory cell 50A compared to the second embodiment shown in Figure 13. The circuit configuration other than the memory cell 50A is the same as in this embodiment, so its explanation is omitted.

[0103] Memory cell 50A consists of a resistive switching element R0 and a cell transistor MC. The second terminal of the resistive switching element R0 is connected to the bit line BLB0, and the first terminal is connected to either the source terminal or the drain terminal of the cell transistor MC. The other terminal of the source terminal or drain terminal of the cell transistor MC is connected to the other bit line pair BL0. The gate terminal of the cell transistor MC is connected to the word line WL0. Thus, memory cell 50A differs from memory cell 50 shown in Figure 13 in that the connection positions of the resistive switching element R0 and the cell transistor MC are reversed.

[0104] Figure 17 is a circuit diagram showing only the circuit related to the reset operation in a modified version of this embodiment. Compared to the second embodiment shown in Figure 13, the write current path 70 is replaced with a write current path 70A. Since the modified version of this embodiment is the same as this embodiment except for the write current path 70A, a detailed explanation is omitted.

[0105] The write current path 70A comprises a resistive switching element R0, a transistor M1 in the source-side column decoder 43A, a cell transistor MC in the memory cell 50A, and write transistors M0 and M2 in the sink-side column decoder 43B. The first terminal of the resistive switching element R0 is connected to the drain terminal of the cell transistor MC. The source terminal of the cell transistor MC is connected to the drain terminal of the write transistor M0. The source terminal of the write transistor M0 is connected to the drain terminal of the transistor M2. The source terminal of the transistor M2 is connected to the ground voltage VSS. The source terminal of the transistor M1 is connected to the write voltage VRST during reset operation, and its drain terminal is connected to the second terminal of the resistive switching element R0. In other words, the write current path 70A consists of the first and second terminals of the resistive switching element R0, the source and drain terminals of the write transistor M0, the source and drain terminals of the transistor M1, the source and drain terminals of the cell transistor MC, and the source and drain terminals of the transistor M2, all connected in series.

[0106] Figure 18 shows the variation in the write current Iw during reset operation for Comparative Examples 1 and 2 described above, the write circuit for the resistive element of this embodiment, and the write circuit for the resistive element of a modified example of this embodiment.

[0107] Here, simulations were performed by varying the transistor characteristics, operating voltage, and ambient temperature to obtain the write current Iw. The variation was defined as the difference between the maximum and minimum values ​​of the obtained write current, divided by the minimum value. Furthermore, the vertical axis of the graph shown in Figure 18 was normalized by the variation of the write current Iw in Comparative Example 1. In other words, the variation of the write current Iw in Comparative Example 1 is set to 100%, and the graph shows the degree of variation in the write current Iw in Comparative Example 2, the resistive switching element writing circuit of this embodiment, and the resistive switching element writing circuit of the modified example of this embodiment.

[0108] Referring to Figure 18, it can be seen that the second embodiment and its modified version exhibit less variation in the write current Iw compared to Comparative Example 1 and Comparative Example 2. Therefore, it can be seen that the semiconductor devices of this embodiment and its modified version can supply a stable write current Iw to the semiconductor manufacturing process, ambient temperature, and operating voltage while suppressing the failure of the resistive switching element R0.

[0109] Furthermore, it can be seen that the variation in the second embodiment shows less variation in the writing current Iw compared to the second embodiment. This is presumed to be because in the second embodiment, the resistive switching element R0 is connected to the source side of the cell transistor MC, resulting in a higher source potential.

[0110] In the simulation, the cell transistor MC and replica cell transistor MRC of the second embodiment operated in the linear region. Furthermore, the cell transistor MC and replica cell transistor MRC of the modified version of the second embodiment also operated in the linear region. Additionally, the source voltage of the cell transistor MC of the second embodiment was higher than that of the modified version of the second embodiment, resulting in a higher on-resistance. The source potential of the replica cell transistor MRC was close to that of the cell transistor MC of the modified version of the second embodiment. For confirmation, when the word line voltage VWL and word line WL0 voltages decreased by 0.1V, the change in gate-source voltage Vgs was approximately the same. If the threshold voltage of the transistor considering the substrate bias effect is Vth, the on-resistance is proportional to 1 / (Vgs-Vth), and the change in on-resistance is 1 / (Vgs-Vth). 2 Since it is proportional to the source potential, the change in on-resistance is larger as the source potential increases.

[0111] In the second embodiment, the on-resistance of the replica writing transistor MR0 on the replica current path 60 decreases to offset the change in the on-resistance of the transistor MRC on the replica current path 60. Although the on-resistance of the writing transistor M0 on the writing current path 70 also decreases, it is presumed that the increase in the on-resistance of the cell transistor MC was greater and not sufficiently offset.

[0112] On the other hand, in the modified version of the second embodiment, the on-resistance of the replica write transistor MR0 on the replica current path 60 is reduced to offset the change in the on-resistance of the replica cell transistor MRC on the replica current path 60. The on-resistance of the write transistor M0 on the write current path 70A is also reduced, which is presumed to more effectively offset the increase in the on-resistance of the cell transistor MC. Therefore, connecting a resistive element R0 to the drain terminal of the cell transistor MC, as in the modified version of the second embodiment, is suitable for semiconductor devices that provide a stable write current Iw during reset operation.

[0113] Thus, the semiconductor device of this embodiment makes it possible to supply a stable write current Iw to the semiconductor manufacturing process, ambient temperature, and operating voltage while suppressing the failure of the resistive switching element R0. This is expected to reduce the margins of the write voltage and current during verify writing, thereby shortening the writing time.

[0114] (Third embodiment) Next, a programming circuit for a resistive switching element in a semiconductor device according to a third embodiment of the present invention will be described. A block diagram of the functional configuration of the semiconductor device of this embodiment is shown in Figure 19.

[0115] The semiconductor device of this embodiment, as shown in Figure 19, comprises a control circuit 41, a row decoder 142, a column decoder 143, a cell array 44, a readout circuit 45, and a voltage control circuit 146. The block diagram shown in Figure 19 differs from the block diagram of the second embodiment shown in Figure 11 only in that the row decoder 42, the column decoder 43, and the voltage control circuit 46 are replaced by the row decoder 142, the column decoder 143, and the voltage control circuit 146, respectively. Therefore, the parts that overlap with the second embodiment will not be explained.

[0116] Next, Figure 20 shows only the circuit for performing a write operation on a single-row, single-column memory cell 50A in the cell array 44.

[0117] The cell array 44 consists of bit line pairs BL0 and BLB0 extending in the vertical direction, a word line WL0 extending in the horizontal direction, and memory cells 50A located at the intersections of the bit line pairs BL0 and BLB0 and the word line WL0. The memory cell 50A consists of a resistive switching element R0 and a cell transistor MC. The first terminal of the resistive switching element R0 is connected to the bit line BLB0, and the second terminal is connected to either the source terminal or the drain terminal of the cell transistor MC. The other terminal of the source terminal or drain terminal of the cell transistor MC is connected to the other bit line BL0 of the bit line pair. The gate terminal of the cell transistor MC is connected to the word line WL0.

[0118] The column decoder 143 consists of a source-side column decoder 143A and a sink-side column decoder 143B. The source-side column decoder 143A is supplied with a write voltage VSET during set operation and a write voltage VRST during reset operation. The sink-side column decoder 143B is supplied with a ground voltage VSS.

[0119] The source-side column decoder 143A comprises two transistors M1 and M101. The source terminal of transistor M1 is connected to the write voltage VRST during reset operation, the drain terminal is connected to the bit line BLB0, and the gate terminal is connected to the column selection signal C0B(RST). The source terminal of transistor M101 is connected to the write voltage VSET during set operation, the drain terminal is connected to the bit line BL0, and the gate terminal is connected to the column selection signal C0B(SET).

[0120] The sink-side column decoder 143B comprises two transistors M2 and M102. The drain terminal of transistor M2 is connected to the bit line BL0, the source terminal is connected to the ground voltage VSS, and the gate terminal is connected to the column selection signal C0 (RST). The drain terminal of transistor M102 is connected to the bit line BLB0, the source terminal is connected to the ground voltage VSS, and the gate terminal is connected to the column selection signal C0 (SET).

[0121] The low decoder 142 consists of transistors M4, M5, M6, and M7. The source terminal of transistor M6 is connected to the bias voltage Vb(RST), the drain terminal is connected to the source terminal of transistor M4, and the gate terminal is connected to the low selection signal R0B(RST). The source terminal of transistor M7 is connected to the bias voltage Vb(SET), the drain terminal is connected to the source terminal of transistor M4, and the gate terminal is connected to the low selection signal R0B(SET). The drain terminal of transistor M4 is connected to the word line WL0, and the gate terminal is connected to the low selection signal R0B. The source terminal of transistor M5 is connected to the ground voltage VSS, the drain terminal is connected to the word line WL0, and the gate terminal is connected to the low selection signal R0B.

[0122] In standby mode, column selection signals C0 (SET) and C0 (RST) cause transistors M2 and M102 to conduct, and bit line pairs BL0 and BLB0 to be grounded. Column selection signals C0B (SET) and C0B (RST) cause transistors M1 and M101 to deconduct. Then, row selection signal R0B causes transistor M5 to conduct, transistor M4 to deconduct, and word line WL0 to be grounded.

[0123] During the set operation, if the resistive element R0 is selected, the column selection signal C0 (SET) causes transistor M102 to conduct and the bit line BLB0 is grounded. Then, the column selection signal C0B (SET) causes transistor M101 to conduct and the bit line BL0 is connected to the write voltage VSET during the set operation. Then, the column selection signals C0 (RST) and C0B (RST) cause transistors M2 and M1 to become non-conductive. Then, the row selection signal R0B (SET) causes transistor M7 to conduct. Then, the row selection signal R0B (RST) causes transistor M6 to become non-conductive. Then, the row selection signal R0B causes transistor M5 to become non-conductive and transistor M4 to conduct, and the word line WL0 is connected to the bias voltage Vb (SET). As a result, the write current flows from the bit line BL0 through the resistive element R0 and the cell transistor MC to the bit line BLB0.

[0124] Furthermore, during a reset operation, if the resistive element R0 is selected, the column selection signal C0 (RST) causes transistor M2 to conduct and the bit line BL0 to be grounded. Then, the column selection signal C0B (RST) causes transistor M1 to conduct, and the bit line BLB0 is connected to the write voltage VRST during the reset operation. Then, the column selection signals C0 (SET) and C0B (SET) cause transistors M102 and M101 to become non-conductive. Then, the row selection signal R0B (SET) causes transistor M7 to become non-conductive. Then, the row selection signal R0B (RST) causes transistor M6 to conduct. Then, the row selection signal R0B causes transistor M5 to become non-conductive and transistor M4 to conduct, and the word line WL0 is connected to the bias voltage Vb (RST). As a result, the write current flows from the bit line BLB0 through the resistive element R0 and the cell transistor MC to the bit line BL0.

[0125] Figure 21 is a circuit diagram showing only the circuits related to the reset operation in a semiconductor device according to a third embodiment of the present invention. The semiconductor device of this embodiment includes a write current path 170 through which a write current Iw flows, and a voltage control circuit 146.

[0126] As described above, the write current path 170 comprises a resistive switching element R0, a transistor M1 in the source-side column decoder 143A, a cell transistor MC in the memory cell 50A, and a transistor M2 in the sink-side column decoder 143B. The first terminal of the resistive switching element R0 is connected to the drain terminal of the cell transistor MC. The source terminal of the cell transistor MC is connected to the drain terminal of the transistor M2. The source terminal of the transistor M2 is connected to the ground voltage VSS. The source terminal of the transistor M1 is connected to the write voltage VRST during reset operation, and its drain terminal is connected to the second terminal of the resistive switching element R0. In other words, the write current path 170 consists of the first and second terminals of the resistive switching element R0, the source and drain terminals of the transistor M1, the source and drain terminals of the cell transistor MC, and the source and drain terminals of the transistor M2, all connected in series.

[0127] The voltage control circuit 146 includes a current source 12 that supplies a replica current Iwr, a differential amplifier 11, and a replica current path 160 through which the replica current Iwr flows.

[0128] The replica current path 160 comprises a replica transistor MR1, a replica cell transistor MRC, and a replica transistor MR2. The source terminal of replica transistor MR1 is connected to the first terminal of the replica current path 160, and its drain terminal is connected to the drain terminal of replica cell transistor MRC. The source terminal of replica cell transistor MRC is connected to the drain terminal of replica transistor MR2. The source terminal of replica transistor MR2 is connected to the ground voltage VSS. In other words, the source and drain terminals of replica transistor MR1, the source and drain terminals of replica cell transistor MRC, and the source and drain terminals of replica transistor MR2 are connected in series.

[0129] If we ignore the resistance change element R0 in the write current path 170 and consider its resistance to be 0, the circuit configuration of the replica current path 160 is equivalent to the circuit configuration of the write current path 170. Therefore, each replica transistor on the replica current path 160 has a one-to-one correspondence with each transistor on the write current path 170.

[0130] Each replica transistor on the replica current path 160 is a transistor with the same characteristics as each transistor on the corresponding write current path 170. Specifically, transistor M1 and replica transistor MR1 are transistors with the same characteristics. Also, cell transistor MC and replica cell transistor MRC are transistors with the same characteristics. Furthermore, transistor M2 and replica transistor MR2 are transistors with the same characteristics.

[0131] Furthermore, the same voltage that turns the transistors ON can be supplied to the gate terminals of each replica transistor on the replica current path 160 and the gate terminals of each transistor on the corresponding write current path 170. Specifically, the control voltage Vb(RST) output from the output terminal of the differential amplifier 11 is applied to the gate terminal of the cell transistor MC and the gate terminal of the replica cell transistor MRC, respectively. In addition, the same voltage column selection signal C0B and replica column selection signal CRB that turn the transistors ON are applied to the gate terminal of transistor M1 and the gate terminal of replica transistor MR1, respectively. In addition, the same voltage column selection signal C0 and replica column selection signal CR that turn the transistors ON are applied to the gate terminal of transistor M2 and the gate terminal of replica transistor MR2.

[0132] As described above, in the semiconductor device of this embodiment, the transistor M1 in the source-side column decoder 143A, the cell transistor MC, the resistive switching element R0, and the transistor M2 in the sink-side column decoder 143B are connected in series between the write voltage VRST and the ground voltage VSS, forming a write current path 170 through which the write current Iw for performing the write operation of the resistive switching element R0 flows.

[0133] The replica current path 160 is configured such that a replica transistor MR1 having approximately the same characteristics as transistor M1, a replica cell transistor MRC having approximately the same characteristics as cell transistor MC, and a replica transistor MR2 having approximately the same characteristics as transistor M2 are connected in series between the current source 12 and the ground voltage VSS, and a replica current Iwr, set based on the current value of the writing current Iw to be passed through the resistive switching element R0, flows through it.

[0134] The differential amplifier 11 has the write voltage VRST connected to its inverting input terminal, the voltage of the output terminal of the current source 12 connected to its non-inverting input terminal, and supplies a bias voltage Vb(RST) which functions as a control voltage output from the output terminal to the gate terminal of the replica cell transistor MRC, and also supplies it to the gate terminal of the cell transistor MC via the low decoder 142.

[0135] Although the circuit configuration of the write current path 170 and the replica current path 160 differs from that of the first embodiment described above, the semiconductor device of this embodiment has the same configuration in all other respects, so the explanation of the connection relationships of the current source 12 and the differential amplifier 11 will be omitted.

[0136] According to the semiconductor device of this embodiment, by directly controlling the gate voltage of the cell transistor MC in the memory cell 50A, the on-resistance can be effectively stabilized against the semiconductor manufacturing process, ambient temperature, and operating voltage, thereby stabilizing the write current Iw. The cell transistor MC in the memory cell 50A tends to have a small transistor size and high on-resistance, and it can be difficult to compensate for this with the on-resistance of other transistors, as in the second embodiment. Therefore, a configuration that directly controls the gate voltage of the cell transistor MC in the memory cell 50A is suitable for a semiconductor device that provides a stable write current Iw.

[0137] Thus, the semiconductor device of this embodiment makes it possible to supply a stable write current Iw to the semiconductor manufacturing process, ambient temperature, and operating voltage while suppressing the failure of the resistive switching element R0. This is expected to reduce the margins of the write voltage and current during verify writing, thereby shortening the writing time.

[0138] (Fourth embodiment) Next, a programming circuit for a resistive switching element in a semiconductor device according to a fourth embodiment of the present invention will be described.

[0139] Figure 22 is a circuit diagram showing the configuration of a programming circuit for a resistive switching element in a semiconductor device according to a fourth embodiment of the present invention.

[0140] The writing circuit for the resistive switching element of the semiconductor device in this embodiment includes a writing current path 130 through which a writing current Iw flows, and a voltage control circuit 110.

[0141] The first terminal of the write current path 130 is subjected to the write voltage Vw, and the second terminal is subjected to a ground voltage VSS that is lower than the write voltage Vw.

[0142] The write current path 130 comprises a resistive switching element R0, a write transistor M0, and a transistor M1. The first terminal of the resistive switching element R0 is connected to the drain terminal of the write transistor M0, and the second terminal of the resistive switching element R0 is connected to the drain terminal of the transistor M1. The source terminal of the transistor M1 is connected to the first terminal of the write current path 130 and is also connected to the write voltage Vw. The source terminal of the write transistor M0 is connected to the second terminal of the write current path 130 and is also connected to the ground voltage VSS. During writing, the write current Iw flows between the first and second terminals of the resistive switching element R0, between the source and drain terminals of the write transistor M0 on the write current path 130, and between the source and drain terminals of the transistor M1 on the write current path 130.

[0143] The voltage control circuit 110 includes a current source 12 that supplies a replica current Iwr, a differential amplifier 11, and a replica current path 120 through which the replica current Iwr flows.

[0144] In this embodiment of the semiconductor device, although the circuit configuration of the write current path 130 and the replica current path 120 differs from that of the first embodiment shown in Figure 5, the other circuit configurations are the same, so the explanation of the connection relationships of the current source 12 and the differential amplifier 11 will be omitted.

[0145] The first terminal of the replica current path 120 is connected to the output terminal of the current source 12, and further connected to the non-inverting input terminal of the differential amplifier 11. The second terminal of the replica current path 120 is connected to the ground voltage VSS.

[0146] The replica current path 120 comprises N subpaths, where N is an integer greater than or equal to 2. One end of each of the N subpaths is connected to the first terminal of the replica current path 120, and the other end of each of the N subpaths is connected to the second terminal of the replica current path 120. In this way, the N subpaths are connected in parallel.

[0147] One of the N subpaths, subpath X, comprises multiple replica write transistors MR0X having the same characteristics as the write transistor M0 of the write current path 130. Subpath X further comprises multiple replica transistors (selection transistors) MR1X having the same characteristics as the transistor M1 of the write current path 130, where X is an integer from 1 to N. The drain terminal of the replica write transistor MR0X is connected to the drain terminal of the replica transistor MR1X, and the source terminal of the replica write transistor MR0X is connected to the second terminal of the replica current path 120. The source terminal of the replica transistor MR1X is connected to the first terminal of the replica current path 120. The gate terminal of the replica write transistor MR0X is connected to the control voltage Vb, and the gate terminal of the replica transistor MR1X is connected to the selection signal SXB.

[0148] Thus, the replica current path 120 has replica writing transistors MR0X and MR1X, which have substantially the same characteristics as the writing transistor M0, and is composed of multiple subpaths connected in parallel between the output terminal of the current source 12 and the ground voltage VSS.

[0149] Then, a selection signal SXB is input to the gate terminal of each of the multiple replica transistors MR1X, causing only one of the multiple replica transistors MR1X to become conductive, and the conductive replica transistor MR1X is controlled to switch sequentially at a preset time interval T.

[0150] Figure 23 shows an example of the waveform of the selection signal SXB. At each time interval T, one selection signal SXB is sequentially selected, the transistor MR1X in the corresponding subpath becomes conductive, and the replica current Iwr flows through the selected subpath. Since the resistive switching element writing circuit in this embodiment has N subpaths, the time during which the replica current Iwr flows in each subpath can be reduced to 1 / N. This suppresses transistor degradation due to hot carriers. Therefore, the resistive switching element writing circuit in this embodiment can suppress transistor degradation on the replica current path 120 and improve transistor reliability, thereby providing a more stable writing current Iw.

[0151] Thus, the semiconductor device of this embodiment makes it possible to supply a stable write current to the semiconductor manufacturing process, ambient temperature, and operating voltage while suppressing the failure of the resistive switching element R0. This is expected to reduce the margins of the write voltage and current during verify writing, thereby shortening the writing time. [Explanation of Symbols]

[0152] 10 Voltage control circuit 11 Differential Amplifier 12 Current source 20 Replica Current Paths 30. Writing current path 41 Control circuits 42 Raw Decoder 43-column decoder 43A Source-side column decoder 43B Sink-side column decoder 44-cell array 45 Readout Circuit 46 Voltage control circuit 50 memory cells 50A Memory Cell 60 Replica Current Paths 70. Write current path 70A writing current path 80 Replica Current Paths 91 1st electrode (active electrode) 92 2nd electrode (inert electrode) 93 Solid electrolyte 100 Resistive switching element 101 1st terminal 102 2nd terminal 110 Voltage control circuit 120 replica current paths 130 Writing current path 142 Low Decoder 143-column decoder 143A Source-side column decoder 143B Sink-side column decoder 146 Voltage control circuit 160 replica current paths 170 Writing current path IWR (Replica Current) Iw write current M0 writing transistor MR0 replica writing transistor R0 Resistance change element VSS Ground Voltage Vb control voltage Vw writing voltage

Claims

1. A programming circuit for a resistive switching element, in which the resistance state changes depending on the direction of the voltage applied between two electrodes, and which performs a programming operation to change the resistance state from a low resistance state to a high resistance state, The resistive element and the writing transistor are connected in series between a writing voltage for performing a writing operation on the resistive element and a ground voltage lower than the writing voltage, and a writing current path through which a writing current flows for performing a writing operation on the resistive element, A current source and The replica current path includes a replica writing transistor having substantially the same characteristics as the writing transistor, the drain terminal of the replica writing transistor being connected to the current source, the source terminal of the replica writing transistor being connected to the ground voltage, and a replica current set based on the current value of the writing current to be passed through the resistance change element. A differential amplifier is provided, in which the writing voltage is connected to an inverting input terminal, the voltage of the output terminal of the current source is connected to a non-inverting input terminal, and the control voltage output from the output terminal is supplied to the gate terminals of the writing transistor and the replica writing transistor, respectively. A programming circuit for a resistive switching element having the following properties.

2. The aforementioned resistance change element is The first electrode is the active electrode, The second electrode is an inert electrode, It is composed of a resistance-changing layer disposed between the first electrode and the second electrode, which contains a solid electrolyte that allows the metal elements constituting the first electrode to diffuse, When the potential of the first electrode becomes higher than that of the second electrode by the amount of the first threshold voltage, the metal elements constituting the first electrode diffuse into the resistance change layer, forming a metal bridge and resulting in a low-resistance state. When the potential of the second electrode becomes higher than that of the first electrode by the amount of the second threshold voltage, the metal bridge formed in the resistance change layer is broken, resulting in a high-resistance state. A programming circuit for a resistive switching element according to claim 1.

3. The writing circuit for a resistive element according to claim 1, wherein the replica current is set to a current value larger than the writing current and is set according to the resistance value of the resistive element in the low-resistance state.

4. The resistive switching element writing circuit according to claim 3, wherein the replica current is set such that the resistance value that generates the maximum amount of heat in the resistive switching element is included within the range of variation of the resistance value in the low-resistance state of the resistive switching element.

5. The resistive switching element writing circuit according to claim 3, wherein the replica current is set such that the resistance value at which the amount of heat generated in the resistive switching element is maximum is smaller than the variation range of the resistance value in the low-resistance state of the resistive switching element.

6. The writing circuit for a resistive switching element according to claim 1, wherein the current value of the replica current is set to Iwr when the gate width and gate length of the replica writing transistor are substantially the same as the gate width and gate length of the writing transistor, respectively, and the current value of the replica current is set to Iwr / K when the ratio of the gate width to gate length of the writing transistor is K times the ratio of the gate width to gate length of the replica writing transistor.

7. In a memory device in which a plurality of memory cells, each composed of a resistive switching element whose resistance state changes according to the direction of the voltage applied between two electrodes and a cell transistor, are arranged at the intersection of a bit line pair and a word line, a writing circuit for a resistive switching element is provided for performing a writing operation on the resistive switching element, which changes the resistance state from a low resistance state to a high resistance state. A column decoder comprising a source-side column decoder connected to a write voltage for performing a write operation on the resistive change element, and a sink-side column decoder connected to a ground voltage lower than the write voltage, which is arranged to apply a predetermined voltage to the bit line pair selected by the column selection signal, The system comprises a row decoder that applies a predetermined voltage to the word line selected by the row selection signal, Between the writing voltage and the ground voltage, the first transistor in the source-side column decoder, the cell transistor, the resistive switching element, and the writing transistor and second transistor in the sink-side column decoder are connected in series, forming a writing current path through which a writing current flows to perform the writing operation of the resistive switching element. Furthermore, a current source and A first replica transistor having substantially the same characteristics as the first transistor, a replica cell transistor having substantially the same characteristics as the cell transistor, a replica writing transistor having substantially the same characteristics as the writing transistor, and a second replica transistor having substantially the same characteristics as the second transistor are connected in series between the current source and the ground voltage, and a replica current path through which a replica current set based on the current value of the writing current to be passed through the resistance change element flows, The differential amplifier comprises a differential amplifier to which the writing voltage is connected to an inverting input terminal, the voltage of the output terminal of the current source is connected to a non-inverting input terminal, and the control voltage output from the output terminal is supplied to the gate terminals of the writing transistor and the replica writing transistor, respectively. A column selection signal of the same voltage is applied to the gate terminal of the first transistor and the gate terminal of the first replica transistor to turn on the operating state, a row selection signal of the same voltage is applied to the gate terminal of the cell transistor and the gate terminal of the replica cell transistor to turn on the operating state, and a column selection signal of the same voltage is applied to the gate terminal of the second transistor and the gate terminal of the second replica transistor to turn on the operating state. A programming circuit for a resistive switching element.

8. In a memory device in which a plurality of memory cells, each composed of a resistive switching element whose resistance state changes according to the direction of the voltage applied between two electrodes and a cell transistor, are arranged at the intersection of a bit line pair and a word line, a writing circuit for a resistive switching element is provided for performing a writing operation on the resistive switching element, which changes the resistance state from a low resistance state to a high resistance state. A column decoder comprising a source-side column decoder connected to a write voltage for performing a write operation on the resistive change element, and a sink-side column decoder connected to a ground voltage lower than the write voltage, which is arranged to apply a predetermined voltage to the bit line pair selected by the column selection signal, The system comprises a row decoder that applies a predetermined voltage to the word line selected by the row selection signal, Between the writing voltage and the ground voltage, the first transistor in the source-side column decoder, the cell transistor, the resistive element, and the second transistor in the sink-side column decoder are connected in series, forming a writing current path through which a writing current flows for performing the writing operation of the resistive element. Furthermore, a current source and A first replica transistor having substantially the same characteristics as the first transistor, a replica cell transistor having substantially the same characteristics as the cell transistor, and a second replica transistor having substantially the same characteristics as the second transistor are connected in series between the current source and the ground voltage, and a replica current path through which a replica current set based on the current value of the writing current to be passed through the resistance change element flows, The differential amplifier comprises a differential amplifier to which the writing voltage is connected to an inverting input terminal, the voltage of the output terminal of the current source is connected to a non-inverting input terminal, and which supplies the control voltage output from the output terminal to the gate terminal of the replica cell transistor, and also supplies the control voltage to the gate terminal of the cell transistor via the low decoder, A column selection signal of the same voltage to turn on the operating state is applied to the gate terminal of the first transistor and the gate terminal of the first replica transistor, and a column selection signal of the same voltage to turn on the operating state is applied to the gate terminal of the second transistor and the gate terminal of the second replica transistor. A programming circuit for a resistive switching element.

9. The writing circuit for a resistive switching element according to claim 1, wherein the replica current path is composed of a plurality of subpaths having substantially the same characteristics as the writing transistor and a selection transistor, and connected in parallel between the output terminal of the current source and the ground voltage.

10. A programming circuit for a resistive element according to claim 9, wherein a selection signal input to the gate terminal of each of the plurality of selection transistors causes only one of the plurality of selection transistors to become conductive, and the selection transistor that becomes conductive is controlled to switch sequentially at a preset time interval.

11. A semiconductor device in which a writing circuit for a resistive switching element according to any one of claims 1 to 10 is configured as a semiconductor integrated circuit.

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