Nanosynapse integrated device and manufacturing method therefor

Abstract

A nanosynapse integrated device and a manufacturing method therefor. The nanosynapse integrated device comprises: a substrate (1); an insulation layer (2) provided on the substrate (1); and a plurality of nanosynapse units (3) provided on the insulation layer (2). Each nanosynapse unit (3) comprises a first microelectrode (31) and a second microelectrode (32) which are opposite, and a GaN-based nanowire (33) provided between the first microelectrode (31) and the second microelectrode (32), a first end of the GaN-based nanowire (33) being bonded to the first microelectrode (31), and a second end of the GaN-based nanowire (33) being bonded to the second microelectrode (32). The nanosynapse integrated device uses the GaN-based nanowires (33) as synapse elements in the device, and the GaN-based nanowires (33) have controllable direct band gaps and stable physical and chemical properties. In the nanosynapse integrated device, the plurality of nanosynapse units (3) are integrally arranged on the same substrate (1), and therefore the nanosynapse integrated device can be manufactured on a scale, and has a small size and high level of integration. The plurality of nanosynapse units (3) can be separately and independently controlled or can be subjected to overall array control according to an arranged array pattern.

Description

A nanosynaptic integrated device and its preparation method Technical Field

[0001] The present invention relates to the field of artificial neural technology, and in particular to a nano-synapse integrated device and a preparation method thereof. Background Art

[0002] In the human brain's nervous system, a synapse is defined as the connection point between two neurons, serving as a crucial pathway for transmitting nerve impulses from the presynaptic neuron to the postsynaptic neuron. When an electrical signal is sent to the presynaptic neuron, an electrical spike called an action potential is generated. This spike then releases chemicals (so-called neurotransmitters) across the synaptic cleft, triggering an impulse in the postsynaptic neuron. Artificial synapses mimic biological synapses in neuromorphic computing systems, and based on this synaptic structure, are applied to various detection devices and biomimetic structures.

[0003] In recent years, with the rapid development of big data, the internet, and artificial intelligence, traditional von Neumann architecture computing systems (with independent memory and storage units) have struggled to meet future application demands. In contrast, the human brain possesses remarkable capabilities for processing large amounts of data. It can simultaneously store, integrate, and process information through a dense, coordinated network of synapses and neurons. When processing analog signals detected by sensory organs, such as visual information received by the retina, it can significantly reduce energy consumption and improve data management efficiency. Interconnected neural networks enable distributed processing and high-speed computing. Inspired by the human brain, artificial synaptic devices have emerged and are attracting widespread attention for their ability to simultaneously process and memorize data. Therefore, artificial synapses are expected to become an indispensable core component in next-generation computing systems.

[0004] Nanowires are considered effective for simulating learning and cognition in artificial synapses due to their outstanding properties, such as a large surface-to-volume ratio and compact size. However, nanosynaptic devices are currently difficult to fabricate and have extremely low integration levels. Consequently, high-density integrated systems based on nanosynaptic devices are difficult to fabricate, significantly limiting their application in areas such as brain-inspired computing systems.

[0005] Summary of the Invention

[0006] In view of this, the present invention provides a nano-synapse integrated device with simple preparation process and high integration and a preparation method thereof.

[0007] In order to achieve the above object, the present invention adopts the following technical solutions:

[0008] A nanosynaptic integrated device, comprising:

[0009] substrate;

[0010] an insulating layer disposed on the substrate;

[0011] a plurality of nanosynapse units disposed on the insulating layer;

[0012] The nanosynaptic unit includes a first microelectrode and a second microelectrode arranged opposite to each other, and a GaN-based nanowire arranged between the first microelectrode and the second microelectrode, wherein the first end of the GaN-based nanowire is bonded to the first microelectrode, and the second end of the GaN-based nanowire is bonded to the second microelectrode.

[0013] In a preferred embodiment, the GaN-based nanowires are GaN nanowires, AlGaN nanowires or InGaN nanowires.

[0014] In a preferred embodiment, the thickness of the first microelectrode and the second microelectrode are respectively 50 nm to 500 nm, and the distance between the first microelectrode and the second microelectrode is 0.8 μm to 5 μm.

[0015] In a preferred embodiment, the plurality of nanosynaptic units are arranged on the insulating layer in an array of M rows × N columns, where M and N are positive integers.

[0016] In a preferred embodiment, in the nanosynaptic unit, the first microelectrode is electrically connected to a first external electrode, and the second microelectrode is electrically connected to a second external electrode; wherein the first microelectrodes of all the nanosynaptic units are connected to a first external electrode one by one, and the second microelectrodes of all the nanosynaptic units are connected to the same second external electrode; or, the first microelectrodes of all the nanosynaptic units are connected to the same first external electrode, and the second microelectrodes of all the nanosynaptic units are connected to the same second external electrode.

[0017] In a preferred embodiment, a first covering electrode is formed on the first microelectrode and covers the first end of the GaN-based nanowire, and a second covering electrode is formed on the second microelectrode and covers the second end of the GaN-based nanowire.

[0018] In a preferred solution, the thickness of the first covering electrode and the second covering electrode are respectively 80 nm to 200 nm.

[0019] In a preferred embodiment, the first microelectrode and the first covering electrode together constitute a source electrode, the second microelectrode and the second covering electrode together constitute a drain electrode, and a gate layer is formed on the surface of the substrate facing away from the insulating layer.

[0020] Another aspect of the present invention is to provide a method for preparing the nanosynaptic integrated device as described above, comprising:

[0021] Providing a substrate and depositing an insulating layer on the substrate;

[0022] Using a photolithography process to prepare a plurality of sets of first microelectrodes and second microelectrodes arranged opposite to each other on the insulating layer;

[0023] Growing GaN-based nanowires on an epitaxial substrate;

[0024] peeling the GaN-based nanowires from the epitaxial substrate and transferring them between the first microelectrode and the second microelectrode;

[0025] The two ends of the GaN-based nanowire are bonded and connected to the first microelectrode and the second microelectrode respectively.

[0026] In a preferred embodiment, after the GaN-based nanowires are transferred between the first microelectrode and the second microelectrode, a dielectrophoresis process is applied so that the two ends of the GaN-based nanowires are respectively overlapped onto the surfaces of the first microelectrode and the second microelectrode; wherein the process parameters of the dielectrophoresis process include: an AC voltage of 3V to 15V, a frequency of 1kHz to 1MHz, a power-on time of 10min to 20min, and a dielectrophoresis solution of acetone, isopropyl alcohol or ethanol.

[0027] The nanosynaptic integrated device and its preparation method provided by embodiments of the present invention utilize GaN-based nanowires as the synaptic elements in the device. GaN-based nanowires have a controllable direct band gap and stable physical and chemical properties. They are compatible with existing semiconductor technologies and have a mature, stable, and simple preparation process. They can be integrated with a light source to form an on-chip optoelectronic neuromorphic device, offering both optical and electrical pulse stimulation capabilities. In this nanosynaptic integrated device, multiple nanosynaptic units are integrated on the same substrate, enabling large-scale production, a compact size, and high integration. The multiple integrated nanosynaptic units can be configured to be independently controllable or to be controlled as a whole array according to a pre-arranged array pattern. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] FIG1 is a cross-sectional view of the nanosynapse integrated device in Example 1;

[0029] FIG2 is a schematic diagram of the distribution structure of nanosynaptic units on the insulating layer in Example 1;

[0030] FIG3 is a SEM image of GaN-based nanowires connected between microelectrodes in Example 1;

[0031] FIG4 is a diagram showing the results of light pulse stimulation response tests with different pulse times in Example 1;

[0032] FIG5 is a diagram showing the results of a sustained light pulse stimulation response test performed in Example 1;

[0033] FIG6 is a schematic diagram of the distribution structure of nanosynapse units on the insulating layer in another preferred embodiment;

[0034] FIG7 is a schematic diagram of the distribution structure of nanosynapse units on the insulating layer in another preferred embodiment;

[0035] FIG8 is a cross-sectional view of the nanosynapse integrated device in Example 2;

[0036] FIG9 is a diagram showing the test results of simulating synaptic learning behavior in Example 2;

[0037] FIG10 is a cross-sectional view of the nanosynapse integrated device in Example 3. DETAILED DESCRIPTION

[0038] To make the objectives, technical solutions, and advantages of the present invention more apparent, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings. Examples of these preferred embodiments are illustrated in the accompanying drawings. The embodiments of the present invention shown in and described with reference to the accompanying drawings are merely exemplary, and the present invention is not limited to these embodiments.

[0039] It should also be noted that, in order to avoid obscuring the present invention due to unnecessary details, the accompanying drawings only show structures and / or processing steps closely related to the solutions according to the present invention, while other details that are not closely related to the present invention are omitted.

[0040] Example 1

[0041] This embodiment provides a nanosynaptic integrated device. FIG1 is a cross-sectional view of the nanosynaptic integrator of this embodiment at a position corresponding to a nanosynaptic unit. FIG2 is a schematic diagram of the distribution structure of the nanosynaptic units on the insulating layer of this embodiment.

[0042] 1 and 2 , the nanosynaptic integrated device includes a substrate 1 and an insulating layer 2 disposed on the substrate 1. The insulating layer 2 is provided with a plurality of nanosynaptic units 3, which are arranged in an array to form a nanosynaptic unit array 4.

[0043] The nanosynaptic unit 3 includes a first microelectrode 31 and a second microelectrode 32 disposed opposite each other, and a GaN-based nanowire 33 disposed between the first microelectrode 31 and the second microelectrode 32. The first end of the GaN-based nanowire 33 is bonded to the first microelectrode 31, and the second end of the GaN-based nanowire 33 is bonded to the second microelectrode 32. In this embodiment, the substrate 1 is a silicon substrate, and the insulating layer 2 is made of SiO2.

[0044] As a preferred solution, in this embodiment, the GaN-based nanowires are GaN nanowires. In some other embodiments, the GaN-based nanowires may be AlGaN nanowires or InGaN nanowires.

[0045] As a preferred solution, in this embodiment, the thickness of the first microelectrode 31 and the second microelectrode 32 are each 80 nm, specifically comprising a stacked 20 nm thick Ti metal layer and a 60 nm thick Au metal layer, and the spacing between the first microelectrode 31 and the second microelectrode 32 is 1 μm. In other embodiments, the thickness of the first microelectrode 31 and the second microelectrode 32 are each preferably set within the range of 50 nm to 500 nm, and the spacing between the first microelectrode 31 and the second microelectrode 32 is preferably set within the range of 0.8 μm to 5 μm.

[0046] In a preferred embodiment, the plurality of nanosynaptic units 3 are arranged on the insulating layer 2 in an array of M rows × N columns, where M and N are positive integers. As shown in FIG2 , in this embodiment, the plurality of nanosynaptic units 3 are arranged on the insulating layer 2 in an array of 4 rows × 2 columns. In other embodiments, as shown in FIG6 and FIG7 , the plurality of nanosynaptic units 3 are arranged on the insulating layer 2 in an array of 6 rows × 1 column.

[0047] In a preferred embodiment, referring to FIG2 , in the nanosynaptic unit 3, the first microelectrode 31 is electrically connected to a first external electrode 51, and the second microelectrode 32 is electrically connected to a second external electrode 52. In some embodiments, as shown in FIG2 and FIG7 , the first microelectrodes 31 of all nanosynaptic units 3 are connected to a first external electrode 51 in a one-to-one correspondence, and the second microelectrodes 32 of all nanosynaptic units 3 are connected to the same second external electrode 52, thereby enabling each nanosynaptic unit 3 to be independently controlled.

[0048] In some other embodiments, as shown in Figure 6, the first microelectrodes 31 of all the nanosynaptic units 3 are commonly connected to the same first external electrode 51, and the second microelectrodes 32 of all the nanosynaptic units 3 are commonly connected to the same second external electrode 52. At this time, all the nanosynaptic units 3 need to be controlled at the same time, that is, all the nanosynaptic units 3 can be controlled as a whole array according to the arranged array pattern.

[0049] The method for preparing the nanosynaptic integrated device provided in this embodiment includes the following steps:

[0050] The first step is to provide a substrate 1 and deposit an insulating layer 2 on the substrate 1 .

[0051] Step 2: Using a photolithography process, a plurality of groups of first microelectrodes 31 and second microelectrodes 32 arranged opposite to each other are prepared on the insulating layer 2 .

[0052] Step 3: Grow GaN nanowires on the epitaxial substrate using molecular beam epitaxy, transfer them to an isopropyl alcohol solution by physical exfoliation, and ultrasonically disperse them to fully fuse the GaN nanowires with the isopropyl alcohol solution.

[0053] Step 4: Place the device obtained in Step 2 on the probe platform. Use a microinjector to extract 5 μL of the solution obtained in Step 3 and drip it between the first microelectrode 31 and the second microelectrode 32. Use dielectrophoresis to ensure that one end of the GaN nanowire in the solution overlaps the first microelectrode 31, and the other end of the GaN nanowire overlaps the second microelectrode 32. The dielectrophoresis process parameters include: the AC voltage can be selected from 3V to 15V, the frequency can be set to 1kHz to 1MHz, and the power-on time is within the range of 10min to 20min until the solution is completely evaporated. The dielectrophoresis solution can be selected from acetone, isopropyl alcohol, or ethanol.

[0054] Step 5: Place the device obtained in the fourth step into an annealing furnace for high-temperature annealing, so that the two ends of the GaN nanowire are bonded to the first microelectrode 31 and the second microelectrode 32 respectively, thereby preparing a nanosynaptic integrated device.

[0055] The surface of the obtained nanosynaptic integrated device was observed by electron scanning electron microscopy (SEM), as shown in FIG3 , where a single GaN nanowire was seen connected between the two microelectrodes.

[0056] The nanosynaptic integrated device obtained in this embodiment was subjected to a light pulse stimulation test. Specifically, the first external electrode 51 and the second external electrode 52 were connected to the two ends of a DC power supply, and a 5V DC voltage was applied to the first microelectrode 31 and the second microelectrode 32 through the first external electrode 51 and the second external electrode 52. The GaN nanowire was irradiated with ultraviolet light for light pulse stimulation: (1) The output power of the ultraviolet lamp was 2W, and the pulse time was set to 100ms, 250ms, 500ms, 1000ms and 1500ms respectively. Multiple groups of tests were conducted. As shown in FIG4, in each group of tests, when there were two light pulse stimulations, the device had a memory function for the detected photon signal. (2) The output power of the ultraviolet lamp was 2W, and the pulse time was set to 1s. The GaN nanowire was subjected to a continuous light pulse stimulation test. As shown in FIG5, when there was continuous signal source stimulation, the device had a continuous response. When the signal source stopped, the device response slowly returned to the initial state. The test results show that by changing the light power, pulse time and number of pulses of ultraviolet light, synaptic-like performance can be obtained, which has the performance of light pulse stimulation.

[0057] The nanosynaptic integrated device obtained in this example was tested for electrical pulse stimulation. Specifically, the first and second external electrodes 51, 52 were connected to a pulse power supply. A pulse voltage with a voltage amplitude of 3V and a pulse duration of 100ms was applied to the first and second microelectrodes 31, 32 via the first and second external electrodes 51, 52. The test results show that by varying the duration, number, and voltage of the voltage pulses, synaptic-like performance can be achieved, demonstrating electrical pulse stimulation capabilities.

[0058] Example 2

[0059] The nanosynaptic integrated device provided in this embodiment is based on the device structure provided in Example 1 and additionally has the following structure: Referring to Figure 8, a first covering electrode 61 is formed on the first microelectrode 31 and covers the first end of the GaN-based nanowire 33, and a second covering electrode 62 is formed on the second microelectrode 32 and covers the second end of the GaN-based nanowire 33.

[0060] In this embodiment, the first microelectrode 31 and the first covering electrode 61 together constitute a source electrode, and the second microelectrode 32 and the second covering electrode 62 together constitute a drain electrode.

[0061] In this embodiment, the thickness of the first cover electrode 61 and the second cover electrode 62 are 80 nm respectively. In some other embodiments, the thickness of the first cover electrode 61 and the second cover electrode 62 can be set in the range of 80 nm to 200 nm.

[0062] The difference between the preparation process of the nanosynaptic integrated device of this embodiment and that of Example 1 is that: referring to the preparation process steps of Example 1, after proceeding to the fourth step of overlapping the GaN nanowire between the two microelectrodes, the first covering electrode 61 is first prepared on the first microelectrode 31 by the overlay method, and the second covering electrode 62 is prepared on the second microelectrode 32, and then the fifth step of the annealing bonding process is carried out.

[0063] An electric pulse stimulation test was performed on the nanosynaptic integrated device obtained in this embodiment. Specifically, the first external electrode 51 and the second external electrode 52 were respectively connected to the two ends of the pulse power supply, and a pulse voltage was applied to the source electrode and the drain electrode through the first external electrode 51 and the second external electrode 52. The voltage amplitude was 5V and the voltage pulse time was 1s. Among them, the source electrode was used to simulate the presynaptic, the drain electrode was used to simulate the postsynaptic, the pulse power supply was used to simulate the presynaptic stimulation, and the GaN nanowire was used to simulate the synaptic effect.

[0064] FIG9 is a diagram illustrating the test results of simulating synaptic learning behavior. A total of four groups of tests were conducted in sequence. As shown in FIG9 , in the order from left to right, after completing the first group of 20 pulse stimulations, the electrical stimulation was stopped for a certain period of time before the second group of 20 pulse stimulations was performed; after completing the second group of 20 pulse stimulations, the electrical stimulation was stopped for a certain period of time before the third group of 20 pulse stimulations was performed; after completing the third group of 20 pulse stimulations, the electrical stimulation was stopped for a certain period of time before the fourth group of 20 pulse stimulations was performed. This simulates the learning-forgetting-relearning process of the synapse: the initial 20 continuous pulse stimulations serve as the training process of the artificial neural synapse, which is similar to the learning process of the human brain. After the pulse stimulation is removed, the weight of the device gradually decreases, similar to the forgetting process of the human brain; after a period of time, when the pulse is applied again, only a smaller number of pulses are required for the synaptic device to return to the memory level before forgetting, similar to the relearning process of the human brain. As can be seen from FIG9 , the nanosynaptic integrated device of this embodiment has the performance of simulating the learning-forgetting-relearning process of the synapse. This learning-forgetting-relearning process can be used in the learning and recognition functions of future artificial neural networks.

[0065] The nanosynaptic integrated device of this embodiment was compared with the device of Example 1 through long-term testing. It was found that after the covering electrode was provided on the microelectrode of this embodiment, the contact point between the GaN nanowire and the electrode could be effectively protected, thereby improving the reliability of the device.

[0066] Example 3

[0067] The nanosynaptic integrated device provided in this embodiment is based on the device structure provided in Example 2 and additionally includes the following structure: Referring to FIG10 , a gate layer 7 is formed on the surface of substrate 1 facing away from insulating layer 2. Specifically, a PCB circuit board can be added below substrate 1, and the two can be connected using silver paste, thereby forming the gate on the PCB.

[0068] The nanosynaptic integrated device obtained in this embodiment was subjected to an electrical pulse stimulation test. Specifically, the first microelectrode 31 and the first covering electrode 61 together formed a source electrode connected to one end of a pulse power supply, the other end of which was connected to the lead port of the gate layer 7. The source electrode was also connected to one end of a DC power supply, the other end of which was connected to a drain electrode formed by the second microelectrode 32 and the second covering electrode 62. The DC power supply voltage was set to 10V, the pulse power supply voltage was set to 5V, and the pulse duration was 1s. The gate was used to simulate presynaptic junctions, the drain electrode was used to simulate postsynaptic junctions, the pulse power supply was used to simulate presynaptic stimulation, the DC power supply was used to supply energy to the source electrode, and the GaN nanowires were used to simulate double-pulse facilitation behavior. The addition of the gate in this embodiment makes the device more controllable.

[0069] In summary, the nanosynaptic integrated device and its preparation method provided by the embodiments of the present invention use GaN-based nanowires as the synaptic elements in the device. GaN-based nanowires have a controllable direct band gap and stable physical and chemical properties. They are compatible with existing semiconductor technology and have a mature, stable and simple preparation process. They can also be integrated with a light source to form an on-chip optoelectronic neuromorphic device, and can simultaneously provide the performance of optical and electrical pulse stimulation. In this nanosynaptic integrated device, multiple nanosynaptic units are integrated on the same substrate, which allows for large-scale preparation, a small size, and high integration. In some specific embodiments, the multiple integrated nanosynaptic units can be independently controlled; in other specific embodiments, the multiple integrated nanosynaptic units can be controlled as a whole array according to a pre-arranged array pattern.

[0070] It should be noted that the above embodiments are merely illustrative of the technical concepts and features of the present invention. Their purpose is to enable those skilled in the art to understand the contents of the present invention and implement them accordingly. They are not intended to limit the scope of protection of the present invention. Any equivalent variations or modifications made in accordance with the spirit and substance of the present invention are intended to be encompassed within the scope of protection of the present invention.

Claims

1. A nanosynaptic integrated device, wherein: include: substrate; An insulating layer disposed on the substrate; a plurality of nanosynapse units disposed on the insulating layer; The nanosynaptic unit includes a first microelectrode and a second microelectrode arranged opposite to each other and a GaN-based nanowire arranged between the first microelectrode and the second microelectrode, wherein the first end of the GaN-based nanowire is bonded to the first microelectrode, and the second end of the GaN-based nanowire is bonded to the second microelectrode.

2. The nanosynaptic integrated device according to claim 1, wherein: The GaN-based nanowires are GaN nanowires, AlGaN nanowires or InGaN nanowires.

3. The nanosynaptic integrated device according to claim 1, wherein: The thickness of the first microelectrode and the second microelectrode are respectively 50 nm to 500 nm, and the distance between the first microelectrode and the second microelectrode is 0.8 μm to 5 μm.

4. The nanosynaptic integrated device according to claim 1, wherein: The plurality of nanosynaptic units are arranged on the insulating layer in an array of M rows×N columns, where M and N are positive integers respectively.

5. The nanosynapse integrated device according to claim 4, wherein: In the nanosynaptic unit, the first microelectrode is electrically connected to a first external electrode, and the second microelectrode is electrically connected to a second external electrode; wherein, The first microelectrodes of all the nanosynaptic units are connected to a first external electrode one by one, and the second microelectrodes of all the nanosynaptic units are connected to the same second external electrode; or, the first microelectrodes of all the nanosynaptic units are connected to the same first external electrode, and the second microelectrodes of all the nanosynaptic units are connected to the same second external electrode.

6. The nanosynapse integrated device according to any one of claims 1 to 5, wherein: A first covering electrode is formed on the first microelectrode and covers the first end of the GaN-based nanowire, and a second covering electrode is formed on the second microelectrode and covers the second end of the GaN-based nanowire.

7. The nanosynapse integrated device according to claim 6, wherein: The thickness of the first covering electrode and the second covering electrode are respectively 80 nm to 200 nm.

8. The nanosynapse integrated device according to claim 6, wherein: The first microelectrode and the first covering electrode together constitute a source electrode, the second microelectrode and the second covering electrode together constitute a drain electrode, and a gate layer is formed on a surface of the substrate facing away from the insulating layer.

9. A method for preparing a nanosynapse integrated device according to any one of claims 1 to 8, wherein: include: Providing a substrate and depositing an insulating layer on the substrate; Using a photolithography process to prepare a plurality of groups of first microelectrodes and second microelectrodes arranged opposite to each other on the insulating layer; Growing GaN-based nanowires on an epitaxial substrate; The GaN-based nanowires are peeled off from the epitaxial substrate and transferred between the first microelectrode and the second microelectrode; The two ends of the GaN-based nanowire are bonded and connected to the first microelectrode and the second microelectrode respectively.

10. The method for preparing a nanosynapse integrated device according to claim 9, wherein: After the GaN-based nanowires are transferred between the first microelectrode and the second microelectrode, a dielectrophoresis process is applied to allow the two ends of the GaN-based nanowires to overlap the surfaces of the first microelectrode and the second microelectrode, respectively; wherein the process parameters of the dielectrophoresis process include: an AC voltage of 3V to 15V, a frequency of 1kHz to 1MHz, a power-on time of 10min to 20min, and a dielectrophoresis solution of acetone, isopropanol or ethanol.

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