Time signal processing circuit based on multiplication-type interpolation circuit

Abstract

A time signal processing circuit based on a multiplication-type interpolation circuit, comprising three parts, i.e., a time signal processing circuit, a calibration circuit, and a digital logic circuit, and implementing a time input signal-digital output signal conversion process. An input time signal is quantized by the time signal processing circuit to obtain a series of digital codes and the digital codes are output; feedback compensation is performed on the time signal processing circuit by means of the calibration circuit; and finally, final digital output is completed by the digital logic circuit. The time signal processing circuit based on a multiplication-type interpolation circuit quantizes a time input signal and outputs the quantized signal as a digital signal. The time signal processing circuit uses a pipeline operation system, so that the conversion speed is significantly increased, and the limitation relationship between the conversion speed and resolution is alleviated; the conversion precision of a time domain circuit is improved due to the assistance of the calibration circuit; and digital codes in different periods are integrated into synchronous digital output by the digital logic circuit, thus implementing a high-performance time signal processing circuit.

Description

A time signal processing circuit based on multiplication type interpolation circuit Technical Field

[0001] The invention relates to a time signal processing circuit based on a multiplication type interpolation circuit, belonging to the technical field of signal processing. Background Art

[0002] Time signal processing circuits convert time signals into different types of signals and play a vital role in fields such as communications systems, aerospace, and medical devices. High-performance time signal processing circuits can be applied to more advanced and sophisticated applications, including military applications and key areas such as radar systems. Conversion rate, conversion accuracy, and power consumption are important performance indicators for time signal processing circuits, but speed, accuracy, and power consumption often constrain the three factors. Improving the quantization accuracy of time signals will help accelerate the resolution of existing technical barriers and enable the realization of high-speed, high-precision, and low-power time signal processing circuits.

[0003] Time signal processing circuits are used in key modules such as time-to-digital conversion circuits, phase-locked loop circuits, and time-domain analog-to-digital conversion circuits. They use a fixed time delay to divide the input time quantity into multiple quantized intervals. By comparing the phase information, a series of digital codes are generated and output. The fixed time delay, or the quantization accuracy of the time signal processing circuit, is a key parameter for measuring its accuracy. In a delay chain structure, the fixed time delay is formed by a buffer, and the quantization accuracy is equal to the delay of one buffer. Due to process limitations, the quantization accuracy is relatively low. To improve the quantization accuracy of time signals, a vernier structure uses two transmission paths with different time delays to achieve time signal conversion. The quantization accuracy of the time signal is equal to the delay difference between the two delay units. However, due to factors such as process, power supply voltage, and temperature variations, the accuracy is moderate. Therefore, improving the quantization accuracy of time signal processing circuits is a technical challenge that needs to be addressed urgently. It is also a key design focus for high-performance time signal processing circuits and has a crucial impact on the performance of related signal processing applications.

[0004] The present invention can overcome the deficiencies of the prior art and further improve and enhance the performance levels of the time signal processing circuit, such as speed and quantization accuracy.

[0005] Summary of the Invention

[0006] The present invention proposes a time signal processing circuit based on a multiplication-type interpolation circuit that quantizes input time signals and outputs them as digital signals. First, the time signal processing circuit quantizes the input time signal, generating a series of digital code outputs. Second, a calibration circuit provides feedback compensation to the time signal processing circuit. Finally, a digital logic circuit produces the final digital output. Compared to existing technologies, this invention improves conversion speed and efficiency, achieves higher time quantization accuracy, and realizes more efficient time signal processing.

[0007] The above purpose is achieved through the following technical solutions:

[0008] A time signal processing circuit based on a multiplication type interpolation circuit comprises three parts: a time signal processing circuit, a calibration circuit and a digital logic circuit, and realizes the conversion process of a time input signal to a digital output signal.

[0009] The time signal processing circuit includes n+1 levels of successive approximation time signal processing sub-circuits SAR TDC nTH SAR TDC n-1TH SAR TDC 1ST SAR TDC 0TH Each sub-SAR TDC module is cascaded, and each level of digital code is weighted by W. n 、W n-1 , W1, and W0 quantize the time quantity and complete the time-to-digital signal conversion in a pipeline manner. nTH The input terminal is the time input signal T P 、T N , whose phase difference can be expressed as the time quantity T res Each level of sub-SAR TDC outputs a digital code D <n:0>and the corresponding clock signal CLK <n:0>To the digital logic circuit, output the calibration signal CAL_IN to the calibration circuit.

[0010] The sub-SAR TDC circuit is a differential structure, divided into two paths, P and N, each path contains a multiplication type interpolation module MPI P 、MPI N , delay module BUFFP 1-3 BUFFN 1-3 , selector MUX P 、MUX N The sub-SAR TDC circuit includes digital logic units such as a time comparator TCOMP, a NAND gate, an OR gate, and an inverter. P The input terminal of the sub-SAR TDC is connected to the input signal T P , the output ends are connected to the delay module BUFFP 1-3 The MPI N The input terminal of the sub-SAR TDC is connected to the input signal T N , the output ends are connected to the delay module BUFFN 1-3 Delay module BUFFP 1-3 The outputs are OUTP1, OUTP2, and OUTP3; the delay module BUFFN 1-3 The outputs of MPI are OUTN1, OUTN2, and OUTN3. P 、MPI N Module, by Φ TB The two input terminals of the time comparator TCOMP are connected to the input signal T of the sub-SARTDC. P 、T N , the output signals are D and DB, and Φ T Controls the reset operation of the time comparator TCOMP. P The input is OUTP1, OUTP3, the control terminal is D, and the output is OUT P ;Selector MUX N Input is OUTN1, OUTN3, control terminal is DB, output is OUT N OUT P OUT N Connect to the input of the next-stage sub-SAR TDC. OUTP2 and OUTN2 are connected to the input of OR gate OR1, and the output of OR gate OR1 is PRO. The outputs D and DB of the comparator TCOMP are connected to NAND gate NAND1. The output of NAND gate NAND1 is READY, and READY and PRO are connected to OR gate OR2. The output of OR gate OR2 is the CLK signal, which is transmitted to the digital logic circuit as the output signal CLK of the sub-SARTDC. The input signal T P 、T N Connect inverter INV P 、INV N Input terminal, inverter INV P 、INV N The output end is connected to the input end of the OR gate OR3. The output end of the OR gate OR3 and the PRO signal are connected to the input end of the NAND gate NAND2. The output end of the NAND gate NAND2 is connected to the input end of the NAND gate OR3. T Connected to the input of inverter INV1, the output of inverter INV1 is Φ TB The sub-SAR TDC circuit outputs the comparison signal D and the clock signal CLK to the digital logic circuit to control it to perform digital code conversion.

[0011] The multiplication type interpolation module (MPI) includes inverters INV0, INV T 、INV B , variable delay modules BUFF0, BUFF2, buffers BUFF1, BUFF3, BUFF4, variable capacitor C T 、C B , reset switch S rst The input end of the inverter INV0 is connected to the input signal IN of the multiplication type interpolation module, and the output end is connected to the input end of the buffer BUFF4 and the input end of the variable delay module BUFF0. The output end of the buffer BUFF4 is connected to the inverter INV T The output of the variable delay module BUFF0 is connected to the inverter INV B Input terminal of the inverter INV T The output terminal and the variable capacitor C T The upper plates are connected to node T, and the inverter INV B The output terminal and the variable capacitor C B The lower plates are connected to node B. The variable capacitor C T Lower plate, C B Upper plate and reset switch S rst One end is commonly connected to the node M. The reset switch S rst The other end is connected to VSS, and the TB Control its closing and closing. The input end of the buffer BUFF1 is connected to the node T, and the output end is the OUT1 signal; the input end of the buffer BUFF3 is connected to the node B, and the output end is the OUT3 signal; the input end of the variable delay module BUFF2 is connected to the node M, and the output end is the OUT2 signal. The OUT1 signal, OUT2 signal, and OUT3 signal are the output signals of the multiplication type interpolation module. The circuit structure of the variable delay modules BUFF0 and BUFF2 includes but is not limited to a buffer with a variable power supply voltage, a variable bias voltage, a scheme for changing the number of cascaded delay units, a change in the size or number of transistors, etc. for the purpose of changing the delay. The variable capacitor C T 、C B The structure includes but is not limited to a scheme in which the capacitance between nodes T, M, and B is changed by unit capacitors having different numbers of series / parallel connections or different capacitance values ​​between nodes T, M, and B.

[0012] The modified structure of the multiplication type interpolation module, namely the multiplication type time amplification circuit, includes a buffer BUFF T BUFF B , BUFF1, BUFF3, variable delay module BUFF2, variable capacitor C T 、C B , reset switch S rst The buffer BUFF T BUFF B The input terminals are connected to the input signal T INP 、T INN The output end is connected to the buffer BUFF1 and BUFF3 at the nodes T and B respectively. The variable capacitor C T The upper plate is connected to the node T, and the lower plate is connected to the node M. The variable capacitor C B The upper plate is connected to node M, and the lower plate is connected to node B. The reset switch S rst One end is connected to the node M, and the other end is connected to the ground VSS. TB The variable delay module BUFF2 has its input connected to the node M and its output connected to the output signal OUT2. The outputs of the buffers BUFF1 and BUFF3 are connected to the output signals OUT1 and OUT3 respectively.

[0013] The calibration circuit can change voltages using analog modules such as LDOs, DLLs, and charge pumps, or it can control circuit components using digital codes using digital logic modules such as switched capacitors. The calibration circuit's input is connected to the CAL_IN output signal of the time signal processing circuit, and the output signal CAL_OUT is fed back to the time signal processing circuit to complete time domain calibration.

[0014] The digital logic circuit realizes the digital signal integration of the time input signal in different periods, and the output signal D of the time signal processing circuit is <n:0>、CLK <n:0>Control its work and obtain the synchronous output digital code DOUT within the same conversion cycle <n:0>.

[0015] The present invention discloses a time signal processing circuit based on a multiplying interpolation circuit that quantizes a time input signal and outputs it as a digital signal. The circuit utilizes a pipelined system to significantly increase conversion speed and alleviate the limiting relationship between conversion speed and resolution. Furthermore, the multiplying interpolation module has a simple structure and time-quantization reduction capabilities, thereby achieving high time quantization accuracy. The calibration circuit improves the conversion accuracy of the time domain circuit. Finally, a digital logic circuit integrates digital codes of different periods into a synchronized digital output, realizing a high-performance time signal processing circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Embodiments of the present invention are illustrated by way of practical examples and are not limited by the accompanying drawings. Similar reference numerals in the drawings may indicate similar components or modules. Components and circuit modules in the drawings are shown for simplicity and clarity and are not necessarily drawn to scale.

[0017] FIG1 is a structural diagram of a time signal processing system of the present invention.

[0018] FIG2 is a schematic diagram of the time signal processing circuit of the present invention.

[0019] FIG3 is a schematic diagram of the sub-SARTDC circuit principle of the present invention.

[0020] FIG4 is a schematic diagram showing the principle structure of a multiplication-type interpolation circuit according to the present invention.

[0021] FIG5 is a structural diagram of the calibration principle of the multiplication type interpolation circuit of the present invention.

[0022] FIG6 is a schematic diagram showing the principle structure of the multiplication type time amplifier circuit of the present invention. DETAILED DESCRIPTION

[0023] The present invention proposes a time signal processing circuit based on a multiplying interpolation circuit, showing its system structure and the circuit structure of each main module, including a time signal processing circuit, a multiplying interpolation circuit (MPI), a calibration circuit, and a digital logic circuit; showing an embodiment of the calibration of the multiplying interpolation circuit; showing a modified structure based on the multiplying interpolation circuit and an embodiment of the multiplying time amplification circuit.

[0024] Figure 1 is a structural diagram of the time signal processing system of the present invention, which includes a time signal processing circuit, a calibration circuit, and a digital logic circuit. The time signal processing circuit quantizes the time input signal and transmits the output signal to the calibration circuit and digital logic circuit. The calibration circuit implements the time signal calibration algorithm using a negative feedback mechanism, improving the accuracy of the time signal processing circuit and achieving a robust design. The digital logic circuit outputs the output signal of the time signal processing circuit in a digital code. Through the cooperation of these modules, the time signal processing is ultimately completed.

[0025] Figure 2 is a schematic diagram of the principle structure of the time signal processing circuit of the present invention. The time signal processing circuit is a successive approximation structure, which is composed of multiple sub-SAR TDCs in cascade, and completes the conversion of time signal to digital signal in a pipeline manner. P 、T N , the phase difference is the time margin T res , time margin T res The output signal CAL_IN of the time signal processing circuit is transmitted to the calibration circuit and fed back by the output signal CAL_OUT of the calibration circuit. The time signal processing circuit converts in a pipeline manner and outputs a digital signal D <n:0>For comparison results of different cycles, CLK <n:0>The digital logic circuit then integrates the data into a digital code output DOUT within the same cycle. <n:0>.

[0026] The working principle of the time signal processing circuit is as follows: the differential time signal T P 、T N Input to the sub-SAR TDC, compared by the time comparator, and the T P 、T N The weight W in the transmission path n 、W n-1 , W1, W0 increase / decrease the same amount of time, that is, change the time margin T res , after passing through each sub-SARTDC, the successive approximation quantization process in the time domain can be realized. nTH 、SARTDC n-1TH SAR TDC 1ST 、SARTDC 0TH The weight W n 、W n-1 W1, W0, and W1 also represent the weights of the comparison results in each sub-SAR TDC stage. To improve time domain conversion accuracy and achieve PVT robustness, a calibration scheme is implemented. The CAL_IN signal from the time signal processing circuit is transmitted to the calibration circuit to provide feedback to the sub-SAR TDC. Each sub-SAR TDC stage outputs the comparison result D and trigger clock CLK generated during the quantization process. The digital logic circuit then integrates the digital code from the successive approximation time signal processing circuit into a synchronized digital output.

[0027] Figure 3 is a schematic diagram of the sub-SAR TDC circuit principle of the present invention. The conversion principle of the sub-SAR TDC is: the differential time input signal T P 、T N The transmission is carried out along two independent paths, the two transmission paths are symmetrical to each other, and the time margin T res T P 、T N The phase difference of this circuit is obtained by multiplying the interpolation circuit MPI. P Get the time signals OUTP1, OUTP2, OUTP3, and use Φ TB Controlling MPI P Reset process. This circuit is multiplied by the interpolation circuit MPI N Get the time signals OUTN1, OUTN2, OUTN3, and use Φ TB Controlling MPI N Reset process. P 、T N Input to the time comparator TCOMP, which is a dynamic comparator structure, T Controls its reset process. D and DB are the comparison results of the time comparator TCOMP, which are output to the selector MUX P 、MUX N D controls the MUX P Select input signals OUTP1 and OUTP3 and output OUT P ;DB control MUX N Select the input signals OUTN1 and OUTN3 and output OUT N , and finally realize the addition and subtraction operations in the time domain.

[0028] The time quantization process is explained in detail using the P end as an example: T P After the multiplication type interpolation circuit MPI P , get three time output signals, connected delay module BUFFP 1-3 To compensate for the comparison delay of TCOMP, OUTP1 and OUTP3 are transmitted to the selector MUX after the time comparator TCOMP completes the comparison. P The time signals OUTP1, OUTP2, and OUTP3 are three square wave signals, and the phase of OUTP2 is located in the middle of the phases of OUTP1 and OUTP3. The time interval between OUTP1 and OUTP3 is the time quantization accuracy T of this level SAR TDC. W , which can be expressed as weight W n At this time, the time input T P It can be represented by OUTP2. Compared with OUTP2, OUTP1 can be regarded as subtracting T W / 2 delay, OUTP3 can be regarded as adding T W / 2 delay, to achieve addition and subtraction operations in the time domain. P Before T N Input, D is high level, DB is low level, selector MUX P Select OUTP3 from the input signals OUTP1 and OUTP3 and output it as OUT P , similarly, selector MUX N Select OUTN1 and output as OUT N . P Addition, T N Do subtraction, time margin T res Change T W ,This process fully demonstrates the addition and subtraction operation process of ,differential time signals, that is, the principle of successive approximation ,quantization in the time domain.

[0029] The reset process and clock generation process are completed by a series of logic units in the sub-SAR TDC circuit. The first is the trigger clock CLK of the comparison result. CLK is generated by the READY and PRO signals through the OR gate OR2. The READY signal is generated by the comparison results D and DB of TCOMP through the NAND gate NAND1, which indicates the end of the comparison process and can trigger the output of the comparison result. In order to avoid the failure of the comparison due to the long comparison time of TCOMP, the present invention designs a clock PRO that plays a protective role. The PRO clock is generated by OUTP2 and OUTN2 through the OR gate OR1. The second is the reset clock Φ of the time comparator TCOMP. T Input signal T P 、T N Through inverter INV P 、INV N And input to OR gate OR3, the output signal and PRO signal are input to NAND gate NAND2 to get Φ T After the sub-SAR TDC signal conversion is completed, the PRO signal becomes high level, Φ T Reset TCOMP. Finally, the reset clock Φ of the multiplication type interpolation circuit TB Φ TB By Φ T In summary, the modules of the sub-SAR TDC cooperate with each other to complete the conversion of the time signal.

[0030] Figure 4 shows the principle structure of the multiplying interpolation circuit of the present invention. This circuit is a key module in the overall time signal processing circuit, crucial for time domain resolution and conversion accuracy. The multiplying interpolation module provides time signal reduction, subdividing the input time signal into multiple, more closely spaced output time signals. Unlike traditional inverter-based interpolation circuits, the multiplying interpolation circuit of the present invention incorporates variable capacitors to further enhance time accuracy.

[0031] The working principle of the multiplication type interpolation circuit of the present invention is as follows: First, the reset switch S rst The input signal IN is transferred to the inverter INV0 and its phase is reversed. The output signal of INV0 is respectively transferred to the input of the buffer BUFF4 and the input of the variable delay module BUFF0. The reversed time signal is transferred to the inverter INV after passing through the buffer BUFF4. T ; After passing through the variable delay module BUFF0, it is transmitted to the inverter INV B At this time, the phase difference between the signals at nodes T and B is the delay difference t0 between the variable delay module BUFF0 and the buffer BUFF4. T 、INV B The output signal of the variable capacitor C T 、C B Charging and discharging, according to the principle of capacitor series connection, the voltage value of point M is between the voltage values ​​of points T and B. Then, the signals of nodes T, M, and B are output through buffers BUFF1, BUFF3 and variable delay module BUFF2, and the output signals are OUT1, OUT2, and OUT3. Finally, the reset switch S rst Close to clear the charge of node M.

[0032] The time reduction function of the multiplication type interpolation circuit of the present invention is realized based on the state response characteristics of the capacitor when charging and discharging. When the level of the node T changes, the variable capacitor C T 、C B It can be regarded as a whole and charged by the signal of node T. The voltage of node B changes with the signal of node T. After the delay t0, the inverter INV B The voltage of the driving node B changes at an accelerated rate. During this process, the signal at point M is always in the middle phase of the T and B signals, thus realizing the interpolation function. The phase difference between the T and B signals realizes the time reduction characteristic of the multiplication type interpolation circuit. The multiplication type interpolation circuit of the present invention can change the delay of the variable delay modules BUFF0 and BUFF2 to change the variable capacitor C T 、C B The size is calibrated to improve the time domain accuracy and achieve PVT robustness design.

[0033] Figure 5 is a possible schematic diagram of the calibration principle of the multiplication type interpolation circuit. To achieve the intermediate phase of OUT2 between OUT1 and OUT3, the delay of BUFF2 and the capacitance of the variable capacitor can be changed; to achieve high-precision time resolution, the delay of BUFF0 can be changed. The present invention can change the phase of OUT2 to the intermediate position by changing the power supply voltage VDD and bias voltage of BUFF2, or the number of module cascades, transistor size, etc. The calibration of the present invention is achieved by changing the capacitance between nodes T and M and the capacitance between nodes B and M. C0 can be regarded as a fixed capacitor, C CAL <m:0>is the m+1 calibration capacitor, which is controlled by switch S <m:0>and SN <m:0>Control its access mode. Switch S <m:0>and SN <m:0>The CAL_OUT output signal of the calibration circuit controls its on and off. For example: when S <m:0>All closed, SN <m:0>When both are turned off, the capacitance between nodes T and M is C0+(m+1)×C CAL , the capacitance between nodes B and M is C0. At this point, more charge is stored between nodes T and M than between nodes B and M, shifting the phase of OUT2 forward. This scheme allows the multiplying interpolation circuit to adjust its phase, placing OUT2 between the phases of OUT1 and OUT3.

[0034] The present invention can increase or decrease the phase difference between the T and B signals by changing the power supply voltage and bias voltage of BUFF0; by changing the power supply voltage of the overall multiplication-type interpolation circuit; or by changing the number of cascaded modules or transistor size in BUFF0. Reducing the delay of BUFF0 reduces the phase difference between OUT1 and OUT3, improving time quantization accuracy. The calibration scheme of the present invention includes but is not limited to the above circuit design scheme. Other circuit structures that modify the delay also fall within the calibration scheme of the present invention.

[0035] The calibration circuits of the present invention include, but are not limited to, analog calibration circuits that modify voltages, such as LDOs, DLLs, and charge pumps. They may also include digital calibration circuits that modify digital codes, such as digital logic modules like switched capacitors. The calibration circuit outputs a signal, CAL_OUT, which is fed back to the time signal processing circuit to complete time-domain calibration.

[0036] FIG6 is a diagram showing the principle structure of a multiplication type time amplifier circuit and a modified structure of a multiplication type interpolation circuit according to the present invention. INP 、T INN As a buffer BUFF T BUFF B The input signals are transmitted independently, and the BUFF0 delay of the multiplication type interpolation circuit is included in the two input signals T INP 、T INN The phase difference of the buffer BUFF T BUFF B The output signal of the variable capacitor C T 、C B Charge and discharge. Reset switch S rst By clock Φ TB The reset process of the control node M. The working principle of the multiplication type time amplifier circuit is similar to that of the multiplication type interpolation circuit. T 、C B Realize the function of reducing the time signal.

[0037] Of course, the above description is not a limitation of the present invention, and the present invention is not limited to the above examples. Changes, modifications, additions or substitutions made by technicians in this technical field within the essential scope of the present invention should also fall within the scope of protection of the present invention.

Claims

1. A time signal processing circuit based on a multiplication type interpolation circuit, characterized in that: include: The three parts of time signal processing circuit, calibration circuit and digital logic circuit realize the conversion process of time input signal to digital output signal; The time signal processing circuit comprises n+1 levels of successive approximation time signal processing sub-SAR TDCnTH, SAR TDCn-1TH, SAR TDC1ST, and SAR TDC0TH circuits; each sub-SAR TDC circuit module is cascaded, and each level of digital code quantizes the time quantity with weights Wn, Wn-1, W1, and W0, and completes the time-digital signal conversion in a pipeline manner; the input end of SAR TDCnTH is the time input signal TP and TN, and the phase difference is expressed as the time quantity T res Each sub-SAR TDC circuit outputs a digital code D <n:0>and the corresponding clock signal CLK <n:0> to the digital logic circuit, outputting a calibration signal CAL_IN to the calibration circuit;< / n:0> The calibration circuit changes the voltage through LDO, DLL, charge pump analog modules, or uses digital logic modules such as switch capacitors to control circuit devices through digital codes; the input end of the calibration circuit is connected to the CAL_IN output signal of the time signal processing circuit, and the output signal CAL_OUT is fed back to the time signal processing circuit to complete the calibration work in the time domain; The digital logic circuit realizes the digital signal integration of the time input signal in different periods, and the output signal D of the time signal processing circuit is <n:0>、CLK <n:0>Control its work and obtain the synchronous output digital code DOUT in the same conversion cycle <n:0> 。< / n:0> 2. A time signal processing circuit based on a multiplication type interpolation circuit according to claim 1, characterized in that: The sub-SAR TDC circuit is a differential structure, divided into two paths, P and N, each path contains a multiplication type interpolation module MPI P 、MPI N , delay module BUFFP 1-3 BUFFN 1-3 , selector MUX P 、MUX N The sub-SAR TDC circuit includes a time comparator TCOMP, a NAND gate, an OR gate, an inverter and other digital logic units; the MPI P The input terminal of the sub-SAR TDC is connected to the input signal T P , the output ends are connected to the delay module BUFFP 1-3 ; The MPI N The input terminal of the sub-SAR TDC is connected to the input signal T N , the output ends are connected to the delay module BUFFN 1-3 ; Delay module BUFFP 1-3 The outputs are OUTP1, OUTP2, OUTP3; the delay module BUFFN 1-3 The outputs are OUTN1, OUTN2, and OUTN3; Among them, MPI P 、MPI N Module, by Φ TB Control its reset work; the two input terminals of the time comparator TCOMP are respectively connected to the input signal T of the sub-SAR TDC P 、T N , the output signal is D, DB, by Φ T Control time comparator TCOMP reset work; the selector MUX P The input is OUTP1, OUTP3, the control terminal is D, and the output is OUT P ; Selector MUX N Input is OUTN1, OUTN3, control terminal is DB, output is OUT N OUT P ,OUT N The input end of the next-stage sub-SAR TDC is connected; the OUTP2 and OUTN2 are connected to the input end of the OR gate OR1, and the output end of the OR gate OR1 is PRO; the output ends D and DB of the comparator TCOMP are connected to the NAND gate NAND1; the output end of the NAND gate NAND1 is READY, and READY and PRO are connected to the OR gate OR2; the output end of the OR gate OR2 is the CLK signal, and is transmitted to the digital logic circuit as the output signal CLK of the sub-SAR TDC; the input signal T P 、T N Connect the inverter INV P 、INV N Input terminal, inverter INV P 、INV N The output end is connected to the input end of the OR gate OR3; the output end of the OR gate OR3 and the PRO signal are connected to the input end of the NAND gate NAND2, and the output end of the NAND gate NAND2 is Φ T Connected to the input of inverter INV1, the output of inverter INV1 is Φ TB The sub-SAR TDC circuit outputs the comparison signal D and the clock signal CLK to the digital logic circuit to control it to perform digital code conversion.

3. A time signal processing circuit based on a multiplication type interpolation circuit according to claim 1, characterized in that: The multiplication type interpolation module MPI comprises inverters INV0, INV T 、INV B , variable delay modules BUFF0, BUFF2, buffers BUFF1, BUFF3, BUFF4, variable capacitor C T , C B , reset switch S rst The inverter INV0 input terminal is connected to the input signal IN of the multiplication type interpolation module, and the output terminal is connected to the buffer BUFF4 input terminal and the variable delay module BUFF0 input terminal; the output terminal of the buffer BUFF4 is connected to the inverter INV T The variable delay module BUFF0 output terminal is connected to the inverter INV B Input terminal: the inverter INV T The output terminal and the variable capacitor C T The upper plates are connected to node T, and the inverter INV B The output terminal and the variable capacitor C B The lower plates are connected to node B; the variable capacitor C T Lower plate, C B Upper plate and reset switch S rst One end is connected to the node M; the reset switch S rst The other end is connected to VSS, and the TB Control its closing and closing; the input end of the buffer BUFF1 is connected to the node T, and the output end is the OUT1 signal; the input end of the buffer BUFF3 is connected to the node B, and the output end is the OUT3 signal; the input end of the variable delay module BUFF2 is connected to the node M, and the output end is the OUT2 signal; the OUT1 signal, OUT2 signal, and OUT3 signal are the output signals of the multiplication type interpolation module.

4. A time signal processing circuit based on a multiplication type interpolation circuit according to claim 3, characterized in that: The circuit structure of the variable delay modules BUFF0 and BUFF2 includes a buffer with a variable power supply voltage and a variable bias voltage, and changes the number of cascaded delay units and the size or number of transistors to change the delay.

5. The time signal processing circuit based on the multiplication type interpolation circuit according to claim 3, characterized in that: The variable capacitor C T , C B The structure includes unit capacitors with different numbers of series / parallel connections or different capacitance values ​​between nodes T, M, and B to change the capacitance between nodes T, M, and B.

6. The time signal processing circuit based on the multiplication type interpolation circuit according to claim 1, characterized in that: The modified structure of the multiplication type interpolation module, namely the multiplication type time amplification circuit, comprises a buffer BUFF T BUFF B , BUFF1, BUFF3, variable delay module BUFF2, variable capacitor C T , C B , reset switch S rst ; The buffer BUFF T BUFF B The input terminals are connected to the input signal T INP 、T INN The output end is connected to the buffer BUFF1 and BUFF3 respectively to the node T and B; the variable capacitor C T The upper plate is connected to the node T, and the lower plate is connected to the node M; the variable capacitor C B The upper plate is connected to node M, and the lower plate is connected to node B; the reset switch S rst One end is connected to node M, and the other end is connected to ground VSS. TB Control its closing and closing; the input end of the variable delay module BUFF2 is connected to the node M, and the output end is connected to the output signal OUT2; the output ends of the buffers BUFF1 and BUFF3 are connected to the output signals OUT1 and OUT3 respectively.

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