Enhanced field effect transistor and manufacturing method therefor

Abstract

The present application discloses an enhanced field effect transistor and a manufacturing method therefor. The enhanced field effect transistor comprises an epitaxial structure, an MIS / MOS gate structure, a source, and a drain; the epitaxial structure comprises at least one heterojunction; a charge carrier channel is formed in the heterojunction; a gate groove is formed in a gate region of the epitaxial structure; the groove bottom of the gate groove is located in a first semiconductor layer, and the opening of the gate groove is located in a second semiconductor layer; the charge carrier channel is separated by the gate groove; the MIS / MOS gate structure comprises a third semiconductor layer, a gate dielectric layer, and a gate that are sequentially stacked in a selected direction; when a forward voltage is applied to the gate, electrons are inversely generated in the third semiconductor layer; the charge carrier channels located on two sides of the gate groove are electrically connected by means of the electrons. The present application has a higher gate forward breakdown voltage and a higher threshold voltage.

Description

Enhancement mode field effect transistor and method for manufacturing the same

[0001] This application is based on and claims priority from the Chinese patent application filed on July 24, 2023 with application number 202310912208.X and application name “Enhancement Mode Field Effect Transistor and Its Preparation Method”. Technical Field

[0002] The present application relates to an enhancement mode field effect transistor and a preparation method thereof, and in particular to a group III nitride enhancement mode field effect transistor and a preparation method thereof, belonging to the technical field of semiconductor electrical devices. Background Art

[0003] Group III nitride semiconductors are known as third-generation semiconductors, with advantages such as wide bandgap, good chemical stability, and high breakdown voltage. High electron mobility transistors (HEMTs) composed of heterostructures such as AlGaN / GaN have the advantages of high electron concentration and mobility, and perform excellently in high frequency, high voltage resistance, and low on-resistance. They can be used as core components in various power conversion systems and have broad prospects in power supply applications such as consumer electronics, 5G base stations, and servers.

[0004] Generally, in practical applications, GaN enhancement-mode HEMTs (HEMTs) with threshold voltages greater than 0V offer inherent advantages in terms of fail-safety and circuit design, making them more suitable for industrial transformation and commercial applications. Certain gate technologies, such as p-GaN gates, recessed gates, and ion-implanted gates, can elevate the energy band of the GaN channel layer to deplete the two-dimensional electron gas (2DEG), thereby achieving enhancement mode. In practical circuits, during rapid high-to-low switching of the gate voltage, the presence of inductive loads can cause gate voltage oscillation and overshoot, requiring the gate to possess high breakdown and threshold voltages. High-frequency switching requires synchronized high-frequency response for carrier transport within the gate stack structure to minimize dynamic threshold voltage drift. Therefore, practical applications place extremely high demands on the performance and reliability of GaN enhancement-mode HEMTs, crucial for the industrialization of GaN HEMTs or field-effect transistors (FETs). Currently, technologically advanced p-GaN gate enhancement-mode HEMTs have begun to achieve industrial transformation and commercial application.

[0005] The common gate structure is a "metal / p-GaN / AlGaN / GaN" stack structure, as shown in Figure 1A. In Figure 1A, 001 is the substrate, 002 is the AlN / AlGaN transition layer, 003 is the high-resistance (Al)GaN voltage-resistant layer, 004 is the (Al)GaN conductive channel layer, 005 is the AlGaN barrier layer, 006 is the p-type (Al)GaN layer, 007 is the gate contact metal, 009 is the source contact metal, and 010 is the drain contact metal. The gate metal layer is mostly deposited by evaporation, sputtering and other processing methods, and the work function is in the range of 4 to 6 eV, such as Ti, Ni, Pd, etc. The p-GaN / AlGaN / GaN stack is mostly grown epitaxially by MOCVD. The p-GaN layer is almost uniformly doped with Mg, with a doping concentration of 1 to 3×10 19 / cm 3 , a single-layer structure with a thickness of 70 to 150 nm. The AlGaN layer is a uniform single-layer structure with an Al component of 10% to 30% and a thickness of 10 to 30 nm, and the GaN channel layer is a single-layer structure with a thickness of 50 to 500 nm. It should be pointed out that the p-GaN E-HEMT prepared by this conventional method usually can only raise the conduction band at the AlGaN / GaN interface from the Fermi level by no more than 2 V, so the threshold voltage of the actual device is relatively low, with a maximum of only between 1 and 2 V.

[0006] As shown in Figure 1A / B, the gate of the metal / p-GaN / AlGaN / GaN stack can be equivalent to a "Schottky junction" (JS) composed of metal / p-GaN and a "double-sided heterojunction" (JP) composed of p-GaN / AlGaN / GaN. When the gate is working in the forward direction, the Schottky junction is in a reverse bias state and bears most of the voltage. Since the effective acceptor concentration of the surface p-GaN is usually 10 19 cm -3 There is a very large electric field in the Schottky depletion region. The tunneling and acceleration of carriers under high electric fields will cause the original defects in the region to be activated or new defects to form. The greatly increased defect state density will cause the Schottky junction to S Failure. When dynamically turned on, the energy band barrier between p-GaN / AlGaN (usually around 0.2-0.4 eV) blocks carrier injection into the GaN channel, while the reverse-biased Schottky junction also blocks carriers from entering the p-GaN from the metal. As a result, carriers are depleted and / or accumulated in the metal / p-GaN Schottky junction depletion region and the p-GaN / AlGaN interface, causing the gate dynamic threshold voltage to drift (usually up to ±2 V), which brings great instability to the gate control.

[0007] In summary, the gates of existing III-nitride enhanced-mode HEMTs are mostly metal / p-GaN / AlGaN / GaN stack structures. The p-GaN epitaxial growth uses Mg doping as an acceptor to provide holes. However, this structure has at least the following drawbacks:

[0008] First, the gate forward breakdown voltage of the above-mentioned prior art is low. Since the acceptor Mg concentration in p-GaN is very high (usually around 10 19 cm -3 The self-built electric field strength of the metal / p-GaN Schottky junction is already very large (on the order of MV / cm). Therefore, when a positive voltage is further applied to the p-GaN gate, the metal / p-GaN Schottky junction is reverse biased, and the electric field is further enhanced. Extreme carrier transport behaviors such as tunneling and impact ionization are prone to occur under strong electric fields, causing the Schottky junction to breakdown. The gate breakdown voltage of a conventional p-GaN E-HEMT is typically no higher than 15V, and the normal operating gate voltage does not exceed 6V. Therefore, this poses a severe challenge to the device's gate drive.

[0009] Second, the threshold voltage of the above-mentioned prior art is low. The threshold voltage of a p-GaN E-HEMT is primarily determined by the p-GaN / AlGaN / GaN stack structure. Factors such as the effective acceptor Mg doping concentration in the p-GaN, the thickness of the AlGaN barrier layer, and the Al composition have a significant impact on the device's threshold voltage. Due to the polarization effect between AlGaN / GaN, even highly Mg-doped p-GaN can only raise the conduction band at the AlGaN / GaN interface by 1-2V from the Fermi level. Therefore, the threshold voltage of traditional p-GaN E-HEMTs is typically no higher than 2V, and actual commercial products are mostly between 1.1 and 1.5V. In actual circuit applications, due to parasitic effects, voltage and current oscillations are easily generated. The low threshold voltage can cause the device to malfunction, resulting in power loss and even circuit damage.

[0010] Third, the above-mentioned prior art suffers from significant dynamic threshold voltage drift. During dynamic switching, the gate carrier transport behavior is affected by the p-GaN gate band structure and defect states, resulting in a localized accumulation of net positive or negative charge on the gate of a conventional p-GaN E-HEMT. This causes the turn-on voltage of the 2DEG in the GaN channel to shift from that in the static state, typically manifesting as a dynamic threshold voltage drift. Furthermore, due to the poor physical performance matching between the Schottky and PN junctions that constitute the p-type gate, the dynamic threshold voltage drift of conventional p-GaN E-HEMTs varies significantly with operating voltage, operating temperature, and other factors. As p-GaN gate enhancement-mode HEMTs (p-GaN E-HEMTs), which are gradually moving towards commercial applications, still suffer from significant deficiencies in gate performance and reliability, hindering their adoption in ultra-large-scale production and high-reliability market applications. This is extremely unfavorable for device application in industrial electronics, automotive electronics, and other fields requiring high stability and reliability.

[0011] Application Contents

[0012] The main purpose of this application is to provide an enhancement mode field effect transistor with high gate forward withstand voltage, high threshold voltage, and low dynamic threshold voltage drift, and a preparation method thereof, so as to overcome the deficiencies in the prior art.

[0013] To achieve the aforementioned application objectives, the technical solutions adopted in this application include:

[0014] On one hand, the present application provides an enhancement mode field effect transistor, comprising an epitaxial structure, a MIS / MOS gate structure, a source electrode, and a drain electrode.

[0015] The epitaxial structure includes at least one heterojunction, the heterojunction including a first semiconductor layer and a second semiconductor layer stacked along the selected direction, a carrier channel formed at the interface between the first semiconductor layer and the second semiconductor layer, the source and the drain being arranged in the ohmic region of the epitaxial structure and electrically connected to the carrier channel; a gate region of the epitaxial structure is provided with a gate groove, the bottom of the gate groove being located in the first semiconductor layer and the opening being located in the second semiconductor layer, the carrier channel being blocked by the gate groove;

[0016] The MIS / MOS gate structure includes a third semiconductor layer, a gate dielectric layer and a gate stacked in sequence along the selected direction, the third semiconductor layer being at least arranged in the gate groove. The MIS / MOS gate structure has a field effect on the regulation of the carrier channel. When a forward voltage is applied to the gate, electrons are inverted and generated in the third semiconductor layer, and the carrier channels located on both sides of the gate groove are electrically connected via the electrons.

[0017] On the other hand, the present application also provides a method for preparing an enhancement mode field effect transistor, comprising:

[0018] Providing an epitaxial structure, the epitaxial structure comprising at least one heterojunction, the heterojunction comprising a first semiconductor layer and a second semiconductor layer stacked along the selected direction, a carrier channel formed at an interface between the first semiconductor layer and the second semiconductor layer;

[0019] removing the entire second semiconductor layer and a portion of the first semiconductor layer located in the gate region of the epitaxial structure, thereby forming a gate groove, wherein the carrier channel is isolated by the gate groove;

[0020] A third semiconductor layer, a gate dielectric layer, and a gate are sequentially stacked in at least the gate region of the epitaxial structure, thereby forming a MIS / MOS gate structure. The MIS / MOS gate structure has a field effect on the regulation of the carrier channel. When a forward voltage is applied to the gate, electrons are inverted and generated in the third semiconductor layer, and the carrier channels located on both sides of the gate groove are electrically connected via the electrons.

[0021] A source electrode and a drain electrode are formed in the ohmic region of the epitaxial structure, and the source electrode and the drain electrode are electrically connected to the carrier channel.

[0022] Compared with the prior art, the advantages of this application include:

[0023] 1) The present application provides a III-nitride enhancement mode field effect transistor (FET) having a higher gate forward breakdown voltage;

[0024] 2) The present application provides a III-nitride enhanced field-effect transistor (FET) having a higher threshold voltage, which can meet the threshold voltage requirements of power electronic devices in more application scenarios;

[0025] 3) The present application provides a III-nitride enhanced field effect transistor (FET) with smaller dynamic threshold voltage drift and better device stability. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] FIG1A is a schematic structural diagram of a conventional enhancement-mode HEMT;

[0027] FIG1B is a schematic diagram of the energy band structure of a conventional enhancement-mode HEMT;

[0028] FIG2 is a schematic structural diagram of a depletion-mode HEMT epitaxial structure provided in a typical embodiment of the present application;

[0029] FIG3 is a schematic structural diagram of a HEMT epitaxial structure in which a gate region is removed to form a gate recess in a typical embodiment of the present application;

[0030] FIG4 is a schematic diagram of the structure after a secondary epitaxial p-type semiconductor layer or an unintentional Mg-doped semiconductor layer is grown on the surface of a HEMT epitaxial structure in a typical embodiment of the present application;

[0031] FIG5 is a schematic diagram of a FET structure after depositing a gate dielectric layer in a typical embodiment of the present application;

[0032] FIG6 is a schematic diagram of a FET structure after source / drain electrodes are prepared in a typical embodiment of the present application;

[0033] FIG7 is a schematic structural diagram of an enhancement mode field effect transistor provided in a typical embodiment of the present application;

[0034] FIG8 is a schematic structural diagram of another enhancement mode field effect transistor provided in a typical embodiment of the present application;

[0035] FIG9 is a schematic structural diagram of another enhancement mode field effect transistor provided in a typical embodiment of the present application;

[0036] FIG10 is a schematic structural diagram of another enhancement mode field effect transistor provided in a typical embodiment of the present application;

[0037] FIG11 is a diagram showing the energy band structure of another enhancement mode field effect transistor at different gate voltages provided in a typical embodiment of the present application;

[0038] FIG12 is a graph showing static and dynamic transfer characteristics of another enhancement mode field effect transistor provided in a typical implementation case of the present application. DETAILED DESCRIPTION

[0039] In view of the shortcomings of the existing technology, the applicant of this case has proposed the technical solution of this application after long-term research and extensive practice. The following will further explain this technical solution, its implementation process and principles.

[0040] On one hand, the present application provides an enhancement mode field effect transistor, comprising an epitaxial structure, a MIS / MOS gate structure, a source electrode, and a drain electrode.

[0041] The epitaxial structure includes at least one heterojunction, the heterojunction including a first semiconductor layer and a second semiconductor layer stacked along the selected direction, a carrier channel formed at the interface between the first semiconductor layer and the second semiconductor layer, the source and the drain being arranged in the ohmic region of the epitaxial structure and electrically connected to the carrier channel; a gate region of the epitaxial structure is provided with a gate groove, the bottom of the gate groove being located in the first semiconductor layer and the opening being located in the second semiconductor layer, the carrier channel being blocked by the gate groove;

[0042] The MIS / MOS gate structure includes a third semiconductor layer, a gate dielectric layer and a gate stacked in sequence along the selected direction, the third semiconductor layer being at least arranged in the gate groove. The MIS / MOS gate structure has a field effect on the regulation of the carrier channel. When a forward voltage is applied to the gate, electrons are inverted and generated in the third semiconductor layer, and the carrier channels located on both sides of the gate groove are electrically connected via the electrons.

[0043] It should be noted that, under zero bias, the carrier type of the semiconductor channel below the gate is opposite to the carrier type of the semiconductor channel in the non-gate region.

[0044] Furthermore, the third semiconductor layer includes at least one p-type semiconductor layer and / or at least one unintentionally doped semiconductor layer having acceptor or acceptor-like defects.

[0045] Furthermore, the third semiconductor layer comprises two or more p-type semiconductor layers or two or more unintentionally doped semiconductor layers having acceptor or acceptor-like defects, which are made of different materials.

[0046] It should be noted that the two layers of p-type semiconductors can be a p-type AlGaN / GaN double-layer structure. When the p-type semiconductor is inverted, the formed electrons can be confined in the potential well formed by AlGaN / GaN, thereby improving the mobility and reducing the resistance of the gate region. When two or more layers of unintentionally doped semiconductor layers with acceptor or acceptor-like defects are set, the effect is basically the same.

[0047] Furthermore, the p-type semiconductor layer is doped with Mg, and the Mg doping concentration of the p-type semiconductor layer is less than 1×10 20 cm -3 .

[0048] Furthermore, the Mg doping concentration of the p-type semiconductor layer is 1×10 15 cm -3 ~1×10 20 cm -3 , preferably 5×10 17 cm -3 ~1×10 19 cm -3 .

[0049] Furthermore, the Mg element in the p-type semiconductor layer is uniformly distributed, linearly distributed, or gradually distributed.

[0050] Furthermore, the material of the p-type semiconductor layer includes p-type group III nitride.

[0051] Furthermore, the material of the p-type semiconductor layer includes, but is not limited to, p-GaN, p-AlGaN, p-AlInGaN, p-InGaN, p-AlInN or p-(Al, In)GaN.

[0052] Furthermore, the concentration of acceptor or acceptor-like defects in the unintentionally doped semiconductor layer is 1×10 15 cm -3 In the above, the unintentionally doped semiconductor layer is in a high resistivity state.

[0053] Furthermore, the material of the unintentionally doped semiconductor layer includes unintentionally Mg-doped Group III nitride.

[0054] Furthermore, the material of the unintentionally doped semiconductor layer includes, but is not limited to, unintentionally Mg-doped GaN, AlGaN, AlInGaN, InGaN, AlInN or (Al, In)GaN.

[0055] It should be noted that the main difference between the unintentionally Mg-doped Group III nitride in the third semiconductor layer and the unintentionally doped Group III nitride used as the channel layer is that the unintentionally Mg-doped Group III nitride has acceptor or acceptor-type defects and presents a high-resistance state, while the unintentionally doped Group III nitride used as the channel layer is usually weakly n-type.

[0056] Furthermore, the third semiconductor layer is arranged in the gate region of the epitaxial structure, or the third semiconductor layer is arranged in the gate region of the epitaxial structure and in a region between the gate region and the ohmic region.

[0057] Furthermore, the gate dielectric layer is provided in the gate region of the epitaxial structure and in the region between the gate region and the ohmic region.

[0058] Furthermore, the material of the gate dielectric layer includes, but is not limited to, Al2O3, HfO2, Si3N4 or SiO2.

[0059] Furthermore, the thickness of the gate dielectric layer is 5-100 nm.

[0060] Furthermore, the epitaxial structure includes two or more heterojunctions stacked along the selected direction, and the bottom of the gate groove is located in the first semiconductor layer of the bottommost heterojunction.

[0061] Furthermore, the materials of the first semiconductor layer and the second semiconductor layer both include Group III nitride.

[0062] Furthermore, the material of the first semiconductor layer and the second semiconductor layer includes GaN, AlGaN, AlInGaN, InGaN, AlInN or (Al, In)GaN, but is not limited thereto.

[0063] Furthermore, the epitaxial structure further includes a high resistance and voltage-resistant layer and a transition layer, the heterojunction is arranged on the high resistance and voltage-resistant layer along the selected direction, and the high resistance and voltage-resistant layer is arranged on the transition layer.

[0064] Furthermore, the materials of the high-resistance voltage layer and the transition layer both include group III nitride.

[0065] On the other hand, the present application also provides a method for preparing an enhancement mode field effect transistor, comprising:

[0066] Providing an epitaxial structure, the epitaxial structure comprising at least one heterojunction, the heterojunction comprising a first semiconductor layer and a second semiconductor layer stacked along the selected direction, a carrier channel formed at an interface between the first semiconductor layer and the second semiconductor layer;

[0067] removing the entire second semiconductor layer and a portion of the first semiconductor layer located in the gate region of the epitaxial structure, thereby forming a gate groove, wherein the carrier channel is isolated by the gate groove;

[0068] A third semiconductor layer, a gate dielectric layer, and a gate are sequentially stacked in at least the gate region of the epitaxial structure, thereby forming a MIS / MOS gate structure. The MIS / MOS gate structure has a field effect on the regulation of the carrier channel. When a forward voltage is applied to the gate, electrons are inverted and generated in the third semiconductor layer, and the carrier channels located on both sides of the gate groove are electrically connected via the electrons.

[0069] A source electrode and a drain electrode are formed in the ohmic region of the epitaxial structure, and the source electrode and the drain electrode are electrically connected to the carrier channel.

[0070] Furthermore, the third semiconductor layer includes at least one p-type semiconductor layer and / or at least one unintentionally doped semiconductor layer having acceptor or acceptor-like defects.

[0071] Furthermore, the third semiconductor layer comprises two or more p-type semiconductor layers or two or more unintentionally doped semiconductor layers having acceptor or acceptor-like defects, which are made of different materials.

[0072] Furthermore, the p-type semiconductor layer is doped with Mg, and the Mg doping concentration of the p-type semiconductor layer is less than 1×10 20 cm -3 .

[0073] Furthermore, the Mg doping concentration of the p-type semiconductor layer is 1×10 15 cm -3 ~1×10 20 cm -3 , preferably 5×10 17 cm -3 1×10 19 cm -3 .

[0074] Furthermore, the material of the p-type semiconductor layer includes p-type group III nitride.

[0075] Furthermore, the material of the p-type semiconductor layer includes, but is not limited to, p-GaN, p-AlGaN, p-AlInGaN, p-InGaN, p-AlInN or p-(Al, In)GaN.

[0076] Furthermore, the concentration of acceptor or acceptor-like defects in the unintentionally doped semiconductor layer is 1×10 15 cm -3 In the above, the unintentionally doped semiconductor layer is in a high resistivity state.

[0077] Furthermore, the concentration of acceptor or acceptor-like defects in the unintentionally doped semiconductor layer is 1×10 15 cm -3 ~1×10 20 cm -3 , preferably 5×10 17 cm -3 ~1×10 19 cm -3 .

[0078] Furthermore, the material of the unintentionally doped semiconductor layer includes unintentionally Mg-doped Group III nitride.

[0079] Furthermore, the material of the unintentionally doped semiconductor layer includes, but is not limited to, unintentionally Mg-doped GaN, AlGaN, AlInGaN, InGaN, AlInN or (Al, In)GaN.

[0080] Furthermore, the third semiconductor layer is arranged in the gate region of the epitaxial structure, or the third semiconductor layer is arranged in the gate region of the epitaxial structure and in a region between the gate region and the ohmic region.

[0081] Furthermore, the gate dielectric layer is provided in the gate region of the epitaxial structure and in the region between the gate region and the ohmic region.

[0082] Furthermore, the material of the gate dielectric layer includes, but is not limited to, Al2O3, HfO2, Si3N4 or SiO2.

[0083] Furthermore, the thickness of the gate dielectric layer is 5-100 nm.

[0084] Furthermore, the epitaxial structure includes two or more heterojunctions stacked along the selected direction, and the bottom of the gate groove is located in the first semiconductor layer of the bottommost heterojunction.

[0085] Furthermore, the materials of the first semiconductor layer and the second semiconductor layer both include Group III nitride.

[0086] Furthermore, the material of the first semiconductor layer and the second semiconductor layer includes GaN, AlGaN, AlInGaN, InGaN, AlInN or (Al, In)GaN, but is not limited thereto.

[0087] The technical solution, its implementation process and principles will be further explained below in conjunction with the accompanying drawings and specific implementation cases. Unless otherwise specified, the semiconductor epitaxial growth process and its equipment, lithography and etching process and its equipment, surface repair process, annealing process and its equipment, metal deposition process and its equipment, IV testing equipment and various reagents used in the embodiments of the present application are all known to those skilled in the art, and their specific process parameters and process equipment models are not limited here.

[0088] Referring to FIG. 2 to FIG. 7 , in some specific embodiments, a method for preparing a III-nitride enhancement mode field effect transistor (FET) may include the following steps:

[0089] 1) A transition layer 102, a high-resistance voltage layer 103, a channel layer (i.e., the aforementioned first semiconductor layer, hereinafter the same) 104, and a barrier layer (i.e., the aforementioned second semiconductor layer, hereinafter the same) 105 are sequentially formed on a substrate 101 to form a depletion-mode HEMT epitaxial wafer, as shown in FIG2 .

[0090] Specifically, the transition layer 102 may be an AlN / AlGaN transition layer, the high resistance and voltage-resistant layer 103 may be a high resistance (Al)GaN voltage-resistant layer, the conductive channel layer 104 may be an (Al)GaN conductive channel layer, and the barrier layer 105 may be an AlGaN barrier layer.

[0091] 2) The gate region of the depletion-mode HEMT epitaxial wafer is patterned by photolithography, and then the barrier layer 105 and part of the channel layer 104 in the gate region are removed by dry etching or other methods to form a gate groove, as shown in FIG3 .

[0092] 3) The etched surface of the depletion-mode HEMT epitaxial wafer is subjected to certain treatments (such as wet etching, heat treatment, decomposition, etc.), and then a p-type semiconductor layer or an unintentionally Mg-doped semiconductor layer 106 is secondary epitaxially grown on the surface of the depletion-mode HEMT epitaxial wafer, as shown in FIG. 4 .

[0093] Specifically, the thickness of the p-type semiconductor layer or the unintentionally Mg-doped semiconductor layer 106 having acceptor or acceptor-like defects is 15-16 nm.

[0094] Specifically, the p-type semiconductor layer is doped with Mg, and the Mg doping concentration of the p-type semiconductor layer is less than 1×10 20 cm -3 Preferably, the Mg doping concentration of the p-type semiconductor layer is 1×10 15 cm -3 ~1×10 20 cm -3 , preferably 5×10 17 cm -3 ~1×10 19 cm -3 For example, the Mg doping concentration of the p-type semiconductor layer increases from 5×10 17 cm -3 Gradient increased to 1×10 19 cm -3 The material of the p-type semiconductor layer includes p-GaN, p-AlGaN, p-AlInGaN, p-InGaN, p-AlInN or p-(Al, In)GaN, etc.

[0095] Specifically, the concentration of acceptor or acceptor-like defects in the unintentional Mg-doped semiconductor layer having acceptor or acceptor-like defects is 1×10 15 cm -3 The concentration of acceptor or acceptor-like defects in the unintentional Mg-doped semiconductor layer having acceptor or acceptor-like defects is 1×10 15 cm -3 ~1×10 20 cm -3 , preferably 5×10 17 cm -3 ~1×10 19 cm -3 Furthermore, the unintentional Mg-doped semiconductor layer having acceptor or acceptor-like defects is in a high resistivity state, and the material of the unintentional Mg-doped semiconductor layer having acceptor or acceptor-like defects includes unintentional Mg-doped GaN, AlGaN, AlInGaN, InGaN, AlInN or (Al, In)GaN, etc.

[0096] 4) Depositing a gate dielectric layer 107 on the p-type semiconductor layer or the unintentionally Mg-doped semiconductor layer 106 having acceptor or acceptor-like defects, as shown in FIG5 .

[0097] Specifically, the thickness of the gate dielectric layer 107 is 5-100 nm, and the material of the gate dielectric layer 107 includes Al 2 O 3 , HfO 2 , Si 3 N 4 or SiO 2 .

[0098] 5) Etching the source and drain regions to expose the channel layer 104 , depositing stacked metals in the source and drain regions respectively, and annealing the stacked metals to form the source 108A and the drain 108B, as shown in FIG6 .

[0099] 6) A gate metal is deposited on the gate dielectric layer 107 in the gate region to form a gate 109. The p-type semiconductor layer or the unintentionally Mg-doped semiconductor layer 106, the gate dielectric layer 107 and the gate 109 form a MOS gate structure, thereby obtaining a MOS gate FET, as shown in FIG7 .

[0100] It should be noted that the above solution may also include more subsequent device processing processes, such as depositing interconnect metal, preparing field plate structures, etc. In addition, the order of preparing the source 108A / drain 108B and gate 109 in the above solution can be changed according to the actual process, or even moved to other steps.

[0101] Specifically, in some other more specific embodiments, in step 4), the first p-type semiconductor layer or unintentional Mg-doped semiconductor layer 106A and the second p-type semiconductor layer or unintentional Mg-doped semiconductor layer 106B can be epitaxially grown in sequence to form p-type semiconductor layers or unintentional Mg-doped semiconductor layers. The materials of the first p-type semiconductor layer or unintentional Mg-doped semiconductor layer 106A and the second p-type semiconductor layer or unintentional Mg-doped semiconductor layer 106B are different. The thickness of the first p-type semiconductor layer or unintentional Mg-doped semiconductor layer 106A is approximately 10 nm, and the thickness of the second p-type semiconductor layer or unintentional Mg-doped semiconductor layer 106B is approximately 5 nm. In this embodiment, the first p-type semiconductor layer or unintentional Mg-doped semiconductor layer 106A, the second p-type semiconductor layer or unintentional Mg-doped semiconductor layer 106B, the gate dielectric layer 107, and the gate 109 form a MIS gate structure. The resulting MIS gate FET is shown in FIG8 .

[0102] Specifically, in some other more specific embodiments, in step 4), the p-type semiconductor layer or the unintentional Mg-doped semiconductor layer 106 is formed only in the gate region, or after the p-type semiconductor layer or the unintentional Mg-doped semiconductor layer 106 is formed, the p-type semiconductor layer or the unintentional Mg-doped semiconductor layer 106 outside the non-gate region is etched away, and the structure of the finally formed III-nitride enhancement field effect transistor (FET) is shown in Figure 9.

[0103] Specifically, in some other more specific implementation schemes, in step 1), a transition layer 102, a high-resistance voltage layer 103, a first channel layer 104A, a first barrier layer 105A, a second channel layer 104B, and a second barrier layer 105B are sequentially formed on a substrate 101 to form a depletion-mode HEMT epitaxial wafer. Accordingly, the bottom of the gate trench is located within the first channel layer 104A. The structure of the ultimately formed III-nitride enhancement-mode field-effect transistor (FET) is shown in FIG. 10 .

[0104] The energy band structure of the III-nitride enhancement mode field effect transistor (FET) at different gate voltages is shown in FIG11 .

[0105] The present application provides a III-nitride enhancement-mode field-effect transistor (FET) with a higher gate forward breakdown voltage. The novel GaN enhancement-mode FET proposed in the present application has an electrically insulating gate dielectric layer (preferably 5 to 100 nm) between the gate metal and the p-type semiconductor layer or the unintentionally Mg-doped semiconductor layer. This dielectric layer is typically made of Al2O3, HfO2, etc. deposited by atomic layer deposition (ALD), or Si3N4 or SiO2 deposited by LPCVD. These deposited gate dielectric layers are of high quality and have a strong breakdown electric field, thus being able to withstand very high operating voltages (above 20V). Consequently, the MIS / MOS gate structure fabricated with these dielectric layers has a high breakdown voltage.

[0106] The present application provides a III-nitride enhancement-mode field-effect transistor (FET) with a higher threshold voltage. In the novel MIS / MOS gate structure proposed in this application, the Fermi level of p-GaN is typically within 1.0 eV above the valence band, and is even pinned to the position of the Mg impurity (EV+ to 0.15 eV). The band gap of GaN reaches 3.4 eV, so the voltage required to force p-GaN to invert is relatively high (usually above 2.5 V). As a result, the threshold voltage can reach 2.4 to 3.3 V, meeting the threshold voltage requirements of power electronic devices in multiple application scenarios.

[0107] The present application provides a III-nitride enhanced field effect transistor (FET) with smaller dynamic threshold voltage drift. Since the inversion electrons in p-GaN are induced by the field effect, there is no problem that the 2DEG concentration of the channel under the gate of the traditional p-GaN E-HEMT is seriously affected by the gate carrier transport behavior. In addition, since the inversion electrons are minority carriers in p-GaN and have a very short lifetime (ps level), it is also difficult for the net charge accumulation effect to occur. Therefore, during the fast switching process, the inversion electrons in the p-GaN channel in the gate region can respond quickly and produce a very small threshold voltage drift, and the device has better stability.

[0108] When an unintentionally doped semiconductor layer having acceptor or acceptor-like defects is used alone as the third semiconductor layer, the mechanism and effect are substantially the same as when a p-type semiconductor layer is used alone as the third semiconductor layer.

[0109] Example 1

[0110] A method for preparing a group III nitride enhancement mode field effect transistor (FET) may include the following steps:

[0111] 1) Growing a depletion-mode HEMT (D-HEMT) epitaxial wafer on a substrate.

[0112] Specifically include: using metal organic vapor deposition (MOCVD) and other methods, on Si <111> A 600nm AlN / AlGaN transition layer, a 4μm C-doped Al 0.07 Ga 0.93 N high resistance layer, 300nm high quality low electron concentration unintentionally doped GaN layer, 40nmAl 0.20 Ga 0.80 The N barrier layer forms a two-dimensional electron gas with a sheet resistance of 350Ω / □ and a concentration of 1.0×10 13 c m -3 , mobility is ~1800cm 2 V -1 s -1 AlGaN / GaN heterojunction depletion-mode HEMT epitaxial wafer.

[0113] 2) Forming a gate groove in the gate region of the depletion-mode HEMT epitaxial wafer.

[0114] Specifically, the gate region of the depletion-mode HEMT epitaxial wafer is patterned using a photoresist as a mask, and all the Al2O3 in the gate region is etched away at a low speed in an inductively coupled plasma (ICP) etching device. 0.20 Ga 0.80N barrier layer and about 8nm of unintentionally doped GaN layer to form the gate groove;

[0115] The photoresist was removed using organic cleaning methods such as acetone, and the depth of the gate groove was found to be 47-48nm.

[0116] After using piranha solution to remove residual organic matter, the depletion-mode HEMT epitaxial wafer with gate grooves was placed in tetramethylammonium hydroxide and heated for a certain period of time, and then transferred to hydrofluoric acid buffer (BOE) for immersion to remove surface oxides and surface silicon impurities.

[0117] 3) Forming a MOS gate structure, source and drain on a depletion-mode HEMT epitaxial wafer.

[0118] Specifically, the processed depletion-mode HEMT epitaxial wafer is reloaded into a metal organic chemical vapor deposition (MOCVD) device, and the temperature is raised to 900°C. After a period of time, Ga source, NH3, N2, Cp2Mg, etc. are introduced to form a p-GaN layer on the surface of the depletion-mode HEMT epitaxial wafer. The thickness of the p-GaN layer is 15 to 16 nm, and the Mg concentration increases from 5×10 17 cm -3 Gradient increased to 1×10 19 cm -3 ;

[0119] After epitaxial growth of the p-GaN layer, the atmosphere in the MOCVD furnace was switched to N2, and the temperature was adjusted to 800°C. After a period of holding, the temperature was lowered to room temperature.

[0120] The depletion-mode HEMT epitaxial wafer was removed and placed in an atomic layer deposition (ALD) device to deposit a 20nm Al2O3 layer on the p-GaN layer.

[0121] Then the source and drain regions (ohmic regions) are patterned by photolithography, and the Al2O3 layer, p-GaN layer and Al2O3 layer located in the source and drain regions are etched away in an ICP device. 0.20 Ga 0.80 N barrier layer, a layer of Ti / Al / Ti / Au = 20 / 130 / 50 / 150nm stack metal is deposited in the source and drain regions, and then rapidly annealed in N2 atmosphere at 890℃ for 30 s Then, the source and drain electrodes are prepared into ohmic contacts;

[0122] A layer of Ti / Au = 20 / 200nm stacked metal is deposited in the gate region, and a MOS gate structure is formed after rapid annealing at 500°C for 60s in an N2 atmosphere, thereby obtaining a MOS gate FET, as shown in FIG7 .

[0123] The fabricated MIS gate FET was subjected to IV testing, with the test results shown in Figure 12: its gate breakdown voltage reached 22V, its threshold voltage reached 3.1V, and its dynamic threshold voltage drift was 0.2V. These data are significantly improved compared to traditional p-GaN E-HEMTs, confirming the advantages of this application in terms of gate control performance and reliability.

[0124] Example 2

[0125] A method for preparing a group III nitride enhancement mode field effect transistor (FET) may include the following steps:

[0126] 1) Growing a depletion-mode HEMT (D-HEMT) epitaxial wafer on a substrate.

[0127] Specifically include: using the metal organic vapor deposition (MOCVD) method, on Si <111> A 600nm AlN / AlGaN transition layer structure, a 4μm C-doped Al 0.07 Ga 0.93 N high resistance layer, 300nm high quality low electron concentration unintentionally doped GaN layer, 45nm Al 0.18 Ga 0.82 The N barrier layer forms a two-dimensional electron gas with a sheet resistance of 360Ω / □ and a concentration of 9.8×10 12 cm -3 , the mobility is ~1800cm 2 V -1 s -1 AlGaN / GaN heterojunction depletion-mode HEMT epitaxial wafer.

[0128] 2) Forming a gate groove in the gate region of the depletion-mode HEMT epitaxial wafer.

[0129] Specifically, the gate region on the depletion-mode HEMT epitaxial wafer is patterned using photoresist as a mask, and all Al2O3 in the gate region is etched away at a low speed in an inductively coupled plasma (ICP) etching device. 0.18 Ga 0.82 N barrier layer and about 8nm of unintentionally doped GaN layer to form the gate groove;

[0130] The photoresist was removed using organic cleaning methods such as acetone, and the depth of the gate groove was found to be 47-48nm.

[0131] After using piranha solution to remove residual organic matter, the depletion-mode HEMT epitaxial wafer with gate grooves was placed in tetramethylammonium hydroxide and heated for a certain period of time, and then transferred to hydrofluoric acid buffer (BOE) for immersion to remove surface oxides and surface silicon impurities.

[0132] 3) Fabricating a MIS gate structure, source, and drain on a depletion-mode HEMT epitaxial wafer.

[0133] Specifically, the processed depletion-mode HEMT epitaxial wafer is reloaded into the metal organic chemical vapor deposition (MOCVD) equipment, and the temperature is raised to 900°C. After a period of time, Ga source, NH3, N2, Cp2Mg, etc. are introduced to sequentially epitaxially grow a p-GaN layer A with a thickness of 10nm and a p-Al layer with a thickness of 5nm on the surface of the depletion-mode HEMT epitaxial wafer. 0.15 Ga 0.85 N layer, p-GaN layer and p-Al 0.15 Ga 0.85 The Mg concentration in the N layer increases from 5×10 17 cm -3 Gradient increased to 1×10 19 cm -3 .

[0134] Epitaxial p-GaN layer and p-Al 0.15 Ga 0.85 After the N layer, the atmosphere in the MOCVD furnace was switched to N2, and the temperature was kept at 800°C for a period of time before being cooled to room temperature;

[0135] The depletion-mode HEMT epitaxial wafer is taken out and placed in an atomic layer deposition (ALD) device. 0.15 Ga 0.85 A 20nm Al2O3 layer is deposited on the N layer;

[0136] The source and drain regions are patterned by photolithography, and the Al2O3 layer, p-GaN layer, and p-Al2O3 layer located in the source and drain regions are etched in an ICP device. 0.15 Ga 0.85 N layer and Al 0.18 Ga 0.82 N barrier layer, deposit a layer of Ti / Al / Ti / Au = 20 / 130 / 50 / 150nm stack metal in the source and drain regions, and then rapidly anneal in N2 atmosphere at 890℃ for 30s to prepare the ohmic contact source and drain;

[0137] A layer of Ti / Au = 20 / 200nm stacked metal is deposited in the gate area, and a MIS gate structure is formed after rapid annealing at 500°C in an N2 atmosphere for 60s, thereby preparing a GaN MIS gate FET, as shown in Figure 8.

[0138] The prepared GaN MOS gate FET was subjected to IV testing. The test results are shown in Figure 12: its gate breakdown voltage reached 25V, the threshold voltage reached 2.8V, and the dynamic threshold voltage drift was 0.08V. The relevant data are significantly improved compared with traditional p-GaN E-HEMT, confirming that this application has great advantages in gate control performance and reliability.

[0139] It should be understood that the above embodiments are merely illustrative of the technical concepts and features of this application. Their purpose is to enable those familiar with the art to understand the content of this application and implement it accordingly. They are not intended to limit the scope of protection of this application. Any equivalent changes or modifications made in accordance with the spirit and substance of this application shall be included within the scope of protection of this application.

Claims

1. An enhancement mode field effect transistor, characterized in that: Including epitaxial structure, MIS / MOS gate structure, source and drain, The epitaxial structure comprises at least one heterojunction, the heterojunction comprises a first semiconductor layer and a second semiconductor layer stacked along the selected direction, a carrier channel is formed at the interface between the first semiconductor layer and the second semiconductor layer, the source electrode and the drain electrode are arranged in the ohmic region of the epitaxial structure and are electrically connected to the carrier channel; a gate groove is arranged in the gate region of the epitaxial structure, the bottom of the gate groove is located in the first semiconductor layer, the notch is located in the second semiconductor layer, and the carrier channel is blocked by the gate groove; The MIS / MOS gate structure includes a third semiconductor layer, a gate dielectric layer and a gate which are stacked in sequence along the selected direction, the third semiconductor layer is at least arranged in the gate groove, and the MIS / MOS gate structure has a field effect on the regulation of the carrier channel. When a forward voltage is applied to the gate, electrons are inverted and generated in the third semiconductor layer, and the carrier channels located on both sides of the gate groove are electrically connected via the electrons.

2. The enhancement mode field effect transistor according to claim 1, characterized in that: The third semiconductor layer includes at least one p-type semiconductor layer and / or at least one unintentionally doped semiconductor layer having acceptor or acceptor-like defects; Preferably, the third semiconductor layer comprises two or more p-type semiconductor layers or two or more unintentionally doped semiconductor layers having acceptor or acceptor-like defects made of different materials; Preferably, the thickness of the third semiconductor layer is 15-16 nm.

3. The enhancement mode field effect transistor according to claim 2, characterized in that: The p-type semiconductor layer is doped with Mg, and the Mg doping concentration of the p-type semiconductor layer is less than 1×10 20 cm -3 ; Preferably, the Mg doping concentration of the p-type semiconductor layer is 1×10 15 cm -3 ~1×10 20 cm -3 , preferably 5×10 17 cm -3 ~1×10 19 cm -3 ; Preferably, the Mg element in the p-type semiconductor layer is uniformly distributed, linearly distributed or gradually distributed; Preferably, the material of the p-type semiconductor layer includes p-type group III nitride; Preferably, the material of the p-type semiconductor layer includes p-GaN, p-AlGaN, p-AlInGaN, p-InGaN, p-AlInN or p-(Al, In)GaN.

4. The enhancement mode field effect transistor according to claim 2, characterized in that: The concentration of acceptor or acceptor-like defects in the unintentionally doped semiconductor layer is 1×10 15 cm -3 In the above, the unintentionally doped semiconductor layer is in a high resistivity state; preferably, the concentration of acceptor or acceptor-like defects in the unintentionally doped semiconductor layer is 1×10 15 cm -3 ~1×10 20 cm -3 , preferably 5×10 17 cm -3 ~1×10 19 cm -3 ; Preferably, the material of the unintentionally doped semiconductor layer comprises unintentionally Mg-doped group III nitride; Preferably, the material of the unintentionally doped semiconductor layer includes unintentionally Mg-doped GaN, AlGaN, AlInGaN, InGaN, AlInN or (Al, In)GaN.

5. The enhancement mode field effect transistor according to claim 1, characterized in that: The third semiconductor layer is arranged in the gate region of the epitaxial structure, or the third semiconductor layer is arranged in the gate region of the epitaxial structure and in the region between the gate region and the ohmic region; And / or, the gate dielectric layer is arranged in the gate region of the epitaxial structure and in the region between the gate region and the ohmic region; Preferably, the material of the gate dielectric layer includes Al2O3, HfO2, Si3N4 or SiO2; Preferably, the thickness of the gate dielectric layer is 5 to 100 nm; And / or, the epitaxial structure comprises two or more heterojunctions stacked along the selected direction, and the bottom of the gate groove is located in the first semiconductor layer of the bottommost heterojunction; Preferably, the materials of the first semiconductor layer and the second semiconductor layer both include group III nitride; Preferably, the material of the first semiconductor layer and the second semiconductor layer includes GaN, AlGaN, AlInGaN, InGaN, AlInN or (Al, In)GaN; And / or, the epitaxial structure further includes a high resistance and voltage-bearing layer and a transition layer, the heterojunction is arranged on the high resistance and voltage-bearing layer along the selected direction, and the high resistance and voltage-bearing layer is arranged on the transition layer; Preferably, the materials of the high-resistance voltage-resistant layer and the transition layer both include group III nitride.

6. A method for preparing an enhancement mode field effect transistor, characterized in that: include: Providing an epitaxial structure, the epitaxial structure comprising at least one heterojunction, the heterojunction comprising a first semiconductor layer and a second semiconductor layer stacked along the selected direction, a carrier channel formed at an interface between the first semiconductor layer and the second semiconductor layer; Removing all of the second semiconductor layer and part of the first semiconductor layer located in the gate region of the epitaxial structure, thereby forming a gate groove, wherein the carrier channel is isolated by the gate groove; A third semiconductor layer, a gate dielectric layer and a gate are sequentially stacked at least in the gate region of the epitaxial structure, so that A MIS / MOS gate structure is formed, wherein the MIS / MOS gate structure has a field effect on the regulation of the carrier channel. When a forward voltage is applied to the gate, electrons are inverted and generated in the third semiconductor layer, and the carrier channels located on both sides of the gate groove are electrically connected via the electrons. A source electrode and a drain electrode are formed in the ohmic region of the epitaxial structure, and the source electrode and the drain electrode are electrically connected to the carrier channel.

7. The preparation method according to claim 6, characterized in that: The third semiconductor layer includes at least one p-type semiconductor layer and / or at least one unintentionally doped semiconductor layer having acceptor or acceptor-like defects; Preferably, the third semiconductor layer comprises two or more p-type semiconductor layers or two or more unintentionally doped semiconductor layers having acceptor or acceptor-like defects made of different materials; Preferably, the thickness of the third semiconductor layer is 15-16 nm.

8. The preparation method according to claim 7, characterized in that: The p-type semiconductor layer is doped with Mg, and the Mg doping concentration of the p-type semiconductor layer is less than 1×10 20 cm -3 ; Preferably, the Mg doping concentration of the p-type semiconductor layer is 1×10 15 cm -3 ~1×10 20 cm -3 , preferably 5×10 17 cm -3 ~1×10 19 cm -3 ; Preferably, the material of the p-type semiconductor layer includes p-type group III nitride; Preferably, the material of the p-type semiconductor layer includes p-GaN, p-AlGaN, p-AlInGaN, p-InGaN, p-AlInN or p-(Al, In)GaN.

9. The enhancement mode field effect transistor according to claim 7, characterized in that: The concentration of acceptor or acceptor-like defects in the unintentionally doped semiconductor layer is 1×10 15 cm -3 In the above, the unintentionally doped semiconductor layer is in a high resistivity state; Preferably, the material of the unintentionally doped semiconductor layer comprises unintentionally Mg-doped group III nitride; Preferably, the material of the unintentionally doped semiconductor layer includes unintentionally Mg-doped GaN, AlGaN, AlInGaN, InGaN, AlInN or (Al, In)GaN.

10. The enhancement mode field effect transistor according to claim 1, characterized in that: The third semiconductor layer is arranged in the gate region of the epitaxial structure, or the third semiconductor layer is arranged in the gate region of the epitaxial structure and in the region between the gate region and the ohmic region; And / or, the gate dielectric layer is arranged in the gate region of the epitaxial structure and in the region between the gate region and the ohmic region; Preferably, the material of the gate dielectric layer includes Al2O3, HfO2, Si3N4 or SiO2; Preferably, the thickness of the gate dielectric layer is 5 to 100 nm; And / or, the epitaxial structure comprises two or more heterojunctions stacked along the selected direction, and the bottom of the gate groove is located in the first semiconductor layer of the bottommost heterojunction; Preferably, the materials of the first semiconductor layer and the second semiconductor layer both include group III nitride; Preferably, the material of the first semiconductor layer and the second semiconductor layer includes GaN, AlGaN, AlInGaN, InGaN, AlInN or (Al, In)GaN.

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