System running method of baseboard management controller and baseboard management controller

Abstract

Embodiments of the present application relate to the technical field of electronic information and provide a system running method of a baseboard management controller and a baseboard management controller. The method comprises: starting a target operating system on a baseboard management controller, wherein the target operating system is used for managing a target hardware partition among a plurality of hardware partitions obtained by dividing on a server host system; loading a target hardware interface for the target operating system, wherein the target hardware interface is configured to establish a connection between the target operating system and the target hardware partition; and running the target operating system on the baseboard management controller, wherein the target operating system is used for managing the target hardware partition by means of the target hardware interface. The present application solves the problem that the applicability of hardware partitions of a server host system is relatively low, thereby achieving the effect of improving the applicability of the hardware partitions of the server host system.

Description

System operation method of baseboard management controller and baseboard management controller

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to the Chinese patent application filed with the China Patent Office on July 26, 2023, with application number 202310923501.6, and entitled “System operation method of baseboard management controller and baseboard management controller”, the entire contents of which are incorporated by reference into this application. Technical Field

[0003] The embodiments of the present application relate to the field of electronic information technology, and in particular to a system operation method of a baseboard management controller and a baseboard management controller. Background Art

[0004] In recent years, with the rapid development of the semiconductor industry and integrated circuit technology, processors have become important computing units in fields such as cloud computing, artificial intelligence, and big data. In the server industry, in order to achieve hardware computing resource sharing and improve the utilization rate of multi-core processors while meeting the real-time requirements of the business, current related technologies partition computing resources such as the host system CPU (Central Processing Unit) into hardware. A server is partitioned into two or even more physical host systems, which independently carry and provide services. However, in order to cope with the hardware partitioning of the host system, the same hardware partitioning design needs to be used to upgrade the BMC (Baseboard Management Controller) chip CPU architecture to adapt to the corresponding host system hardware partitioning architecture. This requires one-to-one development, which not only increases the design complexity and significantly increases the cost of the BMC chip, but also greatly reduces the applicability of the hardware partitioning of the server host system.

[0005] With respect to the problem of low applicability of hardware partitioning of server host systems in related technologies, no effective solution has been proposed.

[0006] Summary of the Invention

[0007] The embodiments of the present application provide a system operation method of a baseboard management controller and a baseboard management controller, so as to at least solve the problem of low applicability of hardware partitioning of a server host system in the related art.

[0008] According to a first aspect, a system operation method of a baseboard management controller is provided, the method comprising:

[0009] Starting a target operating system on the baseboard management controller, wherein the target operating system is used to manage a target hardware partition among a plurality of hardware partitions divided on the server host system;

[0010] loading a target hardware interface for the target operating system, wherein the target hardware interface is configured to establish a connection between the target operating system and the target hardware partition;

[0011] A target operating system is run on the baseboard management controller, wherein the target operating system is used to manage the target hardware partition through the target hardware interface.

[0012] In an exemplary embodiment, loading a target hardware interface for a target operating system includes:

[0013] Searching for a target hardware interface corresponding to a target processor core used by a target operating system from the processor cores and hardware interfaces having corresponding relationships, wherein the hardware interfaces on the baseboard management controller are allocated to each group of processor cores according to the hardware architecture of the hardware partition corresponding to each group of processor cores to obtain the processor cores and hardware interfaces having corresponding relationships;

[0014] Load the target hardware interface for the target operating system on the target processor core.

[0015] In one exemplary embodiment, loading a target hardware interface for a target operating system on a target processor core includes:

[0016] Parsing a target device tree of a target processor core to obtain a target hardware interface, wherein the hardware interface on the baseboard management controller is assigned to each group of processor cores through the device tree to obtain a corresponding relationship between the processor core and the hardware interface, and the physical addresses of the hardware interfaces on the baseboard management controller adopt a unified addressing method;

[0017] Load the target hardware interface driver on the target processor core;

[0018] The file system of the target operating system is booted on the target processor core to complete the startup boot of the target operating system.

[0019] In an exemplary embodiment, before loading the target hardware interface for the target operating system, the method further includes:

[0020] Get multiple hardware partitions of the host system;

[0021] Allocating a processor core on a baseboard management controller to each target hardware partition among the multiple hardware partitions to obtain a target processor core, and allocating a hardware interface on the baseboard management controller to the target hardware partition to obtain a target hardware interface, wherein the target processor core at least meets the management and operation requirements of the target hardware partition, and the target hardware interface at least meets the hardware connection requirements of the target hardware partition;

[0022] A corresponding relationship between a target processor core and a target hardware interface is established to obtain a processor core and a hardware interface having a corresponding relationship.

[0023] In an exemplary embodiment, allocating a processor core on a baseboard management controller to each target hardware partition in a plurality of hardware partitions to obtain a target processor core includes one of the following:

[0024] Evenly distribute the processor cores on the baseboard management controller to each target hardware partition;

[0025] According to the operation architecture of each target hardware partition in the multiple hardware partitions, one or more processor cores on the baseboard management controller are allocated to the target hardware partition to obtain a target processor core.

[0026] In an exemplary embodiment, allocating a hardware interface on a baseboard management controller to a target hardware partition to obtain a target hardware interface includes at least one of the following:

[0027] In a case where a first type of hardware interface exists on the baseboard management controller and the number of resources owned is greater than or equal to the number of resources required in the multiple hardware partitions, the first type of hardware interface is allocated to the target hardware partition as a target exclusive interface in the target hardware interface according to the hardware architecture of each target hardware partition, wherein the target exclusive interface is a hardware interface that is set to allow only the target processor core to access;

[0028] In the case that there is a second type of hardware interface on the baseboard management controller whose number of resources is less than the number of resources required in multiple hardware partitions, a sharing relationship for the second type of hardware interface is established between the target processor core and the reference processor core in the multiple groups of processor cores on the baseboard management controller as the target shared interface in the target hardware interface, wherein the target shared interface is a hardware interface that is set to allow the target processor core and the reference processor core in the multiple groups of processor cores to access.

[0029] In an exemplary embodiment, running a target operating system on a baseboard management controller includes:

[0030] When the target operating system needs to access a target shared interface in a target hardware interface, sending a first interrupt request to a reference processor core in a plurality of processor cores on a baseboard management controller through the target operating system, wherein the target shared interface is a hardware interface configured to allow access by the target processor core and the reference processor core used by the target operating system, and the first interrupt request is used to request use of the target shared interface;

[0031] receiving a second interrupt request returned by a reference operating system running on a reference processor core in response to the first interrupt request, wherein the second interrupt request is used to indicate that the target shared interface has been released;

[0032] In response to the second interrupt request, the target shared interface is accessed through the target operating system.

[0033] In an exemplary embodiment, sending a first interrupt request to a reference processor core in a plurality of groups of processor cores on a baseboard management controller by a target operating system includes:

[0034] Determine whether the target shared interface is occupied by the target operating system;

[0035] In a case where the target operating system does not occupy the target shared interface, a first interrupt request is sent to the reference processor core through the target operating system.

[0036] In an exemplary embodiment, after accessing the target shared interface through the target operating system, the method further includes:

[0037] receiving, through the target operating system, a third interrupt request sent by the reference operating system, wherein the third interrupt request is used to request use of the target shared interface;

[0038] Determine whether the target shared interface is being used by the target operating system;

[0039] If the target shared interface is being used, wait for the target shared interface to be used until it is finished.

[0040] When the target shared interface is not in use or the target shared interface has finished being used, the target shared interface is released;

[0041] A fourth interrupt request is sent to the reference operating system through the target operating system, wherein the fourth interrupt request is used to indicate that the target shared interface has been released.

[0042] In an exemplary embodiment, starting a target operating system on a baseboard management controller includes:

[0043] executing a secondary program loader on the baseboard management controller to load a universal boot loader;

[0044] The kernel of the corresponding target operating system is started on each group of processor cores through a universal boot loader.

[0045] In an exemplary embodiment, executing a secondary program loader on a baseboard management controller to load a universal boot loader includes:

[0046] The baseboard management controller powers on and wakes up a processor core;

[0047] Directing execution of a boot program in a boot memory on a processor core;

[0048] Perform secure boot verification on the secondary program loader through the boot program;

[0049] When the secondary program loader passes the secure boot verification, the secondary program loader is executed to guide the universal boot loader to execute the code.

[0050] According to a second aspect, a baseboard management controller is provided, comprising: a target operating system and a target hardware interface, wherein:

[0051] A target hardware interface is configured to connect a target operating system to a target hardware partition among a plurality of hardware partitions divided on the server host system;

[0052] A target operating system is used to manage the target hardware partition through the target hardware interface.

[0053] In an exemplary embodiment, the target hardware interface includes: a target exclusive interface and / or a target shared interface, wherein:

[0054] The target exclusive interface is a hardware interface that is set to allow only the target processor core where the target operating system is located to access it;

[0055] The target shared interface is a hardware interface configured to allow access by a target processor core and a reference processor core in a plurality of groups of processor cores on a baseboard management controller.

[0056] In an exemplary embodiment, a target device tree is deployed in the target operating system, and the target device tree is used to load a driver of a target hardware interface. The physical addresses of the hardware interfaces on the baseboard management controller adopt a unified addressing method.

[0057] In an exemplary embodiment, the baseboard management controller further includes: a universal boot loader, wherein:

[0058] A universal boot loader is configured to start a kernel of a corresponding target operating system on each group of processor cores on the baseboard management controller;

[0059] The kernel of the target operating system is configured to parse the target device tree and load the driver for the target hardware interface.

[0060] In an exemplary embodiment, the baseboard management controller further includes: a secondary program loader, wherein:

[0061] The secondary program loader is configured to direct the universal boot loader to execute code.

[0062] In an exemplary embodiment, the baseboard management controller further includes: a boot storage, wherein

[0063] The boot storage is configured to perform secure boot verification on the secondary program loader.

[0064] According to a third aspect, a server is provided, comprising: a baseboard management controller and a server host system, wherein:

[0065] The baseboard management controller includes a target operating system and a target hardware interface, the server host system includes multiple hardware partitions, and the target hardware interface establishes a connection between the target operating system and a target hardware partition among the multiple hardware partitions;

[0066] The baseboard management controller is configured to manage the target hardware partition through the target operating system.

[0067] In an exemplary embodiment, the target hardware interface includes: a target exclusive interface and / or a target shared interface, wherein:

[0068] The target exclusive interface is a hardware interface that is set to allow only the target processor core where the target operating system is located to access it, and the target shared interface is a hardware interface that is set to allow the target processor core and a reference processor core in the multiple groups of processor cores on the baseboard management controller to access it;

[0069] The target exclusive interface is directly connected to the target hardware partition;

[0070] The target shared interface is connected to the partition switch device, and the partition switch device is respectively connected to the target hardware partition and the reference hardware partition corresponding to the reference processor core.

[0071] According to a fourth aspect, a system operation device of a baseboard management controller is provided, comprising:

[0072] a startup module configured to start a target operating system on the baseboard management controller, wherein the target operating system is used to manage a target hardware partition among a plurality of hardware partitions divided on the server host system;

[0073] a loading module configured to load a target hardware interface for a target operating system, wherein the target hardware interface is a target hardware interface configured to establish a connection between the target operating system and a target hardware partition;

[0074] The running module is configured to run a target operating system on the baseboard management controller, wherein the target operating system is used to manage a target hardware partition through a target hardware interface.

[0075] According to the fifth aspect, a non-volatile readable storage medium is further provided, in which a computer program is stored, wherein the computer program is configured to execute the steps of any of the above method embodiments when running.

[0076] According to the sixth aspect, an electronic device is also provided, comprising a memory and a processor, wherein a computer program is stored in the memory, and the processor is configured to run the computer program to execute the steps in any one of the above method embodiments.

[0077] Through the present application, multiple hardware interfaces are set on the baseboard management controller, and each hardware interface is configured to connect a hardware partition and an operating system corresponding to the hardware partition. When the target operating system runs on the baseboard management controller, the target hardware partition among the multiple hardware partitions divided on the server host system can be managed through the target hardware interface corresponding to the target operating system. That is, by assigning a corresponding hardware interface to each operating system, different operating systems are allowed to manage the hardware partitions corresponding to the operating system divided on the server host system without having to modify the system architecture of the baseboard management controller according to the architecture of different server host system hardware partitions, thereby improving the adaptability and versatility of the hardware partitions of the server host system. Therefore, the technical problem of low applicability of the hardware partitions of the server host system can be solved, and the technical effect of improving the applicability of the hardware partitions of the server host system can be achieved. BRIEF DESCRIPTION OF THE DRAWINGS

[0078] FIG1 is a hardware structure block diagram of a mobile terminal according to a system operation method of a baseboard management controller according to an embodiment of the present application;

[0079] FIG2 is a flow chart of a system operation method of a baseboard management controller according to an embodiment of the present application;

[0080] 3 is a flowchart of a process of running an operating system in a core partition on a baseboard management controller according to an embodiment of the present application;

[0081] FIG4 is a schematic diagram of a system operation architecture of a baseboard management controller according to an embodiment of the present application;

[0082] 5 is a schematic diagram of a process in which an operating system on a core partition accesses a target shared interface to perform inter-core communication according to an embodiment of the present application;

[0083] FIG6 is a block diagram of a BMC chip according to an embodiment of the present application;

[0084] 7 is a structural block diagram of a system operation device of a baseboard management controller according to an embodiment of the present application;

[0085] FIG8 is a schematic diagram of an electronic device according to an embodiment of the present application. DETAILED DESCRIPTION

[0086] The embodiments of the present application will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0087] It should be noted that the terms "first", "second", etc. in the description and claims of this application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence.

[0088] The method embodiments provided in the embodiments of the present application can be executed in a mobile terminal, a computer terminal or a similar computing device. Taking operation on a mobile terminal as an example, FIG1 is a hardware structure block diagram of a mobile terminal according to a system operation method of a baseboard management controller of an embodiment of the present application. As shown in FIG1 , the mobile terminal may include one or more (only one is shown in FIG1 ) processors 102 (the processor 102 may include but is not limited to a processing device such as a microprocessor MCU or a programmable logic device FPGA) and a memory 104 configured to store data, wherein the mobile terminal may also include a transmission device 106 and an input / output device 108 configured to have a communication function. It will be understood by those skilled in the art that the structure shown in FIG1 is only for illustration and does not limit the structure of the mobile terminal. For example, the mobile terminal may also include more or fewer components than those shown in FIG1 , or have a configuration different from that shown in FIG1 .

[0089] The memory 104 can be configured to store computer programs, for example, software programs and modules of application software, such as the computer program corresponding to the system operation method of the baseboard management controller in the embodiment of the present application. The processor 102 executes various functional applications and data processing by running the computer program stored in the memory 104, that is, implementing the above method. The memory 104 may include a high-speed random access memory, and may also include a non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some instances, the memory 104 may include a memory remotely located relative to the processor 102, and these remote memories may be connected to the mobile terminal via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and a combination thereof.

[0090] The transmission device 106 is configured to receive or transmit data via a network. Optional examples of the aforementioned network may include a wireless network provided by the mobile terminal's communications provider. In one embodiment, the transmission device 106 includes a network interface controller (NIC), which can be connected to other network devices via a base station to enable communication with the Internet. In another embodiment, the transmission device 106 may be a radio frequency (RF) module configured to communicate with the Internet wirelessly.

[0091] In this embodiment, a method for operating a baseboard management controller is provided. FIG2 is a flow chart of a method for operating a baseboard management controller according to an embodiment of the present application. As shown in FIG2 , the flow chart includes the following steps:

[0092] Step S202: starting a target operating system on the baseboard management controller, wherein the target operating system is used to manage a target hardware partition among a plurality of hardware partitions divided on the server host system;

[0093] Step S204, loading a target hardware interface for the target operating system, wherein the target hardware interface is configured to establish a connection between the target operating system and the target hardware partition;

[0094] Step S206 : running a target operating system on the baseboard management controller, wherein the target operating system is used to manage the target hardware partition through the target hardware interface.

[0095] Through the above steps, multiple hardware interfaces are set on the baseboard management controller, and each hardware interface is set to connect the hardware partition and the operating system corresponding to the hardware partition. When the target operating system runs on the baseboard management controller, the target hardware partition among the multiple hardware partitions divided on the server host system can be managed through the target hardware interface corresponding to the target operating system. That is, by assigning a corresponding hardware interface to each operating system, different operating systems are allowed to manage the hardware partitions corresponding to the operating system divided on the server host system without having to modify the system architecture of the baseboard management controller according to the architecture of different server host system hardware partitions, thereby improving the adaptability and versatility of the hardware partitions of the server host system. Therefore, the technical problem of low applicability of the hardware partitions of the server host system can be solved, and the technical effect of improving the applicability of the hardware partitions of the server host system can be achieved.

[0096] Optionally, in this embodiment, the baseboard management controller may be, but is not limited to, a dedicated controller configured to monitor and manage a server, such as a BMC, that provides intelligent management of the motherboard based on the IPMI (Intelligent Platform Management Interface) technical design specifications. A BMC may have an independent arithmetic unit, followed by a controller, as well as memory and input / output devices. It may also have an independent software system, including a basic boot system, an operating system, and various application programs running on the BMC system. On the motherboard, the BMC may be an independent plug-in board or a component integrated into the motherboard, and is often designed on the motherboard of a server or computer.

[0097] In the technical solution provided in the above step S202, the above target operating system can be but is not limited to any operating system running on the baseboard management controller, and can be any operating system of multiple operating systems deployed on the processor of the embedded system, that is, an embedded operating system. Embedded operating systems can be divided into real-time operating systems (RTOS) and non-real-time operating systems according to their sensitivity to response time. Real-time operating systems can include but are not limited to FreeRTOS (Free Real-Time Operating System) and RTLinux (Real-Time Linux), etc. Non-real-time operating systems can include but are not limited to contiki (Contiki Operating System, a small multi-tasking operating system), HeliOS (HeliOS Operating System, a lightweight, high-performance operating system) and Linux (GNU / Linux, a POSIX-based multi-user, multi-tasking operating system that supports multi-threading and multi-CPU), etc.

[0098] Optionally, in this embodiment, the multiple operating systems may be, but are not limited to, multiple heterogeneous or homogeneous operating systems for managing the BMC, that is, the type of each operating system may be the same or different.

[0099] Optionally, in this embodiment, an embedded system is a device used to control, monitor, or assist in the operation of machinery and equipment, and is a specialized computer system. An embedded system is application-centric, based on computer technology, and its software and hardware can be customized to meet the application's stringent requirements for functionality, reliability, cost, size, power consumption, and other aspects. Defined by the application object, an embedded system is a combination of software and hardware, and may also include ancillary devices such as machinery.

[0100] Optionally, in this embodiment, the embedded system may include, but is not limited to, hardware devices such as a processor, memory, and peripheral circuits from a hardware perspective, and the target operating system may be, but is not limited to, running on the processor of the embedded system. From a software perspective, the target operating system may include, but is not limited to, underlying drivers, an operating system, and application programs, and the target operating system is the operating system in the embedded system.

[0101] Optionally, in this embodiment, the server host system can be, but is not limited to, an operating system installed on a computer host equipped with multiple CPU processors, typically Windows, Mac, OS (Operating System) and other systems, which manage the computer's hardware and software resources and provide services and interfaces for users or applications to use.

[0102] Optionally, in this embodiment, the hardware resources of the server host system can be partitioned using, but not limited to, CPU processors as partition units to obtain multiple hardware partitions. Each of the multiple hardware partitions corresponds to an independent operating system, that is, each hardware partition contains the computing, storage, network, and I / O (Input / Output) hardware resources required for the operation of its own system.

[0103] Optionally, in this embodiment, at the software level, each hardware partition can run a different operating system or a different version of the same operating system, and the corresponding operating system for managing each hardware partition runs independently.

[0104] In an exemplary embodiment, the target operating system can be started on the baseboard management controller in the following manner, but is not limited to: executing a secondary program loader on the baseboard management controller to load a universal boot loader; and starting the corresponding target operating system kernel on each group of processor cores through the universal boot loader.

[0105] Optionally, in this embodiment, the secondary program loader can be but is not limited to a program loader compiled with SPL (Secondary Program Loader) code, which is mainly responsible for initializing external RAM (Random Access Memory) and the environment, and loading the Uboot (Universal Boot Loader, used to complete hardware device initialization and operating system code transfer) image into the external RAM for execution.

[0106] Optionally, in this embodiment, the universal boot loader may be, but is not limited to, a boot loader that can start an operating system kernel and deploy and load the entire computer system, such as a Uboot loader (Universal boot loader).

[0107] In an exemplary embodiment, the secondary program loader can be executed on the baseboard management controller to load the universal boot loader in the following manner, but is not limited to: the baseboard management controller is powered on and wakes up a processor core; the boot program in the boot storage is directed to be executed on the processor core; the secondary program loader is subjected to a secure boot check through the boot program; and when the secondary program loader passes the secure boot check, the secondary program loader is executed to direct the universal boot loader to execute the code.

[0108] Optionally, in this embodiment, the target operating system's boot program may be, but is not limited to, stored in a specific storage space on the baseboard management controller specifically for booting the target operating system. A processor core of the target operating system may be, but is not limited to, configured to execute the target operating system's boot program, and the target operating system may be booted by, but is not limited to, executing the target operating system's boot program.

[0109] Optionally, in this embodiment, the process of the boot program performing a secure boot check on the code of the secondary program loader may be, but is not limited to, as follows: the boot program reads the code and verification code of the secondary program loader, performs an operation on the code of the secondary program loader through an agreed operation method (such as a hash operation) to obtain an operation value, and then compares the operation value with the read verification code. If the two are consistent, the inspection result is normal; if the two are inconsistent, the inspection result is abnormal.

[0110] Optionally, in this embodiment, the secondary program loader can also perform a secure boot check on the code of the universal boot loader. The secondary program loader reads the code and verification code of the universal boot loader, and operates on the code of the universal boot loader through an agreed operation method (such as a hash operation, which can be the same or different from the operation method of the boot memory to check the secondary program loader) to obtain an operation value, and then compares the operation value with the read verification code. If the two are consistent, the inspection result is normal; if the two are inconsistent, the inspection result is abnormal. If the inspection result is normal, the target operating system is loaded through the universal boot loader.

[0111] Optionally, in this embodiment, the boot storage may be, but is not limited to, a Boot ROM, which is a small mask ROM or write-protected flash memory embedded in the processor chip and contains the first code executed by the processor when it is powered on or reset.

[0112] Optionally, in this embodiment, the target operating system is described as a Linux system. First, the BMC management system (baseboard management controller) is powered on, and the BMC wakes up one of the cores (core 0 by default) to boot the boot program in the Boot ROM (boot storage); secondly, the SPL (secondary program loader) part of the code is checked for security startup through the Boot ROM boot program. If the check passes, the Uboot loader (universal boot loader) is guided to execute the SPL code and the Uboot code; finally, the kernel of the Linux system is started on core 0 through the Uboot loader.

[0113] In the technical solution provided in step S204 above, the target hardware interface is an interface capable of managing the host system, for example, one or more hardware interface resources strongly associated with the BMC system. The target hardware interface may include, but is not limited to, LPC (Low Pin Count Bus), I2C (Inter-Integrated Circuit) 0 to I2C5, LAN (Local Area Network) 0, LAN1, and PCIE (Peripheral Component Interconnect Express) hardware interface resources.

[0114] Optionally, in this embodiment, the target hardware interface can be deployed on, but is not limited to, a baseboard management controller. The hardware interface required by the operating system to manage the hardware partition can be pre-loaded onto the processor to support the operating system's subsequent calls to the hardware interface during management. After the target operating system is started, the target hardware interface can be loaded for the target operating system on the BMC processor operated by the target operating system, establishing a connection between the target operating system and the target hardware partition, thereby enabling the target operating system to manage various hardware resources in the target hardware partition.

[0115] In an exemplary embodiment, the target hardware interface can be loaded for the target operating system in the following manner, but is not limited to: searching for the target hardware interface corresponding to the target processor core used by the target operating system from the processor cores and hardware interfaces with corresponding relationships, wherein the hardware interface on the baseboard management controller is allocated to each group of processor cores according to the hardware architecture of the hardware partition corresponding to each group of processor cores to obtain processor cores and hardware interfaces with corresponding relationships; and loading the target hardware interface for the target operating system on the target processor core.

[0116] Optionally, in this embodiment, the baseboard management controller may include, but is not limited to, multiple processor cores, and the baseboard management controller may be divided into multiple core partitions using the processor core, ie, the CPU core, as a partition unit.

[0117] Optionally, in this embodiment, if the baseboard management controller includes two processor cores: core 0 and core 1, and four hardware interfaces are deployed on the baseboard management controller: hardware interface 1, hardware interface 2, hardware interface 3, and hardware interface 4, hardware interface 1 and hardware interface 2 are allocated to core 0 according to the hardware architecture of the hardware partition corresponding to core 0 (processor core), that is, hardware interface 1 and hardware interface 2 correspond to core 0; hardware interface 3 and hardware interface 4 are allocated to core 1 according to the hardware architecture of the hardware partition corresponding to core 1, that is, hardware interface 3 and hardware interface 4 correspond to core 1. Then, if the processor used by the target operating system is core 0 (target processor core), hardware interface 1 and hardware interface 2 can be found as the target hardware interfaces, thereby loading the target hardware interfaces for the target operating system on core 0.

[0118] In an exemplary embodiment, the target hardware interface can be loaded for the target operating system on the target processor core in the following manner, but is not limited to: parsing the target device tree of the target processor core to obtain the target hardware interface, wherein the hardware interface on the baseboard management controller is assigned to each group of processor cores through the device tree to obtain corresponding processor cores and hardware interfaces, and the physical address of the hardware interface on the baseboard management controller adopts a unified addressing method; loading the driver of the target hardware interface on the target processor core; booting the file system of the target operating system on the target processor core to complete the startup boot of the target operating system.

[0119] Optionally, in this embodiment, each group of processor cores corresponds to a device tree, and the device tree corresponding to the target processor core is the target device tree. The device tree can be, but is not limited to, a Linux device tree driver, whose function is to provide hardware information to the operating system. The device tree driver is loaded during the startup process of the Linux kernel, so that the system can identify and manage hardware devices. The device tree driver provides the address, interrupt, power supply and other properties of the hardware device to help the operating system to correctly find, identify and control the hardware device. The device tree is usually described by a file called DTS (Device Tree Source), which contains information and properties of the hardware device, such as the device model, manufacturer, I / 0 address range, interrupt controller and pin, etc. When the system starts, the DTS file will be compiled into a binary file (DTB) and loaded and parsed by the Linux kernel.

[0120] Optionally, in this embodiment, different hardware resources can be configured for different processor cores corresponding to different device tree files through, but not limited to, different device tree files, that is, the hardware interfaces on the BMC are allocated to the corresponding different processor cores through different device tree files, thereby obtaining processor cores and hardware interfaces with corresponding relationships.

[0121] Optionally, in this embodiment, the physical addresses of the hardware interfaces on the BMC adopt a unified addressing method, that is, resources such as LPC0, LPC1, I2C0~I2C5, LAN0, LAN1, PCIE, etc. have mutually exclusive address spaces in the BMC system. In this way, as long as the device tree files of different core partitions on the BMC ensure that the hardware resources they define are different, it can be ensured that each core partition will not affect other core partitions when accessing hardware resources.

[0122] In an optional embodiment, the target operating system is a Linux system, and the baseboard management controller is equipped with two processor cores, which are divided into two core partitions: Core0 partition and Core1 partition. An example of the process of running an operating system in a core partition on a baseboard management controller is provided. FIG3 is a flow chart of the process of running an operating system in a core partition on a baseboard management controller according to an embodiment of the present application. As shown in FIG3, the process includes the following steps:

[0123] Step 1: The BMC management system is powered on, and the BMC uses one of the cores (core 0 by default) to boot the boot program in the Boot ROM; Step 2: Boot The ROM performs a secure boot check on the SPL code. If the check passes, the SPL code is executed, and then the Uboot code is executed. Step 3: Use Core0 to start the Linux system kernel, parse the device tree corresponding to the Core0 partition, load the corresponding driver, boot the file system, and complete the Linux system boot. At this point, Core0 has full access to the exclusive resources LPC0, I2C0 to I2C2, and LAN0, and can independently use these interfaces according to the needs of its upper-level applications. On the other hand, it has completed the driver loading of the shared resource PCIE interface controller, and has the upper-level application access to the PCIE interface. Step 4: Use Core1 to start the Linux system kernel, parse the device tree corresponding to the Core1 partition, load the corresponding driver, boot the file system, and complete the Linux system boot. At this point, Core1 has full access to the exclusive resources LPC1, I2C3 to I2C5, and LAN1, and can independently use these interfaces according to the needs of its upper-level applications. On the other hand, it has completed the driver loading of the shared resource PCIE interface controller, and has the upper-level application access to the PCIE interface. Step 5: Core0 independently runs the Linux system of the Core0 partition, and Core1 independently runs the Linux system of the Core1 partition.

[0124] In an exemplary embodiment, before loading the target hardware interface for the target operating system, the system operation method of the baseboard management controller can be implemented in the following manner, but is not limited to: obtaining multiple hardware partitions of the host system; allocating a processor core on the baseboard management controller to each target hardware partition in the multiple hardware partitions to obtain a target processor core, and allocating a hardware interface on the baseboard management controller to the target hardware partition to obtain a target hardware interface, wherein the target processor core at least meets the management and operation requirements of the target hardware partition, and the target hardware interface at least meets the hardware connection requirements of the target hardware partition; establishing a correspondence between the target processor core and the target hardware interface to obtain a processor core and hardware interface with a corresponding relationship.

[0125] Optionally, in this embodiment, if the baseboard management controller is divided into N core partitions according to the number N of processor cores it carries, and it is obtained that the host system has M hardware partitions, a correspondence between the M hardware partitions and the N core partitions can be established, thereby allocating a target processor core that meets the management and operation requirements of the target hardware partition to the target hardware partition among the M hardware partitions, and allocating a target hardware interface that meets the hardware connection requirements of the target hardware partition to the target hardware partition.

[0126] Optionally, in this embodiment, the hardware interfaces on the BMC can be allocated to corresponding different processor cores through, but not limited to, different device tree files, thereby establishing a correspondence between the target processor core and the target hardware interface, and obtaining processor cores and hardware interfaces with corresponding relationships.

[0127] In an exemplary embodiment, a target processor core can be obtained by allocating a processor core on a baseboard management controller to each target hardware partition in a plurality of hardware partitions in one of the following ways, but is not limited to: evenly allocating the processor cores on the baseboard management controller to each target hardware partition; or allocating one or more processor cores on a baseboard management controller to a target hardware partition according to the operating architecture of each target hardware partition in a plurality of hardware partitions to obtain a target processor core.

[0128] Alternatively, in this embodiment, if the baseboard management controller is divided into N core partitions based on the number N of processor cores it carries, and the host system is found to have M hardware partitions, one of the following two allocation methods can be used to allocate target processor cores to the target hardware partitions: 1. Evenly distribute the n processor cores corresponding to the N core partitions to the m target hardware partitions corresponding to the M hardware partitions. 2. Allocate one or more processor cores from the n processor cores on the baseboard management controller to the m target hardware partitions based on the operating architecture of each target hardware partition in the M hardware partitions.

[0129] Optionally, in this embodiment, if a method of allocating target processor cores to a target hardware partition based on the operating architecture is used, the following two priority allocation strategies may be employed: 1. CPU priority, which means allocating to the target hardware partition one or more processor cores that meet or are closest to the number of CPU cores required for the target hardware partition to operate. 2. Memory priority, which means allocating to the target hardware partition one or more processor cores that meet or are closest to the memory bandwidth required for the target hardware partition to operate.

[0130] In an exemplary embodiment, the target hardware interface can be obtained by allocating a hardware interface on the baseboard management controller to the target hardware partition in one of the following ways, but not limited to: when there is a first type of hardware interface on the baseboard management controller whose resource ownership quantity is greater than or equal to the resource requirement quantity in multiple hardware partitions, the first type of hardware interface is allocated to the target hardware partition according to the hardware architecture of each target hardware partition as a target exclusive interface in the target hardware interface, wherein the target exclusive interface is a hardware interface that is set to allow only the target processor core to access; when there is a second type of hardware interface on the baseboard management controller whose resource ownership quantity is less than the resource requirement quantity in multiple hardware partitions, a sharing relationship of the second type of hardware interface is established between the target processor core and the reference processor core in the multiple groups of processor cores on the baseboard management controller as the target shared interface in the target hardware interface, wherein the target shared interface is a hardware interface that is set to allow the target processor core and the reference processor core in the multiple groups of processor cores to access.

[0131] Optionally, in this embodiment, the reference processor core may be, but is not limited to, a CPU core of one or more processors in the plurality of processor groups excluding the target processor. The target shared interface and the target exclusive interface may be, but are not limited to, uniformly addressed in the BMC management system, and multiple processor cores may have access rights to the target shared interface.

[0132] Optionally, in this embodiment, the hardware resources deployed on the baseboard management controller may include, but are not limited to, two types: shared resources and exclusive resources. Exclusive resources may include, but are not limited to, hardware interface resources such as LPC0, LPC1, I2C0-I2C5, LAN0, and LAN1. These resources are exclusive to the core partition in which they are located and can only be accessed by the target operating system corresponding to this core partition. Shared resources may include, but are not limited to, PCIE interface resources. Shared resources are common resources for all core partitions on the baseboard management controller, meaning that the operating systems corresponding to all core partitions have access to the shared resources. A mechanism may be designed to ensure time-sharing access to shared resources by different core partitions.

[0133] Optionally, in this embodiment, that is, if the number of first-type hardware interfaces on the baseboard management controller is N, then if the number of resources owned by the N first-type hardware interfaces is greater than or equal to the number of resource requirements in multiple hardware partitions, then it means that the resources required for loading multiple hardware partitions can all be provided by N first-type hardware interfaces. At this time, the first-type hardware interface can be allocated to the target hardware partition as a target exclusive resource according to the hardware architecture of each target hardware partition, and the target exclusive resource can be used to independently run the target operating system.

[0134] Optionally, in this embodiment, that is, if the number of second-type hardware interfaces on the baseboard management controller is M, then if the number of resources owned by the M second-type hardware interfaces is less than the number of resource requirements in multiple hardware partitions, then it means that the M second-type hardware interfaces cannot be evenly distributed to multiple hardware partitions to ensure that the hardware resources of each hardware partition meet the resource requirements. At this time, a sharing relationship can be established in which both the target processor core and the reference processor core can access the second-type hardware interface, and the second-type hardware interface can be used as the target shared resource, allowing multiple processor cores to access it in time-sharing.

[0135] In an optional embodiment, the server host system is divided into two hardware partitions: hardware partition 1 and hardware partition 2, and the two processor cores carried by the baseboard management controller are divided into two core partitions: Core0 partition and Core1 partition. An example of the system operation architecture of the baseboard management controller is provided. Figure 4 is a schematic diagram of the system operation architecture of a baseboard management controller according to an embodiment of the present application. As shown in Figure 4, for the server Host (host) end system, the Host hardware resources are partitioned with the CPU processor as the partition unit, corresponding to the hardware partition 1 and hardware partition 2 in the figure respectively. The two partitions each correspond to an independent processor system, that is, each partition contains the hardware resources such as computing, storage, network and I / 0 required for the operation of its own system. In order to facilitate the subsequent description of the BMC hardware partition architecture, the figure only shows the LPC and PCIE hardware interface resources that are strongly related to the BMC system, that is, it is assumed that hardware partition 1 and partition 2 have 1 LPC and 1 PCIE interface respectively. At the software level, hardware partition 1 and partition 2 can run different operating systems or different versions of the same operating system respectively, and the operating systems of the two partition systems run independently.

[0136] For the BMC processor system, the BMC management system's hardware resources are partitioned based on CPU cores, corresponding to the Core0 and Core1 partitions in the figure. Similarly, for ease of description, the figure only shows a portion of the BMC's hardware resources, namely the LPC, I2C, LAN, and PCIE interface resources. As shown in Figure 4, the BMC management system's Core0 partition includes one LPC interface (corresponding to LPC0 in the figure), three I2C interfaces (corresponding to I2C0 to I2C2 in the figure), and one network interface (corresponding to LAN0 in the figure); similarly, the Core1 partition includes one LPC interface (corresponding to LPC1 in the figure), three I2C interfaces (corresponding to I2C3 to I2C5 in the figure), and one network interface (corresponding to LAN1 in the figure). At the software level, the two partitions can run different operating systems or different versions of the same operating system, and the operating systems of the two partition systems run independently.

[0137] Optionally, in this embodiment, for the BMC's partition shared resource PCIE, in order to realize its information interaction with the host partition system, an independent PCIE Switch (PCIe switch) device can be designed between the BMC and the host partition system. The Linux systems of the two BMC partitions control the selection path of the PCIE Switch through inter-core communication negotiation, thereby realizing the purpose of interconnection between the BMC two partition systems and the host partition system through the partition shared resources.

[0138] In the technical solution provided in the above step S206, a Linux operating system (target operating system) can be run on the BMC management system (baseboard management controller). The Linux operating system manages the target hardware partition through the target hardware interface that connects the Linux operating system and the corresponding target hardware partition. Therefore, there is no need to upgrade the BMC architecture according to the architecture of the host hardware partition, avoiding the increase in chip costs caused by the upgrade of the BMC processor architecture, thereby reducing the design cost of future server systems and achieving the goal of significantly reducing design costs and improving the computing performance of the host system and the BMC system.

[0139] In an exemplary embodiment, the target operating system can be run on the baseboard management controller in the following manner, but is not limited to: when the target operating system has a need to access a target shared interface in a target hardware interface, a first interrupt request is sent by the target operating system to a reference processor core in multiple groups of processor cores on the baseboard management controller, wherein the target shared interface is a hardware interface that is set to allow the target processor core and the reference processor core used by the target operating system to access, and the first interrupt request is used to request the use of the target shared interface; a second interrupt request is received from the reference operating system running on the reference processor core in response to the first interrupt request, wherein the second interrupt request is used to indicate that the target shared interface has been released; and in response to the second interrupt request, the target shared interface is accessed by the target operating system.

[0140] Optionally, in this embodiment, the reference operating system may be, but is not limited to, one or more operating systems other than the target operating system among a plurality of operating systems running on the baseboard management controller.

[0141] Optionally, in this embodiment, after the reference operating system receives a first interrupt request requesting the use of the target shared interface, it returns a second interrupt request indicating that the target shared interface has been released in response to the first interrupt request to the target operating system, thereby completing the target operating system's access to the target shared interface.

[0142] Optionally, in this embodiment, the target operating system may, but is not limited to, send a first interrupt request to the reference operating system via inter-core communication to access the target shared interface based on its own business needs. The reference operating system then instructs the target shared interface to be released via inter-core communication and returns the release result to the target operating system via a second interrupt request, thereby enabling the target operating system to access the target shared interface. This allows multiple systems to access the target shared interface without causing conflicts.

[0143] Alternatively, in this embodiment, multiple processor cores have access rights to the target shared interface. Simultaneously accessing the target shared interface in the system will inevitably result in an access conflict, triggering a system error. Therefore, a specific access mechanism needs to be designed for the target shared interface to ensure that different partitions have correct access to it.

[0144] Optionally, in this embodiment, the target operating system and the reference operating system may exchange interrupt requests in a manner that is not limited to inter-core communication. The inter-core communication may be implemented by defining interrupt vectors.

[0145] Optionally, in this embodiment, the present application uses a custom interrupt vector table to implement inter-core communication, thereby achieving mutually exclusive access control of partitioned shared resources. For example, if both the target operating system and the reference operating system are Linux systems, and the baseboard management controller is equipped with two processor cores and is divided into two core partitions: Core0 partition and Core1 partition, there are 16 SGI (software generated interrupt) interrupt numbers in the Linux system for inter-core communication, of which interrupt numbers 8 to 15 are user-definable. Table 1 shows a configuration scheme for inter-core interrupt vectors based on the Linux system.

[0146] Table 1

[0147] As can be seen from Table 1, when the interrupt number is defined as 8, the trigger source is Core0 core and the response source is Core1 core, which means that the Core0 partition requests to use PCIE resources; when the interrupt number is defined as 9, the trigger source is Core1 core and the response source is Core0 core, which means that the Core1 partition requests to use PCIE resources; when the interrupt number is defined as 10, the trigger source is Core1 core and the response source is Core0 core, and the Core1 partition releases PCIE resources; when the interrupt number is defined as 11, the trigger source is Core0 core and the response source is Core1 core, which means that the Core0 partition releases PCIE resources.

[0148] In an exemplary embodiment, a first interrupt request can be sent to a reference processor core in multiple groups of processor cores on a baseboard management controller through a target operating system in the following manner, but is not limited to: determining through the target operating system whether a target shared interface is occupied; and sending a first interrupt request to the reference processor core through the target operating system if the target operating system does not occupy the target shared interface.

[0149] Optionally, in this embodiment, whether the target operating system has occupied the target shared interface can be determined by judging the current usage of the target operating system's hardware resources. Taking the PCIE hardware interface as the target shared interface as an example, if the target operating system is currently using PCIE hardware resources, it can be determined that the target operating system has occupied the target shared interface, and at this time there is no need to send a first interrupt request to the reference processor core through the target operating system; if the target operating system is not currently using PCIE hardware resources, it can be determined that the target operating system does not occupy the target shared interface, and at this time it is necessary to send a first interrupt request to the reference processor core through the target operating system.

[0150] Optionally, in this embodiment, when the target operating system does not occupy the target shared interface, the core of the target operating system can find the interrupt number requesting to occupy the target shared interface in the inter-core interrupt vector configuration scheme in the embodiment of this application to send a first interrupt request to the reference processor core, thereby realizing interactive interrupt requests in the form of inter-core communication.

[0151] In an exemplary embodiment, after accessing the target shared interface through the target operating system, the system operation method of the baseboard management controller can be implemented in the following manner, but is not limited to: receiving a third interrupt request sent by the reference operating system through the target operating system, wherein the third interrupt request is used to request the use of the target shared interface; determining whether the target shared interface is being used through the target operating system; if the target shared interface is being used, waiting for the end of use of the target shared interface; if the target shared interface is not being used, or if the use of the target shared interface has ended, releasing the target shared interface; sending a fourth interrupt request to the reference operating system through the target operating system, wherein the fourth interrupt request is used to indicate that the target shared interface has been released.

[0152] Optionally, in this embodiment, after the target operating system receives the third interrupt request sent by the reference system requesting to use the target shared interface, it can be determined whether the target operating system has occupied the target shared interface by judging the current usage of the target operating system's hardware resources. Taking the PCIE hardware interface as the target shared interface as an example, if the target operating system is currently using PCIE hardware resources, it can be determined that the target operating system has occupied the target shared interface. At this time, it is necessary to wait for the PCIE hardware interface to be used up. After the use is completed, the target operating system releases the PCIE hardware interface; if the target operating system is not currently using PCIE hardware resources, it can be determined that the target operating system does not occupy the target shared interface, and the target operating system releases the PCIE hardware interface.

[0153] Optionally, in this embodiment, when the target operating system does not occupy the target shared interface or the target system occupies the target shared interface but has completed use, the core of the target operating system can find the interrupt number indicating that the target shared interface has been released in the inter-core interrupt vector configuration scheme in the embodiment of this application to send a fourth interrupt request to the reference processor core, thereby notifying the reference operating system processing core that needs to use the target shared interface that the target shared interface is currently available, thereby realizing interactive interrupt requests in the form of inter-core communication.

[0154] In this embodiment, each interrupt request may be transmitted between systems in a manner including, but not limited to, a software protocol, or may be transmitted through a hardware module.

[0155] In an optional embodiment, taking the target operating system and the reference operating system as Linux systems, the two processor cores carried by the baseboard management controller are divided into two core partitions: Core0 partition and Core1 partition as an example, and providing an example of a process in which an operating system on a core partition accesses a target shared interface for inter-core communication. FIG5 is a schematic diagram of a process in which an operating system on a core partition accesses a target shared interface for inter-core communication according to an embodiment of the present application. As shown in FIG5 , when the Core0 partition needs to access PCIE shared resources, the Linux system of the Core0 partition will trigger an inter-core interrupt with an interrupt number of 8. After detecting the interrupt, the Linux system of the Core1 partition determines whether the PCIE resources can be released for use by the Core0 partition at this time. If the Core1 partition does not occupy the PCIE resources, the Linux system of the Core1 partition triggers an inter-core interrupt with an interrupt number of 10 to notify the Core0 partition that the PCIE resources have been released; or, if the Core1 partition is occupying the PCIE resources at this time, the Core1 partition ignores the interrupt request from Core0. At this time, the Core0 partition cannot use the resources. When the Core1 partition no longer uses the resources, the resources are released and the inter-core interrupt with an interrupt number of 10 is triggered to hand over the PCIE resources to the Core0 partition for use. Similarly, the inter-core interrupts 9 and 11 in the figure are used by Core 1 to request PCIE resources from Core 0. The interconnection control logic between the BMC management system's PCIE controller and the host system's different hardware partitions is configured through this inter-core communication process, while the PCIE switch device switches the physical link topology.

[0156] Optionally, in this embodiment, the system operation method of the baseboard management controller proposed in this application is conducive to the rapid application and promotion of the host system hardware partitioning technology, avoiding the increase in chip costs caused by the upgrade of the BMC processor architecture, thereby reducing the design cost of future server systems, and ultimately achieving the goal of significantly reducing design costs and improving the computing performance of the host system and BMC system.

[0157] Through the description of the above implementation methods, those skilled in the art can clearly understand that the method according to the above embodiment can be implemented by means of software plus the necessary general hardware platform, and of course it can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of the present application, or the part that contributes to the relevant technology, can be embodied in the form of a software product, which is stored in a non-volatile readable storage medium (such as ROM / RAM, magnetic disk, optical disk), and includes a number of instructions for enabling a terminal device (which can be a mobile phone, computer, server, or network device, etc.) to execute the methods of each embodiment of the present application.

[0158] In this embodiment, a baseboard management controller is also provided, including: a target operating system and a target hardware interface, wherein the target hardware interface is configured to connect the target operating system with a target hardware partition among multiple hardware partitions divided on the server host system; the target operating system is used to manage the target hardware partition through the target hardware interface.

[0159] Through the above-mentioned baseboard management controller, multiple hardware interfaces are set on the baseboard management controller, and each hardware interface is set to connect the hardware partition and the operating system corresponding to the hardware partition. When the target operating system runs on the baseboard management controller, the target hardware partition among the multiple hardware partitions divided on the server host system can be managed through the target hardware interface corresponding to the target operating system. That is, by assigning a corresponding hardware interface to each operating system, different operating systems are allowed to manage the hardware partitions corresponding to the operating system divided on the server host system without having to modify the system architecture of the baseboard management controller according to the architecture of different server host system hardware partitions, thereby improving the adaptability and versatility of the hardware partitions of the server host system. Therefore, the technical problem of low applicability of the hardware partitions of the server host system can be solved, and the technical effect of improving the applicability of the hardware partitions of the server host system can be achieved.

[0160] Optionally, in this embodiment, the baseboard management controller can be, but is not limited to, a dedicated controller configured to monitor and manage a server, such as a BMC, that provides intelligent management of the motherboard based on IPMI technical design specifications. A BMC can have an independent arithmetic unit, a secondary controller, memory, and input / output devices. It can also have an independent software system, including a basic boot system, an operating system, and various applications running on the BMC system. On the motherboard, the BMC can be a standalone plug-in board or integrated into the motherboard, and is often designed on the motherboard of a server or computer.

[0161] The baseboard management controller may not be limited to any chip that allows multiple operating systems to run on the same processor, such as a BMC chip. For example, an example of a BMC chip can be shown in FIG6 . The hardware of the BMC chip can include, but is not limited to, a SOC (SOC is called a system-on-chip, also called a system on a chip, which means that it is a product, a dedicated integrated circuit, which contains all the contents of a complete system and embedded software. It is also a technology used to implement the entire process from determining system functions to software / hardware partitioning and completing the design) sub-module and a BMC out-of-band sub-module. Among them, the SOC sub-module mainly includes an ARM core (ARM Core 1, ARM Core 2, ..., ARM Core X), and can also include, but is not limited to, a DDR (Double Data Rate) 4 controller (memory controller), a MAC (Media Access Control Address) controller (network controller), an SD (Secure Digital) Card / eMMC (Embedded Multi Media Card) controller (storage controller), a PCIE RC (Root Complex) controller, an SRAM (Static Random-Access Memory), and an SPI (Serial Peripheral Interface) controller. Interface, Serial Peripheral Interface, is a high-speed, full-duplex, synchronous communication bus) controller.

[0162] The cores and controllers are interconnected via a second bus, enabling interaction between the cores and the controllers. Simultaneously, the ARM cores are connected to the first bus (e.g., via an AXI (Advanced eXtensible Interface) bridge), and inter-core communication is achieved via the first bus. Furthermore, the SOC submodules also implement interconnection between the first and second buses (e.g., via a bridge), providing a physical path for the SOC submodules to access peripherals on the second bus.

[0163] The DDR4 controller can be connected to other components or devices through the DDR4 PHY (Physical Layer) interface, the MAC controller is connected to other components or devices through the RGMII (Reduced Gigabit Media Independent Interface), the SD card / eMMC controller is connected to other components or devices through the SD interface, and the PCIE RC controller is connected to other components or devices through the PCIE PHY interface.

[0164] The BMC out-of-band submodule primarily includes controllers for chip peripherals such as PWM (Pulse Width Modulation), a highly effective technique for controlling analog circuits using a microprocessor's digital outputs, GPIO (General-purpose input / output), FanTech (fan speed control), and mailbox. These controllers enable out-of-band management functions such as communication with the BMC's PECI (Platform Environment Control Interface) (for example, using GPIO to simulate PECI) and fan control. The BMC out-of-band submodule can, but is not limited to, interact with the SoC submodule via the Advanced Peripheral Bus (APB).

[0165] Optionally, in this embodiment, the BMC chip interconnects the on-chip ARM cores, storage units, and controller hardware resources via the first bus and the second bus. Dynamic balanced scheduling of processor resources primarily involves scheduling of the ARM core resources of the BMC chip, and inter-core communication refers to communication between ARM cores.

[0166] Optionally, in this embodiment, the system operation method of the baseboard management controller proposed in this application is based on running multiple BMC management systems in the BMC multi-core processor hard core, and these BMC management systems run simultaneously in the same embedded system. The system operation method of the baseboard management controller proposed in this application is based on the BMC multi-core processor hard core, and the I2C, GPIO and other hardware resources of the BMC processor are partitioned according to the number of cores. These hardware partition resources and one or several BMC processor hard cores form an independent system and run an independent BMC management system; for a single hardware resource in the BMC processor, such as a PCIE controller, the physical link realizes the interconnection between the BMC processor system and multiple host systems through the PCIE switch device, and the control logic is controlled by multiple BMC management systems through inter-core communication.

[0167] In an exemplary embodiment, the baseboard management controller can be, but is not limited to, configured to: search for a target hardware interface corresponding to a target processor core used by a target operating system from processor cores and hardware interfaces with corresponding relationships, wherein the hardware interface on the baseboard management controller is allocated to each group of processor cores according to the hardware architecture of the hardware partition corresponding to each group of processor cores to obtain processor cores and hardware interfaces with corresponding relationships; and load the target hardware interface for the target operating system on the target processor core.

[0168] Optionally, in this embodiment, the baseboard management controller may include, but is not limited to, multiple processor cores, which are deployed and run on the same BMC multi-core processor hard core. The baseboard management controller may be divided into multiple core partitions based on the processor core, i.e., the CPU core, as the partition unit.

[0169] Optionally, in this embodiment, if the baseboard management controller includes two processor cores: core 0 and core 1, and four hardware interfaces are deployed on the baseboard management controller: hardware interface 1, hardware interface 2, hardware interface 3, and hardware interface 4, hardware interface 1 and hardware interface 2 are allocated to core 0 according to the hardware architecture of the hardware partition corresponding to core 0 (processor core), that is, hardware interface 1 and hardware interface 2 correspond to core 0; hardware interface 3 and hardware interface 4 are allocated to core 1 according to the hardware architecture of the hardware partition corresponding to core 1, that is, hardware interface 3 and hardware interface 4 correspond to core 1. Then, if the processor used by the target operating system is core 0 (target processor core), hardware interface 1 and hardware interface 2 can be found as the target hardware interfaces, thereby loading the target hardware interfaces for the target operating system on core 0.

[0170] In an exemplary embodiment, the baseboard management controller can be configured to, but is not limited to: parse the target device tree of the target processor core to obtain the target hardware interface, wherein the hardware interface on the baseboard management controller is assigned to each group of processor cores through the device tree to obtain corresponding processor cores and hardware interfaces, and the physical address of the hardware interface on the baseboard management controller adopts a unified addressing method; load the driver of the target hardware interface on the target processor core; and boot the file system of the target operating system on the target processor core to complete the startup boot of the target operating system.

[0171] Optionally, in this embodiment, different hardware resources can be configured for different processor cores corresponding to different device tree files through, but not limited to, different device tree files, that is, the hardware interfaces on the BMC are allocated to the corresponding different processor cores through different device tree files, thereby obtaining processor cores and hardware interfaces with corresponding relationships.

[0172] In an exemplary embodiment, the baseboard management controller can be, but is not limited to, configured to: obtain multiple hardware partitions of the host system before loading the target hardware interface for the target operating system; before loading the target hardware interface for the target operating system, assign a processor core on the baseboard management controller to each target hardware partition in the multiple hardware partitions to obtain a target processor core, and assign a hardware interface on the baseboard management controller to the target hardware partition to obtain a target hardware interface, wherein the target processor core at least meets the management and operation requirements of the target hardware partition, and the target hardware interface at least meets the hardware connection requirements of the target hardware partition; before loading the target hardware interface for the target operating system, establish a correspondence between the target processor core and the target hardware interface to obtain a processor core and hardware interface with a corresponding relationship.

[0173] Optionally, in this embodiment, if the baseboard management controller is divided into N core partitions according to the number N of processor cores it carries, and it is obtained that the host system has M hardware partitions, a correspondence between the M hardware partitions and the N core partitions can be established, thereby allocating a target processor core that meets the management and operation requirements of the target hardware partition to the target hardware partition among the M hardware partitions, and allocating a target hardware interface that meets the hardware connection requirements of the target hardware partition to the target hardware partition.

[0174] Optionally, in this embodiment, the hardware interfaces on the BMC can be allocated to corresponding different processor cores through, but not limited to, different device tree files, thereby establishing a correspondence between the target processor core and the target hardware interface, and obtaining processor cores and hardware interfaces with corresponding relationships.

[0175] In an exemplary embodiment, the baseboard management controller can be, but is not limited to, set to one of the following: evenly distributing the processor cores on the baseboard management controller to each target hardware partition; allocating one or more processor cores on the baseboard management controller to the target hardware partition according to the operating architecture of each target hardware partition in multiple hardware partitions to obtain the target processor core.

[0176] Alternatively, in this embodiment, if the baseboard management controller is divided into N core partitions based on the number N of processor cores it carries, and the host system is found to have M hardware partitions, one of the following two allocation methods can be used to allocate target processor cores to the target hardware partitions: 1. Evenly distribute the n processor cores corresponding to the N core partitions to the m target hardware partitions corresponding to the M hardware partitions. 2. Allocate one or more processor cores from the n processor cores on the baseboard management controller to the m target hardware partitions based on the operating architecture of each target hardware partition in the M hardware partitions.

[0177] Optionally, in this embodiment, if a method of allocating target processor cores to a target hardware partition based on the operating architecture is used, the following two priority allocation strategies may be employed: 1. CPU priority, which means allocating to the target hardware partition one or more processor cores that meet or are closest to the number of CPU cores required for the target hardware partition to operate. 2. Memory priority, which means allocating to the target hardware partition one or more processor cores that meet or are closest to the memory bandwidth required for the target hardware partition to operate.

[0178] In an exemplary embodiment, the target hardware interface may include, but is not limited to: a target exclusive interface and / or a target shared interface, wherein the target exclusive interface is a hardware interface that is set to allow only the target processor core where the target operating system is located to access; the target shared interface is a hardware interface that is set to allow the target processor core and the reference processor core in the multiple groups of processor cores on the baseboard management controller to access.

[0179] Optionally, in this embodiment, the target hardware interface may be, but is not limited to, one or more hardware interface resources strongly related to the BMC system, such as: LPC (Low Pin Count Bus, LPC bus), I2C0-I2C5, LAN0, LAN1, and PCIE hardware interface resources. The target hardware interface may be, but is not limited to, deployed on a processor of a baseboard management controller. After the target operating system is started, the target hardware interface may be loaded for the target operating system on the BMC processor operated by the target operating system, and a connection between the target operating system and the target hardware partition may be established, thereby enabling the target operating system to manage various hardware resources in the target hardware partition.

[0180] Optionally, in this embodiment, the reference processor core may be, but is not limited to, a CPU core of one or more processors in the plurality of processor groups excluding the target processor. The target shared interface and the target exclusive interface may be, but are not limited to, uniformly addressed in the BMC management system, and multiple processor cores may have access rights to the target shared interface.

[0181] In an exemplary embodiment, the baseboard management controller can be, but is not limited to, set to one of the following: in the case where there is a first type of hardware interface on the baseboard management controller whose resource ownership quantity is greater than or equal to the resource requirement quantity in multiple hardware partitions, the first type of hardware interface is allocated to the target hardware partition according to the hardware architecture of each target hardware partition as a target exclusive interface in the target hardware interface, wherein the target exclusive interface is a hardware interface set to allow only the target processor core to access; in the case where there is a second type of hardware interface on the baseboard management controller whose resource ownership quantity is less than the resource requirement quantity in multiple hardware partitions, a sharing relationship for the second type of hardware interface is established between the target processor core and the reference processor core in the multiple groups of processor cores on the baseboard management controller as the target shared interface in the target hardware interface, wherein the target shared interface is a hardware interface set to allow the target processor core and the reference processor core in the multiple groups of processor cores to access.

[0182] Optionally, in this embodiment, the hardware resources deployed on the baseboard management controller may include, but are not limited to, two types: shared resources and exclusive resources. Exclusive resources may include, but are not limited to, hardware interface resources such as LPC0, LPC1, I2C0-I2C5, LAN0, and LAN1. These resources are exclusive to the core partition in which they are located and can only be accessed by the target operating system corresponding to this core partition. Shared resources may include, but are not limited to, PCIE interface resources. Shared resources are common resources for all core partitions on the baseboard management controller, meaning that the operating systems corresponding to all core partitions have access to the shared resources. A mechanism may be designed to ensure time-sharing access to shared resources by different core partitions.

[0183] Optionally, in this embodiment, that is, if the number of first-type hardware interfaces on the baseboard management controller is N, then if the number of resources owned by the N first-type hardware interfaces is greater than or equal to the number of resource requirements in multiple hardware partitions, then it means that the resources required for loading multiple hardware partitions can all be provided by N first-type hardware interfaces. At this time, the first-type hardware interface can be allocated to the target hardware partition as a target exclusive resource according to the hardware architecture of each target hardware partition, and the target exclusive resource can be used to independently run the target operating system.

[0184] Optionally, in this embodiment, that is, if the number of second-type hardware interfaces on the baseboard management controller is M, then if the number of resources owned by the M second-type hardware interfaces is less than the number of resource requirements in multiple hardware partitions, then it means that the M second-type hardware interfaces cannot be evenly distributed to multiple hardware partitions to ensure that the hardware resources of each hardware partition meet the resource requirements. At this time, a sharing relationship can be established in which both the target processor core and the reference processor core can access the second-type hardware interface, and the second-type hardware interface can be used as the target shared resource, allowing multiple processor cores to access it in time-sharing.

[0185] In an exemplary embodiment, the baseboard management controller can be, but is not limited to, configured to: send a first interrupt request to a reference processor core in multiple groups of processor cores on the baseboard management controller through the target operating system when there is a need for the target operating system to access a target shared interface in a target hardware interface, wherein the target shared interface is a hardware interface configured to allow access by the target processor core and the reference processor core used by the target operating system, and the first interrupt request is used to request the use of the target shared interface; receive a second interrupt request returned by the reference operating system running on the reference processor core in response to the first interrupt request, wherein the second interrupt request is used to indicate that the target shared interface has been released; and access the target shared interface through the target operating system in response to the second interrupt request.

[0186] Optionally, in this embodiment, the reference operating system may be, but is not limited to, one or more operating systems other than the target operating system among a plurality of operating systems running on the baseboard management controller.

[0187] Optionally, in this embodiment, after the reference operating system receives a first interrupt request requesting the use of the target shared interface, it returns a second interrupt request indicating that the target shared interface has been released in response to the first interrupt request to the target operating system, thereby completing the target operating system's access to the target shared interface.

[0188] Optionally, in this embodiment, the target operating system may, but is not limited to, send a first interrupt request to the reference operating system via inter-core communication to access the target shared interface based on its own business needs. The reference operating system then instructs the target shared interface to be released via inter-core communication and returns the release result to the target operating system via a second interrupt request, thereby enabling the target operating system to access the target shared interface. This allows multiple systems to access the target shared interface without causing conflicts.

[0189] Alternatively, in this embodiment, multiple processor cores have access rights to the target shared interface. Simultaneously accessing the target shared interface in the system will inevitably result in an access conflict, triggering a system error. Therefore, a specific access mechanism needs to be designed for the target shared interface to ensure that different partitions have correct access to it.

[0190] Optionally, in this embodiment, the target operating system and the reference operating system may exchange interrupt requests in a manner that is not limited to inter-core communication. The inter-core communication may be implemented by defining interrupt vectors.

[0191] Optionally, in this embodiment, the present application uses a custom interrupt vector table to implement inter-core communication, thereby achieving mutually exclusive access control of partition shared resources. For example, if both the target operating system and the reference operating system are Linux systems, and the baseboard management controller has two processor cores and is divided into two core partitions: Core0 partition and Core1 partition, there are 16 SGI interrupt numbers in the Linux system for inter-core communication, of which interrupt numbers 8 to 15 can be defined by the user.

[0192] In an exemplary embodiment, the baseboard management controller may be configured to: determine whether the target shared interface is occupied by the target operating system; and send a first interrupt request to the reference processor core by the target operating system if the target shared interface is not occupied by the target operating system.

[0193] Optionally, in this embodiment, whether the target operating system has occupied the target shared interface can be determined by judging the current usage of the target operating system's hardware resources. Taking the PCIE hardware interface as the target shared interface as an example, if the target operating system is currently using PCIE hardware resources, it can be determined that the target operating system has occupied the target shared interface, and at this time there is no need to send a first interrupt request to the reference processor core through the target operating system; if the target operating system is not currently using PCIE hardware resources, it can be determined that the target operating system does not occupy the target shared interface, and at this time it is necessary to send a first interrupt request to the reference processor core through the target operating system.

[0194] Optionally, in this embodiment, when the target operating system does not occupy the target shared interface, the core of the target operating system can find the interrupt number requesting to occupy the target shared interface in the inter-core interrupt vector configuration scheme in the embodiment of this application to send a first interrupt request to the reference processor core, thereby realizing interactive interrupt requests in the form of inter-core communication.

[0195] In an exemplary embodiment, the baseboard management controller can be, but is not limited to, configured to: after accessing the target shared interface through the target operating system, receive a third interrupt request sent by the reference operating system through the target operating system, wherein the third interrupt request is used to request the use of the target shared interface; after accessing the target shared interface through the target operating system, determine through the target operating system whether the target shared interface is being used; after accessing the target shared interface through the target operating system, if the target shared interface is being used, wait for the end of use of the target shared interface; after accessing the target shared interface through the target operating system, if the target shared interface is not being used or the use of the target shared interface has ended, release the target shared interface; after accessing the target shared interface through the target operating system, send a fourth interrupt request to the reference operating system through the target operating system, wherein the fourth interrupt request is used to indicate that the target shared interface has been released.

[0196] Optionally, in this embodiment, after the target operating system receives the third interrupt request sent by the reference system requesting to use the target shared interface, it can be determined whether the target operating system has occupied the target shared interface by judging the current usage of the target operating system's hardware resources. Taking the PCIE hardware interface as the target shared interface as an example, if the target operating system is currently using PC1E hardware resources, it can be determined that the target operating system has occupied the target shared interface. At this time, it is necessary to wait for the PCIE hardware interface to be used up. After the use is completed, the target operating system releases the PCIE hardware interface; if the target operating system is not currently using PCIE hardware resources, it can be determined that the target operating system does not occupy the target shared interface, and the target operating system releases the PCIE hardware interface.

[0197] Optionally, in this embodiment, when the target operating system does not occupy the target shared interface or the target system occupies the target shared interface but has completed use, the core of the target operating system can find the interrupt number indicating that the target shared interface has been released in the inter-core interrupt vector configuration scheme in the embodiment of this application to send a fourth interrupt request to the reference processor core, thereby notifying the reference operating system processing core that needs to use the target shared interface that the target shared interface is currently available, thereby realizing interactive interrupt requests in the form of inter-core communication.

[0198] In this embodiment, each interrupt request may be transmitted between systems in a manner including, but not limited to, a software protocol, or may be transmitted through a hardware module.

[0199] In an exemplary embodiment, a target device tree is deployed in the target operating system, and the target device tree is used to load a driver of a target hardware interface. The physical addresses of the hardware interfaces on the baseboard management controller adopt a unified addressing method.

[0200] Optionally, in this embodiment, each processor core corresponds to a device tree, and the device tree corresponding to the target processor core is the target device tree. The device tree can be, but is not limited to, a Linux device tree driver, whose function is to provide hardware information to the operating system. The device tree driver is loaded during the startup process of the Linux kernel, allowing the system to identify and manage hardware devices. The device tree driver provides the address, interrupt, power supply and other properties of the hardware device to help the operating system to correctly find, identify and control the hardware device. The device tree is usually described by a file called DTS (Device Tree Source), which contains information and properties of the hardware device, such as the device model, manufacturer, I / O address range, interrupt controller and pin, etc. When the system starts, the DTS file will be compiled into a binary file (DTB) and loaded and parsed by the Linux kernel.

[0201] Optionally, in this embodiment, the physical addresses of the hardware interfaces on the BMC (baseboard management controller) adopt a unified addressing method, that is, resources such as LPC0, LPC1, I2C0~I2C5, LAN0, LAN1, PCIE, etc. have mutually exclusive address spaces in the BMC system. In this way, as long as the device tree files of different core partitions on the BMC ensure that the hardware resources they define are different, it can be ensured that each core partition will not affect other core partitions when accessing hardware resources.

[0202] In an exemplary embodiment, the baseboard management controller also includes: a universal boot loader, wherein the universal boot loader is configured to start the kernel of the corresponding target operating system on each group of processor cores on the baseboard management controller; the kernel of the target operating system is configured to parse the target device tree to load the driver of the target hardware interface.

[0203] Optionally, in this embodiment, the universal boot loader can be, but is not limited to, a boot loader that can start the operating system kernel and can deploy and load the entire computer system, such as: Uboot loader (universal boot loader, an open source project that complies with the GPL terms and is used for system booting).

[0204] In an exemplary embodiment, the baseboard management controller further includes: a secondary program loader, wherein the secondary program loader is configured to guide the universal boot loader to execute the code.

[0205] Optionally, in this embodiment, the secondary program loader may be, but is not limited to, a program loader that compiles SPL (secondary program loader) code, which is mainly responsible for initializing the external RAM and environment, and loading the Uboot image into the external RAM for execution.

[0206] In an exemplary embodiment, the baseboard management controller further includes a boot storage configured to perform a secure boot check on the secondary program loader.

[0207] Optionally, in this embodiment, the boot storage may be, but is not limited to, a Boot ROM, which is a small mask ROM or write-protected flash memory embedded in the processor chip, and contains the first code executed by the processor when it is powered on or reset.

[0208] Optionally, in this embodiment, the boot storage may be, but is not limited to, stored in a specific storage space on the baseboard management controller specifically configured to boot the target operating system. A processor core of the target operating system may be, but is not limited to, configured to execute a boot program stored in the boot storage, and the target operating system may be booted by, but is not limited to, executing the boot program stored in the boot storage.

[0209] Optionally, in this embodiment, the process of boot storage performing secure boot verification on the code of the secondary program loader may be, but is not limited to: the boot storage reads the code and verification code of the secondary program loader, performs operations on the code of the secondary program loader through an agreed operation method (such as a hash operation) to obtain an operation value, and then compares the operation value with the read verification code. If the two are consistent, the inspection result is normal; if the two are inconsistent, the inspection result is abnormal.

[0210] Optionally, in this embodiment, the secondary program loader can also perform a secure boot check on the code of the universal boot loader. The secondary program loader reads the code and verification code of the universal boot loader, and operates on the code of the universal boot loader through an agreed operation method (such as a hash operation, which can be the same or different from the operation method of the boot storage check secondary program loader mentioned above) to obtain an operation value, and then compares the operation value with the read verification code. If the two are consistent, the inspection result is normal; if the two are inconsistent, the inspection result is abnormal. If the inspection result is normal, the target operating system is loaded through the universal boot loader.

[0211] Optionally, in this embodiment, the key point of the architecture of the baseboard management controller provided by this application is to implement hardware resource partitioning based on processor cores in the same BMC processor. For hardware resources exclusive to a partition, they are accessed instantly by the operating system of the corresponding partition, while for hardware resources shared by the partition, access control is achieved through inter-core communication between different partition systems, ultimately achieving the effect of hardware partitioning of the server management unit, making it possible to directly apply the traditional BMC management subsystem in the host hardware partition system, effectively avoiding the increase in chip costs caused by the upgrade of the BMC processor architecture, and thus achieving the goal of reducing the design cost of the entire server system.

[0212] In this embodiment, a server is also provided, which includes: a baseboard management controller and a server host system, wherein the baseboard management controller includes a target operating system and a target hardware interface, the server host system includes multiple hardware partitions, and the target hardware interface establishes a connection between the target operating system and a target hardware partition among the multiple hardware partitions; the baseboard management controller is configured to manage the target hardware partition through the target operating system.

[0213] Through the above-mentioned server, multiple hardware interfaces are set on the baseboard management controller, and each hardware interface is set to connect the hardware partition and the operating system corresponding to the hardware partition. When the target operating system runs on the baseboard management controller, the target hardware partition among the multiple hardware partitions divided on the server host system can be managed through the target hardware interface corresponding to the target operating system. That is, by assigning a corresponding hardware interface to each operating system, different operating systems are allowed to manage the hardware partitions corresponding to the operating system divided on the server host system without modifying the system architecture of the baseboard management controller according to the architecture of different server host system hardware partitions, thereby improving the adaptability and versatility of the hardware partitions of the server host system. Therefore, the technical problem of low applicability of the hardware partitions of the server host system can be solved, and the technical effect of improving the applicability of the hardware partitions of the server host system can be achieved.

[0214] Optionally, in this embodiment, the baseboard management controller in the server can be, but is not limited to, a dedicated controller configured to monitor and manage the server, such as a BMC, based on IPMI technical design specifications, providing intelligent management of the motherboard. A BMC can have an independent arithmetic unit, a secondary controller, memory, and input / output devices. It can also have an independent software system, including a basic boot system, an operating system, and various applications running on the BMC system. On the motherboard, the BMC can be a standalone plug-in board or integrated into the motherboard, and is often designed on the motherboard of a server or computer.

[0215] Optionally, in this embodiment, the system operation method of the baseboard management controller proposed in this application is based on running multiple BMC management systems in the BMC multi-core processor hard core, and these BMC management systems run simultaneously in the same embedded system. The system operation method of the baseboard management controller proposed in this application is based on the BMC multi-core processor hard core, and the I2C, GPIO and other hardware resources of the BMC processor are partitioned according to the number of cores. These hardware partition resources and one or several BMC processor hard cores form an independent system and run an independent BMC management system; for a single hardware resource in the BMC processor, such as a PCIE controller, the physical link realizes the interconnection between the BMC processor system and multiple host systems through the PCIE switch device, and the control logic is controlled by multiple BMC management systems through inter-core communication.

[0216] In an exemplary embodiment, the server can be, but is not limited to, configured to: search for a target hardware interface corresponding to a target processor core used by a target operating system from processor cores and hardware interfaces with corresponding relationships, wherein the hardware interface on the baseboard management controller is allocated to each group of processor cores according to the hardware architecture of the hardware partition corresponding to each group of processor cores to obtain processor cores and hardware interfaces with corresponding relationships; and load the target hardware interface for the target operating system on the target processor core.

[0217] Optionally, in this embodiment, the baseboard management controller may include, but is not limited to, multiple processor cores, which are deployed and run on the same BMC multi-core processor hard core. The baseboard management controller may be divided into multiple core partitions based on the processor core, i.e., the CPU core, as the partition unit.

[0218] Optionally, in this embodiment, if the baseboard management controller includes two processor cores: core 0 and core 1, and four hardware interfaces are deployed on the baseboard management controller: hardware interface 1, hardware interface 2, hardware interface 3, and hardware interface 4, hardware interface 1 and hardware interface 2 are allocated to core 0 according to the hardware architecture of the hardware partition corresponding to core 0 (processor core), that is, hardware interface 1 and hardware interface 2 correspond to core 0; hardware interface 3 and hardware interface 4 are allocated to core 1 according to the hardware architecture of the hardware partition corresponding to core 1, that is, hardware interface 3 and hardware interface 4 correspond to core 1. Then, if the processor used by the target operating system is core 0 (target processor core), hardware interface 1 and hardware interface 2 can be found as the target hardware interfaces, thereby loading the target hardware interfaces for the target operating system on core 0.

[0219] Optionally, in this embodiment, the server host system can be, but is not limited to, an operating system installed on a computer host equipped with multiple CPU processors, typically Windows, Mac, OS and other systems, which manage the computer's hardware and software resources and provide services and interfaces for users or applications to use.

[0220] In an exemplary embodiment, the server can be configured to, but is not limited to: parse the target device tree of the target processor core to obtain the target hardware interface, wherein the hardware interface on the baseboard management controller is assigned to each group of processor cores through the device tree to obtain corresponding processor cores and hardware interfaces, and the physical address of the hardware interface on the baseboard management controller adopts a unified addressing method; load the driver of the target hardware interface on the target processor core; and boot the file system of the target operating system on the target processor core to complete the startup boot of the target operating system.

[0221] Optionally, in this embodiment, different hardware resources can be configured for different processor cores corresponding to different device tree files through, but not limited to, different device tree files, that is, the hardware interfaces on the BMC are allocated to the corresponding different processor cores through different device tree files, thereby obtaining processor cores and hardware interfaces with corresponding relationships.

[0222] In an exemplary embodiment, the server can be configured to, but is not limited to, obtain multiple hardware partitions of the host system before loading the target hardware interface for the target operating system; before loading the target hardware interface for the target operating system, allocate a processor core on the baseboard management controller to each target hardware partition in the multiple hardware partitions to obtain a target processor core, and allocate a hardware interface on the baseboard management controller to the target hardware partition to obtain a target hardware interface, wherein the target processor core at least meets the management and operation requirements of the target hardware partition, and the target hardware interface at least meets the hardware connection requirements of the target hardware partition; before loading the target hardware interface for the target operating system, establish a correspondence between the target processor core and the target hardware interface to obtain a processor core and hardware interface with a corresponding relationship.

[0223] Optionally, in this embodiment, if the baseboard management controller is divided into N core partitions according to the number N of processor cores it carries, and it is obtained that the host system has M hardware partitions, a correspondence between the M hardware partitions and the N core partitions can be established, thereby allocating a target processor core that meets the management and operation requirements of the target hardware partition to the target hardware partition among the M hardware partitions, and allocating a target hardware interface that meets the hardware connection requirements of the target hardware partition to the target hardware partition.

[0224] Optionally, in this embodiment, the hardware interfaces on the BMC can be allocated to corresponding different processor cores through, but not limited to, different device tree files, thereby establishing a correspondence between the target processor core and the target hardware interface, and obtaining processor cores and hardware interfaces with corresponding relationships.

[0225] In an exemplary embodiment, the server can be, but is not limited to, set to one of the following: evenly distributing the processor cores on the baseboard management controller to each target hardware partition; allocating one or more processor cores on the baseboard management controller to the target hardware partition according to the operating architecture of each target hardware partition in multiple hardware partitions to obtain the target processor core.

[0226] Alternatively, in this embodiment, if the baseboard management controller is divided into N core partitions based on the number N of processor cores it carries, and the host system is found to have M hardware partitions, one of the following two allocation methods can be used to allocate target processor cores to the target hardware partitions: 1. Evenly distribute the n processor cores corresponding to the N core partitions to the m target hardware partitions corresponding to the M hardware partitions. 2. Allocate one or more processor cores from the n processor cores on the baseboard management controller to the m target hardware partitions based on the operating architecture of each target hardware partition in the M hardware partitions.

[0227] Optionally, in this embodiment, if a method of allocating target processor cores to a target hardware partition based on the operating architecture is used, the following two priority allocation strategies may be employed: 1. CPU priority, which means allocating to the target hardware partition one or more processor cores that meet or are closest to the number of CPU cores required for the target hardware partition to operate. 2. Memory priority, which means allocating to the target hardware partition one or more processor cores that meet or are closest to the memory bandwidth required for the target hardware partition to operate.

[0228] In an exemplary embodiment, the target hardware interface may include, but is not limited to: a target exclusive interface and / or a target shared interface, wherein the target exclusive interface is a hardware interface that is set to allow only the target processor core where the target operating system is located to access it, and the target shared interface is a hardware interface that is set to allow the target processor core and the reference processor core in multiple groups of processor cores on the baseboard management controller to access it; the target exclusive interface is directly connected to the target hardware partition; the target shared interface is connected to the partition switch device, and the partition switch device is respectively connected to the target hardware partition and the reference hardware partition corresponding to the reference processor core.

[0229] Optionally, in this embodiment, the target hardware interface may be, but is not limited to, one or more hardware interface resources strongly related to the BMC system, such as: LPC (Low Pin Count Bus, LPC bus), I2C0-I2C5, LAN0, LAN1, and PCIE hardware interface resources. The target hardware interface may be, but is not limited to, deployed on a processor of a baseboard management controller. After the target operating system is started, the target hardware interface may be loaded for the target operating system on the BMC processor operated by the target operating system, and a connection between the target operating system and the target hardware partition may be established, thereby enabling the target operating system to manage various hardware resources in the target hardware partition.

[0230] Optionally, in this embodiment, the reference processor core may be, but is not limited to, a CPU core of one or more processors in the plurality of processor groups excluding the target processor. The target shared interface and the target exclusive interface may be, but are not limited to, uniformly addressed in the BMC management system, and multiple processor cores may have access rights to the target shared interface.

[0231] In an exemplary embodiment, the server can be, but is not limited to, set to one of the following: in the case where there is a first type of hardware interface on the baseboard management controller whose resource ownership quantity is greater than or equal to the resource requirement quantity in multiple hardware partitions, the first type of hardware interface is allocated to the target hardware partition according to the hardware architecture of each target hardware partition as a target exclusive interface in the target hardware interface, wherein the target exclusive interface is a hardware interface set to allow only the target processor core to access; in the case where there is a second type of hardware interface on the baseboard management controller whose resource ownership quantity is less than the resource requirement quantity in multiple hardware partitions, a sharing relationship for the second type of hardware interface is established between the target processor core and the reference processor core in the multiple groups of processor cores on the baseboard management controller as the target shared interface in the target hardware interface, wherein the target shared interface is a hardware interface set to allow the target processor core and the reference processor core in the multiple groups of processor cores to access.

[0232] Optionally, in this embodiment, the hardware resources deployed on the baseboard management controller may include, but are not limited to, two types: shared resources and exclusive resources. Exclusive resources may include, but are not limited to, hardware interface resources such as LPC0, LPC1, I2C0-I2C5, LAN0, and LAN1. These resources are exclusive to the core partition in which they are located and can only be accessed by the target operating system corresponding to this core partition. Shared resources may include, but are not limited to, PCIE interface resources. Shared resources are common resources for all core partitions on the baseboard management controller, meaning that the operating systems corresponding to all core partitions have access to the shared resources. A mechanism may be designed to ensure time-sharing access to shared resources by different core partitions.

[0233] Optionally, in this embodiment, that is, if the number of first-type hardware interfaces on the baseboard management controller is N, then if the number of resources owned by the N first-type hardware interfaces is greater than or equal to the number of resource requirements in multiple hardware partitions, then it means that the resources required for loading multiple hardware partitions can all be provided by N first-type hardware interfaces. At this time, the first-type hardware interface can be allocated to the target hardware partition as a target exclusive resource according to the hardware architecture of each target hardware partition, and the target exclusive resource can be used to independently run the target operating system.

[0234] Optionally, in this embodiment, that is, if the number of second-type hardware interfaces on the baseboard management controller is M, then if the number of resources owned by the M second-type hardware interfaces is less than the number of resource requirements in multiple hardware partitions, then it means that the M second-type hardware interfaces cannot be evenly distributed to multiple hardware partitions to ensure that the hardware resources of each hardware partition meet the resource requirements. At this time, a sharing relationship can be established in which both the target processor core and the reference processor core can access the second-type hardware interface, and the second-type hardware interface can be used as the target shared resource, allowing multiple processor cores to access it in time-sharing.

[0235] In an exemplary embodiment, the server can be configured, but is not limited to being configured to: send a first interrupt request to a reference processor core in multiple groups of processor cores on a baseboard management controller through the target operating system when there is a need for the target operating system to access a target shared interface in a target hardware interface, wherein the target shared interface is a hardware interface configured to allow access by the target processor core and the reference processor core used by the target operating system, and the first interrupt request is used to request the use of the target shared interface; receive a second interrupt request returned by the reference operating system running on the reference processor core in response to the first interrupt request, wherein the second interrupt request is used to indicate that the target shared interface has been released; and access the target shared interface through the target operating system in response to the second interrupt request.

[0236] Optionally, in this embodiment, the reference operating system may be, but is not limited to, one or more operating systems other than the target operating system among a plurality of operating systems running on the baseboard management controller.

[0237] Optionally, in this embodiment, after the reference operating system receives a first interrupt request requesting the use of the target shared interface, it returns a second interrupt request indicating that the target shared interface has been released in response to the first interrupt request to the target operating system, thereby completing the target operating system's access to the target shared interface.

[0238] Optionally, in this embodiment, the target operating system may, but is not limited to, send a first interrupt request to the reference operating system via inter-core communication to access the target shared interface based on its own business needs. The reference operating system then instructs the target shared interface to be released via inter-core communication and returns the release result to the target operating system via a second interrupt request, thereby enabling the target operating system to access the target shared interface. This allows multiple systems to access the target shared interface without causing conflicts.

[0239] Alternatively, in this embodiment, multiple processor cores have access rights to the target shared interface. Simultaneously accessing the target shared interface in the system will inevitably result in an access conflict, triggering a system error. Therefore, a specific access mechanism needs to be designed for the target shared interface to ensure that different partitions have correct access to it.

[0240] Optionally, in this embodiment, the target operating system and the reference operating system may exchange interrupt requests in a manner that is not limited to inter-core communication. The inter-core communication may be implemented by defining interrupt vectors.

[0241] Optionally, in this embodiment, the present application uses a custom interrupt vector table to implement inter-core communication, thereby achieving mutually exclusive access control of partition shared resources. For example, if both the target operating system and the reference operating system are Linux systems, and the baseboard management controller has two processor cores and is divided into two core partitions: Core0 partition and Core1 partition, there are 16 SGI interrupt numbers in the Linux system for inter-core communication, of which interrupt numbers 8 to 15 can be defined by the user.

[0242] In an exemplary embodiment, the server may be configured to: determine whether the target shared interface is occupied by the target operating system; and send a first interrupt request to the reference processor core by the target operating system if the target shared interface is not occupied by the target operating system.

[0243] Optionally, in this embodiment, whether the target operating system has occupied the target shared interface can be determined by judging the current usage of the target operating system's hardware resources. Taking the PCIE hardware interface as the target shared interface as an example, if the target operating system is currently using PCIE hardware resources, it can be determined that the target operating system has occupied the target shared interface, and at this time there is no need to send a first interrupt request to the reference processor core through the target operating system; if the target operating system is not currently using PCIE hardware resources, it can be determined that the target operating system does not occupy the target shared interface, and at this time it is necessary to send a first interrupt request to the reference processor core through the target operating system.

[0244] Optionally, in this embodiment, when the target operating system does not occupy the target shared interface, the core of the target operating system can find the interrupt number requesting to occupy the target shared interface in the inter-core interrupt vector configuration scheme in the embodiment of this application to send a first interrupt request to the reference processor core, thereby realizing interactive interrupt requests in the form of inter-core communication.

[0245] In an exemplary embodiment, the server can be, but is not limited to, configured to: after accessing the target shared interface through the target operating system, receive a third interrupt request sent by the reference operating system through the target operating system, wherein the third interrupt request is used to request the use of the target shared interface; after accessing the target shared interface through the target operating system, determine through the target operating system whether the target shared interface is being used; after accessing the target shared interface through the target operating system, if the target shared interface is being used, wait for the end of use of the target shared interface; after accessing the target shared interface through the target operating system, if the target shared interface is not being used or the use of the target shared interface has ended, release the target shared interface; after accessing the target shared interface through the target operating system, send a fourth interrupt request to the reference operating system through the target operating system, wherein the fourth interrupt request is used to indicate that the target shared interface has been released.

[0246] Optionally, in this embodiment, after the target operating system receives the third interrupt request sent by the reference system requesting to use the target shared interface, it can be determined whether the target operating system has occupied the target shared interface by judging the current usage of the target operating system's hardware resources. Taking the PCIE hardware interface as the target shared interface as an example, if the target operating system is currently using PCIE hardware resources, it can be determined that the target operating system has occupied the target shared interface. At this time, it is necessary to wait for the PCIE hardware interface to be used up. After the use is completed, the target operating system releases the PCIE hardware interface; if the target operating system is not currently using PCIE hardware resources, it can be determined that the target operating system does not occupy the target shared interface, and the target operating system releases the PCIE hardware interface.

[0247] Optionally, in this embodiment, when the target operating system does not occupy the target shared interface or the target system occupies the target shared interface but has completed use, the core of the target operating system can find the interrupt number indicating that the target shared interface has been released in the inter-core interrupt vector configuration scheme in the embodiment of this application to send a fourth interrupt request to the reference processor core, thereby notifying the reference operating system processing core that needs to use the target shared interface that the target shared interface is currently available, thereby realizing interactive interrupt requests in the form of inter-core communication.

[0248] In this embodiment, each interrupt request may be transmitted between systems in a manner including, but not limited to, a software protocol, or may be transmitted through a hardware module.

[0249] In an exemplary embodiment, the server may be configured to: execute a secondary program loader on a baseboard management controller to load a universal boot loader; and start a kernel of a corresponding target operating system on each group of processor cores through the universal boot loader.

[0250] Optionally, in this embodiment, the secondary program loader may be, but is not limited to, a program loader that compiles SPL (secondary program loader) code, which is mainly responsible for initializing the external RAM and environment, and loading the Uboot image into the external RAM for execution.

[0251] Optionally, in this embodiment, the universal boot loader can be, but is not limited to, a boot loader that can start the operating system kernel and can deploy and load the entire computer system, such as: Uboot loader (universal boot loader, an open source project that complies with the GPL terms and is used for system booting).

[0252] In an exemplary embodiment, the server can be configured to, but is not limited to: power on the baseboard management controller and wake up a processor core; boot the boot program in the boot storage on a processor core to execute; perform a secure boot check on the secondary program loader through the boot program; and if the secondary program loader passes the secure boot check, execute the secondary program loader to boot the universal boot loader to execute the code.

[0253] Optionally, in this embodiment, the target operating system's boot program may be, but is not limited to, stored in a specific storage space on the baseboard management controller specifically for booting the target operating system. A processor core of the target operating system may be, but is not limited to, configured to execute the target operating system's boot program, and the target operating system may be booted by, but is not limited to, executing the target operating system's boot program.

[0254] Optionally, in this embodiment, the process of the boot program performing a secure boot check on the code of the secondary program loader may be, but is not limited to, as follows: the boot program reads the code and verification code of the secondary program loader, performs an operation on the code of the secondary program loader through an agreed operation method (such as a hash operation) to obtain an operation value, and then compares the operation value with the read verification code. If the two are consistent, the inspection result is normal; if the two are inconsistent, the inspection result is abnormal.

[0255] Optionally, in this embodiment, the secondary program loader can also perform a secure boot check on the code of the universal boot loader. The secondary program loader reads the code and verification code of the universal boot loader, and operates on the code of the universal boot loader through an agreed operation method (such as a hash operation, which can be the same or different from the operation method of the boot memory to check the secondary program loader) to obtain an operation value, and then compares the operation value with the read verification code. If the two are consistent, the inspection result is normal; if the two are inconsistent, the inspection result is abnormal. If the inspection result is normal, the target operating system is loaded through the universal boot loader.

[0256] Optionally, in this embodiment, the boot storage may be, but is not limited to, a Boot ROM, which is a small mask ROM or write-protected flash memory embedded in the processor chip, and contains the first code executed by the processor when it is powered on or reset.

[0257] Optionally, in this embodiment, the architecture of the server management unit hardware resource partitioning system proposed in this application comprehensively partitions all hardware resources of the BMC processor according to the different cores of the processor based on the interconnection topology of the management system and the Host system. Different BMC processing cores independently manage different hardware resources, thereby achieving the effect of running multiple management systems in parallel on the same BMC processor.

[0258] In this embodiment, a system operation device for a baseboard management controller is also provided. The device is configured to implement the above-mentioned embodiments and optional implementations. Details that have already been described will not be repeated. As used below, the term "module" may refer to a combination of software and / or hardware that implements a predetermined function. Although the devices described in the following embodiments are preferably implemented in software, implementation using hardware, or a combination of software and hardware, is also possible and contemplated.

[0259] FIG7 is a structural block diagram of a system operation device of a baseboard management controller according to an embodiment of the present application. As shown in FIG7 , the device includes:

[0260] A startup module 702 is configured to start a target operating system on the baseboard management controller, wherein the target operating system is used to manage a target hardware partition among a plurality of hardware partitions divided on the server host system;

[0261] A loading module 704 is configured to load a target hardware interface for a target operating system, wherein the target hardware interface is a target hardware interface configured to establish a connection between the target operating system and a target hardware partition;

[0262] The running module 706 is configured to run a target operating system on the baseboard management controller, wherein the target operating system is used to manage the target hardware partition through the target hardware interface.

[0263] Through the above-mentioned device, multiple hardware interfaces are set on the baseboard management controller, and each hardware interface is set to connect the hardware partition and the operating system corresponding to the hardware partition. When the target operating system runs on the baseboard management controller, the target hardware partition among the multiple hardware partitions divided on the server host system can be managed through the target hardware interface corresponding to the target operating system. That is, by assigning a corresponding hardware interface to each operating system, different operating systems are allowed to manage the hardware partitions corresponding to the operating system divided on the server host system without having to modify the system architecture of the baseboard management controller according to the architecture of different server host system hardware partitions, thereby improving the adaptability and versatility of the hardware partitions of the server host system. Therefore, the technical problem of low applicability of the hardware partitions of the server host system can be solved, and the technical effect of improving the applicability of the hardware partitions of the server host system can be achieved.

[0264] In an exemplary embodiment, the startup module includes: a first loading unit, configured to execute a secondary program loader on a baseboard management controller to load a universal boot loader; and a startup unit, configured to start the kernel of the corresponding target operating system on each group of processor cores through the universal boot loader.

[0265] In an exemplary embodiment, the first loading unit is configured to: power on the baseboard management controller and wake up a processor core; guide the execution of the boot program in the boot storage on a processor core; perform a secure boot check on the secondary program loader through the boot program; and if the secondary program loader passes the secure boot check, execute the secondary program loader to guide the universal boot loader to execute the code.

[0266] In an exemplary embodiment, a loading module includes: a search unit, configured to search for a target hardware interface corresponding to a target processor core used by a target operating system from processor cores and hardware interfaces with corresponding relationships, wherein the hardware interface on the baseboard management controller is allocated to each group of processor cores according to the hardware architecture of the hardware partition corresponding to each group of processor cores to obtain processor cores and hardware interfaces with corresponding relationships; a second loading unit, configured to load the target hardware interface for the target operating system on the target processor core.

[0267] In an exemplary embodiment, the second loading unit is configured to: parse the target device tree of the target processor core to obtain the target hardware interface, wherein the hardware interface on the baseboard management controller is allocated to each group of processor cores through the device tree to obtain corresponding processor cores and hardware interfaces, and the physical address of the hardware interface on the baseboard management controller adopts a unified addressing method; load the driver of the target hardware interface on the target processor core; and boot the file system of the target operating system on the target processor core to complete the startup boot of the target operating system.

[0268] In an exemplary embodiment, the system operation device of the baseboard management controller also includes: an acquisition module, which is configured to acquire multiple hardware partitions of the host system before loading the target hardware interface for the target operating system; an allocation module, which is configured to allocate a processor core on the baseboard management controller to each target hardware partition in the multiple hardware partitions to obtain a target processor core, and allocate a hardware interface on the baseboard management controller to the target hardware partition to obtain a target hardware interface before loading the target hardware interface for the target operating system, wherein the target processor core at least meets the management and operation requirements of the target hardware partition, and the target hardware interface at least meets the hardware connection requirements of the target hardware partition; an establishment module, which is configured to establish a correspondence between the target processor core and the target hardware interface before loading the target hardware interface for the target operating system, and obtain a processor core and hardware interface with a corresponding relationship.

[0269] In an exemplary embodiment, the allocation module includes one of the following: a first allocation unit, configured to evenly allocate processor cores on a baseboard management controller to each target hardware partition; and a second allocation unit, configured to allocate one or more processor cores on the baseboard management controller to the target hardware partition according to the operating architecture of each target hardware partition in a plurality of hardware partitions to obtain a target processor core.

[0270] In an exemplary embodiment, the allocation module further includes one of the following: a third allocation unit, which is configured to allocate the first type of hardware interface to the target hardware partition as a target exclusive interface in the target hardware interface according to the hardware architecture of each target hardware partition when there is a first type of hardware interface on the baseboard management controller whose resource ownership quantity is greater than or equal to the resource requirement quantity in multiple hardware partitions, wherein the target exclusive interface is a hardware interface configured to allow only the target processor core to access; an establishment unit, which is configured to establish a sharing relationship of the second type of hardware interface between the target processor core and the reference processor core in the multiple groups of processor cores on the baseboard management controller as a target shared interface in the target hardware interface when there is a second type of hardware interface on the baseboard management controller whose resource ownership quantity is less than the resource requirement quantity in multiple hardware partitions, wherein the target shared interface is a hardware interface configured to allow the target processor core and the reference processor core in the multiple groups of processor cores to access.

[0271] In an exemplary embodiment, an operation module includes: a first sending unit, configured to send a first interrupt request to a reference processor core in multiple groups of processor cores on a baseboard management controller through a target operating system when a target operating system has a need to access a target shared interface in a target hardware interface, wherein the target shared interface is a hardware interface configured to allow the target processor core and the reference processor core used by the target operating system to access, and the first interrupt request is configured to request the use of the target shared interface; a first receiving unit, configured to receive a second interrupt request returned by the reference operating system running on the reference processor core in response to the first interrupt request, wherein the second interrupt request is configured to indicate that the target shared interface has been released; and an access unit, configured to access the target shared interface through the target operating system in response to the second interrupt request.

[0272] In an exemplary embodiment, the first sending unit is configured to: determine whether the target shared interface is occupied through the target operating system; and send a first interrupt request to the reference processor core through the target operating system if the target shared interface is not occupied by the target operating system.

[0273] In an exemplary embodiment, the running module further includes: a second receiving unit, which is configured to receive a third interrupt request sent by the reference operating system through the target operating system, wherein the third interrupt request is configured to request the use of the target shared interface; a determining unit, which is configured to determine whether the target shared interface is being used through the target operating system; a waiting unit, which is configured to wait for the end of use of the target shared interface when the target shared interface is being used; a releasing unit, which is configured to release the target shared interface when the target shared interface is not in use or when the use of the target shared interface is ended; a second sending unit, which is configured to send a fourth interrupt request to the reference operating system through the target operating system, wherein the fourth interrupt request is used to indicate that the target shared interface has been released.

[0274] It should be noted that the above modules can be implemented by software or hardware. For the latter, it can be implemented in the following ways, but not limited to: all the above modules are located in the same processor; or the above modules are located in different processors in any combination.

[0275] The communication bus of the server may be a PCI (Peripheral Component Interconnect) bus or an EISA (Extended Industry Standard Architecture) bus. The communication bus may be divided into an address bus, a data bus, a control bus, etc. A communication interface is provided for communication between the server and other devices.

[0276] The memory may include RAM (Random Access Memory) or NVM (Non-Volatile Memory), such as at least one disk storage. Optionally, the memory may also be at least one storage device located away from the aforementioned processor. The aforementioned processor may be a general-purpose processor, including a CPU (Central Processing Unit), an NP (Network Processor), etc.; it may also be a DSP (Digital Signal Processing), an ASIC (Application Specific Integrated Circuit), an FPGA (Field-Programmable Gate Array) or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components.

[0277] For servers, they must at least have the characteristics of high scalability and high stability. Among them, since the enterprise network cannot remain unchanged for a long time, in today's network informatization, if the server does not have a certain scalability, it will affect the future development of the enterprise and affect the use of the enterprise. Therefore, scalability has become the most basic feature. Only with higher scalability can better utilization in the future be guaranteed. In addition to hardware scalability, scalability also includes software scalability. Since the functions of servers are still very complex compared to computers, not only hardware configuration, but also software configuration is very important. If you want to achieve more functions, it is unimaginable without comprehensive software support.

[0278] In addition, since the server needs to process a large amount of data to support the continuous operation of the business, the server also has a very important feature, which is high stability. If the server's data transmission cannot run stably, it will undoubtedly have a great impact on business development.

[0279] The solution server of this application can achieve comprehensive and flexible access to the hardware controller by the operating system, whether expanding software resources or hardware resources, thereby improving the scalability of the server. In addition, through the above-mentioned operating system access mechanism to the hardware controller, the hardware controller can be made to operate more stably, thereby improving the stability of the server.

[0280] An embodiment of the present application further provides a non-volatile readable storage medium, in which a computer program is stored. The computer program is configured to execute the steps of any of the above method embodiments when running.

[0281] In an exemplary embodiment, the above-mentioned non-volatile readable storage medium may include, but is not limited to: a USB flash drive, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk or an optical disk, and other non-volatile readable storage media that can store computer programs.

[0282] An embodiment of the present application also provides an example of an electronic device, wherein Figure 8 is a schematic diagram of an electronic device according to an embodiment of the present application. As shown in Figure 8, the electronic device includes one or more processors; a memory, which is configured to store one or more programs, and when the one or more programs are executed by one or more processors, the one or more processors are configured to run the programs, wherein the programs are configured to execute the above-mentioned system operation method of the baseboard management controller when running.

[0283] In an exemplary embodiment, the electronic device may further include a transmission device and an input / output device, wherein the transmission device is connected to the processor, and the input / output device is connected to the processor.

[0284] For optional examples in this embodiment, reference may be made to the examples described in the above embodiments and exemplary implementations, and this embodiment will not be described in detail here.

[0285] Obviously, those skilled in the art should understand that the modules or steps of the present application described above can be implemented using a general-purpose computing device, they can be concentrated on a single computing device, or distributed across a network composed of multiple computing devices, they can be implemented using program code executable by the computing device, and thus, they can be stored in a storage device and executed by the computing device, and in some cases, the steps shown or described can be performed in a different order than herein, or they can be fabricated into separate integrated circuit modules, or multiple modules or steps can be fabricated into a single integrated circuit module for implementation. Thus, the present application is not limited to any specific combination of hardware and software.

[0286] The above are merely optional embodiments of the present application and are not intended to limit the present application. For those skilled in the art, the present application may be subject to various modifications and variations. Any modifications, equivalent substitutions, improvements, etc. made within the principles of the present application shall be included in the scope of protection of the present application.

Claims

1. A system operation method of a baseboard management controller, characterized in that: include: Starting a target operating system on the baseboard management controller, wherein the target operating system is used to manage a target hardware partition among a plurality of hardware partitions divided on a server host system; loading a target hardware interface for the target operating system, wherein the target hardware interface is configured to establish a connection between the target operating system and the target hardware partition; The target operating system is run on the baseboard management controller, wherein the target operating system is used to manage the target hardware partition through the target hardware interface.

2. The method according to claim 1, characterized in that The step of loading a target hardware interface for the target operating system includes: Searching for the target hardware interface corresponding to the target processor core used by the target operating system from the processor cores and hardware interfaces having a corresponding relationship, wherein the hardware interface on the baseboard management controller is allocated to each group of processor cores according to the hardware architecture of the hardware partition corresponding to each group of processor cores to obtain the processor cores and hardware interfaces having a corresponding relationship; The target hardware interface is loaded for the target operating system on the target processor core.

3. The method according to claim 2, characterized in that The step of loading the target hardware interface for the target operating system on the target processor core includes: Parsing the target device tree of the target processor core to obtain the target hardware interface, wherein the hardware interface on the baseboard management controller is allocated to each group of processor cores through the device tree to obtain processor cores and hardware interfaces with corresponding relationships, and the physical addresses of the hardware interfaces on the baseboard management controller adopt a unified addressing method; Loading a driver for the target hardware interface on the target processor core; The file system of the target operating system is booted on the target processor core to complete the startup booting of the target operating system.

4. The method according to claim 2, characterized in that: Before loading the target hardware interface for the target operating system, the method further includes: Acquire the multiple hardware partitions of the host system; Allocating a processor core on the baseboard management controller to each of the target hardware partitions in the multiple hardware partitions to obtain the target processor core, and allocating a hardware interface on the baseboard management controller to the target hardware partition to obtain the target hardware interface, wherein the target processor core at least meets the management and operation requirements of the target hardware partition, and the target hardware interface at least meets the hardware connection requirements of the target hardware partition; A corresponding relationship between the target processor core and the target hardware interface is established to obtain a processor core and a hardware interface having a corresponding relationship.

5. The method according to claim 4, characterized in that The step of allocating a processor core on the baseboard management controller to each of the target hardware partitions in the multiple hardware partitions to obtain the target processor core comprises one of the following: Evenly distribute the processor cores on the baseboard management controller to each of the target hardware partitions; According to the operation architecture of each target hardware partition in the multiple hardware partitions, one or more processor cores on the baseboard management controller are allocated to the target hardware partition to obtain the target processor core.

6. The method according to claim 4, characterized in that The step of allocating a hardware interface on the baseboard management controller to the target hardware partition to obtain the target hardware interface includes at least one of the following: In the case where there is a first type of hardware interface on the baseboard management controller, the first type of hardware interface is allocated to the target hardware partition as a target exclusive interface in the target hardware interface according to the hardware architecture of each target hardware partition, wherein the target exclusive interface is a hardware interface that is set to allow only the target processor core to access; In the case where there is a second type of hardware interface on the baseboard management controller whose number of resources is less than the number of resources required in the multiple hardware partitions, a sharing relationship for the second type of hardware interface is established between the target processor core and a reference processor core in the multiple groups of processor cores on the baseboard management controller as a target shared interface in the target hardware interface, wherein the target shared interface is a hardware interface that is configured to allow the target processor core and the reference processor core in the multiple groups of processor cores to access.

7. The method according to claim 1, characterized in that Running the target operating system on the baseboard management controller includes: In a case where the target operating system has a need to access a target shared interface in the target hardware interface, sending a first interrupt request to a reference processor core in the plurality of processor cores on the baseboard management controller through the target operating system, wherein the target shared interface is a hardware interface configured to allow access by the target processor core and the reference processor core used by the target operating system, and the first interrupt request is used to request use of the target shared interface; Receiving a second interrupt request returned by a reference operating system running on the reference processor core in response to the first interrupt request, wherein the second interrupt request is used to indicate that the target shared interface has been released; In response to the second interrupt request, the target shared interface is accessed through the target operating system.

8. The method according to claim 7, characterized in that The sending a first interrupt request to a reference processor core in a plurality of groups of processor cores on the baseboard management controller through the target operating system comprises: Determining, by the target operating system, whether the target shared interface has been occupied; In a case where the target operating system does not occupy the target shared interface, the first interrupt request is sent to the reference processor core through the target operating system.

9. The method according to claim 7, characterized in that: After accessing the target shared interface through the target operating system, the method further includes: Receiving, by the target operating system, a third interrupt request sent by the reference operating system, wherein the third interrupt request is used to request to use the target shared interface; Determining, by the target operating system, whether the target shared interface is being used; When the target shared interface is being used, waiting for the target shared interface to be finished being used; When the target shared interface is not used or the use of the target shared interface is finished, releasing the target shared interface; A fourth interrupt request is sent to the reference operating system through the target operating system, wherein the fourth interrupt request is used to indicate that the target shared interface has been released.

10. The method according to claim 1, characterized in that The starting the target operating system on the baseboard management controller includes: Executing a secondary program loader on the baseboard management controller to load a universal boot loader; The kernel of the corresponding target operating system is started on each group of processor cores through the universal boot loader.

11. The method according to claim 10, characterized in that The step of executing a secondary program loader on the baseboard management controller to load a universal boot loader includes: The baseboard management controller powers on and wakes up a processor core; Directing execution of a boot program in the boot storage on the one processor core; Performing a secure boot check on the secondary program loader through the boot program; In a case where the secondary program loader passes the secure boot check, the secondary program loader is executed to guide the universal boot loader to execute code.

12. A baseboard management controller, characterized in that: include: Target operating system and target hardware interface, where The target hardware interface is configured to connect the target operating system with a target hardware partition among a plurality of hardware partitions divided on the server host system; The target operating system is used to manage the target hardware partition through the target hardware interface.

13. The baseboard management controller according to claim 12, characterized in that: The target hardware interface includes: a target exclusive interface and / or a target shared interface, wherein: The target exclusive interface is a hardware interface that is configured to allow only the target processor core where the target operating system is located to access; The target shared interface is a hardware interface configured to allow access by the target processor core and a reference processor core in a plurality of groups of processor cores on the baseboard management controller.

14. The baseboard management controller according to claim 12, characterized in that: A target device tree is deployed in the target operating system, and the target device tree is used to load the driver of the target hardware interface. The physical address of the hardware interface on the baseboard management controller adopts a unified addressing method.

15. The baseboard management controller according to claim 14, characterized in that: The baseboard management controller further includes: a universal boot loader, wherein: The universal boot loader is configured to start a kernel of the corresponding target operating system on each group of processor cores on the baseboard management controller; The kernel of the target operating system is configured to parse the target device tree and load the driver of the target hardware interface.

16. The baseboard management controller according to claim 15, characterized in that: The baseboard management controller further includes: a secondary program loader, wherein: The secondary program loader is configured to guide the universal boot loader to execute code.

17. The baseboard management controller according to claim 16, characterized in that: The baseboard management controller further includes: a boot storage, wherein: The boot storage is configured to perform a secure boot check on the secondary program loader.

18. A server, characterized in that: include: Baseboard management controller and server host system, wherein, The baseboard management controller includes a target operating system and a target hardware interface, the server host system includes a plurality of hardware partitions, and the target hardware interface establishes a connection between the target operating system and a target hardware partition among the plurality of hardware partitions; The baseboard management controller is configured to manage the target hardware partition through the target operating system.

19. The server according to claim 18, characterized in that The target hardware interface includes: a target exclusive interface and / or a target shared interface, wherein: The target exclusive interface is a hardware interface that is set to allow only the target processor core where the target operating system is located to access, and the target shared interface is a hardware interface that is set to allow the target processor core and a reference processor core in a plurality of groups of processor cores on the baseboard management controller to access; The target exclusive interface is directly connected to the target hardware partition; The target shared interface is connected to a partition switch device, and the partition switch device is respectively connected to the target hardware partition and a reference hardware partition corresponding to the reference processor core.

20. A system operation device of a baseboard management controller, characterized in that: include: A startup module is configured to start a target operating system on the baseboard management controller, wherein the target operating system is used to manage a target hardware partition among a plurality of hardware partitions divided on a server host system; A loading module, configured to load a target hardware interface for the target operating system, wherein the target hardware interface is configured to establish a connection between the target operating system and the target hardware partition; The running module is configured to run the target operating system on the baseboard management controller, wherein the target operating system is used to manage the target hardware partition through the target hardware interface.

21. A non-volatile readable storage medium, characterized in that: The non-volatile readable storage medium stores a computer program, wherein the computer program implements the steps of the method described in any one of claims 1 to 11 when executed by a processor.

22. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that: When the processor executes the computer program, the steps of the method described in any one of claims 1 to 11 are implemented.

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