Thin film transistor and manufacturing method therefor, and light-emitting substrate

Abstract

Disclosed is a thin film transistor. The thin film transistor comprises a base, an active layer, a first gate, a second gate, a first electrode, and a second electrode. The active layer comprises a channel, and a first heavily doped region and a second heavily doped region which are located on the two sides of the channel. The first gate is located on the side of the active layer close to the base. The second gate is located on the side of the active layer distant from the first gate, and the orthographic projection of the first gate on the base at least partially overlaps with the orthographic projection of the second heavily doped region on the base. The first electrode comprises a first main body portion and a first via hole connecting portion, and the second electrode comprises a second main body portion and a second via hole connecting portion. The first main body portion and the second main body portion are located on the side of the second gate distant from the active layer. The first via hole connecting portion is electrically connected to the first main body portion and the first heavily doped region. The second via hole connecting portion is electrically connected to the second main body portion and is electrically connected to the second heavily doped region and the first gate, and the orthographic projection of the second via hole connecting portion on the base is located within the orthographic projection of the second heavily doped region on the base.

Description

Thin film transistor, manufacturing method thereof, and light-emitting substrate

[0001] This application claims priority to Chinese patent application No. 202310906761.2, filed on July 21, 2023, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present disclosure relates to the field of display technology, and in particular to a thin film transistor, a manufacturing method thereof, and a light-emitting substrate. Background Art

[0003] Due to inherent defects in amorphous silicon (a-Si), such as low on-state current, low mobility, and poor stability caused by numerous defect states, its application in many fields is limited. To compensate for these defects and expand the application of related products in related fields, low-temperature polycrystalline silicon (LTPS, or p-Si) technology has emerged.

[0004] Summary of the Invention

[0005] In one aspect, a thin film transistor is provided. The thin film transistor comprises a substrate, an active layer, a first gate, a second gate, a first electrode, and a second electrode. The active layer is located on one side of the substrate and includes a channel and a first heavily doped region and a second heavily doped region located on either side of the channel. The first gate is located on the side of the active layer closest to the substrate. The second gate is located on the side of the active layer away from the first gate, and the orthographic projection of the first gate on the substrate at least partially overlaps with the orthographic projection of the second heavily doped region on the substrate. The first electrode includes a first main portion and a first via connecting portion, and the second electrode includes a second main portion and a second via connecting portion. The first main portion and the second main portion are located on the side of the second gate away from the active layer. The first via connecting portion electrically connects the first main portion and the first heavily doped region. The second via connecting portion electrically connects the second main portion, the second heavily doped region, and the first gate, and the orthographic projection of the second via connecting portion on the substrate is located within the orthographic projection of the second heavily doped region on the substrate.

[0006] In some embodiments, the second heavily doped region includes at least one via, one end of the second via connecting portion is electrically connected to the second electrode, and the other end of the second via connecting portion passes through the via and is electrically connected to the first gate.

[0007] In some embodiments, an orthographic projection of the first gate on the substrate does not overlap with an orthographic projection of the via on the substrate.

[0008] In some embodiments, a minimum distance between an orthographic projection of the first gate on the substrate and an orthographic projection of the via on the substrate is greater than or equal to 0.5 μm.

[0009] In some embodiments, the orthographic projection of the channel on the substrate is located within the orthographic projection of the first gate on the substrate, and the minimum distance between the outer edge of the orthographic projection of the first gate on the substrate and the outer edge of the orthographic projection of the channel on the substrate is greater than or equal to 0.5 μm.

[0010] In some embodiments, the orthographic projection of the second heavily doped region on the substrate is located within the orthographic projection of the first gate on the substrate.

[0011] In some embodiments, along a first direction, the first gate includes a first side and a second side that are oppositely disposed, and the first side is located on a side of the second side that is closer to the first via connection portion. The first direction is the direction from the first pole to the second pole. The minimum distance between an orthographic projection of the second side of the first gate on the substrate and an orthographic projection of a third side of the second heavily doped region on a side away from the first heavily doped region on the substrate is greater than or equal to 0.5 μm.

[0012] In some embodiments, a minimum distance between an orthographic projection of the second side of the first gate on the substrate and an orthographic projection of a third side of the second heavily doped region away from the first heavily doped region on the substrate is less than or equal to 10 μm.

[0013] In some embodiments, one end of the second via connection portion is electrically connected to the second main body portion of the second electrode, and the other end of the second via connection portion is electrically connected to the first gate through the second heavily doped region.

[0014] In some embodiments, a minimum distance between an outer edge of an orthographic projection of the first gate on the substrate and an outer edge of an orthographic projection of the channel on the substrate is greater than or equal to 0.5 μm.

[0015] In some embodiments, an orthographic projection of the active layer on the substrate is located within an orthographic projection of the first gate on the substrate.

[0016] In some embodiments, the orthographic projection of the channel on the substrate is located within the orthographic projection of the first gate on the substrate, and the minimum distance between the outer edge of the orthographic projection of the first gate on the substrate and the outer edge of the orthographic projection of the active layer on the substrate is greater than or equal to 0.5 μm.

[0017] In some embodiments, a minimum distance between an outer edge of an orthographic projection of the first gate on the substrate and an outer edge of an orthographic projection of the active layer on the substrate is less than or equal to 10 μm.

[0018] In some embodiments, the active layer further includes a first low-doped region and a second low-doped region. The first low-doped region is located between the first heavily doped region and the channel, and the doping concentration of the first low-doped region is lower than the doping concentration of the first heavily doped region. The second low-doped region is located between the second heavily doped region and the channel, and the doping concentration of the second low-doped region is lower than the doping concentration of the second heavily doped region.

[0019] In some embodiments, a projection of the second gate on the substrate substantially coincides with a projection of the channel on the substrate.

[0020] In some embodiments, the thickness of the active layer ranges from

[0021] In another aspect, a method for manufacturing a thin-film transistor is provided. The method comprises: forming a first gate on one side of a substrate; forming an active layer on a side of the substrate remote from the first gate, the active layer comprising a channel and a first to-be-doped region and a second to-be-doped region located on either side of the channel, the orthographic projection of the first gate on the substrate at least partially overlapping the orthographic projection of the second to-be-doped region on the substrate; forming a second gate on a side of the active layer remote from the substrate; performing a conductorization process on the first to-be-doped region and the second to-be-doped region to form corresponding first heavily doped regions and second heavily doped regions; forming a first electrode and a second electrode on a side of the first gate remote from the substrate, the first electrode comprising a first via connection electrically connected to the first heavily doped region; the second electrode comprising a second via connection electrically connected to the second heavily doped region and the first gate, the orthographic projection of the second via connection on the substrate being located within the orthographic projection of the second heavily doped region on the substrate.

[0022] In some embodiments, before forming the first electrode and the second electrode on a side of the first gate away from the substrate, the method further includes forming a via hole in the second heavily doped region. Furthermore, forming the second electrode includes: the second via hole connecting portion of the second electrode passing through the via hole to be electrically connected to the first gate.

[0023] In another aspect, a method for fabricating a thin-film transistor is provided. The method includes forming a first gate on one side of a substrate. Forming an active layer on a side of the substrate remote from the first gate, the active layer including a channel and a first to-be-doped region and a second to-be-doped region located on either side of the channel. The orthographic projection of the first gate on the substrate at least partially overlaps with the orthographic projection of the second to-be-doped region on the substrate, and the second to-be-doped region includes a third via connection electrically connected to the first gate. Forming a second gate on a side of the active layer remote from the substrate. Conducting the first to-be-doped region and the second to-be-doped region to form corresponding first and second heavily doped regions. Forming a first electrode and a second electrode on a side of the first gate remote from the substrate, the first electrode including a first via connection electrically connected to the first heavily doped region. The second electrode including a second via connection electrically connected to the second heavily doped region, and the orthographic projection of the second via connection on the substrate being located within the orthographic projection of the second heavily doped region on the substrate.

[0024] In another aspect, a light-emitting substrate is provided, comprising: a thin film transistor according to any of the above embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] To more clearly illustrate the technical solutions of the present disclosure, the following briefly introduces the drawings required for use in some embodiments of the present disclosure. Obviously, the drawings described below are only drawings of some embodiments of the present disclosure, and those skilled in the art can also derive other drawings based on these drawings. Furthermore, the drawings described below are schematic diagrams and are not intended to limit the actual dimensions of the products, actual processes of the methods, actual timing of signals, and the like involved in the embodiments of the present disclosure.

[0026] FIG1 is a structural diagram of a display device according to some embodiments;

[0027] FIG2 is a structural diagram of a light-emitting substrate according to some embodiments;

[0028] FIG3 is a circuit diagram of a light emitting driving circuit according to some embodiments;

[0029] FIG4 is a structural diagram of a thin film transistor according to some embodiments;

[0030] FIG5 is a structural diagram of a thin film transistor according to some embodiments;

[0031] FIG6 is a diagram of film layers of a thin film transistor according to some embodiments;

[0032] FIG7 is a structural diagram of a thin film transistor according to some other embodiments;

[0033] FIG8 is a film layer diagram of a thin film transistor according to some other embodiments;

[0034] FIG9 is a film layer diagram of a thin film transistor according to yet other embodiments;

[0035] FIG10 is a film layer diagram of a thin film transistor according to yet other embodiments;

[0036] FIG11 is a flow chart of a method for manufacturing a thin film transistor according to some embodiments;

[0037] FIG12 is a diagram of the film structure corresponding to the steps in FIG11;

[0038] FIG13 is a top view corresponding to some steps in FIG11;

[0039] FIG14 is a top view corresponding to other steps in FIG11;

[0040] FIG15 is a diagram of the film structure corresponding to step S14 in FIG11 ;

[0041] FIG16 is a top view corresponding to step S14 in FIG11 ;

[0042] FIG17 is a flow chart of a method for manufacturing a thin film transistor according to some other embodiments;

[0043] FIG18 is a diagram of the film structure corresponding to the steps in FIG17;

[0044] FIG. 19 is a structural diagram illustrating some steps of a method for manufacturing a thin film transistor according to some embodiments. DETAILED DESCRIPTION

[0045] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present disclosure. Obviously, the embodiments described are only some embodiments of the present disclosure, not all embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by ordinary technicians in this field are within the scope of protection of the present disclosure.

[0046] Unless the context requires otherwise, throughout the specification and claims, the term "comprise" and its other forms, such as the third person singular form "comprises" and the present participle form "comprising", are to be interpreted as open and inclusive, that is, "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "example", "specific example" or "some examples" are intended to indicate that the particular features, structures, materials or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present disclosure. The schematic representation of the above terms does not necessarily refer to the same embodiment or example. In addition, the particular features, structures, materials or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

[0047] In the following, the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of the technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.

[0048] When describing some embodiments, the expressions "coupled" and "connected" and their derivatives may be used. The term "connected" should be understood in a broad sense. For example, "connection" can be a fixed connection, a detachable connection, or an integral connection; it can be directly connected or indirectly connected through an intermediate medium. The term "coupled" indicates, for example, that two or more components are in direct physical or electrical contact. The term "coupled" or "communicatively coupled" may also refer to two or more components that are not in direct contact with each other, but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the contents of this document.

[0049] “At least one of A, B and C” has the same meaning as “at least one of A, B or C” and both include the following combinations of A, B and C: A only, B only, C only, the combination of A and B, the combination of A and C, the combination of B and C, and the combination of A, B and C.

[0050] “A and / or B” includes the following three combinations: A only, B only, and a combination of A and B.

[0051] As used herein, the term "if" is optionally interpreted to mean "when" or "upon" or "in response to determining" or "in response to detecting," depending on the context. Similarly, the phrases "if it is determined that" or "if [stated condition or event] is detected" are optionally interpreted to mean "upon determining" or "in response to determining" or "upon detecting [stated condition or event]" or "in response to detecting [stated condition or event]," depending on the context.

[0052] The use of "adapted to" or "configured to" herein is intended to be open and inclusive language that does not exclude devices adapted or configured to perform additional tasks or steps.

[0053] Additionally, the use of “based on” is meant to be open and inclusive, as a process, step, calculation, or other action “based on” one or more stated conditions or values ​​may, in practice, be based on additional conditions or values ​​beyond those stated.

[0054] As used herein, "about," "substantially," or "approximately" includes the stated value and an average value that is within an acceptable range of deviation from the particular value as determined by one of ordinary skill in the art taking into account the measurements in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system).

[0055] As used herein, "perpendicular" includes the conditions described and conditions similar to the conditions described, where the range of the similar conditions is within an acceptable range of deviation, where the acceptable range of deviation is determined by one of ordinary skill in the art taking into account the measurement in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system). For example, "perpendicular" includes both absolute perpendicularity and approximately perpendicularity, where the acceptable range of deviation for approximately perpendicularity can be, for example, within 5°.

[0056] It will be understood that when a layer or element is referred to as being on another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may be present therebetween.

[0057] Exemplary embodiments are described herein with reference to cross-sectional and / or plan views that are idealized exemplary drawings. In the drawings, the thickness of layers and the area of ​​regions are exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are contemplated. Therefore, the exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include deviations in shape due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of regions of the device and are not intended to limit the scope of the exemplary embodiments.

[0058] FIG. 1 is a structural diagram of a display device according to some embodiments.

[0059] Some embodiments of the present disclosure provide a display device. Referring to FIG. 1 , the display device 300 includes a light-emitting substrate 200 .

[0060] In some examples, the display device 300 can be any device that displays an image, whether in motion (e.g., video) or stationary (e.g., still image), and whether textual or graphic. More specifically, it is contemplated that the embodiments described may be implemented in or associated with a variety of electronic devices, such as, but not limited to, mobile phones, wireless devices, personal data assistants (PDAs), handheld or portable computers, GPS receivers / navigators, cameras, MP4 video players, video cameras, game consoles, watches, clocks, calculators, television monitors, flat-panel displays, computer monitors, automotive displays (e.g., speedometer displays, etc.), navigation systems, cockpit controls and / or displays, displays of camera views (e.g., displays of rearview cameras in vehicles), electronic photographs, electronic billboards or signs, projectors, architectural structures, packaging, and aesthetic structures (e.g., displays of images of a piece of jewelry), and the like.

[0061] Exemplarily, the display device 300 can be a liquid crystal display device (full name in English: Liquid Crystal Display, English abbreviation: LCD), a mini light-emitting display device (full name in English: Mini Light-Emitting Diode, English abbreviation: Mini LED) and a micro light-emitting display device (full name in English: Micro Light-Emitting Diode, English abbreviation: Micro LED).

[0062] In some embodiments, when the display device 300 is a liquid crystal display device, the display device 300 may include a cover glass, a liquid crystal display panel, and a backlight assembly. The backlight assembly is used to provide light for the liquid crystal display panel. The backlight assembly includes a light-emitting substrate 200, which provides light to the liquid crystal display panel so that the liquid crystal display panel can display images.

[0063] In some examples, the display device 300 may include an array substrate, an opposing substrate (which may be a color filter substrate), and a liquid crystal layer, wherein the opposing substrate and the array substrate are disposed opposite to each other, and the liquid crystal layer is located between the opposing substrate and the array substrate.

[0064] A first polarizer is provided on the array substrate, and a second polarizer is provided on the opposing substrate. The polarization directions of the first and second polarizers are perpendicular to each other. Liquid crystal molecules in the liquid crystal layer are twisted by the driving electric field formed between the pixel electrodes provided on the array substrate and the common electrode provided on the array substrate or the common electrode provided on the opposing substrate, thereby controlling the polarization direction of light. The first and second polarizers work together to control the transmittance of light, thereby achieving grayscale display.

[0065] In some embodiments, when the display device 300 is a Mini LED display device or a Micro LED display device, the display device 300 includes a light-emitting substrate 200, which can realize image display. In some examples, the display device 300 may also include an anti-reflection film layer and a protective cover plate, with the anti-reflection film layer being located between the light-emitting substrate 200 and the protective cover plate. The anti-reflection film layer includes a polarizer, which may be a circular polarizer. Here, the polarizer can reduce external light emission, preventing the light-emitting substrate 200 from reflecting ambient light and causing glare.

[0066] FIG. 2 is a structural diagram of a light-emitting substrate according to some embodiments.

[0067] In some embodiments, as shown in FIG2 , a light-emitting substrate 200 may include a driving circuit layer 100 and a light source O. The light source O may include a plurality of light-emitting devices E, and the driving circuit layer 100 may include a plurality of light-emitting driving circuits Q. The plurality of light-emitting driving circuits Q in the driving circuit layer 100 are electrically connected to the plurality of light-emitting devices E in the light source O, so that the light-emitting driving circuits Q drive the light-emitting devices E to emit light.

[0068] In some examples, the multiple light-emitting driving circuits Q and the multiple light-emitting devices E can be electrically connected in a one-to-one correspondence. In other examples, one light-emitting driving circuit Q can be coupled to multiple light-emitting devices E, or multiple light-emitting driving circuits Q can be coupled to one light-emitting device E. The following description uses the example of multiple light-emitting driving circuits Q and multiple light-emitting devices E being electrically connected in a one-to-one correspondence.

[0069] In some examples, the light-emitting device E can be at least one of a light-emitting diode (LED), a micro light-emitting diode (Micro LED), or a mini light-emitting diode (Mini LED), but the present disclosure is not limited thereto. The following description uses a Micro LED as an example of the light-emitting device E.

[0070] In some embodiments, the light-emitting drive circuit Q includes multiple structures that can be selected based on actual needs. For example, the structure of the light-emitting drive circuit Q can include "8T2C" or "11T3C." Here, "T" represents a thin-film transistor, and the number preceding "T" represents the number of thin-film transistors; "C" represents a storage capacitor C, and the number preceding "C" represents the number of storage capacitors C.

[0071] FIG. 3 is a circuit diagram of a light emitting driving circuit according to some embodiments.

[0072] In some embodiments, referring to FIG2 and FIG3 , the structure of the light emitting driving circuit Q is described as “11T3C” as an example, where “11T” can be 11 thin film transistors T.

[0073] The light-emitting drive circuit Q includes a storage capacitor Cst, a first reset transistor T1, a compensation transistor T2, a drive transistor T3, a data write transistor T4, a first light-emitting control transistor T5, a second light-emitting control transistor T6, a second reset transistor T7, a first adjustment unit M1, and a second adjustment unit M2. When operating at different grayscales, the second light-emitting control transistor T6 is controlled by the first adjustment unit M1 or the second adjustment unit M2, respectively. The first adjustment unit M1 includes a first write transistor T8, a first adjustment transistor T9, and a first capacitor C1. The second adjustment unit M2 includes a second write transistor T10, a second adjustment transistor T11, and a second capacitor C2.

[0074] Among them, the first reset transistor T1, the compensation transistor T2, the driving transistor T3, the data writing transistor T4, the first light-emitting control transistor T5, the second light-emitting control transistor T6, the second reset transistor T7, the first writing transistor T8, the first regulating transistor T9, the second writing transistor T10 and the second regulating transistor T11 are all thin film transistors.

[0075] In some examples, the aforementioned "11T" may be a P-type transistor. That is, the first reset transistor T1, the compensation transistor T2, the drive transistor T3, the data write transistor T4, the first emission control transistor T5, the second emission control transistor T6, the second reset transistor T7, the first write transistor T8, the first regulating transistor T9, the second write transistor T10, and the second regulating transistor T11 may be P-type transistors.

[0076] In other examples, the aforementioned "11T" may be an N-type transistor. That is, the first reset transistor T1, the compensation transistor T2, the drive transistor T3, the data writing transistor T4, the first emission control transistor T5, the second emission control transistor T6, the second reset transistor T7, the first writing transistor T8, the first regulating transistor T9, the second writing transistor T10, and the second regulating transistor T11 may be N-type transistors.

[0077] A first plate of the storage capacitor Cst is electrically connected to the first power signal line VDD, and a second plate of the storage capacitor Cst is electrically connected to the first node N1.

[0078] A control electrode of the first reset transistor T1 is electrically connected to the first reset signal line RST-A, a first electrode of the first reset transistor T1 is electrically connected to the first initialization signal line Vinit, and a second electrode of the first reset transistor T1 is electrically connected to the first node N1.

[0079] A control electrode of the compensation transistor T2 is electrically connected to the first scan signal line Gate, a first electrode of the compensation transistor T2 is electrically connected to the first node N1, and a second electrode of the compensation transistor T2 is electrically connected to the third node N3.

[0080] The control electrode of the driving transistor T3 is electrically connected to the first node N1 , the first electrode of the driving transistor T3 is electrically connected to the second node N2 , and the second electrode of the driving transistor T3 is electrically connected to the third node N3 .

[0081] The control electrode of the data writing transistor T4 is electrically connected to the first scanning signal line Gate, the first electrode of the data writing transistor T4 is electrically connected to the data writing signal line Data, and the second electrode of the data writing transistor T4 is electrically connected to the second node N2.

[0082] A control electrode of the first emission control transistor T5 is electrically connected to the enable signal line EM, a first electrode of the first emission control transistor T5 is electrically connected to the first power signal line VDD, and a second electrode of the first emission control transistor T5 is electrically connected to the second node N2.

[0083] The control electrode of the second emission control transistor T6 is electrically connected to the first adjustment unit M1 and the second adjustment unit M2, respectively. The first electrode of the second emission control transistor T6 is electrically connected to the third node N3, and the second electrode of the second emission control transistor T6 is electrically connected to the fourth node N4. The fourth node N4 is also electrically connected to the light emitting device E.

[0084] The control electrode of the first write transistor T8 is electrically connected to the second reset signal line RST-B, the first electrode of the first write transistor T8 is electrically connected to the data write signal line Data, and the second electrode of the first write transistor T8 is electrically connected to the fifth node N5.

[0085] The control electrode of the first regulating transistor T9 is electrically connected to the fifth node N5 , the first electrode of the first regulating transistor T9 is electrically connected to the enable signal line EM, and the second electrode of the first regulating transistor T9 is electrically connected to the control electrode of the second light emitting control transistor T6 .

[0086] A first plate of the first capacitor C1 is electrically connected to the first initialization signal line Vinit, and a second plate of the first capacitor C1 is electrically connected to the fifth node N5.

[0087] A control electrode of the second write transistor T10 is electrically connected to the first reset signal line RST-A, a first electrode of the second write transistor T10 is electrically connected to the data write signal line Data, and a second electrode of the second write transistor T10 is electrically connected to the sixth node.

[0088] The control electrode of the second regulating transistor T11 is electrically connected to the sixth node N6 , the first regulating signal line Hf is electrically connected to the second regulating transistor T11 , and the second electrode of the second regulating transistor T11 is electrically connected to the control electrode of the second light emission control transistor T6 .

[0089] A first plate of the second capacitor C2 is electrically connected to the first initialization signal line Vinit, and a second plate of the second capacitor C2 is electrically connected to the sixth node N6.

[0090] The inventors have discovered that when the light-emitting drive circuit (e.g., the light-emitting drive circuit Q) in the light-emitting substrate 200 drives the light-emitting device E to emit light, providing light for the display device 300, and enabling the display device 300 to display images, the display quality of the display device 300 is poor. Furthermore, the display quality of the display device 300 is even worse in a low grayscale state.

[0091] The inventors further discovered that this is because the multiple thin-film transistors T in the light-emitting drive circuit Q use a top-gate structure. In thin-film transistors with a top-gate structure, the channel is floating relative to the substrate, which will cause a floating body effect.

[0092] Taking the driving transistor T3 among the multiple thin-film transistors T in the light-emitting driving circuit Q as an example, the floating body effect of the driving transistor T3 can cause instability in the driving current output by the light-emitting driving circuit Q to the light-emitting device E via the driving transistor T3. Furthermore, the control electrode potential difference of the corresponding driving transistor T3 can be small under different driving currents. As a result, it is impossible to accurately and effectively control the turning on or off of the driving transistor T3, thereby affecting the display quality of the display device 300.

[0093] Furthermore, when the display device 300 (referring to FIG. 1 ) is in a low grayscale state, the voltage required at the control electrode of the driving transistor T3 is lower than the voltage required at the control electrode of the driving transistor T3 when the display device 300 is in a high grayscale state. Consequently, when the display device 300 is in a low grayscale state, the potential difference between the control electrodes of the driving transistor T3 corresponding to different driving currents is smaller, making it more difficult to achieve precise and effective control of turning the driving transistor T3 on or off.

[0094] Based on this, the floating body effect can be improved by improving the structure of the thin film transistor T, so as to achieve precise control of the thin film transistor. The following description takes the thin film transistor T as the driving transistor T3 as an example.

[0095] FIG. 4 is a structural diagram of a thin film transistor according to some embodiments.

[0096] In some possible implementations, referring to FIG. 4 , the thin film transistor T includes a substrate 10 , and an active layer 20 , a first gate 30 , a second gate 40 , a first electrode 50 , and a second electrode 60 formed on the substrate 10 .

[0097] The first gate 30 and the second gate 40 are located on either side of the active layer 20. This description will take as an example a case where the first gate 30 is the bottom gate of a thin film transistor T, and the second gate 40 is the top gate of the thin film transistor T. In this case, the first gate 30 is located between the active layer 20 and the substrate 10, and the second gate 40 is located on the side of the active layer 20 away from the first gate 30.

[0098] Of the first electrode 50 and the second electrode 60 of the thin film transistor T, one is the source electrode of the thin film transistor T, and the other is the drain electrode of the thin film transistor. The following description uses the example where the first electrode 50 of the thin film transistor T is the drain electrode of the thin film transistor T, and the second electrode 60 of the thin film transistor T is the source electrode of the thin film transistor T. The second electrode 60 of the thin film transistor T is configured to have a constant voltage potential.

[0099] By electrically connecting the first gate electrode 30 of the thin film transistor T and the second electrode 60 of the thin film transistor T, the second electrode 60 of the thin film transistor T can be used to provide a constant voltage potential to the first gate electrode 30 of the thin film transistor T, thereby maintaining the first gate electrode 30 of the thin film transistor T at a fixed potential. This improves the floating body effect of the thin film transistor T and contributes to improving the performance of the thin film transistor. Furthermore, the driving current output by the light-emitting driving circuit Q to the light-emitting device E via the driving transistor T3 can be stabilized, thereby improving the display quality of the display device 300.

[0100] Furthermore, the thin film transistor T includes the first gate 30 and the second gate 40. Compared to a thin film transistor having only the second gate 40, the first gate 30 of the thin film transistor T can be maintained at a fixed potential, and the first gate 30 can be used to make it more difficult for the second gate 40 to control the channel of the thin film transistor T. In other words, the gate voltage required for the thin film transistor T having the first gate 30 and the second gate 40 to output a target current can be greater than the gate voltage required for the thin film transistor T having only the second gate 40 to output a target current.

[0101] Therefore, the potential difference of the control electrode of the driving transistor T3 under different driving currents can be increased, which is conducive to achieving accurate and effective control of the opening or closing of the driving transistor T3.

[0102] The inventors further discovered that when electrically connecting the first gate electrode 30 of the thin film transistor T and the second electrode 60 of the thin film transistor T, since the active layer 20 is located between the first gate electrode 30 of the thin film transistor T and the second electrode 60 of the thin film transistor T, a connecting portion F is required to bypass the active layer 20 to electrically connect the first gate electrode 30 of the thin film transistor T and the second electrode 60 of the thin film transistor T.

[0103] However, the connection portion will increase the size of the thin film transistor T. When it is subsequently applied to the backlight module and the display device 300, it will affect the pixel density (Pixels Per Inch, PPI) of the display device 300 and the display effect of the display device 300.

[0104] FIG5 is a structural diagram of a thin film transistor according to some embodiments, and FIG6 is a film layer diagram of a thin film transistor according to some embodiments.

[0105] To address the above problems, the present disclosure provides a thin film transistor T. Referring to FIG5 and FIG6 , the thin film transistor T includes a substrate 10 , an active layer 20 , a first gate 30 , a second gate 40 , a first electrode 50 , and a second electrode 60 .

[0106] In some examples, the substrate 10 may be a flexible substrate. For example, the material of the substrate 10 may be an organic material. For example, the material of the substrate 10 may be any one of polyimide (PI), polycarbonate (PC), or polyvinyl chloride (PVC).

[0107] In other examples, the substrate 10 may be a rigid substrate, for example, a glass substrate or a polymethyl methacrylate (PMMA) substrate.

[0108] The active layer 20 is located on one side of the substrate 10. The active layer 20 includes a channel 21 and a first heavily doped region 22 and a second heavily doped region 23 located on both sides of the channel 21. The first heavily doped region 22 may be a source contact region, and the second heavily doped region 23 may be a drain contact region.

[0109] In some examples, the material of the active layer 20 may include at least one of amorphous silicon, single crystal silicon, or polycrystalline silicon semiconductor materials. The following description will take the active layer 20 as an example of polycrystalline silicon.

[0110] In some examples, the thickness of the active layer 20 ranges from When the thickness of the active layer 20 is within the above range, the subsequent crystallization treatment of the active layer 20 can be guaranteed to improve the conductivity of the channel 21 in the active layer 20 without increasing the difficulty of the process.

[0111] When the thickness of the active layer 20 is equal to or close to When the active layer 20 is thin, the thickness of the active layer 20 is relatively thin, which can help reduce the difficulty of the process when forming the active layer 20, and can also ensure the subsequent crystallization treatment of the active layer 20 to improve the conductivity of the channel 21 in the active layer 20.

[0112] When the thickness of the active layer 20 is equal to or close to When the thickness of the active layer 20 is thicker, the requirements for the crystallization treatment of the active layer 20 can be better met, which is beneficial to improving the conductivity of the channel 21 in the active layer 20 and can also meet the requirements of the corresponding process of the existing active layer 20.

[0113] In other examples, the thickness of the active layer 20 ranges from In some other examples, the thickness of the active layer 20 ranges from In some other examples, the thickness of the active layer 20 ranges from

[0114] For example, the thickness of the active layer 20 is approximately or However, the embodiments of the present disclosure are not limited thereto.

[0115] It should be noted that the thickness of the active layer 20 is about As an example, due to certain uncontrollable errors (such as manufacturing process errors, equipment accuracy, measurement errors, etc.), the thickness error of the active layer 20 fluctuates within a range of When the active layer 20 floats within the range, it can also be considered that the thickness of the active layer 20 satisfies

[0116] In addition, in other examples, due to certain uncontrollable errors (such as manufacturing process errors, equipment accuracy, measurement errors, etc.), the error floating range of the thickness of the active layer 20 is When the active layer 20 floats within the range, it can also be considered that the thickness of the active layer 20 satisfies

[0117] The first gate 30 is located on a side of the active layer 20 that is closer to the substrate 10, and the second gate 40 is located on a side of the active layer 20 that is farther from the first gate 30. The orthographic projection of the first gate 30 on the substrate 10 at least partially overlaps with the orthographic projection of the second heavily doped region 23 on the substrate 10. That is, the first gate 30 and the second gate 40 are located on either side of the active layer 20, respectively, with the first gate 30 being closer to the substrate 10 than the second gate 40. The first gate 30 can serve as the bottom gate of the thin film transistor T, and the second gate 40 can serve as the top gate of the thin film transistor T.

[0118] In some examples, the material of the first gate 30 includes a conductive metal, which may include at least one of aluminum, copper, and molybdenum, but the present disclosure is not limited thereto.

[0119] In some examples, the material of the second gate 40 may be the same as that of the first gate 30. In other examples, the material of the second gate 40 may be different from that of the first gate 30. The embodiments of the present disclosure are not limited thereto.

[0120] In some examples, the thin film transistor T may further include a buffer layer Buffer, which is located between the substrate 10 and the first gate 30 and serves as a support and buffer.

[0121] In some examples, the thin film transistor T further includes a first gate insulating layer (GI) 71 , which is located between the first gate electrode 30 and the active layer 20 . The first gate insulating layer 71 insulates the first gate electrode 30 from the active layer 20 .

[0122] Exemplarily, the material of the first gate insulating layer 71 includes any one of inorganic insulating materials such as silicon nitride, silicon oxynitride, and silicon oxide. The material of the first gate insulating layer 71 may include silicon dioxide, but the present disclosure is not limited thereto.

[0123] In some examples, the thin film transistor T further includes a second gate insulating layer (GI) 72 , which is located between the active layer 20 and the second gate electrode 40 . The second gate insulating layer 72 insulates the second gate electrode 40 from the active layer 20 .

[0124] Exemplarily, the material of the second gate insulating layer 72 includes any one of inorganic insulating materials such as silicon nitride, silicon oxynitride, and silicon oxide. The material of the second gate insulating layer 72 may include silicon dioxide, but the present disclosure is not limited thereto.

[0125] The first electrode 50 and the second electrode 60 are both located on the side of the first gate 30 away from the substrate 10. One of the first electrode 50 and the second electrode 60 serves as the source and drain of the thin-film transistor T, respectively. The following description uses the example of the first electrode 50 of the thin-film transistor T serving as the drain and the second electrode 60 of the thin-film transistor T serving as the source. The second electrode 60 of the thin-film transistor T is configured to have a constant voltage potential.

[0126] The first electrode 50 of the thin film transistor T includes a first via connection portion 51 and a main portion 52. The main portion 52 is located on the side of the first gate 30 away from the substrate 10. The first via connection portion 51 is located between the main portion 52 of the first electrode 50 and the first gate 30. The first via connection portion 51 is used to electrically connect the main portion 52 of the first electrode 50 and the first heavily doped region 22. That is, the first electrode 50 is electrically connected to the first heavily doped region 22 in the active layer 20 using the first via connection portion 51.

[0127] The second electrode 60 of the thin film transistor T includes a second via connection portion 61 and a main body portion 62. The second via connection portion 61 is located between the main body portion 62 of the second electrode 60 and the first gate 30, and the orthographic projection of the second via connection portion 61 on the substrate 10 is located within the orthographic projection of the second heavily doped region 23 on the substrate 10. The main body portion 62 can be electrically connected to the second heavily doped region 23 through the second via connection portion 61, and the main body portion 62 can also be electrically connected to the first gate 30 using the second via connection portion 61. That is, the second electrode 60 can be electrically connected to the second heavily doped region 23 and the first gate 30 respectively using the second via connection portion 61. The second electrode 60 of the thin film transistor T is configured to have a constant voltage potential.

[0128] Based on this, the second electrode 60 of the thin-film transistor T can be used to provide a constant voltage potential for the first gate electrode 30 of the thin-film transistor T, thereby maintaining the first gate electrode 30 of the thin-film transistor T at a fixed potential, thereby improving the floating body effect of the thin-film transistor T and facilitating improved performance of the thin-film transistor. Furthermore, the driving current outputted by the light-emitting driving circuit Q to the light-emitting device E via the driving transistor T3 can be stabilized, thereby improving the display quality of the display device 300.

[0129] Furthermore, since the second electrode 60 can be electrically connected to the second heavily doped region 23 and the first gate 30 using the second via connection portion 61, the second via connection portion 61 already existing in the thin-film transistor T for electrically connecting the second electrode 60 and the second heavily doped region 23 can be utilized to electrically connect the second electrode 60 and the first gate 30. This eliminates the need for a connection portion in the thin-film transistor T that bypasses the active layer 20, thereby alleviating the issue of increased size of the thin-film transistor T due to this connection portion. Furthermore, the orthographic projection of the second via connection portion 61 on the substrate 10 is positioned within the orthographic projection of the second heavily doped region 23 on the substrate 10. This allows full utilization of the longitudinal space between the main portion 62 and the first gate 30, and thus fully utilizes the internal space of the thin-film transistor T, without increasing the size of the thin-film transistor T. Subsequent application of this device in the light-emitting drive circuit Q will not be limited by area size, thereby not affecting the pixel density of the display device 300.

[0130] In some examples, the thin film transistor T further includes an interlayer dielectric layer (ILD) 73. The interlayer dielectric layer 73 is located between the first body portion 52 of the first electrode 50, the second body portion 62 of the second electrode 60, and the second gate 40. The interlayer dielectric layer 73 insulates the first body portion 52 of the first electrode 50 and the second body portion 62 of the second electrode 60 from the second gate 40. Exemplarily, the material of the interlayer dielectric layer 73 may be silicon oxide (SiOx). However, the disclosed embodiments are not limited thereto.

[0131] It should be noted that the main portion 52 of the first electrode 50 and the main portion 62 of the second electrode 60 are located on the side of the first gate 30 away from the substrate 10. The first via connection portion 51 can be a structure formed between the main portion 52 of the first electrode 50 and the first gate 30 when the thin film transistor T forms the first electrode 50. The second via connection portion 61 can be a structure formed between the main portion 52 of the second electrode 60 and the first gate 30 when the thin film transistor T forms the second electrode 60. The first via connection portion 51 and the second via connection portion 61 also need to penetrate the interlayer dielectric layer 73.

[0132] In summary, the thin film transistor T provided in the embodiment of the present disclosure is configured such that the orthographic projection of the first gate electrode 30 on the substrate 10 at least partially overlaps with the orthographic projection of the second heavily doped region 23 on the substrate 10, and the orthographic projection of the second via connection portion 61 on the substrate 10 is located within the orthographic projection of the second heavily doped region 23 on the substrate 10. This allows the second via connection portion 61 to both electrically connect the main body 62 of the second electrode 60 to the second heavily doped region 23 and the first gate electrode 30, and also to alleviate the problem of increasing the size of the thin film transistor T due to the addition of the second via connection portion 61 of the second electrode 60. That is, the thin film transistor T provided in the embodiment of the present disclosure can improve the floating body effect of the thin film transistor T while minimizing the change in the size of the thin film transistor T, thereby improving the display quality of the display device 300 while ensuring the pixel density of the display device 300.

[0133] The “second via connection portion 61 is electrically connected to the first gate 30 ” may include two situations:

[0134] First, the second via connection portion 61 is directly electrically connected to the first gate 30 .

[0135] The second type is that the second via connection portion 61 is indirectly electrically connected to the first gate 30 .

[0136] The disclosed embodiments are not limited to the above methods for electrically connecting the second via-hole connecting portion 61 to the first gate 30. The two aforementioned connection methods will be described in detail below with reference to the accompanying drawings. However, whether the second via-hole connecting portion 61 is electrically connected to the first gate 30 or indirectly, the first gate 30 of the thin-film transistor T and the second electrode 60 of the thin-film transistor T can both be electrically connected. First, the first connection method will be described below with reference to the relevant accompanying drawings.

[0137] In some embodiments, as shown in Figures 5 and 6, the second heavily doped region 23 includes at least one via W, one end of the second via connection portion 61 is electrically connected to the second main body portion 62 of the second pole 60, and the other end of the second via connection portion 61 passes through the via W and is electrically connected to the first gate 30.

[0138] Based on this, when forming the second electrode 60, the other end of the second via connection portion 61 fills the via W of the second heavily doped region 23, and the via W that passes through the second heavily doped region 23 extends to be electrically connected to the first gate 30 at the lower position. The second via connection portion 61 is used to electrically connect the second heavily doped region 23 and the first gate 30 at the same time. Furthermore, there is no need to add a connection portion that needs to bypass the active layer 20 in the thin film transistor T, which can improve the problem of the size of the thin film transistor T being enlarged due to the connection portion. In addition, since the thin film transistor T is electrically connected to the second heavily doped region 23 and the first gate 30 by extending the second via connection portion 61, there is no need to increase the process of the thin film transistor T.

[0139] Furthermore, by drilling a hole in the second heavily doped region 23 within the thin film transistor T, the second via connection portion 61 is electrically connected to the first gate 30 via the second heavily doped region 23. This allows full utilization of the longitudinal area between the second heavily doped region 23 and the first gate 30, and thus fully utilizes the internal space of the thin film transistor T, without increasing the size of the thin film transistor T. Subsequent application of the thin film transistor in the light-emitting drive circuit Q will not be limited by area size, and thus will not affect the pixel density of the display device 300.

[0140] In some examples, the second heavily doped region 23 may include a via W. Here, one end of the second via connection portion 61 is electrically connected to the second body portion 62 of the second electrode 60 , and the other end of the second via connection portion 61 fills and passes through the via W to be electrically connected to the first gate 30 .

[0141] In some examples, the second heavily doped region 23 may include multiple vias W. The orthographic projection of the second main portion 62 of the second electrode 60 on the active layer 20 covers all the vias W in the second heavily doped region 23. The second via connecting portion 61 may include multiple sub-portions corresponding one-to-one to the multiple vias W. One sub-portion of the second via connecting portion 61 fills one via W and passes through the via to be electrically connected to the first gate 30.

[0142] 5 is illustrated by taking the example that the second heavily doped region 23 may include four via holes W. However, the embodiment of the present disclosure is not limited to this number of via holes W in the second heavily doped region 23 .

[0143] In some embodiments, referring to FIG. 5 and FIG. 6 , since the first gate electrode 30 is provided in the thin film transistor T and is electrically connected to the second electrode 60 of the thin film transistor T, the orthographic projection of the first gate electrode 30 on the substrate 10 can be set to not overlap with the orthographic projection of the via W on the substrate 10. This is equivalent to setting the orthographic projection of the first gate electrode 30 on the substrate 10 to not overlap with the orthographic projection of the second via hole connecting portion 61 on the substrate 10.

[0144] Based on this, a gap can be created between the orthographic projection of the first gate 30 on the substrate 10 and the orthographic projection of the second via connection portion 61 on the substrate 10, thereby preventing the first via connection portion 51 in the first electrode 50 from short-circuiting with the first gate 30, thereby preventing the first electrode 50 and the second electrode 60 in the thin film transistor T from short-circuiting, thereby ensuring the characteristics of the thin film transistor T.

[0145] In some embodiments, in combination with Figures 5 and 6, on the basis of setting the orthographic projection of the first gate 30 on the substrate 10 to have no overlap with the orthographic projection of the via W on the substrate 10, the orthographic projection of the first gate 30 on the substrate 10 can be set to have a minimum distance D1 greater than or equal to 0.5 μm.

[0146] As shown in the above structure, a minimum distance D1 can be present between the orthographic projection of the first gate 30 on the substrate 10 and the orthographic projection of the second via connection portion 61 on the substrate 10, thereby preventing the first via connection portion 51 in the first electrode 50 from being short-circuited with the first gate 30, thereby preventing the first electrode 50 and the second electrode 60 in the thin film transistor T from being short-circuited, thereby ensuring the characteristics of the thin film transistor T.

[0147] In some examples, as shown in conjunction with Figures 5 and 6 , in the first direction X, the first gate 30 includes a first side L1 and a second side L2 that are opposite to each other, and the first side L1 is located on a side of the second side L2 that is closer to the first via connection portion 51. The first direction X is the direction from the first electrode 50 to the second electrode 60.

[0148] On the basis of setting the minimum distance D1 between the orthographic projection of the first gate 30 on the substrate 10 and the orthographic projection of the via W on the substrate 10 to be greater than or equal to 0.5 μm, it is equivalent to setting the minimum distance D1 between the orthographic projection of the second side L2 of the first gate 30 on the substrate 10 and the orthographic projection of the via W on the substrate 10 to be greater than or equal to 0.5 μm.

[0149] When the minimum distance D1 between the orthographic projection of the second side L2 of the first gate 30 on the substrate 10 and the orthographic projection of the via W on the substrate 10 is equal to or close to 0.5 μm, the first via connection portion 51 in the first electrode 50 can be prevented from short-circuiting with the first gate 30, thereby preventing the first electrode 50 and the second electrode 60 in the thin film transistor T from short-circuiting.

[0150] Furthermore, since the minimum distance D1 between the orthographic projection of the second side L2 of the first gate 30 on the substrate 10 and the orthographic projection of the via W on the substrate 10 is equal to or close to 0.5 μm, the minimum distance D1 is small, and thus the minimum distance between the orthographic projection of the second side L2 of the first gate 30 on the substrate 10 and the orthographic projection of the channel 21 in the active layer 20 on the substrate 10 can be lengthened. In other words, the first gate 30 can be extended to the outside of the channel in the active layer 20 along the first direction X. Based on this, the problem of the first gate 30 causing the active layer 20 to be uneven can be prevented, and the problem of imperfect polysilicon being generated in the active layer during the crystallization process can be prevented, thereby improving the conductivity of the channel 21 in the active layer 20.

[0151] In some embodiments, please refer to Figures 5 and 6 , on the basis of setting the orthographic projection of the first gate 30 on the substrate 10 to have no overlap with the orthographic projection of the via W on the substrate 10, the orthographic projection of the first gate 30 on the substrate 10 can be set to have a minimum distance D1 less than or equal to 5 μm.

[0152] With the above structure, a minimum distance D1 can be maintained between the orthographic projection of the first gate 30 on the substrate 10 and the orthographic projection of the second via-hole connecting portion 61 on the substrate 10, and the minimum distance D1 is relatively large. This can effectively prevent the first via-hole connecting portion 51 in the first electrode 50 from short-circuiting with the first gate 30, thereby preventing the first electrode 50 and the second electrode 60 in the thin film transistor T from short-circuiting, thereby ensuring the characteristics of the thin film transistor T.

[0153] In some examples, continuing with FIG. 5 and FIG. 6 , on the basis that the minimum distance D1 between the orthographic projection of the first gate 30 on the substrate 10 and the orthographic projection of the via W on the substrate 10 is less than or equal to 5 μm, it is equivalent to setting the minimum distance D1 between the orthographic projection of the second side L2 of the first gate 30 on the substrate 10 and the orthographic projection of the via W on the substrate 10 to be less than or equal to 5 μm.

[0154] When the minimum distance D1 between the orthographic projection of the second side L2 of the first gate 30 on the substrate 10 and the orthographic projection of the via W on the substrate 10 is equal to or close to 5 μm, the minimum distance D1 can be made larger, thereby better preventing the first via connection portion 51 in the first electrode 50 from being short-circuited with the first gate 30, thereby causing the first electrode 50 and the second electrode 60 in the thin film transistor T to be short-circuited.

[0155] Furthermore, since the minimum distance D1 between the orthographic projection of the second side L2 of the first gate 30 on the substrate 10 and the orthographic projection of the via W on the substrate 10 is equal to or close to 5 μm, the minimum distance D1 is not too large, and a gap can be provided between the orthographic projection of the second side L2 of the first gate 30 on the substrate 10 and the orthographic projection of the channel 21 in the active layer 20 on the substrate 10. In other words, the first gate 30 can be extended to the outside of the channel in the active layer 20 along the first direction X. Based on this, the problem of the first gate 30 causing the active layer 20 to be uneven can be prevented, and the problem of imperfect polysilicon being generated during the crystallization process of the active layer can be prevented, thereby improving the conductivity of the channel 21 in the active layer 20.

[0156] In some embodiments, as shown in conjunction with FIG5 and FIG6 , the minimum distance D1 between the orthographic projection of the first gate 30 on the substrate 10 and the orthographic projection of the via W on the substrate 10 is in the range of 0.5 μm to 5 μm. Based on this, a gap can be provided between the orthographic projection of the second side L2 of the first gate 30 on the substrate 10 and the orthographic projection of the via W on the substrate 10, thereby preventing a short circuit between the first via connecting portion 51 in the first electrode 50 and the first gate 30; and a gap can be provided between the orthographic projection of the second side L2 of the first gate 30 on the substrate 10 and the orthographic projection of the channel 21 in the active layer 20 on the substrate 10, thereby preventing the first gate 30 from causing unevenness in the active layer 20.

[0157] In other embodiments, the minimum distance D1 between the orthographic projection of the first gate 30 on the substrate 10 and the orthographic projection of the via W on the substrate 10 may be in the range of 0.5 μm to 3 μm. In still other embodiments, the minimum distance D1 between the orthographic projection of the first gate 30 on the substrate 10 and the orthographic projection of the via W on the substrate 10 may be in the range of 0.5 μm to 2 μm.

[0158] In some examples, the minimum distance D1 between the orthographic projection of the first gate 30 on the substrate 10 and the orthographic projection of the via W on the substrate 10 is approximately 0.5 μm, 0.8 μm, 1 μm, 1.5 μm, 2 μm, 3 μm, 4 μm, or 5 μm. The present disclosure is not limited thereto.

[0159] It should be noted that, taking the minimum spacing D1 between the orthographic projection of the first gate 30 on the substrate 10 and the orthographic projection of the via W on the substrate 10 as approximately 0.5 μm as an example: due to certain uncontrollable errors (such as manufacturing process errors, equipment accuracy, measurement errors, etc.), when the error floating range of the minimum spacing D1 fluctuates within the range of 10%×0.5 μm, it can also be considered that the minimum spacing D1 satisfies equal to 0.5 μm.

[0160] In addition, in other examples, due to certain uncontrollable errors (such as manufacturing process errors, equipment accuracy, measurement errors, etc.), when the error fluctuation range of the minimum spacing D1 fluctuates within the range of 5%×0.5μm, it can also be considered that the minimum spacing D1 satisfies 0.5μm.

[0161] In some examples, as shown in conjunction with Figures 5 and 6 , the first gate 30 in the thin film transistor T is located on a layer of the active layer 20 close to the substrate 10. Furthermore, when manufacturing the thin film transistor T, the first gate 30 is first formed on the substrate 10, and then the active layer 20 is formed. When forming the active layer 20, an amorphous silicon layer must first be formed on the side of the first gate 30 away from the substrate 10, that is, an amorphous silicon layer must be formed on the side of the first gate insulating layer 71 away from the substrate 10. The amorphous silicon layer is then subjected to an excimer laser annealing process (ELA) to form the polycrystalline silicon active layer 20.

[0162] However, since the first gate 30 has a certain thickness, the amorphous silicon layer will be formed on an uneven surface when the active layer 20 is manufactured, which will also cause protrusions or steps to form on the surface of the amorphous silicon layer. The problem of poor crystallization is likely to occur when the amorphous silicon layer is subsequently subjected to an excimer laser annealing process, thereby reducing the quality of the subsequently formed polycrystalline silicon active layer 20.

[0163] Based on the above problem, in the embodiment of the present disclosure, the orthographic projection of the channel 21 in the thin film transistor T on the substrate 10 may be set to be located within the orthographic projection of the first gate 30 on the substrate 10 .

[0164] Since the first heavily doped region 22 and the second heavily doped region 23 in the active layer 20 are formed by conductorization, when the first heavily doped region 22 and the second heavily doped region 23 in the active layer 20 are formed on an uneven surface, the impact on the performance of the first heavily doped region 22 and the second heavily doped region 23 in the active layer 20 is small.

[0165] Based on this, the orthographic projection of the channel 21 in the thin film transistor T on the substrate 10 is set to be located within the orthographic projection of the first gate 30 on the substrate 10. The step region formed at the edge of the first gate 30 can be made to avoid the channel 21 in the active layer 20 to prevent the channel 21 of the active layer 20 from being formed on an uneven surface, thereby ensuring the conductivity of the channel 21 of the active layer 20.

[0166] In some embodiments, continuing with FIG. 5 and FIG. 6 , based on the fact that the orthographic projection of the channel 21 on the substrate 10 in the thin film transistor T is located within the orthographic projection of the first gate 30 on the substrate 10, a minimum spacing D2 between an outer edge of the orthographic projection of the first gate 30 on the substrate 10 and an outer edge of the orthographic projection of the channel 21 on the substrate 10 is set to be greater than or equal to 0.5 μm.

[0167] When the minimum distance D2 between the outer edge of the orthographic projection of the first gate 30 on the substrate 10 and the outer edge of the orthographic projection of the channel 21 on the substrate 10 is equal to or close to 0.5 μm, the first gate 30 can be expanded so that the step area formed at the edge of the first gate 30 avoids the channel 21 in the active layer 20 to prevent the channel 21 of the active layer 20 from being formed on an uneven surface, thereby ensuring the conductivity of the channel 21 of the active layer 20.

[0168] In another embodiment, a minimum distance D2 between an outer edge of an orthographic projection of the first gate 30 on the substrate 10 and an outer edge of an orthographic projection of the channel 21 on the substrate 10 is greater than or equal to 5 μm.

[0169] When the minimum distance D2 between the outer edge of the orthographic projection of the first gate 30 on the substrate 10 and the outer edge of the orthographic projection of the channel 21 on the substrate 10 is equal to or close to 5 μm, the first gate 30 can be expanded to a greater extent so that the step area formed at the edge of the first gate 30 can better avoid the channel 21 in the active layer 20, thereby preventing the channel 21 of the active layer 20 from being formed on an uneven surface, thereby ensuring the conductivity of the channel 21 of the active layer 20.

[0170] For example, the minimum distance D2 between the outer edge of the orthographic projection of the first gate 30 on the substrate 10 and the outer edge of the orthographic projection of the channel 21 on the substrate 10 is approximately 0.5 μm, 1 μm, or 2 μm. However, the present disclosure is not limited thereto.

[0171] It should be noted that, taking the minimum spacing D2 between the outer edge of the orthographic projection of the first gate 30 on the substrate 10 and the outer edge of the orthographic projection of the channel 21 on the substrate 10 as approximately 0.5 μm as an example: due to certain uncontrollable errors (such as manufacturing process errors, equipment accuracy, measurement errors, etc.), when the error floating range of the minimum spacing D2 fluctuates within the range of 10%×0.5 μm, it can also be considered that the minimum spacing D2 satisfies 0.5 μm.

[0172] In addition, in other examples, due to certain uncontrollable errors (such as manufacturing process errors, equipment accuracy, measurement errors, etc.), when the error fluctuation range of the minimum spacing D2 fluctuates within the range of 5%×0.5μm, it can also be considered that the minimum spacing D2 satisfies 0.5μm.

[0173] It should be noted that since the first gate 30 includes a first side L1 and a second side L2, the second side L2 is closer to the first via-hole connecting portion 51 than the first side L1. In order to prevent the first gate 30 from short-circuiting with the first electrode 50, a minimum distance D1 needs to be set between the first gate 30 and the first via-hole connecting portion 51 (via W) (this has been described in the above embodiment and will not be repeated here). Based on this, the second side L2 of the first gate 30 needs to take into account the extension range to ensure that the minimum distance D1 is reserved.

[0174] The extent of the extension of the first side L1 of the first gate 30 will be described in detail below with reference to the accompanying drawings.

[0175] In the above embodiment, it is introduced that “the orthographic projection of the first gate 30 on the substrate 10 at least partially overlaps with the orthographic projection of the second heavily doped region 23 on the substrate 10 ”, so that the second via connection portion 62 electrically connects the second heavily doped region 23 and the first gate 30 at the same time.

[0176] The phrase “the orthographic projection of the first gate 30 on the substrate 10 at least partially overlaps with the orthographic projection of the second heavily doped region 23 on the substrate 10 ” includes the following situations:

[0177] The first method involves partially overlapping the orthographic projection of the first gate 30 on the substrate 10 and the orthographic projection of the second heavily doped region 23 on the substrate 10. This is equivalent to extending the first side L1 of the first gate 30 to overlap with the orthographic projection of the second heavily doped region 23 on the substrate 10. This allows the step region formed at the edge of the first gate 30 (the first side L1) to avoid the channel 21 in the active layer 20, preventing the channel 21 of the active layer 20 from forming on an uneven surface and ensuring the conductivity of the channel 21 in the active layer 20.

[0178] The second type: the orthographic projection of the second heavily doped region 23 on the substrate 10 is located within the orthographic projection of the first gate 30 on the substrate 10. Based on this, it is equivalent to extending the first side L1 of the first gate 30 to overlap with the orthographic projection of the edge of the second heavily doped region 23 away from the first heavily doped region 22 on the substrate 10. Alternatively, the first side L1 of the first gate 30 is extended to the outside of the second heavily doped region 23, so that the step area formed at the edge of the first gate 30 (the first side L1) can avoid the second heavily doped region 23 and the channel 21 in the active layer 20, so as to prevent the second heavily doped region 23 and the channel 21 of the active layer 20 from being formed on an uneven surface, thereby ensuring the performance of the active layer 20.

[0179] In some embodiments, in combination with Figures 5 and 6 , in the case where "the first side L1 of the first gate 30 extends to the outside of the second heavily doped region 23", the minimum distance D3 between the orthographic projection of the second side L2 of the first gate 30 on the substrate 10 and the orthographic projection of the third side L3 of the second heavily doped region 23 away from the first heavily doped region 22 on the substrate 10 can be set to be greater than or equal to 0.5 μm.

[0180] When the minimum distance D3 between the orthographic projection of the second side L2 of the first gate 30 on the substrate 10 and the orthographic projection of the side L3 of the second heavily doped region 23 on the side away from the first heavily doped region 22 on the substrate 10 is equal to or close to 0.5 μm, the step region formed at the edge of the first gate 30 (the first side L1) can avoid the second heavily doped region 23 and the channel 21 in the active layer 20, thereby preventing the second heavily doped region 23 and the channel 21 of the active layer 20 from forming on an uneven surface, thereby ensuring the performance of the active layer 20. Furthermore, in this case, the second side L2 of the first gate 30 has a small degree of expansion, which is equivalent to not increasing the size of the thin film transistor T. This prevents the subsequent application of the first gate 30 in the light-emitting drive circuit Q from being limited by area size, thereby not affecting the pixel density of the display device 300.

[0181] In some embodiments, continuing with FIG. 5 and FIG. 6 , a minimum distance D3 between an orthographic projection of the second side L2 of the first gate 30 on the substrate 10 and an orthographic projection of a third side L3 of the second heavily doped region 23 away from the first heavily doped region 22 on the substrate 10 is less than or equal to 10 μm.

[0182] When the minimum distance D3 between the orthographic projection of the second side L2 of the first gate 30 on the substrate 10 and the orthographic projection of the third side L3 of the second heavily doped region 23 on the side away from the first heavily doped region 22 on the substrate 10 is equal to or close to 10 μm, the second side L2 of the first gate 30 can be expanded to a greater extent without significantly increasing the size of the thin film transistor T. At the same time, the step region formed at the edge of the first gate 30 (the first side L1) can better avoid the second heavily doped region 23 and the channel 21 in the active layer 20, thereby preventing the second heavily doped region 23 and the channel 21 of the active layer 20 from forming on an uneven surface, thereby ensuring the performance of the active layer 20.

[0183] In some embodiments, continuing with FIG. 5 and FIG. 6 , a minimum distance D3 between an orthographic projection of the second side L2 of the first gate 30 on the substrate 10 and an orthographic projection of a third side L3 of the second heavily doped region 23 away from the first heavily doped region 22 on the substrate 10 has a value in the range of 0.5 μm to 10 μm.

[0184] Based on this, the step area formed at the edge of the first gate 30 (the first side L1) can better avoid the second heavily doped region 23 and the channel 21 in the active layer 20 to prevent the second heavily doped region 23 and the channel 21 of the active layer 20 from being formed on an uneven surface to ensure the performance of the active layer 20; and it can also prevent the second side L2 of the first gate 30 from expanding too much and affecting the size of the thin film transistor T.

[0185] In some other embodiments, the minimum distance D3 between the orthographic projection of the second side L2 of the first gate 30 on the substrate 10 and the orthographic projection of the third side L3 of the second heavily doped region 23 on the side away from the first heavily doped region 22 on the substrate 10 is in a range of 0.5 μm to 5 μm. In still other embodiments, the minimum distance D3 between the orthographic projection of the second side L2 of the first gate 30 on the substrate 10 and the orthographic projection of the third side L3 of the second heavily doped region 23 on the side away from the first heavily doped region 22 on the substrate 10 is in a range of 0.5 μm to 3 μm.

[0186] For example, a minimum distance D3 between an orthographic projection of the second side L2 of the first gate 30 on the substrate 10 and an orthographic projection of a third side L3 of the second heavily doped region 23 on a side away from the first heavily doped region 22 on the substrate 10 is approximately 0.5 μm, 1 μm, 2 μm, 3 μm, 5 μm, 7 μm, or 10 μm. The present disclosure is not limited thereto.

[0187] It should be noted that, taking the orthographic projection of the second side L2 of the first gate 30 on the substrate 10 and the orthographic projection of the third side L3 of the second heavily doped region 23 on the side away from the first heavily doped region 22 on the substrate 10 as an example, the minimum spacing D3 is approximately 0.5 μm: due to certain uncontrollable errors (such as manufacturing process errors, equipment accuracy, measurement errors, etc.), when the error floating range of the minimum spacing D3 fluctuates within the range of 10%×0.5 μm, it can also be considered that the minimum spacing D1 satisfies the requirement of being equal to 0.5 μm.

[0188] In addition, in other examples, due to certain uncontrollable errors (such as manufacturing process errors, equipment accuracy, measurement errors, etc.), when the error fluctuation range of the minimum spacing D3 fluctuates within the range of 5%×0.5μm, it can also be considered that the minimum spacing D1 satisfies the requirement of being equal to 0.5μm.

[0189] In some embodiments, as shown in FIG5 , the first gate 30 further includes a fourth side L4 and a fifth side L5 that are oppositely disposed along the second direction Y. One side of the fourth side L4 is electrically connected to the first side L1, and the other side of the fourth side L4 is electrically connected to the second side L3. One side of the fifth side L5 is electrically connected to the first side L1, and the other side of the fifth side L5 is electrically connected to the second side L3.

[0190] In some examples, for the above-mentioned case where "the first side L1 of the first gate 30 extends to the outside of the second heavily doped region 23", the distance between the orthographic projection of the fourth side L4 on the substrate 10 and the orthographic projection of the second heavily doped region 23 on the substrate 10 is greater than or equal to 0.5 μm.

[0191] Based on this, the step area formed at the edge of the first gate 30 (the fourth side L4) can better avoid the second heavily doped region 23 and the channel 21 in the active layer 20 to prevent the second heavily doped region 23 and the channel 21 of the active layer 20 from being formed on an uneven surface to ensure the performance of the active layer 20; it can also prevent the second side L2 of the first gate 30 from expanding too much and affecting the size of the thin film transistor T.

[0192] In some examples, for the above-mentioned case where "the first side L1 of the first gate 30 extends to the outside of the second heavily doped region 23", the distance between the orthographic projection of the fifth side L5 on the substrate 10 and the orthographic projection of the second heavily doped region 23 on the substrate 10 is greater than or equal to 0.5 μm.

[0193] Based on this, the step area formed at the edge of the first gate 30 (the fifth side L5) can better avoid the second heavily doped region 23 and the channel 21 in the active layer 20 to prevent the second heavily doped region 23 and the channel 21 of the active layer 20 from being formed on an uneven surface to ensure the performance of the active layer 20; it can also prevent the second side L2 of the first gate 30 from expanding too much and affecting the size of the thin film transistor T.

[0194] It should be noted that, for the limitation of the distance between the fourth side L4 and the fifth side L5 and the orthographic projection of the second heavily doped region 23 on the substrate 10, reference can be made to the limitation of the distance between the first side L1 and the orthographic projection of the second heavily doped region 23 on the substrate 10, which will not be repeated here.

[0195] The above mainly introduces the situation where the second via connection portion 61 is directly electrically connected to the first gate 30 in combination with the relevant drawings. The following will mainly introduce the second connection method between the second via connection portion 61 and the first gate 30 in combination with the relevant drawings: the second via connection portion 61 is indirectly electrically connected to the first gate 30.

[0196] FIG7 is a structural diagram of a thin film transistor according to some other embodiments, and FIG8 is a film layer diagram of a thin film transistor according to some other embodiments.

[0197] In some embodiments, as shown in Figures 7 and 8, one end of the second via connection portion 61 is electrically connected to the second main body 62 of the second electrode 60, and the other end of the second via connection portion 61 is electrically connected to the first gate 30 through the second heavily doped region 23.

[0198] The second heavily doped region 23 may include a third via connection portion H that penetrates the first gate insulating layer 71, electrically connecting the second medium doped region 23 to the first gate 30. Furthermore, the second electrode 60 may be electrically connected to the first gate 30 via the second via connection portion 61 and the second heavily doped region 23, in sequence. That is, the second electrode 60 may be indirectly electrically connected to the first gate 30 via the second via connection portion 61.

[0199] Based on this, there is no need to add a connection portion in the thin-film transistor T that needs to bypass the active layer 20, which can alleviate the problem of the thin-film transistor T being larger due to this connection portion. In addition, the longitudinal area between the second heavily doped region 23 and the first gate 30 can be fully utilized, that is, the internal space of the thin-film transistor T is fully utilized, without increasing the size of the thin-film transistor T. When it is subsequently applied to the light-emitting drive circuit Q, it will not be limited by the area size, and thus will not affect the pixel density of the display device 300.

[0200] In some embodiments, as shown in Figures 7 and 8 , the first gate 30 of the thin film transistor T is located on a layer of the active layer 20 close to the substrate 10. Furthermore, when fabricating the thin film transistor T, the first gate 30 is first formed on the substrate 10, followed by the active layer 20. When forming the active layer 20, an amorphous silicon layer is first formed on the side of the first gate 30 away from the substrate 10. Specifically, an amorphous silicon layer is formed on the side of the first gate insulating layer 71 away from the substrate 10. The amorphous silicon layer is then subjected to an excimer laser annealing process to form the polycrystalline silicon active layer 20.

[0201] However, since the first gate 30 has a certain thickness, the amorphous silicon layer will be formed on an uneven surface when the active layer 20 is manufactured, which will also cause protrusions or steps to form on the surface of the amorphous silicon layer. The problem of poor crystallization is likely to occur when the amorphous silicon layer is subsequently subjected to an excimer laser annealing process, thereby reducing the quality of the subsequently formed polycrystalline silicon active layer 20.

[0202] Based on the above problem, in the embodiment of the present disclosure, the orthographic projection of the channel 21 in the thin film transistor T on the substrate 10 may be set to be located within the orthographic projection of the first gate 30 on the substrate 10 .

[0203] Since the first heavily doped region 22 and the second heavily doped region 23 in the active layer 20 are formed by conductorization, when the first heavily doped region 22 and the second heavily doped region 23 in the active layer 20 are formed on an uneven surface, the impact on the performance of the first heavily doped region 22 and the second heavily doped region 23 in the active layer 20 is small.

[0204] Based on this, the orthographic projection of the channel 21 in the thin film transistor T on the substrate 10 is set to be located within the orthographic projection of the first gate 30 on the substrate 10. The step region formed at the edge of the first gate 30 can be made to avoid the channel 21 in the active layer 20 to prevent the channel 21 of the active layer 20 from being formed on an uneven surface, thereby ensuring the conductivity of the channel 21 of the active layer 20.

[0205] In some embodiments, continuing with FIG. 7 and FIG. 8 , based on the fact that the orthographic projection of the channel 21 on the substrate 10 in the thin film transistor T is located within the orthographic projection of the first gate 30 on the substrate 10 , a minimum spacing between an outer edge of the orthographic projection of the first gate 30 on the substrate 10 and an outer edge of the orthographic projection of the channel 21 on the substrate 10 is greater than or equal to 0.5 μm.

[0206] When the minimum distance D2 between the outer edge of the orthographic projection of the first gate 30 on the substrate 10 and the outer edge of the orthographic projection of the channel 21 on the substrate 10 is equal to or close to 0.5 μm, the first gate 30 can be expanded so that the step area formed at the edge of the first gate 30 avoids the channel 21 in the active layer 20 to prevent the channel 21 of the active layer 20 from being formed on an uneven surface, thereby ensuring the conductivity of the channel 21 of the active layer 20.

[0207] In another embodiment, a minimum distance D2 between an outer edge of an orthographic projection of the first gate 30 on the substrate 10 and an outer edge of an orthographic projection of the channel 21 on the substrate 10 is greater than or equal to 5 μm.

[0208] When the minimum distance D2 between the outer edge of the orthographic projection of the first gate 30 on the substrate 10 and the outer edge of the orthographic projection of the channel 21 on the substrate 10 is equal to or close to 5 μm, the first gate 30 can be expanded to a greater extent so that the step area formed at the edge of the first gate 30 can better avoid the channel 21 in the active layer 20, thereby preventing the channel 21 of the active layer 20 from being formed on an uneven surface, thereby ensuring the conductivity of the channel 21 of the active layer 20.

[0209] For example, the minimum distance D2 between the outer edge of the orthographic projection of the first gate 30 on the substrate 10 and the outer edge of the orthographic projection of the channel 21 on the substrate 10 is approximately 0.5 μm, 1 μm, or 2 μm. However, the present disclosure is not limited thereto.

[0210] In some embodiments, as shown in conjunction with FIG. 7 and FIG. 8 , the orthographic projection of the active layer 20 on the substrate 10 is located within the orthographic projection of the first gate 30 on the substrate 10 .

[0211] Based on this, the orthographic projection of the channel 21 in the thin film transistor T on the substrate 10 is set to be located within the orthographic projection of the first gate 30 on the substrate 10. The step region formed at the edge of the first gate 30 can be avoided from the active layer 20 to prevent the active layer 20 from being formed on an uneven surface, thereby ensuring the performance of the active layer 20.

[0212] In some embodiments, as shown in FIG. 7 and FIG. 8 , a minimum distance D4 between an outer edge of an orthographic projection of the first gate 30 on the substrate 10 and an outer edge of an orthographic projection of the active layer 20 on the substrate 10 is greater than or equal to 0.5 μm.

[0213] When the minimum distance D4 between the outer edge of the orthographic projection of the first gate 30 on the substrate 10 and the outer edge of the orthographic projection of the active layer 20 on the substrate 10 is equal to or close to 0.5 μm, the first gate 30 can be expanded outward so that the step area formed at the edge of the first gate 30 avoids the active layer 20 to prevent the active layer 20 from being formed on an uneven surface, thereby ensuring the performance of the active layer 20.

[0214] In another embodiment, a minimum distance D4 between an outer edge of an orthographic projection of the first gate 30 on the substrate 10 and an outer edge of an orthographic projection of the active layer 20 on the substrate 10 is greater than or equal to 5 μm.

[0215] When the minimum distance D4 between the outer edge of the orthographic projection of the first gate 30 on the substrate 10 and the outer edge of the orthographic projection of the active layer 20 on the substrate 10 is equal to or close to 5 μm, the first gate 30 can be expanded to a greater extent so that the step area formed at the edge of the first gate 30 can better avoid the active layer 20, thereby preventing the active layer 20 from being formed on an uneven surface and ensuring the performance of the active layer 20.

[0216] For example, the minimum distance D4 between the outer edge of the orthographic projection of the first gate 30 on the substrate 10 and the outer edge of the orthographic projection of the active layer 20 on the substrate 10 is approximately 0.5 μm, 1 μm, or 2 μm. However, the present disclosure is not limited thereto.

[0217] It should be noted that, taking the minimum spacing D4 between the outer edge of the orthographic projection of the first gate 30 on the substrate 10 and the outer edge of the orthographic projection of the active layer 20 on the substrate 10 as approximately 0.5 μm as an example: due to certain uncontrollable errors (such as manufacturing process errors, equipment accuracy, measurement errors, etc.), when the error floating range of the minimum spacing D4 fluctuates within the range of 10%×0.5 μm, it can also be considered that the minimum spacing D4 satisfies 0.5 μm.

[0218] In addition, in other examples, due to certain uncontrollable errors (such as manufacturing process errors, equipment accuracy, measurement errors, etc.), when the error fluctuation range of the minimum spacing D4 fluctuates within the range of 5%×0.5μm, it can also be considered that the minimum spacing D4 satisfies the requirement of being equal to 0.5μm.

[0219] In some embodiments, as shown in FIG. 7 and FIG. 8 , a minimum distance D4 between an outer edge of an orthographic projection of the first gate 30 on the substrate 10 and an outer edge of an orthographic projection of the active layer 20 on the substrate 10 is less than or equal to 10 μm.

[0220] When the minimum distance D4 between the outer edge of the orthographic projection of the first gate 30 on the substrate 10 and the outer edge of the orthographic projection of the active layer 20 on the substrate 10 is equal to or close to 10 μm, the first gate 30 can be expanded to a greater extent without significantly increasing the size of the thin film transistor T. At the same time, the step region formed at the edge of the first gate 30 can be better avoided from the active layer 20, thereby preventing the active layer 20 from being formed on an uneven surface and ensuring the performance of the active layer 20.

[0221] In some embodiments, as shown in FIG7 and FIG8 , the minimum distance D4 between the outer edge of the orthographic projection of the first gate 30 on the substrate 10 and the outer edge of the orthographic projection of the active layer 20 on the substrate 10 is in the range of 0.5 μm to 10 μm.

[0222] Based on this, the step area formed at the edge of the first gate 30 can better avoid the active layer 20 to prevent the active layer 20 from being formed on an uneven surface to ensure the performance of the active layer 20; it can also prevent the first gate 30 from expanding too much and affecting the size of the thin film transistor T.

[0223] In other embodiments, the minimum distance D4 between the outer edge of the orthographic projection of the first gate 30 on the substrate 10 and the outer edge of the orthographic projection of the active layer 20 on the substrate 10 is in the range of 0.5 μm to 3 μm. In still other embodiments, the minimum distance D4 between the outer edge of the orthographic projection of the first gate 30 on the substrate 10 and the outer edge of the orthographic projection of the active layer 20 on the substrate 10 is in the range of 0.5 μm to 5 μm. The embodiments of the present disclosure are not limited thereto.

[0224] In some embodiments, as shown in Figures 5 to 8 , when forming the channel 21 in the active layer 20, the second gate 40 can be used as a mask to form the first heavily doped region 22 and the second heavily doped region 23 in the active layer 20. This allows the projection of the second gate 40 on the substrate 10 to roughly coincide with the projection of the channel 21 on the substrate 10.

[0225] Based on this, it is possible to prevent the orthographic projection of the second gate 40 on the substrate 10 from overlapping with the orthographic projections of the first heavily doped region 22 and / or the second heavily doped region 23 on the substrate 10, thereby preventing the overlapping regions from introducing parasitic capacitance and parasitic resistance. This can help reduce parasitic effects and signal delays within the thin film transistor T, thereby improving the performance of the thin film transistor T.

[0226] It should be noted that "substantially overlap" includes both absolute overlap and approximate overlap. Specifically, the floating range of the gap between the projection of the second gate 40 on the substrate 10 and the projection of the channel 21 on the substrate 10 does not exceed the error threshold. Alternatively, the projection of the second gate 40 on the substrate 10 and the edge of the projection of the channel 21 on the substrate 10 can be considered to relatively "overlap." The present disclosure does not limit the specific value of the error threshold.

[0227] Figure 9 is a diagram of film layers of thin film transistors according to further embodiments, and Figure 10 is a diagram of film layers of thin film transistors according to further embodiments. Figure 9 corresponds to a thin film transistor in which the second via connection portion 61 and the first gate 30 are electrically connected in the first manner (direct electrical connection), and Figure 10 corresponds to a thin film transistor in which the second via connection portion 61 and the first gate 30 are electrically connected in the second manner (indirect electrical connection).

[0228] In some embodiments, as shown in Figures 9 and 10 , the active layer 20 further includes a first lightly doped region (Lightly Doped Drain, LDD) 24 and a second lightly doped region (Lightly Doped Drain, LDD) 25. The first lightly doped region 24 is located between the first heavily doped region 22 and the channel 21, and the doping concentration of the first lightly doped region 24 is lower than the doping concentration of the first heavily doped region 22. The second lightly doped region 25 is located between the second heavily doped region 23 and the channel 21, and the doping concentration of the second lightly doped region 25 is lower than the doping concentration of the second heavily doped region 23.

[0229] A first low-doped region 24 is provided between the first heavily doped region 22 and the channel 21, and a second low-doped region 25 is provided between the second heavily doped region 23 and the channel 21. That is, a region having a low-doped region doping concentration one order of magnitude lower than that of the high-doped region is provided between the channel 21 and the heavily doped region. The low-doped regions (the first low-doped region 24 and the second low-doped region 25) are equivalent to a large resistor connected in series between the source and drain (the first electrode 50 and the second electrode 60) of the thin film transistor T and the channel 21. This helps to reduce the horizontal electric field in the channel 21, reducing hot carriers generated by impact ionization caused by electric field acceleration, and can effectively suppress leakage current by two orders of magnitude.

[0230] Figure 11 is a flow chart of a method for fabricating a thin film transistor according to some embodiments, Figure 12 is a diagram of the film layer structure corresponding to the steps in Figure 11, Figure 13 is a top view corresponding to some steps in Figure 11, and Figure 14 is a top view corresponding to other steps in Figure 11. The substrate is not shown in Figures 13 and 14.

[0231] In some embodiments, in conjunction with FIG. 11 to FIG. 14 , the present disclosure provides a method for manufacturing a thin film transistor, the method comprising:

[0232] S11 : forming a first gate 30 on one side of the substrate 10 .

[0233] S12: An active layer 20 is formed on a side of the substrate 10 away from the first gate 30, wherein the active layer 20 includes a channel 21, and a first region to be doped 21A and a second region to be doped 21B located on both sides of the channel 21. The orthographic projection of the first gate 30 on the substrate 10 at least partially overlaps with the orthographic projection of the second region to be doped 21B on the substrate 10.

[0234] S13 : forming a second gate 40 on a side of the active layer 20 away from the substrate 10 .

[0235] S14: Conducting the first region to be doped 21A and the second region to be doped 21B to form the corresponding first heavily doped region 22 and second heavily doped region 23. The first region to be doped 21A is subjected to conductorization to form the first heavily doped region 22 in the active layer 20, and the second region to be doped 21B is subjected to conductorization to form the second heavily doped region 23, using a masking process.

[0236] S15: A first pole 50 and a second pole 60 are formed on the side of the first gate 30 away from the substrate 10, the first pole 50 includes a first via connection portion 51, and the first via connection portion 51 is electrically connected to the first heavily doped region 22; the second pole 60 includes a second via connection portion 61, and the second via connection portion 61 is electrically connected to the second heavily doped region 23 and the first gate 30, and the orthographic projection of the second via connection portion 61 on the substrate 10 is located within the range of the orthographic projection of the second heavily doped region 23 on the substrate 10.

[0237] In step S5, the first electrode 50 formed includes a first via connection portion 51 and a first main portion 52, and the second electrode 60 formed includes a second via connection portion 61 and a second main portion 62. The first main portion 52 of the first electrode 50 and the second main portion 62 of the second electrode 60 are formed on the side of the first gate 30 away from the substrate 10. The first via connection portion 51 of the first electrode 50 and the second via connection portion 61 of the second electrode 60 are formed between the main portions (the first main portion 52 and the second main portion 52) and the first gate 30, so as to electrically connect the first main portion 52 and the first heavily doped region 22 using the first via connection portion 51. In addition, the second main portion 62 is electrically connected to the second heavily doped region 23 and the first gate 30 using the second via connection portion 61.

[0238] In summary, the method for manufacturing a thin-film transistor provided in the embodiment of the present disclosure provides a method for fabricating a thin-film transistor by setting the orthographic projection of the first gate electrode 30 on the substrate 10 to at least partially overlap with the orthographic projection of the second heavily doped region 23 on the substrate 10, and the orthographic projection of the second via connection portion 61 on the substrate 10 is located within the orthographic projection of the second heavily doped region 23 on the substrate 10. This allows the second via connection portion 61 to electrically connect the main body 62 of the second electrode 60 to the second heavily doped region 23 and the first gate electrode 30, while also improving the problem of increasing the size of the thin-film transistor T due to the addition of the second via connection portion 61 of the second electrode 60. That is, the thin-film transistor T provided in the embodiment of the present disclosure can improve the floating body effect of the thin-film transistor T while minimizing the change in the size of the thin-film transistor T, thereby improving the display quality of the display device 300 while ensuring the pixel density of the display device 300.

[0239] Figure 15 is a diagram of the film structure corresponding to step S14 in Figure 11. Figure 16 is a top view corresponding to step S14 in Figure 11.

[0240] In some embodiments, please refer to Figures 15 and 16 , step S14 in the method for manufacturing a thin film transistor, before step S15, that is, before forming the first electrode 50 and the second electrode 60 on the side of the first gate 30 away from the substrate 10, may also include: S141: forming a via W in the second heavily doped region 23.

[0241] Based on this, in step S15, forming the second pole 60 includes: the second via connection portion 61 of the second pole 60 passes through the via W and is electrically connected to the first gate 30. That is, when forming the second pole 60, the other end of the second via connection portion 61 fills the via W of the second heavily doped region 23, and the via W passing through the second heavily doped region 23 extends to be electrically connected to the first gate 30 at a position below. The second via connection portion 61 is used to electrically connect the second heavily doped region 23 and the first gate 30 at the same time. Furthermore, there is no need to add a connection portion that needs to bypass the active layer 20 in the thin film transistor T, which can improve the problem of the size of the thin film transistor T being increased due to the connection portion. In addition, since the thin film transistor T is electrically connected to the second heavily doped region 23 and the first gate 30 by extending the second via connection portion 61, there is no need to increase the process of the thin film transistor T.

[0242] Furthermore, by drilling a hole in the second heavily doped region 23 within the thin film transistor T, the second via connection portion 61 is electrically connected to the first gate 30 via the second heavily doped region 23. This allows full utilization of the longitudinal area between the second heavily doped region 23 and the first gate 30, and thus fully utilizes the internal space of the thin film transistor T, without increasing the size of the thin film transistor T. Subsequent application of the thin film transistor in the light-emitting drive circuit Q will not be limited by area size, and thus will not affect the pixel density of the display device 300.

[0243] FIG17 is a flow chart of a method for manufacturing a thin film transistor according to some other embodiments, and FIG18 is a diagram of a film layer structure corresponding to the steps in FIG17 .

[0244] In some embodiments, referring to FIG. 17 and FIG. 18 , a method for manufacturing a thin film transistor includes:

[0245] S21 : forming a first gate 30 on one side of the substrate 10 .

[0246] S22: An active layer 20 is formed on a side of the substrate 10 away from the first gate 30, the active layer 20 includes a channel 21, and a first region to be doped 21A and a second region to be doped 21B located on both sides of the channel 21, the orthographic projection of the first gate 30 on the substrate 10 at least partially overlaps with the orthographic projection of the second region to be doped 21B on the substrate 10, and the second region to be doped 21B includes a third via connection portion H, and the third via connection portion H is electrically connected to the first gate 30.

[0247] Before step S22 and after step S21 , the following steps may be included: forming a first gate insulating layer 71 on a side of the first gate 30 away from the substrate 10 , and forming a through hole in the first gate insulating layer 71 to expose the first gate 30 .

[0248] In step S22, an active layer 20 is formed on a side of the substrate 10 away from the first gate 30, that is, an active layer 20 is formed on a side of the first gate insulating layer 71 away from the first gate 30. When forming the active layer 20, the third via connection portion H of the second to-be-doped region 21B can fill the through hole in the first gate insulating layer 71, so that the third via connection portion H passes through the through hole and is electrically connected to the first gate 30.

[0249] It should be noted that in this step, only through holes are formed in the first gate insulating layer 71 at positions corresponding to the second to-be-doped regions 21B. That is, no drilling process is required in the first gate insulating layer 71 at positions corresponding to the first to-be-doped regions 21A.

[0250] Based on this, in the subsequent thin film transistor manufacturing method, when forming the first electrode 50, it will not extend to the first gate insulating layer 71, that is, it will not extend to the position of the first gate 30, causing the problem of short circuit with the first gate 30. Furthermore, when manufacturing the first gate 30 in the thin film transistor, there is no need to consider the problem of avoiding the first electrode 50. The first gate 30 can be expanded as much as possible so that the orthographic projection of the channel 21 in the subsequently formed active layer 20 on the substrate 10 is located within the orthographic projection of the first gate 30 on the substrate 10. This arrangement can ensure that the orthographic projection of the subsequently formed active layer 20 on the substrate 10 is located within the orthographic projection of the first gate 30 on the substrate 10.

[0251] This arrangement allows the step area formed at the edge of the first gate 30 to avoid the active layer 20 (the channel 21 in the active layer 20 ) to prevent the active layer 20 from being formed on an uneven surface, thereby ensuring the performance of the active layer 20 .

[0252] S23 : forming a second gate 40 on a side of the active layer 20 away from the substrate 10 .

[0253] S24 : Conducting the first to-be-doped region 21A and the second to-be-doped region 21B to form corresponding first heavily doped region 22 and second heavily doped region 23 .

[0254] S25: A first pole 50 and a second pole 60 are formed on the side of the first gate 30 away from the substrate 10, the first pole 50 includes a first via connection portion 51, and the first via connection portion 51 is electrically connected to the first heavily doped region 22; the second pole 60 includes a second via connection portion 61, and the second via connection portion 61 is electrically connected to the second heavily doped region 23, and the orthographic projection of the second via connection portion 61 on the substrate 10 is located within the range of the orthographic projection of the second heavily doped region 23 on the substrate 10.

[0255] In summary, in the method for fabricating a thin film transistor provided by the embodiments of the present disclosure, the second heavily doped region 23 may include a third via connection portion H, which penetrates the first gate insulating layer 71, electrically connecting the second medium doped region 23 to the first gate 30. Furthermore, the second electrode 60 may be electrically connected to the first gate 30 via the second via connection portion 61 and the second heavily doped region 23, in sequence. That is, the second electrode 60 may be indirectly electrically connected to the first gate 30 via the second via connection portion 61.

[0256] Based on this, there is no need to add a connection portion in the thin-film transistor T that needs to bypass the active layer 20, which can alleviate the problem of the thin-film transistor T being larger due to this connection portion. In addition, the longitudinal area between the second heavily doped region 23 and the first gate 30 can be fully utilized, that is, the internal space of the thin-film transistor T is fully utilized, without increasing the size of the thin-film transistor T. When it is subsequently applied to the light-emitting drive circuit Q, it will not be limited by the area size, and thus will not affect the pixel density of the display device 300.

[0257] FIG. 19 is a structural diagram illustrating some steps of a method for manufacturing a thin film transistor according to some embodiments.

[0258] In some embodiments, referring to FIG. 19 , FIG. 12 , or FIG. 18 , in step S12 (as shown in FIG. 12 ) or step S22 (as shown in FIG. 18 ), “forming an active layer 20 on a side of the substrate 10 away from the first gate 30 ” may include:

[0259] S101 : forming an amorphous silicon layer 201 on a side of the substrate 10 away from the first gate 30 .

[0260] S102 : performing an excimer laser annealing process (full name in English: Eximer Laser Annealing, English abbreviation: ELA) on the amorphous silicon layer 201 to form an initial active layer 202 of polycrystalline silicon.

[0261] S103 : etching the initial active layer 202 of polysilicon to form an active layer 20 .

[0262] However, since the first gate 30 has a certain thickness, the amorphous silicon layer will be formed on an uneven surface when the active layer 20 is manufactured, which will also cause protrusions or steps to form on the surface of the amorphous silicon layer. The problem of poor crystallization is likely to occur when the amorphous silicon layer is subsequently subjected to an excimer laser annealing process, thereby reducing the quality of the subsequently formed polycrystalline silicon active layer 20.

[0263] Based on the above problems, in the embodiment of the present disclosure, the orthographic projection of the channel 21 in the thin film transistor T on the substrate 10 can be set to be located within the orthographic projection of the first gate 30 on the substrate 10. The step region formed at the edge of the first gate 30 can be made to avoid the channel 21 in the active layer 20 to prevent the channel 21 of the active layer 20 from being formed on an uneven surface, thereby ensuring the conductivity of the channel 21 of the active layer 20.

[0264] In some embodiments, referring to FIG. 12 or FIG. 18 , in step S14 (as shown in FIG. 12 ) or step S24 (as shown in FIG. 18 ), “performing a conductor process on the first to-be-doped region 21A and the second to-be-doped region 21B using a masking process to form the corresponding first heavily doped region 22 and second heavily doped region 23 ” may include:

[0265] Using a self-aligned process, the first gate 30 is used as a mask to conduct the first and second regions to be doped 21A and 21B, thereby forming corresponding first and second heavily doped regions 22 and 23. This allows the projection of the second gate 40 on the substrate 10 to roughly coincide with the projection of the channel 21 on the substrate 10.

[0266] As described above, not only does a separate mask plate not need to be provided, but the orthographic projection of the second gate 40 on the substrate 10 can also be prevented from overlapping with the orthographic projections of the first heavily doped region 22 and / or the second heavily doped region 23 on the substrate 10, thereby preventing the introduction of parasitic capacitance and parasitic resistance in the overlapping region. This can help reduce parasitic effects and signal delays within the thin film transistor T, thereby improving the performance of the thin film transistor T.

[0267] The above description is merely a specific embodiment of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that a person skilled in the art can conceive within the technical scope disclosed in the present disclosure should be included within the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. A thin film transistor, comprising: substrate; An active layer, located on one side of the substrate, the active layer comprising a channel and a first heavily doped region and a second heavily doped region located on both sides of the channel; A first gate, located on a side of the active layer close to the substrate; a second gate, located at a side of the active layer away from the first gate, and an orthographic projection of the first gate on the substrate at least partially overlaps with an orthographic projection of the second heavily doped region on the substrate; A first electrode and a second electrode, the first electrode comprising a first main body portion and a first via-hole connecting portion, the second electrode comprising a second main body portion and a second via-hole connecting portion; the first main body portion and the second main body portion are located on a side of the second gate away from the active layer; The first via connection portion electrically connects the first main body portion and the first heavily doped region; the second via connection portion electrically connects the second main body portion, the second heavily doped region and the first gate, and the orthographic projection of the second via connection portion on the substrate is located within the orthographic projection of the second heavily doped region on the substrate.

2. The thin film transistor according to claim 1, wherein: The second heavily doped region includes at least one via hole, one end of the second via hole connecting portion is electrically connected to the second electrode, and the other end of the second via hole connecting portion passes through the via hole and is electrically connected to the first gate.

3. The thin film transistor according to claim 2, wherein: The orthographic projection of the first gate on the substrate does not overlap with the orthographic projection of the via on the substrate.

4. The thin film transistor according to any one of claims 1 to 3, wherein A minimum distance between an orthographic projection of the first gate on the substrate and an orthographic projection of the via hole on the substrate is greater than or equal to 0.5 μm.

5. The thin film transistor according to any one of claims 1 to 4, wherein: The orthographic projection of the channel on the substrate is located within the orthographic projection of the first gate on the substrate, and the minimum distance between the outer edge of the orthographic projection of the first gate on the substrate and the outer edge of the orthographic projection of the channel on the substrate is greater than or equal to 0.5 μm.

6. The thin film transistor according to claim 5, wherein: The orthographic projection of the second heavily doped region on the substrate is located within the orthographic projection of the first gate on the substrate.

7. The thin film transistor according to claim 6, wherein: Along the first direction, the first gate includes a first side and a second side that are arranged opposite to each other, and the first side is located on a side of the second side close to the first via connecting portion; the first direction is the direction from the first pole to the second pole; A minimum distance between an orthographic projection of the second side of the first gate on the substrate and an orthographic projection of a third side of the second heavily doped region away from the first heavily doped region on the substrate is greater than or equal to 0.5 μm.

8. The thin film transistor according to claim 7, wherein: A minimum distance between an orthographic projection of the second side of the first gate on the substrate and an orthographic projection of a third side of the second heavily doped region away from the first heavily doped region on the substrate is less than or equal to 10 μm.

9. The thin film transistor according to claim 1, wherein: One end of the second via connection portion is electrically connected to the second main body portion of the second electrode, and the other end of the second via connection portion is electrically connected to the first gate through the second heavily doped region.

10. The thin film transistor according to claim 9, wherein the orthographic projection of the channel on the substrate is located within the orthographic projection of the first gate on the substrate, and a minimum spacing between an outer edge of the orthographic projection of the first gate on the substrate and an outer edge of the orthographic projection of the channel on the substrate is greater than or equal to 0.5 μm.

11. The thin film transistor according to claim 9 or 10, wherein: The orthographic projection of the active layer on the substrate is located within the orthographic projection of the first gate on the substrate.

12. The thin film transistor according to any one of claims 9 to 11, wherein: A minimum distance between an outer edge of an orthographic projection of the first gate on the substrate and an outer edge of an orthographic projection of the active layer on the substrate is greater than or equal to 0.5 μm.

13. The thin film transistor according to claim 12, wherein: A minimum distance between an outer edge of an orthographic projection of the first gate on the substrate and an outer edge of an orthographic projection of the active layer on the substrate is less than or equal to 10 μm.

14. The thin film transistor according to any one of claims 1 to 13, wherein: The active layer further includes a first low-doping region and a second low-doping region; The first low-doped region is located between the first heavily-doped region and the channel, and the doping concentration of the first low-doped region is less than the doping concentration of the first heavily-doped region; The second low-doped region is located between the second heavily-doped region and the channel, and a doping concentration of the second low-doped region is less than a doping concentration of the second heavily-doped region.

15. The thin film transistor according to any one of claims 1 to 14, wherein: The projection of the second gate on the substrate substantially coincides with the projection of the channel on the substrate.

16. The thin film transistor according to any one of claims 1 to 15, wherein the thickness of the active layer ranges from 17. A method for manufacturing a thin film transistor, comprising: forming a first gate on one side of the substrate; An active layer is formed on a side of the substrate away from the first gate, the active layer comprising a channel, and a first region to be doped and a second region to be doped located on both sides of the channel, and an orthographic projection of the first gate on the substrate at least partially overlaps with an orthographic projection of the second region to be doped on the substrate; forming a second gate on a side of the active layer away from the substrate; Conducting the first region to be doped and the second region to be doped to form a corresponding first heavily doped region and a second heavily doped region; A first pole and a second pole are formed on a side of the first gate away from the substrate, the first pole includes a first via connection portion, the first via connection portion is electrically connected to the first heavily doped region; the second pole includes a second via connection portion, the second via connection portion is electrically connected to the second heavily doped region and the first gate, and the orthographic projection of the second via connection portion on the substrate is located within the range of the orthographic projection of the second heavily doped region on the substrate.

18. The manufacturing method according to claim 17, before forming the first electrode and the second electrode on the side of the first gate away from the substrate, further comprising: forming a via hole in the second heavily doped region; Forming the second electrode includes: the second via hole connecting portion of the second electrode passes through the via hole and is electrically connected to the first gate.

19. A method for manufacturing a thin film transistor, comprising: forming a first gate on one side of the substrate; An active layer is formed on a side of the substrate away from the first gate, the active layer comprising a channel, and a first region to be doped and a second region to be doped located on both sides of the channel, an orthographic projection of the first gate on the substrate at least partially overlaps with an orthographic projection of the second region to be doped on the substrate, and the second region to be doped comprises a third via connection portion, and the third via connection portion is electrically connected to the first gate; forming a second gate on a side of the active layer away from the substrate; Conducting the first region to be doped and the second region to be doped to form a first heavily doped region and a second heavily doped region; A first pole and a second pole are formed on a side of the first gate away from the substrate, the first pole includes a first via connection portion, the first via connection portion is electrically connected to the first heavily doped region; the second pole includes a second via connection portion, the second via connection portion is electrically connected to the second heavily doped region, and the orthographic projection of the second via connection portion on the substrate is located within the range of the orthographic projection of the second heavily doped region on the substrate.

20. A light-emitting substrate, comprising: The thin film transistor according to any one of claims 1 to 16.

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