Display panel and manufacturing method therefor, and display apparatus

Abstract

A display panel (100) and a manufacturing method therefor, and a display apparatus, which relate to the technical field of display. The display panel (100) comprises: an array substrate (10) and a light-emitting layer (20), wherein the light-emitting layer (20) has a plurality of light-emitting units, and each light-emitting unit comprises an anode block (211), a light-emitting functional layer (221) and a cathode block (231), which are sequentially stacked in the direction away from the array substrate (10); and the light-emitting layer (20) comprises a cathode layer (23), which cathode layer (23) comprises a plurality of cathode blocks (231), and the plurality of cathode blocks (231) are distributed at intervals. The cathode layer (23) comprises a plurality of cathode blocks (231) distributed at intervals, and thus the brightness of the cathode layer (23) in a region other than the light-emitting units is reduced, thereby further improving the brightness of the display panel (100) when displaying pictures, and improving a display effect.

Description

Display panel, manufacturing method, and display device

[0001] Cross-references

[0002] This disclosure claims priority to Chinese patent application number 202310931110.9 filed on July 27, 2023, entitled “Display panel, manufacturing method, and display device,” and the entire contents of this Chinese patent application are incorporated herein by reference. Technical Field

[0003] The present disclosure relates to the field of display technology, and in particular to a display panel and a manufacturing method thereof, and a display device. Background Art

[0004] Display panels have been widely used in electronic devices such as mobile phones, computers and televisions, and with the rapid development of display panels, users have increasingly higher requirements for the display quality of display panels, such as the brightness of the display screen.

[0005] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present disclosure, and therefore may include information that does not constitute prior art known to ordinary technicians in the field.

[0006] Summary of the Invention

[0007] The present disclosure aims to provide a display panel, a manufacturing method thereof, and a display device, which can improve the brightness of a displayed image.

[0008] According to one aspect of the present disclosure, there is provided a display panel, comprising:

[0009] array substrate;

[0010] a light-emitting layer located on one side of the array substrate and having a plurality of light-emitting units, each light-emitting unit including an anode block, a light-emitting functional layer, and a cathode block stacked in sequence in a direction away from the array substrate;

[0011] The light-emitting layer includes a cathode layer, and the cathode layer includes a plurality of cathode blocks, and the plurality of cathode blocks are distributed at intervals.

[0012] According to any display panel described in the present disclosure, the cathode layer includes multiple groups of cathode blocks, and each group of cathode blocks is an integrated structure.

[0013] According to any display panel described in the present disclosure, each group of cathode blocks includes two cathode blocks.

[0014] According to any display panel described in the present disclosure, the cathode layer further includes a voltage signal line, and the voltage signal line is connected to the cathode block.

[0015] According to any display panel disclosed herein, the array substrate has a voltage signal line, and the light-emitting layer further has a transition portion, and the transition portion is respectively connected to the voltage signal line and the cathode block.

[0016] According to any display panel described in the present disclosure, the array substrate includes a single source-drain metal layer, and the source-drain metal layer has the voltage signal line.

[0017] According to any display panel described in the present disclosure, the array substrate includes multiple source / drain metal layers, and at least one of the source / drain metal layers has the voltage signal line.

[0018] According to any display panel disclosed herein, at least two of the multiple source / drain metal layers have the voltage signal lines, and the voltage signal lines of at least two of the source / drain metal layers extend in different directions.

[0019] According to any display panel described in the present disclosure, the source-drain metal layer is a composite structure layer.

[0020] According to any display panel described in the present disclosure, the source / drain metal layer includes a titanium metal layer, an aluminum metal layer, and a titanium metal layer stacked in sequence.

[0021] According to any display panel disclosed in the present invention, the adapter portion includes an anode adapter block and a light-emitting adapter block, the anode adapter block and the anode block are on the same layer and are distributed at intervals, the light-emitting adapter block is on the same layer as the light-emitting functional layer, and the light-emitting adapter block includes at least one layer of a hole injection layer, a hole transport layer, an electron blocking layer, a hole blocking layer, an electron transport layer and an electron injection layer.

[0022] According to any of the display panels disclosed herein, the light-emitting adapter blocks and the light-emitting functional layer are spaced apart from each other.

[0023] According to any display panel described in the present disclosure, the light-emitting layer further includes a partition portion, which is in the same layer as the light-emitting adapter block and is located between the light-emitting functional layer and the light-emitting adapter block.

[0024] According to one aspect of the present disclosure, a method for manufacturing a display panel is provided, the method comprising:

[0025] manufacturing an array substrate;

[0026] A light-emitting layer is produced on one side of the array substrate, and the light-emitting layer has a plurality of light-emitting units. The light-emitting units include an anode block, a light-emitting functional layer, and a cathode block stacked in sequence in a direction away from the array substrate. The light-emitting layer includes a cathode layer, and the cathode layer includes a plurality of cathode blocks, and the plurality of cathode blocks are distributed at intervals.

[0027] According to any of the methods described in the present disclosure, the cathode layer further includes a voltage signal line, and the voltage signal line is connected to the cathode block.

[0028] According to any method of the present disclosure, manufacturing an array substrate includes: manufacturing an array substrate having voltage signal lines;

[0029] The light emitting layer is manufactured on one side of the array substrate, comprising: manufacturing the light emitting layer having a transition portion on one side of the array substrate, wherein the transition portion is respectively connected to the voltage signal line and the cathode block.

[0030] According to one aspect of the present disclosure, a display device is provided, comprising the display panel described in the above aspect.

[0031] The embodiments of the present disclosure include at least the following technical effects:

[0032] In the embodiment of the present disclosure, the cathode layer includes a plurality of cathode blocks distributed at intervals to reduce the shading of the brightness by the cathode layer in areas outside the light-emitting units, thereby further improving the brightness of the display panel when displaying images and improving the display effect.

[0033] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] The accompanying drawings are incorporated into and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification, are used to explain the principles of the present disclosure. Obviously, the drawings described below are only some embodiments of the present disclosure, and those skilled in the art can derive other drawings based on these drawings without inventive effort.

[0035] FIG1 is a schematic cross-sectional view of a display panel according to an embodiment of the present disclosure.

[0036] FIG2 is a schematic cross-sectional view of another display panel provided in an embodiment of the present disclosure.

[0037] FIG3 is a schematic cross-sectional view of another display panel provided in an embodiment of the present disclosure.

[0038] FIG4 is a schematic diagram of a top view of a display panel provided in an embodiment of the present disclosure.

[0039] FIG5 is a schematic cross-sectional view of another display panel provided in an embodiment of the present disclosure.

[0040] FIG6 is a schematic cross-sectional view of another display panel provided in an embodiment of the present disclosure.

[0041] FIG. 7 is a schematic diagram of a manufacturing process of a display panel provided in an embodiment of the present disclosure.

[0042] Figure numerals: 100, display panel; 10, array substrate; 20, light-emitting layer; 30, voltage signal line; 11, base substrate; 12, driving layer; 121, buffer layer; 122, semiconductor layer; 123, gate insulating layer; 124, gate metal layer; 125, interlayer dielectric layer; 126, source-drain metal layer; 127, flat layer; 21, anode layer; 22, organic light-emitting layer; 23, cathode layer; 24, pixel definition layer; 25, transfer part; 211, anode block; 212, anode transfer block; 221, light-emitting functional layer; 222, light-emitting transfer block; 223, partition part 223; 231, cathode block; 241, pixel opening; 242, transfer opening. DETAILED DESCRIPTION

[0043] Example embodiments will now be described more fully with reference to the accompanying drawings. However, the example embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the concepts of the example embodiments to those skilled in the art. Like reference numerals in the figures represent identical or similar structures, and thus their detailed descriptions will be omitted. Furthermore, the figures are merely schematic illustrations of the present disclosure and are not necessarily drawn to scale.

[0044] Although relative terms such as "upper" and "lower" are used in this specification to describe the relationship of one illustrated component to another, these terms are used herein for convenience only, such as in accordance with the orientation of the illustrations in the accompanying drawings. It will be understood that if the illustrated device were flipped upside down, the component described as "upper" would become the component "lower." When a structure is referred to as "on" another structure, this may mean that the structure is integrally formed with the other structure, that the structure is "directly" disposed on the other structure, or that the structure is "indirectly" disposed on the other structure via the other structure.

[0045] The terms "a", "an", "the", "said" and "at least one" are used to indicate the presence of one or more elements / components / etc.; the terms "including" and "having" are used to express open-ended inclusion and mean that additional elements / components / etc. may be present in addition to the listed elements / components / etc.; the terms "first", "second" and "third" etc. are used only as labels and are not intended to limit the quantity of their objects.

[0046] In the present disclosure, a transistor refers to an element that includes at least three terminals: a gate, a drain, and a source. The transistor has a channel region between the drain (drain terminal, drain region, or drain electrode) and the source (source terminal, source region, or source electrode), and current can flow through the drain, the channel region, and the source. The channel region refers to the region where the current mainly flows. In cases where transistors of opposite types are used or the direction of current changes during circuit operation, the functions of the "source" and the "drain" are sometimes interchanged. Therefore, in the present disclosure, the "source" and the "drain" can be interchanged. Structurally, a transistor can have a first electrode, a second electrode, and a control electrode, wherein the gate of the transistor can serve as the control electrode of the transistor; one of the source and the drain of the transistor can serve as the first electrode of the transistor, and the other can serve as the second electrode of the transistor.

[0047] In this disclosure, the "on" state of a transistor refers to a state in which the source and drain of the transistor are electrically connected. The "off" state of a transistor refers to a state in which the source and drain of the transistor are electrically disconnected. It is understood that when a transistor is off, leakage current may still exist.

[0048] The present disclosure provides a display panel 100. As shown in FIG1 , the display panel 100 includes an array substrate 10 and a light-emitting layer 20. The array substrate 10 is formed with a plurality of pixel circuits. The light-emitting layer 20 is located on one side of the array substrate 10 and has a plurality of light-emitting units. Each pixel circuit is connected to at least one corresponding light-emitting unit (for example, one pixel circuit is connected to one corresponding light-emitting unit). In this way, the pixel circuit can drive the corresponding light-emitting unit to emit light, thereby realizing image display.

[0049] The multiple pixel circuits on the array substrate 10 can be arranged in an array. The pixel circuits can be 1T1C, 2T1C, 7T1C, or other circuits, as long as they can drive at least one corresponding light-emitting unit to emit light. This is not particularly limited in the present embodiment. nTmC indicates that a pixel circuit includes n transistors (represented by the letter "T") and m capacitors Cst (represented by the letter "C").

[0050] The capacitor Cst included in the pixel circuit can be a storage capacitor, a parasitic capacitor, etc. Of course, each pixel circuit can also include both a storage capacitor and a parasitic capacitor. For the same type of capacitor Cst included in multiple pixel circuits, the projected areas of the capacitors Cst in the thickness direction of the array substrate 10 are equal (equal here refers to the equality in theoretical design and does not limit the error caused by the manufacturing process). This ensures that the electrical parameters of each pixel circuit are the same, and thus ensures that the light-emitting units corresponding to each pixel circuit have the same luminous effect when emitting light.

[0051] As shown in FIG1 , the array substrate 10 includes a transparent base substrate 11 and a driving layer 12 located on one side of the base substrate 11 , or includes a silicon substrate and a wiring layer located on one side of the silicon substrate.

[0052] Taking the array substrate 10 as an example, the base substrate 11 and the drive layer 12 may be, for example, a glass substrate, a quartz substrate, a plastic substrate, or other transparent, rigid or flexible substrate, and may be a single-layer or multi-layer structure. Taking a multi-layer structure as an example, the base substrate 11 includes a first PI (polyimide) layer, a first protective layer, a second PI (polyimide) layer, and a second protective layer stacked from bottom to top. The two protective layers are used to protect the PI layer and prevent damage to the PI layer during subsequent processes. The second protective layer is also covered with a buffer layer 121 to block water and oxygen and block alkaline ions.

[0053] As shown in FIG1 , the driving layer 12 includes a buffer layer 121, a transistor layer, an interlayer dielectric layer 125, a source / drain metal layer 126, and a planar layer 127, which are sequentially distributed in a direction away from the substrate 11. The transistor layer includes a semiconductor layer 122, a gate insulating layer 123, and a gate metal layer 124, which are stacked between the buffer layer 121 and the interlayer dielectric layer 125. The positional relationship of the various film layers included in the transistor layer can be determined based on the film layer structure of the thin film transistor.

[0054] Among them, the material of the buffer layer 121 can be an inorganic insulating material such as silicon oxide, silicon nitride, etc., and the buffer layer 121 can be a layer of inorganic material layer or a multi-layer stacked inorganic material layer. The semiconductor layer 122 can be used to form the active part of each transistor included in the pixel circuit, and each active part includes a channel region and two connecting parts located on both sides of the channel region (i.e., the source and drain of the transistor). Among them, the channel region can maintain semiconductor properties, and the semiconductor materials corresponding to the two connecting parts are partially or completely conductive. The gate metal layer 124 can be used to form scan lines (the scan lines form the gate of the transistor in the area overlapping with the channel region of the active part) and other wirings, and can also be used to form the second plate of the storage capacitor. The source and drain metal layer 126 can be used to form source and drain metal layer 126 wirings such as power lines, data lines, sensing lines, and connecting lines, and can also be used to form a first plate for forming a storage capacitor.

[0055] In some embodiments, the semiconductor layer 122 may be a single semiconductor layer 122 or a double semiconductor layer 122. Exemplarily, the semiconductor layer 122 includes a low-temperature polysilicon semiconductor layer 122. The gate metal layer 124 may be a single gate metal layer 124 or a double or triple gate metal layer 124. Exemplarily, the gate metal layer 124 includes a single gate metal layer 124.

[0056] It is understood that when the gate metal layer 124 or the semiconductor layer 122 has a multi-layer structure, the gate insulating layer 123 in the transistor layer can be adaptively increased or decreased. For example, the driving layer 12 includes a low-temperature polysilicon semiconductor layer 122, a gate insulating layer 123, and a gate metal layer 124 stacked in sequence on the base substrate 11.

[0057] In some embodiments, the source / drain metal layer 126 may be a single source / drain metal layer 126, or may be two or three source / drain metal layers 126. For example, as shown in FIG2 , the driving layer 12 includes a single source / drain metal layer 126, and as shown in FIG1 , the driving layer 12 includes two source / drain metal layers 126. In the case of multiple source / drain metal layers 126, a passivation layer and / or a planarization layer 127 is provided between two adjacent source / drain metal layers 126 to achieve insulation between the two adjacent source / drain metal layers 126 via the passivation layer and / or the planarization layer 127.

[0058] In some embodiments, the light-emitting unit may be an organic light-emitting diode, a micro light-emitting diode, a quantum dot-organic light-emitting diode, a quantum dot light-emitting diode, or other types of light-emitting units.

[0059] For example, in some embodiments, the light emitting unit is an organic light emitting diode, and the display panel 100 is an OLED display panel 100. Below, taking the light emitting unit as an organic light emitting diode as an example, a feasible structure of the light emitting unit is described.

[0060] As shown in Figure 1 or Figure 2, the light-emitting unit includes an anode block 211, a light-emitting functional layer 221 and a cathode block 231 stacked in sequence in a direction away from the array substrate 10. The light-emitting functional layer 221 may include an organic electroluminescent material layer, and may also include one or more of a hole injection layer, a hole transport layer, an electron blocking layer, a hole blocking layer, an electron transport layer and an electron injection layer.

[0061] In addition, as shown in Figure 1 or Figure 2, the light-emitting layer 20 also includes a pixel definition layer 24 arranged on the side of the driving layer 12 away from the base substrate 11. The pixel definition layer 24 is provided with pixel openings 241 corresponding to multiple light-emitting units one by one. Each light-emitting unit is located in the corresponding pixel opening 241, and the anode block 211 includes an exposed area exposed at the corresponding pixel opening 241 and an area covered by the pixel definition layer 24. The exposed area of ​​the anode block 211 forms the light-emitting area of ​​the corresponding light-emitting unit.

[0062] In some embodiments, the display panel 100 may further include a thin film encapsulation layer disposed on a side of the light emitting layer 20 facing away from the array substrate 11 . The thin film encapsulation layer may include an inorganic encapsulation layer and an organic encapsulation layer alternately stacked.

[0063] Among them, the inorganic encapsulation layer can effectively block external moisture and oxygen, preventing water and oxygen from invading the organic light-emitting functional layer 221 and causing material degradation; the organic encapsulation layer is located between two adjacent inorganic encapsulation layers to achieve flattening and reduce stress between the inorganic encapsulation layers.

[0064] The display panel 100 includes a display area and a peripheral area located outside the display area. The edge of the inorganic encapsulation layer may be located in the peripheral area, and the edge of the organic encapsulation layer may be located between the edge of the display area and the edge of the inorganic encapsulation layer. For example, the thin film encapsulation layer includes a first inorganic encapsulation layer, an organic encapsulation layer, and a second inorganic encapsulation layer sequentially stacked on the side of the light-emitting layer 20 facing away from the array substrate 11.

[0065] In some embodiments, the display panel 100 may further include a touch function layer, which is disposed on a side of the thin film encapsulation layer facing away from the array substrate 11 , for implementing touch operation of the display panel 100 .

[0066] In an embodiment of the present disclosure, as shown in Figure 1 or Figure 2, the light-emitting layer 20 includes an anode layer 21, an organic light-emitting layer 22 and a cathode layer 23 stacked in a direction away from the array substrate 10, the anode layer 21 includes an anode block 211 of a plurality of light-emitting units, the organic light-emitting layer 22 includes a light-emitting functional layer 221 of a plurality of light-emitting units, and the cathode layer 23 includes a cathode block 231 of a plurality of light-emitting units.

[0067] 1 or 2 , the cathode layer 23 includes a plurality of cathode blocks 231 that are spaced apart. This reduces the brightness obstruction of the cathode layer 23 in areas outside the light-emitting unit, thereby further increasing the brightness of the display panel 100 when displaying images and improving the display effect.

[0068] The display panel 100 includes a voltage signal line 30 to load a voltage signal (i.e., a VSS signal) onto the cathode block 231 via the voltage signal line 30. For the multiple cathode blocks 231 included in the cathode layer 23, when displaying an image, a voltage signal can be loaded onto each cathode block 231 individually. In this case, the display panel 100 includes multiple voltage signal lines 30 corresponding one-to-one to the multiple cathode blocks 231, thereby loading voltage signals onto the multiple cathode blocks 231 respectively via the multiple voltage signal lines 30. Of course, some of the multiple cathode blocks 231 can also be used as an integrated structure to load voltage signals. In this case, the display panel 100 includes multiple voltage signal lines 30, and each voltage signal line 30 corresponds to the multiple cathode blocks 231 of the integrated structure, thereby loading voltage signals onto the multiple cathode blocks 231 of the integrated structure via one voltage signal line 30.

[0069] Regarding the aforementioned integrated cathode blocks 231, as shown in Figures 3 and 4 , the cathode layer 23 includes multiple groups of cathode blocks 231, each group of cathode blocks 231 being an integrated structure. Thus, the cathode blocks 231 included in the cathode layer 23 are divided into multiple groups, thereby reducing the number of voltage signal lines 30 carrying voltage signals, thereby simplifying the structure of the display panel 100 and simplifying the manufacturing process.

[0070] Among them, the multiple groups of cathode blocks 231 of the cathode layer 23 can be produced through a fine mask plate, and the multiple cathode blocks 231 included in each group can be integrated into an integrated structure through connecting strips, so as to reduce the obstruction of brightness through the narrower connecting strips and ensure the brightness of the display panel 100 when displaying the picture.

[0071] The number of cathode blocks 231 included in each group may be the same, different, or not all the same. For example, if the number of cathode blocks 231 included in each group is the same, as shown in FIG3 or FIG4 , each group of cathode blocks 231 includes two cathode blocks 231 . For example, if the number of cathode blocks 231 included in each group is not all the same, some of the multiple groups of cathode blocks 231 include two cathode blocks 231 , and the remaining groups include three cathode blocks 231 .

[0072] In the embodiment of the present disclosure, for the voltage signal line 30 that loads a voltage signal on the cathode block 231, combined with the above-mentioned display panel 100 including the array substrate 10 and the light-emitting layer 20, the voltage signal line 30 can be formed on the array substrate 10, or on the light-emitting layer 20. Of course, the voltage signal line 30 can also be formed on both the array substrate 10 and the light-emitting layer 20.

[0073] In some embodiments, the voltage signal line 30 is formed on the light emitting layer 20 , that is, the light emitting layer 20 includes the voltage signal line 30 , and the voltage signal line 30 is connected to the cathode block 231 .

[0074] In particular, in conjunction with the aforementioned situation where the light-emitting layer 20 includes an anode layer 21, an organic light-emitting layer 22, and a cathode layer 23, the voltage signal line 30 can be formed on the anode layer 21, or can be formed on the cathode layer 23. Of course, to avoid increased process difficulty due to a large number of voltage signal lines 30 when a single layer is provided, the voltage signal line 30 can be formed on both the anode layer 21 and the cathode layer 23, but the embodiments of the present disclosure are not limited to this.

[0075] When the anode layer 21 is formed with a voltage signal line 30, the voltage signal line 30 extends outside the anode block 211 and is spaced apart from the anode block 211 to avoid crosstalk between the anode block 211 and the voltage signal line 30. In conjunction with the aforementioned case where the light-emitting layer 20 includes the pixel definition layer 24, the pixel definition layer 24 has, in addition to the pixel opening 241, a transfer opening 242 (there is no overlap between the transfer opening 242 and the pixel opening 241), so that after the pixel definition layer 24 covers the voltage signal line 30, the voltage signal line 30 is exposed at the transfer opening 242, and the exposed portion of the voltage signal line 30 at the transfer opening 242 is then connected to the cathode block 231.

[0076] When the voltage signal line 30 is connected to the cathode block 231 at the transfer opening 242, if the multiple light-emitting functional layers 221 included in the organic light-emitting layer 22 form an integrated structure, the voltage signal line 30 can be connected to the cathode block 231 through the organic light-emitting layer 22. In this case, although leakage current will be generated between the voltage signal line 30 and the adjacent anode block 211 due to the presence of the organic light-emitting layer 22, the resistivity of the organic light-emitting layer 22 in the direction perpendicular to the display panel 100 is more than 20 times the resistivity of the anode block 211, and the resistivity of the organic light-emitting layer 22 is even greater within the plane of the display panel 100. Therefore, the leakage current generated by the organic light-emitting layer 22 can be ignored, ensuring that the voltage signal applied to the cathode block 231 by the voltage signal line 30 is sufficient.

[0077] If the organic light-emitting layer 22 includes multiple light-emitting functional layers 221 that are distributed at intervals, the transfer opening 242 on the pixel definition layer 24 is located in an area outside the pixel opening 241, thereby ensuring that the cathode block 231 is directly connected to the voltage signal line 30 on the anode layer 21 at the transfer opening 242, while avoiding leakage current between the voltage signal line 30 and the anode block 211.

[0078] When the cathode layer 23 is formed with a voltage signal line 30, as shown in Figure 1 or Figure 3, the voltage signal line 30 is located outside the cathode block 231. The voltage signal line 30 and the cathode block 231 can be connected by a connecting block or can be an integral structure, which is not limited in the present embodiment.

[0079] It should be noted that, compared with the case where the voltage signal line 30 is formed in the cathode layer 23, when the voltage signal line 30 is formed in the anode layer 21, whether the voltage signal line 30 is light-transmitting will not affect the brightness of the display panel 100, thereby facilitating the use of a metal material with a lower resistivity to make the voltage signal line 30, so as to reduce the voltage drop when the voltage signal is loaded on the cathode block 231, thereby reducing power consumption.

[0080] In other embodiments, as shown in FIG. 2 or FIG. 5 , the voltage signal line 30 is formed on the array substrate 10. That is, the array substrate 10 includes the voltage signal line 30. In this case, the light-emitting layer 20 further includes a transition portion 25, which is respectively connected to the voltage signal line 30 and the cathode block 231. In this manner, since whether the voltage signal line 30 is light-transmissive does not affect the brightness of the display panel 100, it is convenient to use a metal material with a low resistivity to manufacture the voltage signal line 30, thereby reducing the voltage drop when the voltage signal is applied to the cathode block 231, thereby reducing power consumption.

[0081] The voltage signal lines 30 formed on the array substrate 10 include a metal layer. Optionally, the metal layer comprises a composite structure to further reduce the resistivity of the voltage signal lines 30 on the metal layer, thereby reducing power consumption during voltage signal transmission. For example, the metal layer includes a titanium metal layer, an aluminum metal layer, and a titanium metal layer stacked in sequence.

[0082] In conjunction with the above-mentioned case where the array substrate 10 includes a source-drain metal layer 126, as shown in Figure 5 or Figure 6, the source-drain metal layer 126 can be formed with a voltage signal line 30. In this case, the voltage signal on the source-drain metal layer 126 can be connected to the adapter 25 through the via hole on the flat layer 127. In this case, the source-drain metal layer 126 can be a composite structure layer to reduce power consumption during voltage signal transmission. For example, the source-drain metal layer 126 includes a titanium metal layer, an aluminum metal layer, and a titanium metal layer stacked in sequence. In addition, the voltage signal line 30 located on the source-drain metal layer 126 can be implemented using SIP technology.

[0083] When the array substrate 10 includes a single source / drain metal layer 126 , the source / drain metal layer 126 has a voltage signal line 30 ; when the array substrate 10 includes multiple source / drain metal layers 126 , at least one source / drain metal layer 126 has a voltage signal line 30 .

[0084] Among them, for the case where one of the multiple source-drain metal layers 126 has a voltage signal line 30, if the voltage signal line 30 is formed on a layer of the multiple source-drain metal layers 126 close to the base substrate 11, the voltage signal line 30 can be connected to the transition part 25 through the vias on the interlayer dielectric layer 125 and the flat layer 127; and if the voltage signal line 30 is formed on a layer of the multiple source-drain metal layers 126 close to the light-emitting layer 20, the voltage signal line 30 can be connected to the transition part 25 through the vias on the flat layer 127.

[0085] In the case where at least two of the multiple source / drain metal layers 126 have voltage signal lines 30, the voltage signal lines 30 on the two source / drain metal layers 126 can be connected to different cathode blocks 231 via different adapters 25, or can be connected to the same cathode block 231 via the same adapter 25. Furthermore, when voltage signal lines 30 of different layers are connected to the same cathode block 231, the transmission resistance of the voltage signal can be further reduced, thereby reducing power consumption while also reducing voltage drop.

[0086] The voltage signal lines 30 on at least two source / drain metal layers 126 may extend in the same direction. Alternatively, the voltage signal lines 30 on at least two source / drain metal layers 126 may extend in different directions. For example, both source / drain metal layers 126 have voltage signal lines 30 , and the voltage signal lines 30 on the two source / drain metal layers 126 extend in directions perpendicular to each other.

[0087] Regarding the adapter 25 of the light-emitting layer 20 , in combination with the structure of the light-emitting layer 20 described above, the adapter 25 includes an anode adapter block 212 , or as shown in FIG. 5 or 6 , the adapter 25 includes an anode adapter block 212 and a light-emitting adapter block 222 .

[0088] The anode adapter block 212 is located in the anode layer 21 of the light-emitting layer 20 and is spaced apart from the anode block 211. The anode adapter block 212 is directly connected to the voltage signal line 30 and the cathode block 231. The light-emitting adapter block 222 is located in the organic light-emitting layer 22 of the light-emitting layer 20 and includes at least one of a hole injection layer, a hole transport layer, an electron blocking layer, a hole blocking layer, an electron transport layer, and an electron injection layer. The connection between the anode adapter block 212 and the cathode block 231 is achieved through the light-emitting adapter block 222. The light-emitting adapter block 222 and the light-emitting functional layer 221 can be spaced apart or formed as an integrated structure.

[0089] When the adapter portion 25 includes the anode adapter block 212, the anode adapter block 212 is respectively connected to the voltage signal line 30 and the cathode block 231 of the array substrate 10. To ensure the connection between the anode adapter block 212 and the cathode block 231, the organic light-emitting layer 22 includes multiple light-emitting functional layers 221 spaced apart, and the pixel definition layer 24 has an adapter opening 242 located outside the pixel opening 241. At least a portion of the anode adapter block 212 is exposed at the adapter opening 242. The cathode block 231 is located outside the light-emitting functional layers 221 and is connected to the exposed portion of the anode adapter block 212 at the adapter opening.

[0090] When the adapter portion 25 includes the anode adapter block 212 and the light-emitting adapter block 222, the anode adapter block 212 and the light-emitting adapter block 222 function as a whole to connect the voltage signal line 30 to the cathode block 231. If the light-emitting adapter block 222 and the light-emitting functional layer 221 are an integral structure, leakage current may occur between the anode adapter block 212 and the anode block 211 due to the organic light-emitting layer 22. However, since the resistivity of the organic light-emitting layer 22 in a direction perpendicular to the display panel 100 is more than 20 times that of the anode block 211, and the resistivity of the organic light-emitting layer 22 is even greater within the plane of the display panel 100, the leakage current generated between the anode adapter block 212 and the anode block 211 can be ignored, ensuring that the voltage signal applied to the cathode block 231 by the voltage signal line 30 is carried.

[0091] If the light-emitting adapter block 222 and the light-emitting functional layer 221 are spaced apart, leakage current generated between the anode adapter block 212 and the anode block 211 due to the organic light-emitting layer 22 can be completely avoided. Furthermore, the light-emitting layer 20 also includes a partition portion 223, which is on the same layer as the light-emitting adapter block 222 and is located between the light-emitting functional layer 221 and the light-emitting adapter block 222. That is, as shown in Figure 5 or Figure 6, the organic light-emitting layer 22 of the light-emitting layer 20 has a partition portion 223, and the partition portion 223 is located between the light-emitting adapter block 222 and the light-emitting functional layer 221, so that the partition portion 223 effectively blocks the conduction between the light-emitting functional layer 221 and the light-emitting adapter block 222.

[0092] The present disclosure also provides a method for manufacturing a display panel, which is used to manufacture the display panel described in the above embodiment. As shown in FIG7 , the method includes the following steps S110 to S120 .

[0093] Step S110: manufacturing an array substrate;

[0094] Step S120: A light-emitting layer is produced on one side of the array substrate. The light-emitting layer has multiple light-emitting units. The light-emitting units include an anode block, a light-emitting functional layer, and a cathode block stacked in sequence in a direction away from the array substrate. The light-emitting layer includes a cathode layer. The cathode layer includes multiple cathode blocks, and the multiple cathode blocks are distributed at intervals.

[0095] In the embodiment of the present disclosure, the plurality of cathode blocks distributed at intervals can reduce the shading of brightness by the cathode layer in areas outside the light-emitting units, thereby increasing the brightness of the display panel when displaying images and improving the display effect.

[0096] In conjunction with the above embodiment, the display panel further includes voltage signal lines. In this case, if the voltage signal lines are formed on the cathode layer of the light-emitting layer, the cathode layer of the light-emitting layer produced in step S120 also includes voltage signal lines, and the voltage signal lines are connected to the cathode block. The specific structure of the array substrate produced in step S110 can be referred to the above embodiment.

[0097] If the electrical signal lines are formed on the array substrate, step S110 includes fabricating an array substrate having voltage signal lines. Step S120 includes fabricating a light-emitting layer having a transition portion on one side of the array substrate, the transition portion being connected to the voltage signal lines and the cathode block, respectively. The specific structures of the array substrate and light-emitting layer fabricated in steps S110 and S120 can be referenced to those described in the above embodiments and will not be further described in this disclosure.

[0098] The present disclosure also provides a display device, which includes the display panel described in the above embodiment. Thus, by using the display panel described in the above embodiment, the brightness of the display screen of the display device can be effectively increased, thereby improving the display effect.

[0099] Those skilled in the art will readily appreciate other embodiments of the present disclosure after considering the specification and practicing the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present disclosure that follow the general principles of the present disclosure and include common knowledge or customary techniques in the art not disclosed herein. The description and examples are to be considered as exemplary only, with the true scope and spirit of the present disclosure being indicated by the appended claims.

Claims

1. A display panel, characterized in that: include: An array substrate; A light-emitting layer, located on one side of the array substrate, and having a plurality of light-emitting units, wherein the light-emitting units include an anode block, a light-emitting functional layer, and a cathode block stacked in sequence in a direction away from the array substrate; Wherein, the light-emitting layer includes a cathode layer, the cathode layer includes a plurality of cathode blocks, and the plurality of cathode blocks are distributed at intervals.

2. The display panel according to claim 1, wherein: The cathode layer includes a plurality of groups of cathode blocks, and each group of cathode blocks is an integral structure.

3. The display panel according to claim 2, wherein: Each group of cathode blocks includes two cathode blocks.

4. The display panel according to any one of claims 1 to 3, characterized in that: The cathode layer further includes a voltage signal line, and the voltage signal line is connected to the cathode block.

5. The display panel according to any one of claims 1 to 3, characterized in that: The array substrate has a voltage signal line, and the light-emitting layer further has a switching portion, and the switching portion is respectively connected to the voltage signal line and the cathode block.

6. The display panel according to claim 5, characterized in that: The array substrate comprises a single source-drain metal layer, and the source-drain metal layer has the voltage signal line.

7. The display panel according to claim 6, wherein: The array substrate comprises a plurality of source-drain metal layers, and at least one of the source-drain metal layers has the voltage signal line.

8. The display panel according to claim 7, wherein: At least two of the multiple source-drain metal layers have the voltage signal line, and the voltage signal lines of at least two of the source-drain metal layers extend in different directions.

9. The display panel according to any one of claims 6 to 8, characterized in that: The source-drain metal layer is a composite structure layer.

10. The display panel according to claim 9, wherein: The source-drain metal layer includes a titanium metal layer, an aluminum metal layer, and a titanium metal layer stacked in sequence.

11. The display panel according to claim 5, characterized in that: The adapter part includes an anode adapter block and a light-emitting adapter block. The anode adapter block is in the same layer as the anode block and is distributed at intervals. The light-emitting adapter block is in the same layer as the light-emitting functional layer, and the light-emitting adapter block includes at least one of a hole injection layer, a hole transport layer, an electron blocking layer, a hole blocking layer, an electron transport layer and an electron injection layer.

12. The display panel according to claim 11, wherein: The light-emitting adapter block and the light-emitting functional layer are spaced apart from each other.

13. The display panel according to claim 12, wherein: The light-emitting layer further includes a partition portion, which is in the same layer as the light-emitting adapter block and is located between the light-emitting functional layer and the light-emitting adapter block.

14. A method for manufacturing a display panel, characterized in that: The method comprises: manufacturing an array substrate; A light-emitting layer is manufactured on one side of the array substrate, wherein the light-emitting layer has a plurality of light-emitting units, wherein the light-emitting units include an anode block, a light-emitting functional layer and a cathode block stacked in sequence in a direction away from the array substrate, wherein the light-emitting layer includes a cathode layer, wherein the cathode layer includes a plurality of cathode blocks, and the plurality of cathode blocks are distributed at intervals.

15. The method according to claim 14, characterized in that The cathode layer further includes a voltage signal line, and the voltage signal line is connected to the cathode block.

16. The method according to claim 14, characterized in that Manufacturing an array substrate, including: manufacturing an array substrate with voltage signal lines; The light emitting layer is manufactured on one side of the array substrate, comprising: manufacturing the light emitting layer having a transition portion on one side of the array substrate, wherein the transition portion is respectively connected to the voltage signal line and the cathode block.

17. A display device, characterized in that: A display panel comprising any one of claims 1 to 13.

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