Processing circuit and method for performing data conversion

Abstract

The invention refers to a processing circuit (10) for performing a data conversion and a corresponding method for performing a data conversion. The processing circuit (10) comprises a first signal path (20) and a second signal path (30). Both signal paths (10, 30) comprise a converter circuit using a sampling frequency according to a first oscillator signal (11). The processing circuit (10) further comprises a compensation unit (40), wherein the compensation unit (40) is configured to compensate a phase error and / or a timing error in a converted data input signal (22) of the first signal path (20) based on an error signal (32) that is generated by the second signal path (30).

Description

PROCESSING CIRCUIT AND METHOD FOR PERFORMING DATA CONVERSIONTECHNICAL FIELD

[0001] The invention refers to a processing circuit and method for performing a data conversion.

[0002] Processing circuits and methods for performing a data conversion, wherein a data conversion is an analog-to-digital conversion or a digital-to-analog conversion, are known in the art.BACKGROUND

[0003] Current CMOS technology allows integration of high-performance data converters running at multi giga-samples per second. In wireless communication systems this allows processing of RF (radio frequency) and IF (intermediate frequency) signals in the digital domain. Thus, it is possible to limit the impact from analog mixer impediments, like IQ- imbalance in single sideband, SSB, mixers etc.

[0004] One additional factor to consider in a digital RF / IF system is the impact of uncertainty between sampling intervals that can be traced back to the phase noise characteristics of the oscillator driving the sampling process.

[0005] The cycle-to-cycle jitter Jcyc of the sampling clock is basically

[0006] for the k:th sample, where (|)(k) is the absolute phase uncertainty of the sample clock, wherein Tsis a time between subsequent samples. Thus, the total timing error at the k:th sample is the accumulated cycle-to-cycle jitter up to that sample:

[0007] Assuming c|)(0) normalized to 0 deg. This means that the timing error Terr(k) of the samples are directly correlated to the phase noise of the sampling clock.

[0008] If a single tone with the angular frequency ocis sampled the result is s(t) = sin(mct)

[0009] Therefore, the phase noise of the single tone is identical to the phase noise of the sampling clock scaled by the ratio of the respective frequencies.

[0010] If the sampled signal is a coherently modulated SSB IF signal with the angular frequency o IF and the absolute phase uncertainty (|)iF(k), assuming I+jQ being the representation of the information carrying signal, the impact of the sampling uncertainty becomes:

[0011] After digital down conversion to base band, the sampling uncertainty can be described as follows:

[0012] What is observed in base band, because of the sampling uncertainty, is the information carrying signal distorted partly by a timing error, and partly by a phase error. Both these errors emerge from the phase noise characteristics of the oscillator acting as a source for the sampling clock.

[0013] What is described above relates to the conversion of an analog signal to its digital representation (ADC). Analyzing digital to analog conversion (DAC) leads to similar results, with the exceptions of sign conventions for the timing error.

[0014] The IEEE publication “sampling clock jitter estimation and compensation in ADC circuits” by Zaid J. Towfic, Shang-Kee Ting, and Ali H. Sayed, as published in the proceedings of 2010 IEEE International Symposium on Circuits and Systems, discloses a technique in which a low frequency oscillator signal and a high frequency oscillator signal are injected as training signals to a signal that is received by a superheterodyne receiver. The injected signals are analyzed for jitter determination and compensation. A circuit 100 according to this publication is depicted in Figure 5. It is shown that low frequency oscillator signal w(t) and a high frequency oscillator signal y(t) are added to an input signal r(t) on an input side 101. A single ADC is used for analog-to-digital conversion and the signals that have been modulated onto the input signal r(t) are used for jitter estimation 102 and jitter compensation 102.

[0015] The IEEE publication “Sampling Jitter Cancellation in Direct- Sampling Radio” by Ville Syrjala and Mikko Valkama, as published at 2010 IEEE Wireless Communication and Networking Conference, discloses a technique of super-imposing a reference tone at sampler input, which is then used for digital jitter estimation and cancellation from the actual received signal in a direct-sampling radio.

[0016] The IEEE publication “Clock Jitter Compensation in High-Rate ADC Circuits” by Zaid J. Towfic, Shang-Kee Ting, and Ali H. Sayed, as published in IEEE Transactions on Signal Processing, Volume: 60, Issue: 11, November 2012, discloses a low-complexity digital signal processing methods for estimating the jitter in real-time for direct down conversion receivers at high sampling rates and compensation methods for the jitter.

[0017] The undesired effects of the cycle-to-cycle jitter of the sampling clock might be reduced by using more precise oscillator signals for generating the sampling clock. However, implementing high performance data converters in CMOS is very cost efficient. At the same time, a big challenge is to design high performance oscillators for the sampling clock in that semiconductor technology. This can lead to power hungry implementations or designs requiring complicated clock distribution solutions, driving cost and complexity.SUMMARY

[0018] A processing circuit for performing a data conversion from an analogue to digital or digital to analogue signal according to the invention comprises a first signal path, a second signal path and a compensation unit. The first signal path comprises an input side that is configured to receive a data input signal and an output side that is configured to provide a converted data input signal, and the first signal path comprises a first converter circuit that is configured to perform a first data conversion on the data input signal using a sampling frequency according to a first oscillator signal for generating the converted data input signal. The second signal path comprises a second converter circuit that is configured to perform a second data conversion using the sampling frequency according to the first oscillator signal to generate an error signal that is indicating a phase error and / or a timing error that results from using the sampling frequency according to the first oscillator signal by the second converter circuit. The compensation unit is configured to compensate a phase error and / or a timing error in the converted data input signal based on the error signal.

[0019] A method for performing a data conversion from an analogue to digital or digital to analogue signal according to the invention comprises receiving a data input signal on aninput side of a first signal path, performing a first data conversion on the data input signal by a first converter circuit using a sampling frequency according to a first oscillator signal for generating a converted data input signal, providing the converted data input signal on an output side of the first signal path, performing a second data conversion by a second converter circuit of a second signal path using the sampling frequency according to the first oscillator signal to generate an error signal that is indicating a phase error and / or a timing error that results from using the sampling frequency according to the first oscillator signal is caused by the second converter circuit and compensating a phase error and / or a timing error in the converted data input signal by a compensation unit based on the error signal.

[0020] The first signal path and the second signal path are both entities of one or more electronic components, wherein each signal path is capable to perform a signal processing on a signal that is provided to an input side at the beginning of the respective signal path and to provide the processed signal on an output of the respective signal path.

[0021] Preferably, different input signals are provided to the first signal path and the second signal path. The first signal path is preferably configured to perform an analog-to-digital conversion for a radio frequency signal or an intermediate frequency signal in a radio transmitter or in a radio receiver. The second signal path is preferably not configured to receive the radio frequency signal or the intermediate frequency signal that is converted by the first signal path but is configured to independently generate the error signal that is representative for jitter that is induced to the first signal path by the first oscillator signal, wherein the information in respect to the jitter is derived by analyzing the first oscillator signal using a reference signal, in particular a reference oscillator signal. That is, an impact of jitter in first converter circuit is determined based on a jitter that is determined based on the second converter circuit. Preferably the reference signal has a significant lower phase noise compared to the first oscillator signal, therefore the error signal can be used for correcting the jitter caused by the phase noise of the first oscillator.

[0022] The first signal path comprises an input side that is configured to receive a data input signal and an output side that is configured to provide a converted data input signal. Preferably, the data input signal is the radio frequency signal or the intermediate frequency signal. The converted data input signal is based on the data input signal, wherein the data input signal has changed it characteristic from analog to digital or from digital to analog.

[0023] The first signal path comprises the first converter circuit that is configured to perform the first data conversion on the data input signal using a first oscillator signal. The first converter circuit is preferably an analog-to-digital converter or a digital -to-analog converter.The first oscillator signal is used to set a sampling frequency of the first converter circuit. In particular, the first oscillator signal is used for defining a sampling clock of the first converter circuit. The first data conversion on the data input signal is performed for generating the converted data input signal. Optionally, this includes that further signal processing is applied to the data input signal in the process of generating the converted data input signal. That is, the converted data input signal is not necessarily the direct output signal of the first converter circuit.

[0024] The reference signal is a signal with known characteristics that allows to determine a phase error and / or a timing error that is caused by the second converter circuit when using the sampling frequency according to the first oscillator signal. For example, the reference signal is generated by a reference oscillator with a high quality, which is causing a lower phase error and / or timing error than the first oscillator.

[0025] The second signal path is parallel to the first signal path, wherein the second signal path is not receiving the data input signal on its input side. The second signal path comprises the second converter circuit that is configured to perform the second data conversion using the first oscillator signal. The first oscillator signal is used to set a sampling frequency of the second converter circuit. In particular the first oscillator signal is used for defining a sampling clock of the second converter circuit.

[0026] The second signal path is configured to generate an error signal, that is indicating a phase error and / or a timing error that is caused by the second converter circuit, in particular by using the first oscillator signal for setting the sampling frequency. By performing the second data conversion using the same oscillator signal for setting the sampling frequency, the same effects of jitter that occur in the first signal path due to the first oscillator signal are replicated in the second signal path. Thus, it is not necessary to analyze the signals in the first signal path to determine the effects of jitter, which can be difficult as it is necessary to differentiate between the data input signal and characteristics in the signal that are caused by jitter. The reference signal is preferably a signal that has a lower phase error and / or timing error than the first oscillator signal. The first and second converter circuits preferably are implemented on the same chip or at least in the same technology.

[0027] The compensation unit is configured to compensate, that is to correct, a phase error and / or a timing error in the converted data input signal based on the error signal. In particular, the phase error and / or timing error that has been determined to be caused by the sampling of the second converter circuit is used to compensate the phase error and / or the timing error that is caused by the sampling of the first converter circuit. In case a phase error is determined basedon the second converter circuit in the first signal path, a phase error that is caused by sampling of the first converter circuit is compensated. In case a timing error is determined based on the second converter circuit in the first signal path, a timing error that is caused by sampling of the first converter circuit is compensated.

[0028] The use of the reference signal can compensate for data converter timing impediments. The reference signal is provided by a separate converter. Similar schemes can be used for analog-to-digital conversion and for digital -to-analog conversion. In the case of analog-to-digital conversion the solution can preferably compensate for both timing and phase errors. For digital-to-analog conversion, the possibility of handling phase errors is preferable. The processing circuit has a general applicability on data conversion, but its advantages are analyzed in the context of wireless radio communication in the following, for example when an IF frequency is generated and processed in the digital domain.

[0029] By the processing circuit and the method according to the invention, it is possible to compensate for phase / timing impairments of a sampling clock. This makes it possible to relax the sampling clock requirements for high performance applications. This is especially important in the case of highly integrated CMOS data converters. It is possible to make use of already existing high performance clock signals used for up and down conversion in the radio line up, thus simplifying the system solution. A compensation of timing errors and phase noise errors is possible to be performed separately. Thus, the design of interpolators is simplified.

[0030] A wireless communication systems comprising the processing circuit according to the invention is suitable to achieve all advantages of the processing circuit.

[0031] The dependent claims define advantageous embodiments of the invention.

[0032] Preferably, the second signal path is configured to receive a reference oscillator signal, wherein the reference oscillator signal is used as the reference signal. That is, the reference oscillator signal is preferably sampled by using the sampling frequency that is set according to a first oscillator signal. The reference oscillator signal is preferably a signal that has a lower phase error and / or timing error than the first oscillator signal. Thus, any change in the output signal of the second converter circuit can be asserted to be caused by jitter effects that are induced to the second converter circuit due to the first oscillator signal, creating a signal that is indicating the effects of jitter that are to be corrected or compensated.

[0033] Preferably, the reference oscillator is generating a digital oscillator signal if the processing circuit for performing the data conversion is performing a conversion from a digital to an analog signal and the reference oscillator is generating an analog oscillator signal if the processing circuit for performing the data conversion is performing a conversion from ananalog to a digital to signal. The reference oscillator signal preferably has the same frequency as the data input signal. Preferably, the reference oscillator that is generating the reference oscillator signal is the same oscillator that is used for modulating the data input signal. The data input signal is preferably an analog signal in this case.

[0034] The reference oscillator is preferably a free running oscillator or an already existing oscillator in a receiver or transmitter line up. The reference oscillator signal is preferably a signal that has a lower phase error and / or timing error than the first oscillator signal. The reference oscillator signal is not necessarily a part of the processing circuit for performing a data conversion but can be an external oscillator that is providing the reference oscillator signal to the processing circuit. However, the reference oscillator can also be a component of the processing circuit for performing the data conversion. Optionally, the reference oscillator signal has a different frequency than the first oscillator signal, wherein the different frequency is caused by the higher phase error and / or timing error of the first oscillator signal.

[0035] Preferably, the processing circuit further comprising a reference oscillator that is configured to generate the reference oscillator signal such that a phase error and / or a timing error of the reference oscillator signal is smaller than a phase error and / or a timing error of the first oscillator signal. That is, the reference oscillator is a component of the processing circuit, wherein it is preferable that the processing circuit is providing an output for the reference oscillator signal so that the reference oscillator signal can be used in parallel by any circuits that are connected to the processing circuit.

[0036] Preferably, one or more components of the processing circuit are comprised by an integrated circuit.

[0037] In particular, the processing circuit further comprises a first oscillator that is configured to generate the first oscillator signal, wherein the first oscillator is comprised by the integrated circuit. The first oscillator is preferably part of an integrated circuit, which allows a compact and energy efficient implementation. This might lead to a less precise first oscillator signal, which might result in an increase of jitter effects that are induced to the converted data input signal. However, as a phase error and / or a timing error are compensated in the converted data input signal, a signal quality can be maintained high.

[0038] Preferably, the first converter circuit and the second converter circuit are comprised by the integrated circuit. As the converter circuits are parts of the same integrated circuit, a similar behavior of the first converter circuit and the second converter circuit can be achieved, which leads to the outcome that the phase error and / or the timing error that is caused by the second converter circuit is more similar to the phase error and / or the timing error that is causedby the first converter circuit, consequently leading to an improved compensation of the phase error and / or the timing error in the converted data input signal based on the error signal.

[0039] Preferably, the first converter circuit and the second converter circuit are identically constructed. Therefore, a similar behavior of the first converter circuit and the second converter circuit can be achieved, which leads to the outcome that the phase error and / or the timing error that is caused by the second converter circuit is more similar to the phase error and / or the timing error that is caused by the first converter circuit, consequently leading to an improved compensation of the phase error and / or the timing error in the converted data input signal based on the error signal.

[0040] Preferably, the first converter circuit and the second converter circuit are analog- to-digital converters, wherein the reference signal is an analog signal, wherein the first signal path is configured to receive an analog signal as the data input signal and to provide a digital signal as the converted data input signal, and wherein the second signal path is configured to sample the reference signal by using the second converter circuit to generate a sampled reference signal and to generate the error signal based on the sampled reference signal. Thus, the processing circuit for performing a data conversion is suitable to perform an analog-to- digital conversion. The error signal is generated based on the sampled reference signal, wherein the error signal is optionally equal to the sampled reference signal. In the alternative, an additional signal processing is applied to the sampled reference signal to obtain the error signal. In any case, the error signal comprises the information on what phase error and / or timing error is induced by the second converter circuit.

[0041] Preferably, the second signal path comprises a phase locked loop and the second converter circuit is coupled to an input of the phase locked loop such that the sampled reference signal is provided to the input of the phase locked loop, wherein the error signal is an output signal of the phase locked loop that is indicative for a phase deviation that is detected by the phase locked loop. A phase locked loop is an entity that can be either a digital unit or a physical circuit. Phase locked loops are typically designed to provide an error signal at the output of a comparator, wherein this error signal of the phase locked loop can also be used as the error signal that is provided to the compensation unit for compensating the phase error and / or a timing error in the converted data input signal based on the error signal.

[0042] Preferably, the compensation circuit comprises a conjugate generating unit that is configured to generate a complex conjugate based on the error signal to generate a conjugated error signal, wherein the compensation unit comprises a multiplying unit that is configured to multiply two signals to compensate the timing error in the converted data input signal, whereinone of the signals is derived from the output side of the first signal path and the other signal is derived from the conjugated error signal. Thus, a simple signal processing is provided that allows a compensation of a timing error in the converted data input signal.

[0043] Preferably, the compensation circuit comprises a scaling unit that is configured to generate a scalar value based on the error signal, wherein the compensation circuit comprises an interpolation filter unit that is configured to apply interpolation filtering to a signal that is derived from the output side of the first signal path, wherein the interpolation filter unit is configured to receive the scalar value and to set filter parameters for the interpolation filtering according to the scalar value to compensate the timing error in the converted data input signal. Thus, a simple signal processing is provided that allows a compensation of a phase error in the converted data input signal.

[0044] Preferably, an output signal of the first digital converter is digitally down converted and passed through a pulse shaping filter in the first signal path. Preferably, the error signal is run through a matching pulse shaping filter for alignment with the data input signal.

[0045] Preferably, the first converter circuit and the second converter circuit are digital - to-analog converters, wherein the reference signal is a digital signal, wherein the first signal path is configured to receive a digital signal as the data input signal and to provide an analog signal as the converted data input signal, wherein the second signal path is configured to sample the reference signal by using the second converter circuit to generate a sampled reference signal and to generate the error signal based on the sampled reference signal. Thus, the processing circuit for performing a data conversion is suitable to perform a digital-to-analog conversion. The error signal is generated based on a reference signal, wherein the reference signal is preferably a single digital tone of a certain frequency, wherein the certain frequency is preferably a center frequency of the data input signal. The error signal is optionally equal to the sampled reference signal. In the alternative, an additional signal processing is applied to the sampled reference signal to obtain the error signal. In any case, the error signal comprises the information on what phase error is caused by the second converter circuit.

[0046] Preferably, the second signal path comprises a first mixer, wherein the first mixer is configured to receive a reference oscillator signal and the sampled reference signal as input and to output the error signal, wherein the compensation circuit comprises a first bandpass filter that is configured to generate a compensation signal based on the error signal, wherein the compensation unit comprises a second mixer that is configured to mix two signals to compensate the phase error in the converted data input signal, wherein one of the signals is derived from the output side of the first signal path and the other signal is derived from thecompensation signal. The reference oscillator signal is preferably a signal that has a lower phase error and / or timing error than the first oscillator signal. The reference oscillator signal preferably has the same frequency as the data input signal.

[0047] Preferably, the converted data input signal is upconverted to a radio frequency after compensation by the compensation unit. Preferably, the converted data input signal is filtered by a image rejection filter after compensation by the compensation unit and before up- conversion to radio frequency.BRIEF DESCRIPTION OF THE DRAWINGS

[0048] Exemplary embodiments of the invention are described below with reference to the drawings. The figures in the drawings show in:

[0049] Figure 1 a circuit diagram of a processing circuit according to the invention according to a first embodiment of the invention,

[0050] Figure 2 a circuit diagram of a processing circuit according to the invention according to a second embodiment of the invention,

[0051] Figure 3 a circuit diagram of a processing circuit according to the invention according to a third embodiment of the invention,

[0052] Figures 4a to 4c a representation of simulation results that are indicating a possible efficiency of a compensation of a phase error and a timing error according to the invention, and

[0053] Figure 5 a circuit diagram of a processing circuit according to the prior art.DETAILED DESCRIPTION

[0054] Some of the embodiments contemplated herein will now be described more fully with reference to the accompanying drawings. Embodiments are provided by way of example to convey the scope of the subject matter to those skilled in the art.

[0055] Figure 1 shows a circuit diagram of a processing circuit 10 according to a first embodiment of the invention. With this, figure 1 shows a compensation of phase noise dominated jitter impairments when a reference signal is fed through a separate ADC. In this case there is no degradation of the user signal due to impact from the reference signal.

[0056] The processing circuit 10 is for performing a data conversion and comprises a first signal path 20, a second signal path 30 and a compensation unit 40. Each one of the first signal path 20, the second signal path 30 and the compensation unit 40 is a circuit for signal processing. The processing circuit 10 is suitable to perform a conversion of an analog signal to its digital representation.

[0057] The first signal path 20 comprises an input side that is configured to receive a data input signal 21 and an output side that is configured to provide a converted data input signal 22. The first signal path 20 comprises a first converter circuit 23 that is configured to perform a first data conversion on the data input signal 21 using a sampling frequency according to a first oscillator signal 11 for generating the converted data input signal.

[0058] The first converter circuit is an analog-to-digital converter. The data input signal 21 is a SSB IF signal with a center frequency of fiF. The data input signal 21 is sampled by the first converter circuit 23, which is an ADC, wherein the data input signal is converted to its digital representation. The sampling is done using the sampling frequency according to the first oscillator signal 11. The first oscillator signal 11 is provided by a first oscillator 13.

[0059] The sampled data input signal 21 that is generated by the first converter circuit 23 is digitally down converted by a down-conversion mixer 24 and passed through the pulse shaping filter 25. Due to the phase noise characteristics of the first oscillator 13, the resulting base band representation, that is the converted data input signal 22, is affected by timing and phase errors. The characteristics of the converted data input signal 22 can be described as follows:

[0060] The second signal path 30 comprises a second converter circuit 31, which is an ADC, that is configured to perform a second data conversion on a reference signal 33 using the sampling frequency according to the first oscillator signal 11 to generate an error signal 32 that is indicating a phase error and / or a timing error that is caused by the second converter circuit 31.

[0061] The first converter circuit 23 and the second converter circuit 31 are identically constructed. Also, the first converter circuit 23 and the second converter circuit 31 are parts of the same integrated circuit. That is, the first converter circuit 23 and the second converter circuit 31 are preferably both areas on the same semiconductor chip. Preferably, also the first oscillator 13 is comprised by the integrated circuit and is an area on the same semiconductor chip as the first converter circuit 23 and the second converter circuit 31.

[0062] The reference signal 33 is a reference oscillator signal that is provided by a reference oscillator 12. The reference oscillator 12 is generating a single tone signal at the IF signal center frequency fiF. The reference oscillator is either a free running oscillator or an already existing oscillator in a receiver line up. The reference oscillator 12 is configured to generate the reference oscillator signal such that a phase error and / or a timing error of the reference oscillator signal is smaller than a phase error and / or a timing error of the first oscillator signal 11. That is, the reference oscillator signal has much better phase noise characteristics than the sampling clock generator that is provided by the first oscillator 13 with reference to fiF. The reference signal 33 is sampled by the second converter circuit 31 and will thus be degraded the same way as the IF signal that is provided to the first converter circuit 23since both ADCs are running from the same sampling clock generator, that is the first oscillator 13.

[0063] Optionally, the second signal path 30 comprises a phase locked loop 34 and an output of the second converter circuit 31 is coupled to an input of the phase locked loop 34 such that the sampled reference signal 33 is provided to the input of the phase locked loop 34. In the digital domain, the phase locked loop 34, PLL, locks to the sampled and impaired reference signal. An error signal 32 from the PLL circuit will then be a representation of the momentary angular error at the frequency of the reference signal, which is provided to the compensation unit 40. Therefore, the error signal 32 is an output signal of the phase locked loop 35 that is indicative for a phase deviation that is detected by the phase locked loop 34.

[0064] The compensation unit 40 is configured to compensate a phase error and / or a timing error in the converted data input signal 22 based on the error signal 32. That is, the error signal that comprises information about the phase error and / or the timing error that is induced by the second converter circuit 31 is used to compensate the phase error and / or the timing error that is induced by the first converter circuit 31. This compensation is based on the assumption that a similar phase error and / or the timing error is caused by the first converter circuit 23 and the second converter circuit 31, as sampling is driven by the same first oscillator signal 11 for both of these converters. Therefore, the compensation unit 40 is preferable configured to generate a compensation signal that is compensating the phase error and / or the timing error that is caused to the reference signal by the second converter circuit 31 when combined with the converted data input signal 22.

[0065] In the first embodiment, the compensation circuit 40 comprises a matching pulse shaping filter 45 and the error signal is run through the matching pulse shaping filter 45 for alignment with the received base band signal.

[0066] The compensation circuit 40 further comprises a conjugate generating unit 41 that is configured to generate a complex conjugate based on the error signal 32 that has been filtered by the matching pulse shaping filter 45 to generate a conjugated error signal, which is then used as the compensation signal.

[0067] The compensation unit 40 comprises a multiplying unit 42 that is configured to multiply two signals to compensate the timing error in the converted data input signal 22, wherein one of the signals is derived from the output side of the first signal path 20 and the other signal is derived from the conjugated error signal. This means that the complex conjugate that is defined by the conjugated error signal is multiplied with the impaired (base band) signal, that is the converted data input signal 22, which leads to the effect that the phase noise causedby sampling imperfections can be cancelled out, as can be understood from the following mathematical presentation of the signal processing that is achieved by the multiplying unit 42:

[0068] Thus, the compensation unit is suitable to compensate a phase error.

[0069] Figure 2 shows a circuit diagram of a processing circuit according to the invention according to a first embodiment of the invention.

[0070] The processing circuit 10 according to the second embodiment is essentially identical to the processing circuit 10 according to the first embodiment, wherein the compensation unit 40 according to the second embodiment is further suitable to compensate a timing error. For this, the compensation circuit 40 further comprises a scaling unit 43 that is configured to generate a scalar value based on the error signal 32. The scaling unit 43 receives the error signal 32 that has been filtered by the matching pulse shaping filter 45 and is generating a filter parameter that is used for setting a filter parameter of an interpolation filter unit 44 that is serially connected with the multiplying unit 42 and is configured to apply interpolation filtering to a signal that is provided from the output side of the first signal path 20. That is, the converted data input signal 22 is provided to the interpolation filter unit 44 through the multiplying unit 42. The interpolation filter unit 44 is configured to receive the scalar value and to set filter parameters for the interpolation filtering according to the scalar value to compensate the timing error in the converted data input signal 22. Since the phase error and the timing error in the base band signal both emerges from the phase noise characteristics of the sampling clock, the error signal derived from the reference signal can be scaled to a timing error, which is done by the scaling unit 43. That timing error can be used to control the interpolation filter unit 44 to adjust the sampling position. This is preferably used in combination with a wideband information carrying signal that is provided as data input signal. Also, this allows to further relax the phase noise requirement on the sampling clock, which is the first oscillator 13. In case of a wide band signal that is not an IF-signal, the phase compensation can be entirely removed, and corrections made only by the interpolating filter.

[0071] Referring to the processing circuit 10 according to the first embodiment and the processing circuit 10 according to the second embodiment, it is pointed out that also a processing circuit 10 is advantageous that is able to compensate only a timing error. The compensation unit 40 of such a processing circuit 10 preferably comprises the elementsaccording to the second embodiment without comprising the multiplying unit 42 and the conjugate generating unit 41.

[0072] Figure 3 shows a circuit diagram of a processing circuit 50 according to a third embodiment of the invention. This shows one possible embodiment of a circuit compensating for phase noise due to data converter timing errors during digital to analog conversion.

[0073] The processing circuit 50 is for performing a data conversion and comprises a first signal path 60, a second signal path 70 and a compensation unit 80. Each one of the first signal path 60, the second signal path 70 and the compensation unit 80 is a circuit for signal processing. The processing circuit 50 is suitable to perform a conversion of a digital signal to its analog representation.

[0074] The first signal path 60 comprises an input side that is configured to receive a data input signal 61 and an output side that is configured to provide a converted data input signal 62. The first signal path 60 comprises a first converter circuit 63 that is configured to perform a first data conversion on the data input signal 61 using a sampling frequency according to a first oscillator signal 51 for generating the converted data input signal 62.

[0075] The data input signal 61 is a digital SSB IF signal with a center frequency of fiF. It is sampled by the first converter circuit 63, which is a DAC, and converted to its analog representation. The sampling is done using the sampling frequency according to the first oscillator signal 51. The first oscillator signal 51 is provided by a first oscillator 53.

[0076] The second signal path 70 comprises a second converter circuit 71, which is a DAC, that is configured to perform a second data conversion on a reference signal 73 using the sampling frequency according to the first oscillator signal 51 to generate an error signal 72 that is indicating a phase error and / or a timing error that is caused by the second converter circuit 71. Thus, both of the first converter circuit 63 and the second converter circuit 71 are fetching their sampling clock from an oscillator, that is the first oscillator 53, that is limited by phase noise.

[0077] The first converter circuit 63 and the second converter circuit 71 are identically constructed. Also, the first converter circuit 63 and the second converter circuit 71 are parts of the same integrated circuit. That is, the first converter circuit 63 and the second converter circuit 71 are preferably both areas on the same semiconductor chip. Preferably, also the first oscillator 53 is comprised by the integrated circuit and is an area on the same semiconductor chip as the first converter circuit 63 and the second converter circuit 71.

[0078] The reference signal 73 is generated by a reference signal generator 54, wherein the reference signal (73) is a digital signal, in particular a single digital tone of frequency fiF.The reference signal generator 54 is a reference oscillator and the reference signal 73 is a reference oscillator signal.

[0079] The second signal path 70 is configured to sample the reference signal 73 by using the second converter circuit 71 to generate a sampled reference signal. That is, the single digital tone of frequency fiF is converted to its analog representation by the second converter circuit 71.

[0080] Therefore, a SSB output from the first converter circuit 63 can be written as:err (O ^IF^'err^J')'

[0081] Accordingly, the sampled reference signal, which is a correction signal output from the second converter circuit 71, can be written as:

[0082] The second signal path 70 comprises a first mixer 74, wherein the first mixer 74 is configured to receive a second oscillator signal and the sampled reference signal as input and to output the error signal 72.

[0083] The second oscillator signal is provided by a second oscillator 52. The second oscillator 52 is generating a single tone signal at a frequency fim. The reference oscillator 52 is either a free running oscillator or an already existing oscillator in a receiver line up. The second oscillator 52 is configured to generate the second oscillator signal such that a phase error and / or a timing error of the second oscillator signal is smaller than a phase error and / or a timing error of the first oscillator signal 51. In other words, the second oscillator 52 has much better phase noise characteristics than the sampling clock of the first converter circuit 63 and the second converter circuit 71 and is running at frequency fim.

[0084] The sampled reference signal from the second converter circuit 71 is multiplied with the clock according to the reference oscillator signal in the first mixer 74 to generate the error signal 72 that is indicating a phase error and / or a timing error that is caused by the second converter circuit 71. It is noted that also the output signal of the second converter circuit 71 might be understood as the error signal, as also this signal is that is also indicating the phase error and / or the timing error that is caused by the second converter circuit 71. Accordingly, the first mixer 74 is optionally a component of the compensation unit 80.

[0085] In this embodiment, the converted data input signal 62 and the output signal of the first mixer 74 are both input signals of the compensation unit 80. The compensation unit 80 comprises a second mixer 82 and a first bandpass filter 81. The first bandpass filter 81 isconfigured to generate a compensation signal based on the error signal 72, wherein the first bandpass filter 81 acts as an image rejection filter. The error signal 72 is passed through this first bandpass filter 81 that is acting as the image rejection filter, resulting in a local oscillator input to the second mixer 82, which is referred to as the compensation signal.

[0086] The second mixer 82 is configured to mix two signals to compensate the phase error in the converted data input signal 62, wherein one of the signals is derived from the output side of the first signal path 50 and the other signal is derived from the compensation signal. In this embodiment, the converted data input signal 62 and the compensation signal are mixed by the second mixer 82.

[0087] The converted data input signal 62 is therefore provided to the second mixer 82 of the compensation unit 80 and is upconverted by the first mixer 82 to a high IF frequency, fim, and is then passed through an image rejection filter 55 and finally upconverted to a radio frequency RF by an upconversion mixer 56. The desired high IF frequency provided by the second oscillator 52 and the compensation of the phase error in the converted data input signal 62 is achieved during the upconversion of the the converted data input signal 62 to the high IF frequency.

[0088] The compensation signal can be described as follows:

[0089] When this signal is multiplied by the SSB signal, that is the converted data input signal 62, in the second mixer 82 and passed through the image rejection filter 55 it results in a phase noise corrected SSB signal at the higher IF frequency, which has been referred to as frequency fim:5SSB (0 = l(t - Terr(t)) • cos(m / Fftt) — Q(t - Terr(t)) • sin(mZFftt)

[0090] This higher IF frequency can then be upconverted to the radio frequency by the upconversion mixer 56.

[0091] Figures 4a to 4c are depicting diagrams that show a representation of simulation results that are indicating a possible efficiency of a compensation of a phase error and a timing error according to the invention. In the diagrams, the X-Axis is representing an In-phase amplitude and the Y-Axis is representing a Quadrature amplitude. For all diagrams, a 100 MHz 64 QAM signal at an intermediate frequency, IF, of 1.8 GHz has been provided as a data input signal to a processing circuit for performing a data conversion. That is, Figures 4a to 4c show a signal processing that is applied to the same input data signal.

[0092] Figure 4a is showing the converted data input signal in a scenario in which no phase error and / or timing error would be caused by due to jitter by the first converter circuit 23 and the converted data input signal is only degraded by additive white gaussian noise, AWGN.

[0093] Figure 4b and no correction is made by use of the second signal path 30; 70 and the compensation circuit 40; 80. Figure 4b

[0094] Figure 4b is showing the converted data input signal in a scenario in which a phase error and a timing error is caused by due to jitter by the first converter circuit 23. However, no compensation of the phase error and the timing error according to the invention is performed by the second signal path 30 and the compensation unit 40. Thus, a significant distortion of the constellation points can be observed, which is mainly caused by jitter that is induced by the first converter circuit 23.

[0095] Figure 4c is showing the converted data input signal in a scenario in which the phase error is compensated according to the invention. As no compensation of the timing error is performed, there is still some degradation. That’s due to that only compensation for phase noise is applied. I.e. are is still timing errors remaining in the narrow band signal. This can be improved by applying the compensation for the timing error.

Claims

CLAIMS1. A processing circuit (10; 50) for performing a data conversion from an analogue to digital or digital to analogue signal, comprising: a first signal path (20; 60), wherein: the first signal path (20; 60) comprises an input side that is configured to receive a data input signal (21; 61) and an output side that is configured to provide a converted data input signal (22; 62), and the first signal path (20; 60) comprises a first converter circuit (23; 63) that is configured to perform a first data conversion on the data input signal (21; 61) using a sampling frequency according to a first oscillator signal (11; 51) for generating the converted data input signal (22; 62); a second signal path (30; 70), wherein: the second signal path (30; 70) comprises a second converter circuit (31; 71) that is configured to perform a second data conversion on a reference signal (33; 73) using the sampling frequency according to the first oscillator signal (11; 51) to generate an error signal (32; 72) that is indicating a phase error and / or a timing error that results from using the sampling frequency according to the first oscillator signal (11; 51) by the second converter circuit (31; 71); and a compensation unit (40; 80), wherein the compensation unit (40) is configured to compensate a phase error and / or a timing error in the converted data input signal (22) based on the error signal (32).

2. The processing circuit (10; 50) according to claim 1, wherein the second signal path (30; 70) is configured to receive a reference oscillator signal, wherein the reference oscillator signal is used as the reference signal (33).

3. The processing circuit (10; 50) according to claim 2, further comprising a reference oscillator (12; 52) that is configured to generate the reference oscillator signal such that a phase error and / or a timing error of the reference oscillator signal is smaller than a phase error and / or a timing error of the first oscillator signal (11; 51).

4. The processing circuit (10; 50) according to any one of the preceding claims, whereinone or more components of the processing circuit (10; 50) are comprised by an integrated circuit.

5. The processing circuit (10; 50) according to claim 4, further comprising a first oscillator (13; 53) that is configured to generate the first oscillator signal (11; 51), wherein the first oscillator (13; 53) is comprised by the integrated circuit.

6. The processing circuit (10; 50) according to any one of claims 4 and 5, wherein the first converter circuit (23; 63) and the second converter circuit (31; 51) are comprised by the integrated circuit.

7. The processing circuit (10; 50) according to any one of the preceding claims, wherein the first converter circuit (23; 63) and the second converter circuit (31; 51) are identically constructed.

8. The processing circuit (10) according to any one of the preceding claims, wherein the first converter circuit (23) and the second converter circuit (31) are analog-to- digital converters, wherein the reference signal (33) is an analog signal, wherein the first signal path (20) is configured to receive an analog signal as the data input signal (21) and to provide a digital signal as the converted data input signal (22), wherein the second signal path (30) is configured to sample the reference signal by using the second converter circuit (31) to generate a sampled reference signal and to generate the error signal based on the sampled reference signal.

9. The processing circuit (10) according to claim 8, wherein the second signal path (30) comprises a phase locked loop (34) and the second converter circuit (31) is coupled to an input of the phase locked loop (34) such that the sampled reference signal (33) is provided to the input of the phase locked loop (34), wherein the error signal (32) is an output signal of the phase locked loop (34) that is indicative for a phase deviation that is detected by the phase locked loop (34).

10. The processing circuit (10) according to any one of claims 8 and 9,wherein the compensation circuit (40) comprises a conjugate generating unit (41) that is configured to generate a complex conjugate based on the error signal (32) to generate a conjugated error signal, and wherein the compensation unit (40) comprises a multiplying unit (42) that is configured to multiply two signals to compensate the timing error in the converted data input signal (22), wherein one of the signals is derived from the output side of the first signal path (20) and the other signal is derived from the conjugated error signal.

11. The processing circuit (10) according to any one of claims 8 to 10, wherein the compensation circuit (40) comprises a scaling unit (43) that is configured to generate a scalar value based on the error signal (32), and wherein the compensation circuit (40) comprises an interpolation filter unit (44) that is configured to apply interpolation filtering to a signal that is derived from the output side of the first signal path (20), wherein the interpolation filter unit (44) is configured to receive the scalar value and to set filter parameters for the interpolation filtering according to the scalar value to compensate the timing error in the converted data input signal (22).

12. The processing circuit (50) according to any one of the preceding claims 1 to 7, wherein the first converter circuit (63) and the second converter circuit (71) are digital -to- analog converters, wherein the reference signal (73) is a digital signal, wherein the first signal path (60) is configured to receive a digital signal as the data input signal (61) and to provide an analog signal as the converted data input signal (62), wherein the second signal path (70) is configured to sample the reference signal by using the second converter circuit (71) to generate a sampled reference signal and to generate the error signal (72) based on the sampled reference signal.

13. The processing circuit (50) according to claim 12, wherein the second signal path (70) comprises a first mixer (74), wherein the first mixer (74) is configured to receive a reference oscillator signal and the sampled reference signal as input and to output the error signal (72), wherein the compensation circuit (80) comprises a first bandpass filter (81) that is configuredto generate a compensation signal based on the error signal (72), wherein the compensation unit (80) comprises a second mixer (82) that is configured to mix two signals to compensate the phase error in the converted data input signal (62), wherein one of the signals is derived from the output side of the first signal path (50) and the other signal is derived from the compensation signal.

14. Wireless communication systems comprising a processing circuit (10; 50) according to any one of the preceding claims.

15. Method for performing a data conversion from an analogue to digital or digital to analogue signal, the method comprising: receiving a data input signal (21) on an input side of a first signal path (20); performing a first data conversion on the data input signal (21) by a first converter circuit using a sampling frequency according to a first oscillator signal (11) for generating a converted data input signal (22); providing the converted data input signal (22) on an output side of the first signal path (20); performing a second data conversion on a reference signal by a second converter circuit (31) of a second signal path (30) using the sampling frequency according to the first oscillator signal (11) to generate an error signal that is indicating a phase error and / or a timing error that results from using the sampling frequency according to the first oscillator signal (11; 51) by the second converter circuit (31); and compensating a phase error and / or a timing error in the converted data input signal (22) by a compensation unit (40) based on the error signal (32).

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