Method and apparatus for identifying wafer edge defect type, medium and wafer processing method

Abstract

The embodiments of the present disclosure disclose a method and apparatus for identifying a wafer edge defect type, a medium and a wafer processing method. The method for identifying a wafer edge defect type comprises: receiving a collected edge image of a wafer under test; according to image features of the edge image, determining an area to be identified having a defect; acquiring morphology features of the defect present in said area; and, according to the morphology features and features of said area, determining the type of the defect present in said area.

Description

Method, device, medium and wafer processing method for identifying wafer edge defect types

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This disclosure claims priority to Chinese Patent Application No. 202310953229.6 filed in China on July 31, 2023, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The embodiments of the present disclosure relate to the field of semiconductor manufacturing technology, and more particularly to a method, device, medium, and wafer processing method for identifying wafer edge defect types. Background Art

[0004] During the integrated circuit manufacturing process, defects may form on the wafer during each process flow. With the development of semiconductor technology, semiconductor devices are becoming increasingly miniaturized, and the impact of defects on wafers in the semiconductor process is becoming increasingly greater. Therefore, during the integrated circuit manufacturing process, defect detection is required on the wafer. Based on the detection results, the cause of the defects can be analyzed and the production process or process equipment can be adjusted to reduce the occurrence of defects.

[0005] Wafer edges are prone to scratches and foreign matter residue. These defects can become a source of contamination, spreading to the wafer's interior and surface, impacting the devices within. As feature sizes continue to shrink, devices are placed closer and closer to the wafer's edge. Wafer edge defects are increasingly impacting process flow and product yield. Especially in manufacturing processes at 65nm and below, wafer edge defects have already severely impacted the process and caused significant product scrap. Therefore, wafer edge defects have become a must-detect and control issue.

[0006] Traditionally, wafer edges can be manually inspected using a microscope, but this is inefficient and slows down production. Currently, automated edge defect scanning equipment designed specifically for wafer edge scanning and monitoring only detects the presence of edge defects, but is unable to classify them, making it impossible to adjust production processes or equipment based on the inspection results.

[0007] Summary of the Invention

[0008] In view of this, the embodiments of the present disclosure hope to provide a method, device, medium and wafer processing method for identifying wafer edge defect types; and can accurately identify wafer edge defect types.

[0009] In a first aspect, an embodiment of the present disclosure provides a method for identifying wafer edge defect types, the method comprising:

[0010] receiving a captured edge image of a wafer to be measured;

[0011] determining a region to be identified where defects exist based on image features of the edge image;

[0012] Obtaining morphological features of defects existing in the area to be identified;

[0013] The type of defects existing in the area to be identified is determined according to the morphological features and the features of the area to be identified.

[0014] In some examples, determining the area to be identified where defects exist based on image features of the edge image includes:

[0015] In the grayscale image corresponding to the edge image, the grayscale value at a position where the grayscale fluctuation value is less than a set first threshold is selected as a reference value;

[0016] The area where the grayscale fluctuation amplitude value with respect to the reference value is greater than the set second threshold is used as the area to be expanded;

[0017] Taking the center of the area to be expanded as the center, obtain the longest distance of the boundary of the area to be expanded in the horizontal direction and the vertical direction respectively, to form the width side and the height side of the area to be identified;

[0018] The area to be identified is determined according to the width side and the height side of the area to be identified and the center of the area to be expanded.

[0019] In some examples, the morphological features include: the area ratio of the defect in the area to be identified and the deflection angle of the longest axis of the defect relative to a set reference angle; the features of the area to be identified include the horizontal length and vertical length of the area to be identified.

[0020] In some examples,

[0021] The determining the type of defects in the area to be identified based on the morphological features and the features of the area to be identified includes:

[0022] Corresponding to the area ratio of the defect in the to-be-identified area being not less than a set area ratio threshold, and the horizontal length and the vertical length of the to-be-identified area being not less than a set first length threshold and a set second length threshold, respectively, determining that the type of the defect in the to-be-identified area is a chipping defect;

[0023] In response to the fact that the deflection angle of the longest axis of the defect relative to the set reference angle is within a set first deflection angle range, the vertical length of the area to be identified is not less than the second length threshold, and the area ratio of the defect in the area to be identified is less than the area ratio threshold, it is determined that the type of defect present in the area to be identified is a crack defect;

[0024] Corresponding to the deflection angle of the longest axis of the defect relative to the set reference angle being within the set second deflection angle range, the horizontal length of the area to be identified is not less than the first length threshold, and the area ratio of the defect in the area to be identified is less than the area ratio threshold, it is determined that the type of defect existing in the area to be identified is a scratch defect.

[0025] In some examples, obtaining morphological features of defects in the area to be identified includes:

[0026] In the area to be identified, the two ends of the defect area are connected, and the rotation angle of the longest connection line to the set reference line in the set rotation direction is determined as the deflection angle of the longest axis of the defect relative to the set reference angle.

[0027] In a second aspect, an embodiment of the present disclosure provides a device for identifying wafer edge defect types, the device comprising: a receiving part, a determining part, an acquiring part, and an identifying part; wherein,

[0028] The receiving part is configured to receive the collected edge image of the wafer to be measured;

[0029] The determining part is configured to determine a region to be identified where defects exist based on image features of the edge image;

[0030] The acquisition part is configured to acquire the morphological characteristics of the defects existing in the area to be identified;

[0031] The identification part is configured to determine the type of defects existing in the area to be identified based on the morphological features and the features of the area to be identified.

[0032] In a third aspect, an embodiment of the present disclosure provides a computing device comprising: a processor and a memory; the processor is used to execute instructions stored in the memory to implement the method for identifying wafer edge defect types as described in the first aspect and any example in the first aspect.

[0033] In a fourth aspect, an embodiment of the present disclosure provides a computer storage medium storing at least one instruction, wherein the at least one instruction is used to be executed by a processor to implement the method for identifying wafer edge defect types as described in the first aspect and any example in the first aspect.

[0034] In a fifth aspect, an embodiment of the present disclosure provides a computer program product, which includes computer instructions stored in a computer-readable storage medium; a processor of an electronic device reads the computer instructions from the computer-readable storage medium, and the processor executes the computer instructions, so that the electronic device executes to implement the method for identifying wafer edge defect types as described in the first aspect and any example in the first aspect.

[0035] In a sixth aspect, an embodiment of the present disclosure provides a wafer processing method, the method comprising:

[0036] Performing wafer processing on the single crystal silicon ingot pulled by the set method to obtain a plurality of wafers;

[0037] For each of the plurality of wafers, an edge defect type is identified by using the method for identifying a wafer edge defect type described in the first aspect and any example of the first aspect.

[0038] The embodiments of the present disclosure provide a method, device, medium and wafer processing method for identifying the type of wafer edge defects; after obtaining the area to be identified where defects exist, the edge defect type is identified by combining the features of the area to be identified that can frame the defects and the morphological features of the defects, thereby improving the accuracy of identifying the wafer edge defect type. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] FIG1 is a schematic diagram of an implementation environment provided by an embodiment of the present disclosure;

[0040] FIG2 is a schematic flow chart of a method for identifying wafer edge defect types provided by an embodiment of the present disclosure;

[0041] FIG3 is a schematic diagram of a wafer edge image provided by an embodiment of the present disclosure;

[0042] FIG4 is a schematic diagram of a defect on a wafer edge according to an embodiment of the present disclosure;

[0043] FIG5 is a schematic diagram of an edge collapse defect provided by an embodiment of the present disclosure;

[0044] FIG6 is a schematic diagram of a crack defect provided by an embodiment of the present disclosure;

[0045] FIG7 is a schematic diagram of a scratch defect provided by an embodiment of the present disclosure;

[0046] FIG8 is a schematic diagram of a device for identifying wafer edge defect types according to an embodiment of the present disclosure;

[0047] FIG9 is a schematic diagram of the structure of a computing device provided by an embodiment of the present disclosure;

[0048] FIG10 is a schematic flow chart of a wafer processing method provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0049] The technical solutions in the embodiments of the present disclosure will be described clearly and completely below with reference to the accompanying drawings in the embodiments of the present disclosure.

[0050] After obtaining a single crystal silicon ingot through the Czochralski method, the single crystal silicon ingot can be sequentially processed through cutting, grinding, polishing, cleaning and other processing steps to obtain a polished wafer; in some cases, a single crystal silicon epitaxial layer is formed on the surface of the polished wafer through chemical vapor deposition and other methods to obtain an epitaxial wafer.

[0051] Whether for polished or epitaxial wafers, edge defects are increasingly impacting subsequent integrated circuit manufacturing processes and product yield. Based on long-term observations and statistics of the wafer production process, we have found that over 90% of edge defects are chip defects, crack defects, and scratch defects.

[0052] For the above three types of defects, specifically, chip defects are edge bump defects with unstable angles, which can easily cause the risk of fragmentation in the subsequent manufacturing process and easily lead to customer complaints. In addition, this type of defect cannot be removed by rework. Crack defects are linear defects and extend along the longitudinal direction of the wafer. They are very likely to cause fragmentation after heating, so they must be intercepted before shipment, and this type of defect is definitely not reworkable. Scratch defects are mostly horizontal extension defects and are mostly caused by abnormalities in edge polishing equipment. Most of them can be removed by rework.

[0053] Based on the specific descriptions of the three types of defects above, since chip defects and crack defects carry a greater risk of fragmentation, while scratch defects can be removed through rework, it is necessary to accurately identify the type of wafer edge defects. In view of this, the disclosed embodiments aim to identify edge defect types in edge images by combining the features of the selected defect's to-be-identified area with the defect's morphological features, thereby improving the accuracy of wafer edge defect type identification.

[0054] Refer to Figure 1, which shows a schematic diagram of an implementation environment provided by an embodiment of the present disclosure. In Figure 1, the wafer W to be tested is placed flat on a carrying platform 10 that can rotate around a central axis C, and a laser emitter 20 emits a laser beam Laser to the wafer W to be tested. The scanning camera 30 collects the reflected light or refracted light of the laser beam passing through the edge of the wafer W to be tested (as shown by the dotted arrow), generates an edge image of the wafer W to be tested and transmits it to the computing device 40. The computing device 40 can execute the technical solution of the embodiment of the present disclosure according to the received edge image, thereby identifying the edge defect type of the wafer to be tested.

[0055] It should be noted that the implementation environment shown in FIG1 is for illustrative purposes only and is not intended to be limiting. It is understandable that those skilled in the art can acquire edge images of the wafer W to be measured using other methods or systems, and the embodiments of the present disclosure will not be described in detail.

[0056] In some examples, the computing device 40 can be at least one of a smartphone, a smartwatch, a desktop computer, a laptop computer, a virtual reality terminal, an augmented reality terminal, a wireless terminal, and a portable laptop computer. The computing device 40 has a communication function and can access a wired network or a wireless network. The computing device 40 can generally refer to one of a plurality of terminals. Those skilled in the art will appreciate that the number of the above-mentioned terminals can be more or less. In some examples, the computing device 40 can receive the edge image transmitted by the scanning camera 30 based on the wired network or wireless network to which it is connected. It can be understood that the computing device 40 is responsible for the calculation and processing work of the technical solution of the present disclosure, and the embodiments of the present disclosure are not limited to this.

[0057] 2 , which shows a method for identifying wafer edge defect types provided by an embodiment of the present disclosure. The method may be executed by the computing device 40 shown in FIG. 1 . The method may include:

[0058] S210: receiving a captured edge image of a wafer to be measured;

[0059] In the embodiments of the present disclosure, the wafer to be tested typically has a notch. Taking the implementation environment shown in FIG1 as an example, since the carrier platform 10 is rotatable, a complete edge image should be as shown in FIG3 , starting with and ending at a notch-shaped pattern. Therefore, the embodiments of the present disclosure can process the portion of the image between two notch patterns in the complete image as the edge image of the wafer to be tested.

[0060] In some examples, the collected original image of the edge of the wafer to be tested can be binarized, that is, the grayscale values ​​of the pixels in the image are set to the range of 0 to 255; compared with the original image, the normal part and the defective part in the edge of the wafer to be tested can be more clearly distinguished.

[0061] S220: Determine a defective area to be identified based on image features of the edge image;

[0062] In the embodiment of the present disclosure, the area to be identified where defects exist can be determined based on the change in the grayscale value in the image. It should be noted that for the portion of the edge of the wafer without defects, the laser will be mirror-reflected at that portion, so that the scanning camera 30 collects more laser beams, and the corresponding portion in the image has a brighter grayscale value; for the portion of the edge of the wafer with defects, the laser will be diffusely reflected at the defect, so that the scanning camera 30 collects fewer laser beams, and the grayscale value of the defective portion in the image changes significantly and is darker. Based on the above description of the characteristics of defects in the image, when an area with a significant change in grayscale value and a darker area appears in the edge image, it can be determined that there is a defect in that area. In some examples, the shape of the area to be identified can be selected as a rectangle, and the defects within it can be completely framed.

[0063] S230: Acquire morphological features of defects existing in the area to be identified;

[0064] In the embodiment of the present disclosure, after completing the confirmation of the area to be identified in accordance with the above steps, the morphological features presented in the image can be obtained for the defects existing in the area. For various edge defect types, due to the different mechanisms of their formation, the morphology appearing at the edge of the wafer is also correspondingly different. Further, the morphological features presented in the image are also different. Therefore, the morphological features can directly characterize the morphological parameters such as the shape, size, and area occupied by the defects at the edge of the wafer. Compared with image features such as grayscale values, they can provide a more accurate identification basis for the defect type. Continuing with Figure 3, the morphological diagrams of the most common chip defects, crack defects, and scratch defects in edge defects are respectively presented. It can be seen from the morphology presented in Figure 3 that the morphological differences of these three types of defects are quite obvious, which can provide a more accurate identification basis for the defect type.

[0065] S240: Determine the type of defects existing in the area to be identified based on the morphological features and the features of the area to be identified.

[0066] In the disclosed embodiments, in addition to morphological features, since the region to be identified can completely enclose the defects within it, the characteristic parameters of this region can also characterize the morphology of the defects in some aspects. Based on this, the disclosed embodiments combine morphological features and the characteristics of the region to be identified to jointly identify the type of edge defects, which improves the accuracy of defect type identification compared to using either morphological features or the characteristics of the region to be identified alone.

[0067] In addition, among the most common defects such as chip defects, crack defects and scratch defects, since scratch defects can be eliminated through rework, accurate identification of edge defect types can identify wafers with scratch defects for rework, eliminating the need to scrap all wafers with edge defects, thereby reducing manufacturing costs.

[0068] For the above technical solution, the embodiment of the present disclosure, for the edge image of the wafer, after obtaining the area to be identified where defects exist, combines the features of the area to be identified that can frame the defects and the morphological features of the defects to identify the edge defect type, thereby improving the recognition accuracy of the wafer edge defect type.

[0069] Regarding the technical solution shown in FIG2 , in some possible implementations, determining the area to be identified where defects exist based on the image features of the edge image includes:

[0070] In the grayscale image corresponding to the edge image, the grayscale value at a position where the grayscale fluctuation value is less than a set first threshold is selected as a reference value;

[0071] The area where the grayscale fluctuation amplitude value with respect to the reference value is greater than the set second threshold is used as the area to be expanded;

[0072] Taking the center of the area to be expanded as the center, obtain the longest distance of the boundary of the area to be expanded in the horizontal direction and the vertical direction respectively, to form the width side and the height side of the area to be identified;

[0073] The area to be identified is determined according to the width side and the height side of the area to be identified and the center of the area to be expanded.

[0074] It should be noted that in the grayscale image corresponding to the edge image, the portion of the wafer edge without defects appears as brighter grayscale values ​​with relatively gentle fluctuations in grayscale values, which can be considered to be roughly consistent. For the portion of the wafer edge with defects, the corresponding portion of the image appears as a darker grayscale value with significant grayscale value changes. In the above implementation, the degree of grayscale value fluctuation is characterized by a first threshold and a second threshold, respectively. Specifically, if the grayscale value fluctuation is less than the first threshold, it indicates that the degree of fluctuation is relatively gentle, and the portion of the wafer edge corresponding to the region with relatively gentle fluctuations in the image is defect-free. If the grayscale value fluctuation is greater than the second threshold, it indicates that the degree of fluctuation is relatively large, and the portion of the wafer edge corresponding to the region with relatively large fluctuations in the image is defective. Regions of the image with large grayscale value fluctuations can be identified as containing defects, but the defects cannot be fully selected. Therefore, the region of the image with large grayscale value fluctuations is considered to be the area to be expanded and expanded to form a region to be identified that can be selected for defect selection.

[0075] Regarding the implementation process of expanding the area to be expanded to form the area to be identified, in detail, as shown in FIG4 , the area with grayscale is the area to be expanded with a defect (Defect). With the center of gravity of the defect area in the area to be expanded as the center, the longest distance of the boundary of the area to be expanded (i.e., the boundary of the defect) is obtained in the horizontal and vertical directions (as shown by the dotted lines in the horizontal and vertical directions) to form the width (Width) and height (Height) of the area to be identified (as shown by the Box in FIG4 ). The area to be identified is formed based on the width and height of the area to be identified and the center of the area to be expanded.

[0076] For the technical solution shown in Figure 2, in some possible implementations, the morphological characteristics of the defect include: the area ratio of the defect in the area to be identified and the deflection angle of the longest axis of the defect relative to the set reference angle; the characteristics of the area to be identified include the horizontal length and vertical length of the area to be identified.

[0077] In the above implementations, in some examples, the process of obtaining the morphological features of a defect can, specifically, on the one hand, obtain the area ratio of the defect within the to-be-identified region based on the ratio of the area occupied by the defect within the to-be-identified region to the area of ​​the to-be-identified region. On the other hand, within the to-be-identified region, a line can be drawn connecting the two ends of the area occupied by the defect, with the line with the longest distance being used as the longest axis of the defect; and, the rotation angle of the longest axis of the defect relative to the set reference angle can be determined as the rotation angle of the longest axis of the defect relative to the set reference angle.

[0078] For the above example, referring to Figure 4, the grayscale area is the area occupied by the defect within the to-be-identified region, denoted as the Defect Area. The Box Area is the product of the width (Width) and height (Height) lengths. The Fill Ratio of the defect within the to-be-identified region is calculated as: Defect Area / Box Area.

[0079] Additionally, within the area to be identified, the line connecting the two ends of the defect area with the longest distance is the longest axis of the defect, marked as the Major axis. The rotation direction can be set to counterclockwise, with the reference line set to the dashed line marked 0° in Figure 4. The dashed line with a deflection angle θ of 0° is rotated counterclockwise until it coincides with the Major axis.

[0080] In the above implementation, in some examples, the features of the area to be identified include at least: the horizontal length and the vertical length of the area to be identified.

[0081] For the above example, the width side length (Width) and the height side length (height) of the area to be identified may be determined as the horizontal length and the vertical length of the area to be identified, respectively.

[0082] It should be noted that through the above implementation and its examples, after the defective area to be identified is determined and the morphological characteristics of the defects in the area to be identified are obtained, the defect type identification can be performed for each defect in the area to be identified. Taking the three common types of defects on the wafer edge as an example, the specific morphology and the shape of the area to be identified formed by the morphology are significantly different.

[0083] Chip defects are usually caused by bumps on the edge of the wafer. The width side length and high-speed side length of the area to be identified with this type of defect are relatively close. From the rectangular shape of the area to be identified, it is relatively "full", and the area of ​​the defect in the area to be identified accounts for a large proportion. The deflection angle of the longest axis of the defect relative to the set reference angle does not have a fixed angle range.

[0084] For a crack defect, its morphology is linear, and the area to be identified where it is located is also correspondingly in the shape of an elongated strip. The area of ​​the defect in the area to be identified is relatively small, and it extends longitudinally (vertically).

[0085] For scratch defects, their morphology is linear, and the area to be identified where they are located is also correspondingly long and thin strips. The area of ​​the defect in the area to be identified is relatively small, but compared with crack defects, they extend laterally (horizontally).

[0086] Based on the above analysis of the three types of defects, and using the morphological features of the defects and the features of the area to be identified obtained by the aforementioned implementations and examples, in some examples, determining the type of defects in the area to be identified based on the morphological features and the features of the area to be identified includes:

[0087] Corresponding to the area ratio of the defect in the to-be-identified area being not less than a set area ratio threshold, and the horizontal length and the vertical length of the to-be-identified area being not less than a set first length threshold and a set second length threshold, respectively, determining that the type of the defect in the to-be-identified area is a chipping defect;

[0088] In response to the fact that the deflection angle of the longest axis of the defect relative to the set reference angle is within a set first deflection angle range, the vertical length of the area to be identified is not less than the second length threshold, and the area ratio of the defect in the area to be identified is less than the area ratio threshold, it is determined that the type of defect present in the area to be identified is a crack defect;

[0089] Corresponding to the deflection angle of the longest axis of the defect relative to the set reference angle being within the set second deflection angle range, the horizontal length of the area to be identified is not less than the first length threshold, and the area ratio of the defect in the area to be identified is less than the area ratio threshold, it is determined that the type of defect existing in the area to be identified is a scratch defect.

[0090] For the edge chipping defect described in the above example, in the specific implementation process, the area ratio of the defect in the area to be identified, the horizontal length and the vertical length of the area to be identified can be compared with the set area ratio threshold, the first length threshold and the second length threshold respectively; when the area ratio of the defect in the area to be identified is not less than the area ratio threshold, and the horizontal length and the vertical length of the area to be identified are not less than the first length threshold and the second length threshold respectively, it can be determined that the type of defect existing in the area to be identified is an edge chipping defect.

[0091] Regarding the above specific implementation process, in detail, first, the embodiment of the present disclosure characterizes the degree of "fullness" of the shape of the area to be identified by comparing the horizontal length (Width) and the vertical length (height) of the area to be identified with the first length threshold a and the second length threshold b respectively. In addition, the size of the area ratio of the defect in the area to be identified can be characterized by comparing the area ratio (Fill Ratio) of the defect in the area to be identified with the area ratio threshold c. As shown in Figure 5, through the above identification means, it can be determined that the defect in the box is a chip defect. The shape of the area to be identified formed by the defect is relatively "full", and the area ratio of the defect in the area to be identified is relatively large. In addition, the deflection angle θ in Figure 5 does not have an obvious pattern, that is, there is no fixed angle range, and it can be ignored in the process of determining the chip defect.

[0092] For the crack defect described in the above example, in the specific implementation process, the deflection angle of the longest axis of the defect relative to the set reference angle, the vertical length of the area to be identified, and the area ratio of the defect in the area to be identified can be compared with the set first deflection angle range, the second length threshold, and the area ratio threshold respectively; when the deflection angle of the longest axis of the defect relative to the set reference angle is within the first deflection angle range, the vertical length of the area to be identified is not less than the second length threshold, and the area ratio of the defect in the area to be identified is less than the area ratio threshold, it can be determined that the type of defect existing in the area to be identified is a crack defect.

[0093] For the above specific implementation process, in detail, first, determine whether the deflection angle θ of the longest axis of the defect relative to the set reference angle satisfies -90°≤θ≤-d or d≤θ≤90°, where d is the set angle value. When the deflection angle θ of the defect satisfies the above-mentioned first deflection angle range, it can be considered that the defect is longitudinally extended. Secondly, the vertical length height of the area to be identified is compared with the set second length threshold b. If it is greater than, it can be said that the shape of the area to be identified is an elongated strip. Finally, the area ratio (Fill Ratio) of the defect in the area to be identified is compared with the area ratio threshold c. If it is less than, it can be considered that the area ratio of the defect in the area to be identified is small. As shown in Figure 6, through the above-mentioned identification means, it can be determined that the defect in the box is a crack defect.

[0094] For the scratch defect described in the above example, in the specific implementation process, the deflection angle of the longest axis of the defect relative to the set reference angle, the horizontal length of the area to be identified, and the area ratio of the defect in the area to be identified can be compared with the set second deflection angle range, the first length threshold, and the area ratio threshold respectively; when the deflection angle of the longest axis of the defect relative to the set reference angle is within the second deflection angle range, the horizontal length of the area to be identified is not less than the first length threshold, and the area ratio of the defect in the area to be identified is less than the area ratio threshold, it can be determined that the type of defect existing in the area to be identified is a scratch defect.

[0095] For the above specific implementation process, in detail, the horizontal Width length of the area to be identified is compared with the set first length threshold a. If it is greater than, it can be said that the shape of the area to be identified is a slender strip. Secondly, it is determined whether the deflection angle θ of the longest axis of the defect relative to the set reference angle satisfies -d≤θ≤d, where d is the set angle value. When the deflection angle θ of the defect meets the above second deflection angle range, it can be considered that the defect is horizontally extended. Secondly, finally, the area ratio (Fill Ratio) of the defect in the area to be identified is compared with the area ratio threshold c. If it is less than, it can be considered that the area ratio of the defect in the area to be identified is small. As shown in Figure 7, through the above identification means, it can be determined that the defect in the box is a scratch defect.

[0096] Through the above examples and their specific implementation process, based on the morphological features of defects in images and the features of the area to be identified used to frame defects, it is not only possible to accurately distinguish the three types of defects on the wafer edge, but also to accurately scrap wafers that cannot be reworked and rework wafers that can be reworked to eliminate defects, thereby reducing production costs.

[0097] Based on the same inventive concept as the above technical solution, referring to FIG8 , it shows a device 80 for identifying wafer edge defect types provided by an embodiment of the present disclosure, the device 80 includes: a receiving part 801 , a determining part 802 , an acquiring part 803 and an identifying part 804 ; wherein,

[0098] The receiving part 801 is configured to receive the collected edge image of the wafer to be measured;

[0099] The determining part 802 is configured to determine a region to be identified where defects exist based on image features of the edge image;

[0100] The acquisition part 803 is configured to acquire the morphological characteristics of the defects existing in the area to be identified;

[0101] The identification part 804 is configured to determine the type of defects existing in the area to be identified based on the topographic features and the features of the area to be identified.

[0102] In some examples, the determining portion 802 is configured to:

[0103] In the grayscale image corresponding to the edge image, the grayscale value at a position where the grayscale fluctuation value is less than a set first threshold is selected as a reference value;

[0104] The area where the grayscale fluctuation amplitude value with respect to the reference value is greater than the set second threshold is used as the area to be expanded;

[0105] Taking the center of the area to be expanded as the center, obtain the longest distance of the boundary of the area to be expanded in the horizontal direction and the vertical direction respectively, to form the width side and the height side of the area to be identified;

[0106] The area to be identified is determined according to the width side and the height side of the area to be identified and the center of the area to be expanded.

[0107] In some examples, the morphological features include: the area ratio of the defect in the area to be identified and the deflection angle of the longest axis of the defect relative to a set reference angle; the features of the area to be identified include the horizontal length and vertical length of the area to be identified.

[0108] In some examples, the identification portion 804 is configured to:

[0109] Corresponding to the area ratio of the defect in the to-be-identified area being not less than a set area ratio threshold, and the horizontal length and the vertical length of the to-be-identified area being not less than a set first length threshold and a set second length threshold, respectively, determining that the type of the defect in the to-be-identified area is a chipping defect;

[0110] In response to the fact that the deflection angle of the longest axis of the defect relative to the set reference angle is within a set first deflection angle range, the vertical length of the area to be identified is not less than the second length threshold, and the area ratio of the defect in the area to be identified is less than the area ratio threshold, it is determined that the type of defect present in the area to be identified is a crack defect;

[0111] Corresponding to the deflection angle of the longest axis of the defect relative to the set reference angle being within the set second deflection angle range, the horizontal length of the area to be identified is not less than the first length threshold, and the area ratio of the defect in the area to be identified is less than the area ratio threshold, it is determined that the type of defect existing in the area to be identified is a scratch defect.

[0112] In some examples, the obtaining portion 803 is configured to:

[0113] In the area to be identified, the two ends of the defect area are connected, and the rotation angle of the longest connection line to the set reference line in the set rotation direction is determined as the deflection angle of the longest axis of the defect relative to the set reference angle.

[0114] Please refer to Figure 9, which shows a block diagram of a computing device provided by an exemplary embodiment of the present application. The computing device in the present application may include one or more of the following components: a processor 910 and a memory 920.

[0115] Optionally, the processor 910 uses various interfaces and lines to connect the various parts of the entire computing device, and performs various functions of the computing device and processes data by running or executing instructions, programs, code sets or instruction sets stored in the memory 920, and calling data stored in the memory 920. Optionally, the processor 910 can be implemented in at least one hardware form of digital signal processing (DSP), field-programmable gate array (FPGA), and programmable logic array (PLA). The processor 910 can integrate one or a combination of a central processing unit (CPU), a graphics processing unit (GPU), a neural network processing unit (NPU), and a baseband chip. Among them, the CPU mainly processes the operating system, user interface, and application programs; the GPU is responsible for rendering and drawing the content required to be displayed on the touch screen; the NPU is used to implement artificial intelligence (AI) functions; and the baseband chip is used to handle wireless communications. It is understandable that the above-mentioned baseband chip may not be integrated into the processor 910, but may be implemented by a separate chip.

[0116] The memory 920 may include a random access memory (RAM) or a read-only memory (ROM). Optionally, the memory 920 includes a non-transitory computer-readable storage medium. The memory 920 may be used to store instructions, programs, codes, code sets, or instruction sets. The memory 920 may include a program storage area and a data storage area, wherein the program storage area may store instructions for implementing an operating system, instructions for at least one function (such as a touch function, a sound playback function, an image playback function, etc.), instructions for implementing the various method embodiments described below, etc.; the data storage area may store data created based on the use of the computing device, etc.

[0117] In addition, those skilled in the art will understand that the structure of the computing device shown in the above figures does not constitute a limitation of the computing device. The computing device may include more or fewer components than shown, or a combination of certain components, or a different arrangement of components. For example, the computing device also includes a display screen, a camera assembly, a microphone, a speaker, a radio frequency circuit, an input unit, sensors (such as an accelerometer, an angular velocity sensor, a light sensor, etc.), an audio circuit, a WiFi module, a power supply, a Bluetooth module, and other components, which will not be described in detail here.

[0118] An embodiment of the present application further provides a computer-readable storage medium storing at least one instruction, wherein the at least one instruction is used to be executed by a processor to implement the method for identifying wafer edge defect types as described in the above embodiments.

[0119] An embodiment of the present application also provides a computer program product, which includes computer instructions stored in a computer-readable storage medium; a processor of a computing device reads the computer instructions from the computer-readable storage medium, and the processor executes the computer instructions, so that the computing device executes the method for identifying wafer edge defect types provided in various optional implementations of the above aspects.

[0120] Those skilled in the art will appreciate that in one or more of the above examples, the functions described in the embodiments of the present application can be implemented using hardware, software, firmware, or any combination thereof. When implemented using software, these functions can be stored in a computer-readable medium or transmitted as one or more instructions or codes on a computer-readable medium. Computer-readable media include computer storage media and communication media, wherein communication media include any media that facilitates the transmission of computer programs from one place to another. The storage medium can be any available medium that can be accessed by a general-purpose or special-purpose computer.

[0121] Based on the above-described solution for identifying wafer edge defect types, referring to FIG10 , a wafer processing method provided by an embodiment of the present disclosure is shown. The method may include:

[0122] S1010: performing wafer processing on the single crystal silicon ingot pulled by the set method to obtain a plurality of wafers;

[0123] S1020: For each of the plurality of wafers, identify an edge defect type using the method for identifying wafer edge defect types described in any of the aforementioned embodiments.

[0124] With respect to the wafer processing method, in some examples, the method further includes:

[0125] Wafers identified as having edge chipping defects or crack defects are determined to be defective wafers that cannot be reworked and are scrapped;

[0126] Wafers identified as having scratch defects are determined to be defective wafers that can be reworked, and the scratch defects are removed through rework.

[0127] It should be noted that the technical solutions described in the embodiments of the present disclosure can be arbitrarily combined without conflict.

[0128] The above description is merely a specific embodiment of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this disclosure should be included in the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. A method for identifying a type of wafer edge defect, the method comprising: Receiving the acquired edge image of the wafer to be tested; Determining a defective area to be identified according to image features of the edge image; Acquiring morphological features of defects existing in the area to be identified; The type of defects existing in the area to be identified is determined according to the morphological features and the features of the area to be identified.

2. The method according to claim 1, wherein: The step of determining the area to be identified where defects exist according to the image features of the edge image comprises: In the grayscale image corresponding to the edge image, the grayscale value at the position where the grayscale fluctuation value is less than a set first threshold is selected as the reference value; The area where the grayscale fluctuation amplitude value with the reference value is greater than the set second threshold is taken as the area to be expanded; Taking the center of the area to be expanded as the center, obtaining the longest distance of the boundary of the area to be expanded in the horizontal direction and the vertical direction respectively, to form the width side and the height side of the area to be identified; The area to be identified is determined according to the width side and the height side of the area to be identified and the center of the area to be expanded.

3. The method according to claim 1, wherein: The morphological features include: the area ratio of the defect in the area to be identified and the deflection angle of the longest axis of the defect relative to a set reference angle; the features of the area to be identified include the horizontal length and vertical length of the area to be identified.

4. The method according to claim 3, wherein: The determining the type of defects existing in the to-be-identified area according to the morphological features and the features of the to-be-identified area includes: Corresponding to the area ratio of the defect in the to-be-identified region being not less than a set area ratio threshold, and the horizontal length and the vertical length of the to-be-identified region being not less than a set first length threshold and a second length threshold, respectively, determining that the type of the defect existing in the to-be-identified region is an edge collapse defect; Corresponding to the deflection angle of the longest axis of the defect relative to the set reference angle being within the set first deflection angle range, the vertical length of the to-be-identified region being not less than the second length threshold, and the area ratio of the defect in the to-be-identified region being less than the area ratio threshold, it is determined that the type of the defect existing in the to-be-identified region is a crack defect; Corresponding to the deflection angle of the longest axis of the defect relative to the set reference angle being within the set second deflection angle range, the horizontal length of the area to be identified is not less than the first length threshold, and the area ratio of the defect in the area to be identified is less than the area ratio threshold, it is determined that the type of defect existing in the area to be identified is a scratch defect.

5. The method according to claim 1, wherein: The step of obtaining the morphological features of the defects in the area to be identified includes: In the area to be identified, the two ends of the defect area are connected, and the rotation angle of the longest connection line to the set reference line in the set rotation direction is determined as the deflection angle of the longest axis of the defect relative to the set reference angle.

6. A device for identifying wafer edge defect types, the device comprising: receiving part, determining part, acquiring part and identifying part; wherein, The receiving part is configured to receive the collected edge image of the wafer to be tested; The determining part is configured to determine a defective area to be identified according to image features of the edge image; The acquisition part is configured to acquire the morphological characteristics of the defects existing in the area to be identified; The identification part is configured to determine the type of defects existing in the area to be identified according to the morphological features and the features of the area to be identified.

7. A computing device, comprising: Processor and memory; The processor is used to execute instructions stored in the memory to implement the method for identifying wafer edge defect types as described in any one of claims 1 to 5.

8. A computer storage medium storing at least one instruction, wherein the at least one instruction is used to be executed by a processor to implement the method for identifying a wafer edge defect type according to any one of claims 1 to 5.

9. A wafer processing method, the method comprising: Performing wafer processing on the single crystal silicon ingot pulled by the set method to obtain a plurality of wafers; For each of the plurality of wafers, an edge defect type is identified by using the method for identifying a wafer edge defect type according to any one of claims 1 to 5.

10. The method according to claim 9, wherein: The method further comprises: Wafers identified as having edge collapse defects or crack defects are determined to be defective wafers that cannot be reworked; Wafers identified as having scratch defects are determined as defective wafers that can be reworked, and the scratch defects are removed through rework.

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