Solar cell unit and manufacturing method therefor

Abstract

Embodiments of the present disclosure provide a solar cell unit and a manufacturing method therefor. The solar cell unit comprises: a silicon substrate which is an n-type silicon substrate; a passivation layer; a seed layer; an interfacial energy level adjustment layer which is a p-type hydrogenated doped silicon layer; and a first p-type conductive layer. The passivation layer, the seed layer, the interfacial energy level adjustment layer, and the first p-type conductive layer are successively stacked on a first side of the silicon substrate, and the passivation layer is closest to the silicon substrate. The interfacial energy level adjustment layer contains a silicon element, an oxygen element, a carbon element, a hydrogen element, and a boron element. The band gap of the interfacial energy level adjustment layer is 1.9-2.3 eV, and the thickness of the interfacial energy level adjustment layer is 0.5-4 nm.

Description

Solar cell and method for manufacturing the same

[0001] This application claims priority to Chinese patent application No. 202310942977.4, entitled “Solar cell unit and method for manufacturing the same,” filed on July 28, 2023. The contents of the Chinese patent application disclosure are hereby incorporated by reference in their entirety as a part of this application. Technical Field

[0002] The present disclosure relates to a solar cell unit and a method for manufacturing a solar cell unit. Background Art

[0003] A crystalline silicon-based heterojunction solar cell is a semiconductor device that converts sunlight into electrical output. Typically, a heterojunction solar cell is fabricated using an n-type silicon substrate. It comprises a silicon substrate, two passivation layers on either side of the silicon substrate, and a doped conductive layer on each of the passivation layers. The silicon-based heterojunction solar cell fabrication process involves depositing hydrogenated amorphous silicon layers on both sides of the textured silicon substrate, depositing phosphorus- and boron-doped silicon layers on the surfaces of the hydrogenated amorphous silicon layers, depositing a transparent conductive ITO (indium tin oxide) layer on the surface of the doped silicon layers, and finally forming electrodes on the ITO layers. Heterojunction solar cells offer numerous advantages, including high efficiency, no degradation, a reduced number of process steps, and low energy consumption (temperatures are all below 300°C). Currently, the main factor limiting the large-scale market penetration of heterojunction solar cells is their slightly higher production cost than other photovoltaic cell products. Therefore, continuously improving the photoelectric conversion efficiency and cost-effectiveness of heterojunction solar cells remains the key development direction for heterojunction solar cells.

[0004] Summary of the Invention

[0005] At least one embodiment of the present disclosure provides a solar cell unit, comprising: a silicon substrate, which is an n-type silicon substrate; a passivation layer; a seed layer; an interface energy level adjustment layer, which is a p-type hydrogenated doped silicon layer; and a first p-type conductive layer. The passivation layer, the seed layer, the interface energy level adjustment layer, and the first p-type conductive layer are sequentially stacked on at least a portion of a first surface of a first side of the silicon substrate, with the passivation layer being closest to the silicon substrate. The interface energy level adjustment layer contains silicon, oxygen, carbon, hydrogen, and boron.

[0006] For example, in some embodiments, the thickness of the interface energy level adjustment layer is 0.5-4 nm.

[0007] For example, in some embodiments, the thickness of the interface energy level adjustment layer is 0.7-1.8 nm.

[0008] For example, in some embodiments, the band gap of the interface energy level adjustment layer is 1.9-2.3 eV.

[0009] For example, in some embodiments, the interface energy level adjustment layer is a hydrogenated amorphous silicon layer and is embedded with crystallized silicon, and the crystallization rate of the interface energy level adjustment layer is in the range of 30-65%.

[0010] For example, in some embodiments, the interface energy level adjustment layer includes Si-Si, Si-O, Si-C, Si-B, CC, CO, C=O, CB, and BO chemical bonds.

[0011] For example, in some embodiments, the total molar content of carbon and oxygen in the interface energy level adjustment layer is 18-45%. The active boron atom concentration in the interface energy level adjustment layer is 5×10 17 -5×10 19 atoms per cubic centimeter.

[0012] For example, in some embodiments, the molar content of carbon in the interface energy level adjustment layer is within a range of 8-16%, and the carbon exists through the formation of Si-C, C-C, CO, C=O, CB, and CH chemical bonds. The molar proportions of carbon existing through Si-C, C-C, CO, C=O, CB, and CH chemical bonds in the total carbon content are 30-54%, 30-45%, 8-14%, 1-5%, 3-7%, and 3-9%, respectively.

[0013] For example, in some embodiments, the molar content of oxygen in the interface energy level adjustment layer is in the range of 18-32%, and the oxygen exists through the formation of Si-O, CO, and BO chemical bonds. The molar proportions of oxygen existing through Si-O, CO, and BO chemical bonds account for 78-92%, 6-15%, and 4-11% of the total oxygen, respectively.

[0014] For example, in some embodiments, the molar content of silicon in the interface energy level adjustment layer is within a range of 50-65%, and the silicon exists by forming Si-Si, Si-O, Si-C, Si-B, and Si-H chemical bonds. The molar proportion of silicon existing through Si-Si, Si-B, and Si-H chemical bonds is 40-60% of the total silicon, the molar proportion of silicon existing through Si-O chemical bonds is 35-45% of the total silicon, and the molar proportion of silicon existing through Si-C chemical bonds is 7-12% of the total silicon.

[0015] For example, in some embodiments, the molar content of boron in the interface energy level adjustment layer is in the range of 1-5%. Inactive boron atoms exist in the film layer in the form of BO, BC, BB, and BH.

[0016] For example, in some embodiments, in the interface energy level adjustment layer, the concentration of active boron atoms increases gradually in a direction away from the silicon substrate, and the crystallization rate of the interface energy level adjustment layer increases gradually.

[0017] For example, in some embodiments, the passivation layer is a hydrogenated amorphous silicon layer. In the passivation layer, the concentration of hydrogen atoms decreases in a direction away from the silicon substrate.

[0018] For example, in some embodiments, the first p-type conductive layer is a p-type microcrystalline silicon layer. The crystallinity of the first p-type conductive layer is in the range of 30-70%. In the first p-type conductive layer, the crystallinity increases in a direction away from the silicon substrate.

[0019] For example, in some embodiments, the passivation layer is a hydrogenated amorphous silicon layer, the first p-type conductive layer is a p-type microcrystalline silicon layer, the thickness of the passivation layer is in the range of 5-8 nm, the thickness of the seed layer is less than 1 nm, and the thickness of the first p-type conductive layer is in the range of 20-38 nm.

[0020] For example, in some embodiments, the solar cell unit further includes a second p-type conductive layer disposed on the first p-type conductive layer and further away from the silicon substrate than the first p-type conductive layer.

[0021] For example, in some embodiments, the second p-type conductive layer is a boron-doped amorphous silicon layer. The concentration of active boron atoms in the second p-type conductive layer is 2×10 18 -1×10 19 The thickness of the second p-type conductive layer is in the range of 0.5-3 nm.

[0022] For example, in some embodiments, the first side is the backlight side of the solar cell.

[0023] For example, in some embodiments, the solar cell unit further includes: a second passivation layer; and an n-type conductive layer. The second passivation layer and the n-type conductive layer are sequentially stacked on a second surface of a second side of the silicon substrate, the second side being opposite to the first side, and the second passivation layer being closest to the silicon substrate.

[0024] For example, in some embodiments, the solar cell further comprises: a second passivation layer; and an n-type conductive layer. The passivation layer, seed layer, interface energy level adjustment layer, first p-type conductive layer, and second p-type conductive layer are sequentially stacked in a p-region on the first surface of the first side of the silicon substrate. The second passivation layer and n-type conductive layer are sequentially stacked in an n-region on the first surface of the silicon substrate, which is different from the p-region.

[0025] The present disclosure also provides a method for manufacturing a solar cell unit, comprising: providing a silicon substrate, the silicon substrate being an n-type silicon substrate; and sequentially stacking a passivation layer, a seed layer, an interface energy level adjustment layer, and a first p-type conductive layer on at least a portion of a first surface of a first side of the silicon substrate. The interface energy level adjustment layer is a p-type hydrogenated doped silicon layer containing silicon, oxygen, carbon, hydrogen, and boron.

[0026] For example, in some embodiments, the thickness of the interface energy level adjustment layer is 0.5-4 nm.

[0027] For example, in some embodiments, the thickness of the interface energy level adjustment layer is 0.7-1.8 nm.

[0028] For example, in some embodiments, the band gap of the interface energy level adjustment layer is 1.9-2.3 eV.

[0029] For example, in some embodiments, the interface energy level adjustment layer is a hydrogenated amorphous silicon layer and is embedded with crystallized silicon, and the crystallization rate of the interface energy level adjustment layer is in the range of 30-65%.

[0030] For example, in some embodiments, the reaction chamber pressure is 2.5-3.5 Torr and the RF power density is 260-340 mW / cm 2 The interface energy level adjustment layer is formed under the following conditions. The silicon element of the interface energy level adjustment layer comes from one or more of SiH4 and Si2H6, the boron element of the interface energy level adjustment layer comes from one or more of TMB, B2H6, and BF3, the hydrogen element of the interface energy level adjustment layer comes from one or more of H2, SiH4, B2H6, and TMB, the oxygen element of the interface energy level adjustment layer comes from one or more of N2O, O2, CO, and CO2, and the carbon element of the interface energy level adjustment layer comes from CO2, CO, CH4, C2H6, and C3H 10 and one or more of C2H4.

[0031] For example, in some embodiments, the manufacturing method further includes: sequentially stacking a second passivation layer and an n-type conductive layer on a second surface of a second side of the silicon substrate, the second side being opposite to the first side.

[0032] For example, in some embodiments, a passivation layer, a seed layer, an interface energy level adjustment layer, and a first p-type conductive layer are sequentially stacked in a p-region on the first surface of the silicon substrate. The method further includes sequentially stacking a second passivation layer and an n-type conductive layer in an n-region on the first surface of the silicon substrate that is different from the p-region.

[0033] For example, in some embodiments, the method further includes: disposing a second p-type conductive layer on the first p-type conductive layer, wherein the second p-type conductive layer is further away from the silicon substrate than the first p-type conductive layer.

[0034] For example, in some embodiments, the second p-type conductive layer is a boron-doped amorphous silicon layer. The concentration of active boron atoms in the second p-type conductive layer is 2×10 18- 1×10 19 The thickness of the second p-type conductive layer is in the range of 0.5-3 nm. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] FIG1 shows a schematic cross-sectional view of a solar cell unit according to an embodiment of the present disclosure;

[0036] 2 shows the effect of using gases with different oxygen-to-silicon ratios and gases with different carbon-to-silicon ratios on the active boron atom content in the interface energy level adjustment layer when forming the interface energy level adjustment layer according to an embodiment of the present disclosure;

[0037] 3 shows the results of analyzing the boron element in the interface energy level adjustment layer formed using hydrogen, silane, methane and trimethylboron using X-ray photoelectron spectroscopy according to an embodiment of the present disclosure;

[0038] FIG4 shows the results of analyzing the boron element in the interface energy level adjustment layer formed using hydrogen, silane, oxygen, and trimethylboron using X-ray photoelectron spectroscopy according to an embodiment of the present disclosure;

[0039] 5 to 8 respectively show the results of analyzing silicon, carbon, oxygen, and boron in an interface energy level adjustment layer formed using hydrogen, silane, carbon monoxide, and trimethylboron using X-ray photoelectron spectroscopy according to an embodiment of the present disclosure, and FIG9 shows a Raman test spectrum of the interface energy level adjustment layer;

[0040] FIG10 shows the effect of providing an interface energy level adjustment layer on the performance of a solar cell unit according to an embodiment of the present disclosure;

[0041] FIG11 shows a schematic cross-sectional view of a solar cell unit according to another embodiment of the present disclosure;

[0042] FIG12 shows the effects of interface energy level adjustment layers of different thicknesses on the performance of a solar cell unit according to an embodiment of the present disclosure;

[0043] FIG. 13 illustrates the effect of providing a second p-type conductive layer on the performance of a solar cell according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0044] Hereinafter, a solar cell unit and a method for manufacturing the same according to embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0045] At least one embodiment of the present disclosure provides a solar cell unit and a method for fabricating the same. By providing an interface energy level adjustment layer between the passivation layer and the p-type conductive layer, the energy level structure at the interface between the silicon substrate and the other semiconductor layers is optimized, enhancing the energy level curvature at the interface and, in turn, the interface's ability to separate, collect, and conduct carriers. This improves electrical properties such as the fill factor of the heterojunction cell and increases the device's photoelectric conversion efficiency.

[0046] FIG1 shows a schematic cross-sectional view of a solar cell according to an embodiment of the present disclosure. The solar cell is a silicon-based heterojunction cell. As shown in FIG1 , the solar cell includes an n-silicon substrate 101, a passivation layer 102, a seed layer 103, an interface energy level adjustment layer 104, a first p-type conductive layer 105, a second p-type conductive layer 106, and an ITO conductive layer 107 sequentially disposed on the surface of a first side of the silicon substrate 101 in a direction away from the silicon substrate 101, and a second passivation layer 108, an n-type conductive layer 109, and a second ITO conductive layer 110 sequentially disposed on the surface of a second side of the silicon substrate 101 in a direction away from the silicon substrate 101, the second side being opposite to the first side. In addition, the solar cell also includes an electrode 111 disposed on the ITO conductive layer 107 and the second ITO conductive layer 110.

[0047] For example, the first side is the backlight side of the solar cell, and the second side is the light-facing side. The passivation layer 102 can be a hydrogenated amorphous silicon layer. The thickness of the passivation layer 102 is in the range of 5-8 nm. Moreover, in the passivation layer 102, the concentration of hydrogen atoms decreases in the direction away from the silicon substrate 101. Therefore, in the passivation layer, the passivation performance close to the silicon substrate 101 is better, and the order of the part away from the silicon substrate 101 increases, and the conductivity is good. The first p-type conductive layer 105 is a p-type microcrystalline silicon layer. The crystallization rate of the first p-type conductive layer 105 is in the range of 30-70%. In the first p-type conductive layer 105, the crystallization rate increases in the direction away from the silicon substrate 101. Moreover, in the first p-type conductive layer 105, the doping concentration of active boron atoms increases in the direction away from the silicon substrate 101. For example, from 5×10 17 atoms per cubic centimeter increased to 2×10 21 atoms per cubic centimeter. For example, from 1×10 18 atoms per cubic centimeter increased to 5×10 20 atoms per cubic centimeter. For example, from 1×10 19 atoms per cubic centimeter increased to 2×10 20 atoms per cubic centimeter.

[0048] A silicon-based heterojunction solar cell uses an intrinsic hydrogenated amorphous silicon layer to passivate the surface of the silicon substrate 101. Doped conductive silicon layers of different doping types are then deposited on the surface of the intrinsic hydrogenated amorphous silicon layer. This allows the inner intrinsic hydrogenated amorphous silicon layer to passivate the surface of the silicon substrate 101, while the outer doped conductive silicon layer, through its own doping, bends the energy band at the interface between the silicon substrate 101 and the semiconductor stack disposed thereon, enabling the extraction and transport of corresponding carriers. Therefore, the properties and matching of each layer are particularly important for heterojunction solar cells. Due to the significant differences in the chemical composition and structure of the materials, different silicon layers have different properties. For example, crystalline silicon is an indirect bandgap material with a bandgap of, for example, 1.12 eV. The intrinsic amorphous silicon layer is a material similar to a direct bandgap, with a bandgap of, for example, 1.6-1.7 eV. The bandgap of the intrinsic microcrystalline silicon layer lies between that of amorphous silicon and crystalline silicon, and varies with the crystallinity of the film layer. Doping microcrystalline silicon can alter the bandgap of the film. Generally speaking, the bandgap of phosphorus-doped microcrystalline silicon is between 1.2 and 1.7 eV, while that of boron-doped microcrystalline silicon is between 1.2 and 1.6 eV. The general rule is that the bandgap of microcrystalline silicon decreases with increasing active boron or phosphorus doping concentrations. Oxidation and carbonization of boron- or phosphorus-doped hydrogenated microcrystalline silicon layers can increase the bandgap of the film. For example, the bandgap of a boron-doped hydrogenated oxidized microcrystalline silicon layer can be adjusted from 1.2 eV to 2.3 eV.

[0049] When preparing a pn junction on the surface of a heterojunction battery, an intrinsic amorphous silicon layer as a passivation layer 102 is first deposited on the surface of an n-type textured silicon substrate 101 to passivate the silicon substrate 101, and then a doped hydrogenated silicon layer is deposited on the surface of the passivation layer 102. The doped hydrogenated silicon layer can be further divided into a doped hydrogenated amorphous silicon layer and a doped hydrogenated microcrystalline silicon layer. Because some silicon atoms in the microcrystalline silicon layer have completed crystallization, the doping concentration of active boron atoms is increased, thereby improving the conductive properties of the film layer. When the deposition of the doped hydrogenated silicon layer on the surface of the silicon substrate 101 is completed to prepare a pn junction, the energy level structure of the interface between the silicon substrate 101 and the other semiconductor stack is also formed at the same time. The Fermi level of the interface tends to be flattened due to the migration and compensation of carriers. The band gap width of each film layer is fixed. If the energy level structure of the interface cannot be well matched, a potential barrier will be formed at the interface, which is not conducive to the separation and conduction of carriers. For heterojunction solar cells with pn junctions, due to the presence of the doped silicon layer, a spatially charged region is formed within a certain area on the surface of the n-type silicon substrate 101. This is manifested as an upward bend in the energy level structure within the silicon substrate 101 in this area, i.e., the conduction band and valence band on the surface of the silicon substrate 101 in contact with the passivation layer 102 simultaneously bend upward. The upward bend of the valence band on the surface of the silicon substrate 101 in the electronic energy level structure at this interface is crucial for the separation, collection, and conduction of carriers and holes. Enhancing the upward bend of the valence band on the silicon substrate 101 side of this interface is an effective method for further improving the fill factor of heterojunction solar cells and is also the key to further improving the conversion efficiency of heterojunction solar cells.

[0050] In the embodiment of the present disclosure, an interface energy level adjustment layer 104 is provided between the passivation layer 102 and the p-type conductive layer, which can improve the electronic energy level structure of the interface, thereby improving the battery fill factor.

[0051] In one embodiment, the interface energy level adjustment layer 104 is a carbon- and oxygen-containing boron hydride-doped microcrystalline silicon layer. For example, the interface energy level adjustment layer 104 has a band gap between 1.9 and 2.3 eV.

[0052] On the one hand, because the interface energy level adjustment layer 104 has a relatively wide bandgap, when it is disposed between the intrinsic amorphous silicon layer serving as the passivation layer 102 and the p-type microcrystalline silicon layer serving as the p-type conductive layer, the energy level realignment increases the upward curvature of the energy levels on the silicon substrate 101 side at the interface. Specifically, the valence band energy level height on the surface of the silicon substrate 101 further bends upward at the interface with the passivation layer 102. This facilitates the migration and accumulation of holes within the silicon substrate 101 toward this interface, increasing the unidirectional extraction and conduction probability of holes by the semiconductor stack disposed on the silicon substrate 101, and improving the fill factor of the heterojunction cell.

[0053] On the other hand, because the interface energy level adjustment layer 104 has a relatively wide bandgap, the conduction bands of the intrinsic amorphous silicon layer serving as the passivation layer 102 and the interface energy level adjustment layer 104 on one side of the semiconductor stack are further bent upward. This allows the interface to repel electrons from the silicon substrate 101, while also enhancing the ability of electrons from the semiconductor stack to be injected into the silicon substrate 101, thereby reducing the probability of carrier recombination at the interface.

[0054] In one embodiment, the interface energy level adjustment layer 104 contains oxygen and carbon, and includes Si-O and Si-C chemical bonds. For example, the interface energy level adjustment layer 104 includes silicon, oxygen, carbon, hydrogen, and boron, so that Si-Si, Si-O, Si-C, Si-B, CC, CO, C=O, CB, and BO chemical bonds serve as film network formers, and hydrogen forms Si-H, CH, and BH chemical bonds as network modifiers to passivate dangling bonds in the saturated film.

[0055] The interface energy level adjustment layer 104 contains oxygen elements. When the film is deposited, the oxygen elements in the reaction gas will react with the boron elements to generate boron oxides, thereby reducing the concentration of active boron atoms in the film. As a result, the activation energy of the film increases due to the reduction in the content of active boron atoms, resulting in a deterioration in the conductivity of the film. However, if the oxygen content is directly reduced during film deposition, the band gap of the film will be reduced, and the energy level adjustment function will not be achieved. The present invention solves this contradiction by increasing the carbon content in the film, thereby controlling the total carbon and oxygen content while reducing the oxygen content in the film, thereby maintaining the film with a higher band gap. At the same time, reducing the oxygen content in the film can increase the content of active boron atoms in the film, so that the interface energy level adjustment layer 104 has both good conduction capability and excellent energy level adjustment capability.

[0056] The energy level adjustment capability of the interface energy level adjustment layer 104 can be optimized by adjusting the thickness of the interface energy level adjustment layer 104. In some embodiments, the thickness of the interface energy level adjustment layer 104 is 0.5-4 nm, or 0.7-1.8 nm.

[0057] In addition, the refractive index of the interface energy level adjustment layer 104 can be in the range of 2.0-2.4. The interface energy level adjustment layer 104 is a hydrogenated amorphous silicon layer in which crystallized silicon is embedded (or in other words, a hydrogenated microcrystalline oxidized silicon carbide layer). The crystallization rate of the interface energy level adjustment layer 104 is in the range of 30-65%. In the direction away from the silicon substrate 101, the concentration of active boron atoms increases, and the crystallization rate of the interface energy level adjustment layer 104 increases. For example, the molar content of boron element in the interface energy level adjustment layer 104 is in the range of 1-5%. For example, the molar content of active boron atoms in the interface energy level adjustment layer 104 is in the range of 5×1017 -5×10 19 atoms per cubic centimeter, and the remaining inactive boron atoms exist in the film layer in the form of BO, BC, BB and BH.

[0058] The molar content of silicon in the interface energy level adjustment layer 104 may be in the range of 50-65%, and the silicon may exist by forming Si-Si, Si-O, Si-C, Si-B, and Si-H chemical bonds. For example, the molar ratio of silicon existing through Si-Si, Si-B, and Si-H chemical bonds is 40-60% of the total silicon, the molar ratio of silicon existing through Si-O chemical bonds is 35-45%, and the molar ratio of silicon existing through Si-C chemical bonds is 7-12%.

[0059] The molar content of carbon in the interface energy level adjustment layer 104 may be in the range of 8-16%, and the carbon may be present via Si-C, C-C, CO, C=O, CB, and CH chemical bonds. For example, the molar ratios of carbon present via Si-C, C-C, CO, C=O, CB, and CH chemical bonds to the total carbon content are 30-54%, 30-45%, 8-14%, 1-5%, 3-7%, and 3-9%, respectively.

[0060] The molar content of oxygen in the interface energy level adjustment layer 104 may be in the range of 18-32%, and the oxygen may exist through Si-O, CO, and BO chemical bonds. For example, the molar proportions of oxygen existing through Si-O, CO, and BO chemical bonds are 78-92%, 6-15%, and 4-11%, respectively, of the total oxygen.

[0061] The seed layer 103 provides conditions for uniform growth of the interface energy level adjustment layer 104. For example, the thickness of the seed layer 103 is less than 1 nm. The seed layer may include hydrogenated amorphous silicon and hydrogenated microcrystalline silicon, for example, a small amount of hydrogenated amorphous silicon and a large amount of hydrogenated microcrystalline silicon.

[0062] The first p-type conductive layer 105 is a p-type microcrystalline silicon layer. The crystallinity of the first p-type conductive layer 105 is within a range of 30-70%. Furthermore, the crystallinity of the first p-type conductive layer 105 increases in a direction away from the silicon substrate 101. The thickness of the first p-type conductive layer 105 can be within a range of 20-38 nm, but the present disclosure is not limited thereto.

[0063] The second p-type conductive layer 106 is a boron heavily doped amorphous silicon layer. For example, in the second p-type conductive layer, the active boron atomic concentration is 2×10 18 -1×10 19The thickness of the second p-type conductive layer 106 may be in the range of 0.5-3 nm, but the present disclosure is not limited thereto.

[0064] The n-type conductive layer may be a phosphorus-doped microcrystalline silicon layer, and its thickness may be 12-18 nm.

[0065] In one embodiment of the present disclosure, the thickness of the passivation layer is in the range of 5-8 nm, the thickness of the seed layer is less than 1 nm, the thickness of the interface energy level adjustment layer is 0.5-4 nm, and the thickness of the first p-type conductive layer is in the range of 20-38 nm. Preferably, the thickness of the interface energy level adjustment layer is 0.7-1.8 nm. Due to the provision of an interface energy level adjustment layer of appropriate thickness, the upward curvature of the valence band energy level on the silicon substrate side and the downward curvature of the conduction band on the semiconductor stack side at the interface with the silicon substrate are significantly improved, thereby improving the performance of the solar cell unit. By providing a seed layer with a thickness of less than 1 nm, the crystallization rate and crystallization uniformity of the interface energy level adjustment layer are improved. In addition, the first p-type conductive layer is an important component in the formation of the pn junction of the heterojunction cell. By setting the first p-type conductive layer to a certain thickness to form a more appropriate pn junction structure, it is ensured that carriers are selectively separated and conducted under the action of the built-in electric field of the interface pn junction, thereby ensuring the performance of the solar cell unit and at the same time avoiding the energy consumption and material waste caused by an excessively thick first p-type conductive layer.

[0066] Preferably, the concentration of boron atoms in the first p-type conductive layer is gradually increased from the silicon substrate outward by gradient setting. The valence band of the film layer is further bent upward due to the gradual change of the doping concentration in the first p-type conductive layer, thereby enhancing the unidirectional conduction and transmission capability of the hole in the film layer, and further improving the performance of the solar cell unit.

[0067] Furthermore, preferably, a second p-type conductive layer with a thickness in the range of 0.5-3 nm is further provided on the first p-type conductive layer. The second p-type conductive layer can further improve the performance of the solar cell unit (described in detail below).

[0068] FIG11 shows a schematic cross-sectional view of a solar cell according to another embodiment of the present disclosure. The solar cell is a silicon-based heterojunction cell. As shown in FIG11 , the solar cell includes an n-type silicon substrate 201; a passivation layer 202, a seed layer 203, an interface energy level adjustment layer 204, a first p-type conductive layer 205, a second p-type conductive layer 206, and an ITO conductive layer 207, which are sequentially disposed in a p-region on a first side of the surface of the silicon substrate 201 in a direction away from the silicon substrate 201; a passivation layer 202, an n-type conductive layer 209, and a second ITO conductive layer 210, which are sequentially disposed in an n-region on the first side of the surface of the silicon substrate 201 in a direction away from the silicon substrate 201; and a silicon oxide layer 213 and a silicon nitride layer 214, which are sequentially disposed on a second side of the silicon substrate 201. For example, the first side is the backlight side, and the second side is the light-facing side. In addition, the solar cell includes an electrode 211 disposed on the ITO conductive layer 207 and the second ITO conductive layer 210. The properties of each film layer of the solar cell unit can be set to be the same as or similar to the properties of the corresponding film layer mentioned above.

[0069] At least one embodiment of the present disclosure further provides a method for manufacturing a solar cell unit, which can be used, for example, to manufacture the solar cell unit described above. The method may include the following steps: Step S11, providing an n-type silicon substrate 101, 201; and Step S12, sequentially stacking a passivation layer 102, 202, a seed layer 103, 203, an interface energy level adjustment layer 104, 204, a first p-type conductive layer 105, 205, and a second p-type conductive layer 106, 206 on a first side of the silicon substrate 101, 201.

[0070] In one embodiment, the method is used to manufacture the solar cell unit described above, wherein a plasma-enhanced chemical vapor deposition (PECVD) process can be used to form the passivation layer 102, 202, the seed layer 103, 203, the interface energy level adjustment layer 104, 204, the first p-type conductive layer 105, 205, and the second p-type conductive layer 106, 206. For example, a radio frequency (RF) power source or a very high frequency (VHF) power source can be used as a plasma excitation source, the film deposition pressure is 0.4-5 Torr, and the film deposition temperature is 140-220 degrees Celsius.

[0071] In step S12, the reaction gas is used, the pressure in the reaction chamber is 2.5-3.5 Torr, and the RF power density is 260-340 mW / cm 2Under the conditions of , the interface energy level adjustment layer 104, 204 with a thickness of 0.7-4 nm is formed. For example, the silicon element of the interface energy level adjustment layer 104, 204 is selected from one or more of SiH4 and Si2H6, the boron element is selected from one or more of TMB (trimethylboron), B2H6, and BF3, the hydrogen element is selected from one or more of H2, SiH4, B2H6, and TMB, the oxygen element is selected from one or more of N2O, O2, CO, and CO2, and the carbon element is selected from CO2, CO, CH4, C2H6, and C3H 10 and one or more of C2H4.

[0072] In step S12, silane is used as the deposition gas and a 13.56 MHz radio frequency power source is used as the plasma excitation source. 2 Under the conditions of , a passivation layer 102, 202 with a thickness of 5-8 nm is formed.

[0073] In step S12, hydrogen and silane are used as reaction gases, a 13.56 MHz radio frequency power source is used as a plasma excitation source, a hydrogen to silane flow ratio is greater than 300, and a radio frequency power density is 100-150 mW / cm 2 Under the conditions of , seed layers 103 and 203 with a thickness of less than 1 nm are formed.

[0074] In step S12, hydrogen, silane and diborane are used as reaction gases, and a 13.56 MHz radio frequency power source is used as a plasma excitation source. 2 Under the conditions of , a first p-type conductive layer with a thickness of 0-38 nm is formed.

[0075] In step S12, silane and diborane are used as reaction gases, and a 13.56 MHz radio frequency power source is used as a plasma excitation source. 2 Under the conditions of , a second p-type conductive layer with a thickness of 0.5-3 nm is formed.

[0076] The formed solar cell unit may be the solar cell unit described in conjunction with FIG. 1 or FIG. 11 .

[0077] In one embodiment of the present disclosure, the interface energy level adjustment layer is prepared by using different reaction gases, and the active boron atom content in the formed interface energy level adjustment layer is detected, including the following steps:

[0078] Step S21 : providing an n-type single crystal silicon substrate having a bulk resistivity of 2.5 Ω·cm.

[0079] Step S22: cleaning the surface of the silicon substrate.

[0080] Step S23, depositing an interface energy level adjustment layer on the surface of the silicon substrate. A 30 nm thick film layer is deposited on the surface of the silicon substrate using a PECVD process. Hydrogen, silane, methane, and trimethylboron are used as reaction gases, and the flow ratio of the mixed gas is 500:1:(0-1.2):0.02. When depositing the film layer, the chamber pressure is 450 Pa and the RF power density is 320 mW / cm 2 .

[0081] Instead of step S23, step S23' is performed to deposit an interface energy level adjustment layer on the surface of the silicon substrate. A 30 nm thick film layer is deposited on the surface of the silicon substrate using a PECVD process. Unlike step S23, hydrogen, silane, oxygen and trimethylboron are used as reaction gases, and the flow ratio of the mixed gas is 500:1:(0-1.7):0.02. When depositing the film layer, the chamber pressure is 450 Pa and the RF power density is 320 mW / cm 2 .

[0082] Instead of step S23, step S23' is performed to deposit an interface energy level adjustment layer on the surface of the silicon substrate. A 30 nm thick film layer is deposited on the surface of the silicon substrate using a PECVD process. Unlike step S23, hydrogen, silane, carbon monoxide, and trimethylboron are used as reaction gases, and the flow ratio of the mixed gas is 500:1:2:0.02. When depositing the film layer, the chamber pressure is 450 Pa and the RF power density is 320 mW / cm 2 .

[0083] In step S24 , the concentration of active boron atoms in the interface energy level adjustment layers formed in steps S23 , S23 ′, and S23 ″ are detected respectively.

[0084] Figure 2 shows the effect of using different oxygen-to-silicon ratio gases and carbon-to-silicon ratio gases on the active boron atom content in the interface energy level adjustment layer when forming the interface energy level adjustment layer. Specifically, Figure 2 shows the active boron atom concentration in the interface energy level adjustment layer formed in steps S23 and S23'. As shown in Figure 2, as the oxygen content in the interface energy level adjustment layer increases, the active boron atom content in the interface energy level adjustment layer decreases sharply.

[0085] FIG3 shows the results of an X-ray photoelectron spectroscopy analysis of the boron element in the interface energy level adjustment layer formed using hydrogen, silane, methane, and trimethylboron (i.e., in step S23), and FIG4 shows the results of an X-ray photoelectron spectroscopy analysis of the boron element in the interface energy level adjustment layer formed using hydrogen, silane, oxygen, and trimethylboron (in step S23′). As shown in FIG3 , when the interface energy level adjustment layer is formed using methane as the reaction gas, the boron element is not oxidized. As shown in FIG4 , when the interface energy level adjustment layer is formed using oxygen as the reaction gas, some boron atoms combine with oxygen to form boron oxide compounds, which reduces the concentration of active boron atoms in the interface energy level adjustment layer, thereby increasing the activation energy of the interface energy level adjustment layer and weakening its electrical conductivity.

[0086] 5 to 8 respectively show the results of analyzing the silicon, carbon, oxygen, and boron elements in the interface energy level adjustment layer formed using hydrogen, silane, carbon monoxide, and trimethylboron (in step S23") using X-ray photoelectron spectroscopy, and FIG. 9 shows a Raman test spectrum of the interface energy level adjustment layer. As shown in FIG. 5 and FIG. 7 , a large proportion of silicon atoms in the interface energy level adjustment layer are combined with oxygen atoms. Since the number of oxygen atoms provided is insufficient to oxidize all silicon atoms, the results show that the chemical state of silicon atoms in the silicon oxide in the interface energy level adjustment layer is distributed from +1 to +4; some silicon atoms Combined with carbon, it forms Si-C chemical bonds. Due to the formation of Si-O and Si-C bonds, the band gap of the interface energy level adjustment layer is widened. As shown in Figure 6, nearly half of the carbon atoms form Si-C bonds with silicon. The entry of carbon atoms into the interface energy level adjustment layer widens its band gap. As shown in Figure 8, the total molar content of boron atoms in the interface energy level adjustment layer reaches 5%. Nearly 45% of the boron atoms are oxidized, while the remaining boron atoms enter the interface energy level adjustment layer by forming BC, BB, B-Si, and BH chemical bonds. As shown in Figure 9, the crystallization rate of the silicon component of the interface energy level adjustment layer is 48%.

[0087] In another embodiment (Example 1) of the present disclosure, a solar cell unit is prepared by the following steps:

[0088] Step S31 : providing an n-type single crystal silicon substrate having a bulk resistivity of 2.5 Ω·cm.

[0089] Step S32: Surface treatment of the silicon substrate, including texturing and cleaning, can be performed by anisotropically etching the silicon substrate with a sodium hydroxide solution having a mass fraction of 5%, to obtain a textured silicon substrate surface with a reflectivity of no more than 12%.

[0090] In step S33, a passivation layer and a second passivation layer are formed on both surfaces of the first and second sides of the silicon substrate, respectively. A PECVD process can be used to form hydrogenated amorphous silicon layers on both surfaces of the silicon substrate as the passivation layer and the second passivation layer. The thickness of the passivation layer and the second passivation layer can be 10 nm. After double-sided passivation, the simulated open circuit voltage reaches 750 mV.

[0091] Step S34: Form an n-type conductive layer on the second passivation layer on the second side. A phosphorus-doped hydrogenated microcrystalline silicon oxycarbide layer can be formed on the second passivation layer using a PECVD process. The reaction gases used are SiH4, H2, CO2, and PH3, and the thickness of the n-type conductive layer is 15 nm.

[0092] In step S35 , a seed layer, a first p-type conductive layer, and a second p-type conductive layer are sequentially formed on the passivation layer on the first side. The stacked layers may be formed using a PECVD process.

[0093] Specifically, SiH4 and H2 were used as reaction gases, and the flow ratio of silane to hydrogen was 300, forming a seed layer with a thickness of 0.5 nm. In addition, a 13.56 MHz RF power source was used as a plasma excitation source, and the RF power density was 120 mW / cm 2 The seed layer is formed under the condition of

[0094] Using the PECVD process, a mixed gas of silane, hydrogen, and trimethylboron was used as a reaction precursor to form a first p-type conductive layer with a thickness of 28nm on the seed layer. The first p-type conductive layer was a boron-doped microcrystalline silicon layer. In addition, a 13.56MHz RF power source was used as the plasma excitation source. At an RF power density of 300mW / cm 2 The first p-type conductive layer is formed under the condition of.

[0095] The PECVD process was used to form a second p-type conductive layer with a thickness of 1.6 nm using SiH4 and B2H6 as reaction gases. The second p-type conductive layer was a boron-doped amorphous silicon layer. A 13.56 MHz RF power source was used as the plasma excitation source. The RF power density was 30 mW / cm 2 The second p-type conductive layer is formed under the condition of.

[0096] Step S36: Form ITO layers on the second p-type conductive layer and the n-type conductive layer, respectively. PVD equipment can be used to form the two ITO transparent conductive layers, with a thickness of 80 nm.

[0097] Step S37 , forming electrodes by printing low-temperature silver paste on the two ITO layers.

[0098] In another embodiment of the present disclosure (Example 2), a solar cell is prepared using steps similar to steps S31-S37. Unlike the preparation method including steps S31-S37, step S35' is replaced with step S35'. In step S35', a seed layer, an interface energy level adjustment layer, a first p-type conductive layer, and a second p-type conductive layer are sequentially formed on the passivation layer on the first side.

[0099] Specifically, a seed layer, a first p-type conductive layer, and a second p-type conductive layer are formed in the same manner as in step S35. Furthermore, a 2 nm thick interface energy level adjustment layer is formed on the seed layer using a PECVD process with a mixture of silane, hydrogen, carbon monoxide, and trimethylboron as a reaction precursor.

[0100] The formed solar cell unit may be the solar cell unit described in conjunction with FIG. 1 .

[0101] The performance of the solar cell unit formed by steps S31 - S37 and the solar cell unit formed by steps S31 - S34 , S35 ′ and S36 - S37 were tested, and the results are shown in FIG. 10 .

[0102] As shown in Figure 10, when the short-circuit current, open-circuit voltage, fill factor, and photoelectric conversion efficiency of the solar cell unit (Example 1) formed using steps S31-S37 are set to 100%, the short-circuit current, open-circuit voltage, fill factor, and photoelectric conversion efficiency of the solar cell unit (Example 2) formed using steps S31-S34, S35', and S36-S37 are 100.1%, 100.02%, 127.56%, and 127.65%, respectively. By providing an interface energy level adjustment layer, the fill factor and photoelectric conversion efficiency of the solar cell unit can be greatly improved.

[0103] In another embodiment of the present disclosure (Example 3), a solar cell unit is prepared by the following steps:

[0104] Step S41 : providing an n-type single crystal silicon substrate having a bulk resistivity of 2.3 Ω·cm.

[0105] Step S42: Surface treatment of the silicon substrate, including texturing and cleaning, can be performed by anisotropically etching the silicon substrate with a sodium hydroxide solution having a mass fraction of 5%, to obtain a textured silicon substrate surface with a reflectivity of no more than 12%.

[0106] Step S43: Form a stack of a silicon oxide layer and a silicon nitride layer on the surface of the second side of the silicon substrate. The silicon oxide layer can be formed on the surface of the second side of the silicon substrate (e.g., the front side) using a thermal oxidation process, and then a silicon nitride layer with a thickness of 78 nm is formed on the silicon oxide layer using a PECVD process. The refractive index of the stack is 2.1.

[0107] In step S44, the surface of the first side of the silicon substrate is cleaned by using a 1% hydrofluoric acid solution to clean the surface of the first side of the silicon substrate (eg, the back side).

[0108] Step S44: forming a passivation layer on the surface of the first side of the silicon substrate. A hydrogenated amorphous silicon layer may be formed on the surface of the first side of the silicon substrate using a PECVD process, and the thickness of the hydrogenated amorphous silicon layer may be 10 nm.

[0109] In step S45, phosphorus is locally doped in the n-region of the passivation layer to form an n-type conductive layer. A mold can be used to mask the pre-designed p-region, leaving the n-region exposed. A phosphorus-doped hydrogenated microcrystalline silicon oxycarbide layer is then formed on the passivation layer using a PECVD process to serve as the n-type conductive layer. The reaction gases used are SiH₄, H₂, CO₂, and PH₃. The thickness of the n-type conductive layer is 15 nm.

[0110] In step S46, a seed layer, an interface energy level adjustment layer, a first p-type conductive layer, and a second p-type conductive layer are sequentially formed in the p-region on the passivation layer. A mold can be used to mask the pre-designed n-region, leaving the p-region exposed; the stack is then formed using a PECVD process. The seed layer, interface energy level adjustment layer, first p-type conductive layer, and second p-type conductive layer can be formed using the same or similar methods as in step S35'.

[0111] In step S47, a second ITO layer is formed on the n-type conductive layer in the n-region and an ITO layer is formed on the second p-type conductive layer in the p-region. A film tool can be used to mask the local ITO layer, and a PVD process is used to form an 80nm thick ITO transparent conductive film layer in the corresponding regions.

[0112] Step S48 , forming electrodes by using low-temperature silver paste printing to form electrodes on the ITO layer and the second ITO layer respectively.

[0113] The formed solar cell unit may be the solar cell unit described in conjunction with FIG. 11 .

[0114] In another embodiment of the present disclosure (Example 4), a solar cell unit is prepared by the following steps:

[0115] Step S51 : providing an n-type single crystal silicon substrate having a bulk resistivity of 2.5 Ω·cm.

[0116] Step S52: Surface treatment of the silicon substrate, including texturing and cleaning, can be performed by anisotropically etching the silicon substrate with a sodium hydroxide solution having a mass fraction of 5%, to obtain a textured silicon substrate surface with a reflectivity of no more than 12%.

[0117] In step S53, a passivation layer and a second passivation layer are formed on both surfaces of the first and second sides of the silicon substrate, respectively. A PECVD process can be used to form hydrogenated amorphous silicon layers on both surfaces of the silicon substrate as the passivation layer and the second passivation layer. The thickness of the passivation layer and the second passivation layer can be 10 nm. After double-sided passivation, the simulated open circuit voltage reaches 750 mV.

[0118] Step S54: Form an n-type conductive layer on the second passivation layer on the second side. A phosphorus-doped hydrogenated microcrystalline silicon oxycarbide layer can be formed on the second passivation layer using a PECVD process. The reaction gases used are SiH4, H2, CO2, and PH3, and the thickness of the n-type conductive layer is 15 nm.

[0119] In step S55, a seed layer and an interface energy level adjustment layer are formed on the passivation layer on the first side. SiH4 and H2 can be used as the reaction gases, with a flow ratio of silane to hydrogen of 300:1, to form a seed layer with a thickness of 0.5 nm. Furthermore, a phosphorus-doped hydrogenated microcrystalline silicon oxycarbide layer can be formed on the second passivation layer using a PECVD process as the interface energy level adjustment layer.

[0120] In various examples, a PECVD process can be used to form a boron-doped hydrogenated microcrystalline oxidized silicon carbide layer of varying thicknesses on the passivation layer using a mixture of SiH4, H2, CO2, and B2H6 as a reaction precursor. In various examples, the thickness of the interface energy level adjustment layer is 0.5 nm, 0.9 nm, 1.25 nm, 1.6 nm, 1.9 nm, and 2.6 nm, respectively. This thickness can be controlled by adjusting the deposition time.

[0121] Step S56: forming a first p-type conductive layer on the interface energy level adjustment layer on the first side. A PECVD process can be used, using a mixed gas as a reaction precursor, to form a 24nm thick boron-doped hydrogenated microcrystalline silicon layer on the interface energy level adjustment layer as the first p-type conductive layer, and a 13.56MHz radio frequency power source as a plasma excitation source at a radio frequency power density of 290mW / cm 2 The first p-type conductive layer is formed under the condition of.

[0122] In step S57, a second p-type conductive layer is formed on the first p-type conductive layer on the first side. The second p-type conductive layer with a thickness of 1.6 nm can be formed by PECVD process using SiH4 and B2H6 as reaction gases. The second p-type conductive layer is a boron-doped amorphous silicon layer. A 13.56 MHz RF power source is used as the plasma excitation source. The RF power density is 400 mW / cm 2 The second p-type conductive layer is formed under the condition of.

[0123] Step S58: Form ITO layers on the second p-type conductive layer and the n-type conductive layer, respectively. The two ITO transparent conductive layers can be formed using PVD equipment, with a thickness of 80 nm.

[0124] Step S59 , forming electrodes by printing low-temperature silver paste on the two ITO layers.

[0125] Figure 12 shows the effect of different thicknesses of the interface energy level adjustment layer on the performance of the solar cell. As shown in Figure 12, when the thickness of the interface energy level adjustment layer is 0.50nm, 0.91nm, 1.25nm, 1.59nm, 1.92nm, and 2.60nm, the corresponding fill factors (FF) of the solar cell are 83.200%, 83.930%, 84.019%, 83.776%, 82.939%, and 82.100%, respectively. The corresponding photoelectric conversion efficiency (Eta) of the solar cell is 24.65%, 24.77%, 24.86%, 24.76%, 24.38%, and 24.01%, respectively. Trend analysis based on the results shown in Figure 12 shows that when the thickness of the interface energy level adjustment layer ranges from 0.7 to 1.8nm, the solar cell has a relatively excellent fill factor and photoelectric conversion efficiency (Eta). Considering that the diameter of a silicon atom is on the order of one-tenth of an angstrom, if the interface energy level adjustment layer is too thin, the distribution of various atoms will be uneven, and thus the interface energy level adjustment layer will not be sufficient to achieve the desired curvature of the silicon substrate surface. In addition, if the interface energy level adjustment layer is too thick, its inherent poor conductivity will also reduce the conductivity of the entire interface energy level adjustment layer.

[0126] In another embodiment of the present disclosure (Embodiment 5), a solar cell is prepared using steps similar to those of steps S31-S34, S35', and S36-S37 described above. Unlike the method comprising steps S31-S34, S35', and S36-S37 described above, a second p-type conductive layer is not formed in step S35', and thus the resulting solar cell does not have a second p-type conductive layer.

[0127] FIG. 13 shows a comparison of the performance of a solar cell having a second p-type conductive layer and a solar cell having no second p-type conductive layer.

[0128] As shown in Figure 13, when the short-circuit current, open-circuit voltage, fill factor, photoelectric conversion efficiency, and series resistance of the solar cell according to Example 5 without the second p-type conductive layer are set to 100%, the short-circuit current, open-circuit voltage, fill factor, photoelectric conversion efficiency, and series resistance of the solar cell according to Example 2 are 99.99%, 100.01%, 101.64%, 101.36%, and 77.10%, respectively. Therefore, the second p-type conductive layer can further reduce the activation energy of the semiconductor stack, lower contact resistance, improve the fill factor, and thus enhance the conversion efficiency of the solar cell.

[0129] Specifically, there may be the following reasons: First, the second P-type conductive layer can have a better energy level matching with the interface energy level adjustment layer and the first P-type conductive layer. The second P-type conductive layer can enhance the conductivity of the semiconductor stack and increase the conductivity of the entire semiconductor stack by reducing the activation energy of the semiconductor stack; second, the second P-type conductive layer is an amorphous silicon layer, which is flat, uniform and has good continuous coverage, thereby preventing the overflow of highly doped boron elements in the inner layer and causing reduced contact; third, the outer doped amorphous silicon layer has a better energy level matching with the ITO film, which reduces the contact barrier and improves the fill factor.

[0130] In this article, the formation of Si-H, C-H, and B-H chemical bonds in the film layer refers to the general term for this type of chemical bond. Specifically, the Si-H chemical bonds in the film layer include chemical bonds such as Si-H, Si-H2, and Si-H3. It is further pointed out that the bonding state between hydrogen atoms and silicon atoms (i.e., the electron cloud distribution tendency of the silicon hydrogen group) can include various forms, such as forming H0, H+, or hydrogen antibonding. Specifically, the C-H chemical bonds in the film layer include chemical bonds such as C-H2, and C-H3; specifically, the BH chemical bonds in the film layer include chemical bonds such as BH, B-H2, B2-H1, B2-H2, B2-H3, B2-H4, and B2-H5.

[0131] The scope of the present disclosure is not limited by the above-described embodiments but by the appended claims and their equivalents.

Claims

1. A solar cell unit, comprising: A silicon substrate, which is an n-type silicon substrate; Passivation layer; seed layer; An interface energy level adjustment layer, which is a p-type hydrogenated doped silicon layer; as well as a first p-type conductive layer, The passivation layer, the seed layer, the interface energy level adjustment layer and the first p-type conductive layer are sequentially stacked in at least a portion of the first surface of the first side of the silicon substrate, and the passivation layer is closest to the silicon substrate. The interface energy level adjustment layer contains silicon, oxygen, carbon, hydrogen and boron. The bandgap width of the interface energy level adjustment layer is 1.9-2.3 eV, and the thickness of the interface energy level adjustment layer is 0.5-4 nm.

2. The solar cell unit according to claim 1, wherein: The thickness of the interface energy level adjustment layer is 0.7-1.8 nm.

3. The solar cell unit according to claim 1 or 2, wherein: The interface energy level adjustment layer is a hydrogenated amorphous silicon layer and is embedded with crystallized silicon. The crystallization rate of the interface energy level adjustment layer is in the range of 30-65%.

4. The solar cell unit according to any one of claims 1 to 3, wherein: The interface energy level adjustment layer includes Si-Si, Si-O, Si-C, Si-B, CC, CO, C=O, CB and BO chemical bonds.

5. The solar cell unit according to claim 4, wherein: The total molar content of carbon and oxygen in the interface energy level adjustment layer is 18-45%, and the concentration of active boron atoms in the interface energy level adjustment layer is 5×10 17 -5×10 19 atoms per cubic centimeter.

6. The solar cell unit according to claim 5, wherein: The molar content of carbon in the interface energy level adjustment layer is in the range of 8-16%, and the carbon exists by forming Si-C, CC, CO, C=O, CB and CH chemical bonds, The molar proportions of carbon elements present through Si-C, CC, CO, C=O, CB and CH chemical bonds to all carbon elements are 30-54%, 30-45%, 8-14%, 1-5%, 3-7% and 3-9% respectively.

7. The solar cell unit according to claim 5 or 6, wherein: The molar content of oxygen in the interface energy level adjustment layer is in the range of 18-32%, and the oxygen exists by forming Si-O, CO and BO chemical bonds, The molar proportions of oxygen elements present through Si-O, CO and BO chemical bonds to all oxygen elements are 78-92%, 6-15% and 4-11% respectively.

8. The solar cell unit according to any one of claims 5 to 7, wherein: The molar content of silicon in the interface energy level adjustment layer is in the range of 50-65%, and the silicon exists by forming Si-Si, Si-O, Si-C, Si-B and Si-H chemical bonds, The molar ratio of silicon elements existing through Si-Si, Si-B and Si-H chemical bonds is 40-60% of all silicon elements, the molar ratio of silicon elements existing through Si-O chemical bonds is 35-45% of all silicon elements, and the molar ratio of silicon elements existing through Si-C chemical bonds is 7-12% of all silicon elements.

9. The solar cell unit according to any one of claims 5 to 8, wherein: The molar content of boron in the interface energy level adjustment layer is in the range of 1-5%, Inactive boron atoms exist in the film in the form of BO, BC, BB and BH.

10. The solar cell unit according to any one of claims 5 to 9, wherein: In the interface energy level adjustment layer, in a direction away from the silicon substrate, the concentration of active boron atoms increases gradually, and the crystallization rate of the interface energy level adjustment layer increases gradually.

11. The solar cell unit according to any one of claims 1 to 10, wherein: The passivation layer is a hydrogenated amorphous silicon layer, and wherein, In the passivation layer, the concentration of hydrogen atoms decreases in a direction away from the silicon substrate.

12. The solar cell unit according to any one of claims 1 to 11, wherein: The first p-type conductive layer is a p-type microcrystalline silicon layer, The crystallinity of the first p-type conductive layer is in the range of 30-70%, In the first p-type conductive layer, the crystallization rate increases in a direction away from the silicon substrate.

13. The solar cell unit according to any one of claims 1 to 12, wherein: The passivation layer is a hydrogenated amorphous silicon layer, The first p-type conductive layer is a p-type microcrystalline silicon layer, The thickness of the passivation layer is in the range of 5-8 nm, The thickness of the seed layer is less than 1 nm, and The thickness of the first p-type conductive layer is in the range of 20-38 nm.

14. The solar cell unit according to any one of claims 1 to 13, further comprising: The second p-type conductive layer is disposed on the first p-type conductive layer and is further away from the silicon substrate than the first p-type conductive layer.

15. The solar cell unit according to claim 14, wherein: The second p-type conductive layer is a boron-doped amorphous silicon layer, The concentration of active boron atoms in the second p-type conductive layer is 2×10 18 -1×10 19 atoms per cubic centimeter, The thickness of the second p-type conductive layer is in the range of 0.5-3 nm.

16. The solar cell unit according to any one of claims 1 to 15, wherein: The first side is a backlight side of the solar cell unit.

17. The solar cell unit according to any one of claims 1 to 16, further comprising: a second passivation layer; as well as n-type conductive layer, The second passivation layer and the n-type conductive layer are sequentially stacked on a second surface of a second side of the silicon substrate, the second side is opposite to the first side, and the second passivation layer is closest to the silicon substrate.

18. The solar cell unit according to any one of claims 1 to 17, further comprising: a second passivation layer; as well as n-type conductive layer, The passivation layer, the seed layer, the interface energy level adjustment layer, the first p-type conductive layer and the second p-type conductive layer are sequentially stacked in a p region on the first surface of the first side of the silicon substrate. The second passivation layer and the n-type conductive layer are sequentially stacked in an n-region different from a p-region on the first surface of the silicon substrate.

19. A method for manufacturing a solar cell unit, for manufacturing the solar cell unit according to any one of claims 1 to 18, the method comprising: providing a silicon substrate; as well as A passivation layer, a seed layer, an interface energy level adjustment layer and a first p-type conductive layer are sequentially stacked on at least a portion of the first surface of the first side of the silicon substrate. The bandgap width of the interface energy level adjustment layer of the solar cell unit is 1.9-2.3 eV, and the thickness of the interface energy level adjustment layer is 0.5-4 nm.

20. The manufacturing method according to claim 19, wherein: Using the reaction gas, the pressure in the reaction chamber is 2.5-3.5Torr, and the RF power density is 260-340mW / cm 2 The interface energy level adjustment layer is formed under the conditions of The silicon element of the interface energy level adjustment layer comes from one or more of SiH4 and Si2H6. The boron element of the interface energy level adjustment layer comes from one or more of TMB, B2H6, and BF3. The hydrogen element of the interface energy level adjustment layer comes from one or more of H2, SiH4, B2H6, TMB, The oxygen element of the interface energy level adjustment layer is selected from one or more of N2O, O2, CO and CO2, and The carbon elements of the interface energy level adjustment layer come from: CO2, CO, CH4, C2H6, C3H 10 and one or more of C2H4.

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