Alignment method and apparatus for wafer bonding

Abstract

Provided in the present invention are an alignment method and apparatus for wafer bonding. A plurality of image collection apparatuses are located on the same side of a wafer to be bonded and have the same collection direction. The alignment method comprises: transferring a first wafer to a predetermined position of a first motion platform, and then fixing the first motion platform; making a plurality of image collection apparatuses perform focused imaging on the first wafer, and using a preset algorithm to determine position coordinates of the first wafer; transferring a second wafer to a predetermined position of a second motion platform, such that the first wafer and the second wafer face each other, wherein the position of the second motion platform is parallel to the position of the first motion platform; making the plurality of image collection apparatuses perform focused imaging on the second wafer, so as to determine position coordinates of the second wafer; adjusting the second motion platform on the basis of the position coordinates of the first wafer and the position coordinates of the second wafer, such that the position of the second wafer is aligned and coincides with the position of the first wafer in an axial direction of the wafers; and adjusting the second motion platform in the axial direction of the wafers, such that the two wafers approach each other for bonding.

Description

Wafer bonding alignment method and device Technical Field

[0001] The present invention relates to the field of semiconductors, and in particular to a wafer bonding alignment method and device. Background Art

[0002] Existing wafer bonding techniques typically require both wafers to be bonded to have alignment marks. While this bonding method offers high alignment accuracy, it is expensive and complex. Furthermore, this method inevitably requires additional die marking and preparation, hindering production capacity gains.

[0003] At the same time, in some wafer bonding application scenarios, such as bonding bare dies and wafers with circuits, the process production requirements of these scenarios are relatively low in terms of alignment accuracy between wafers, but require higher production capacity, so that the wafer bonding alignment methods in the existing technology cannot meet the usage requirements of these special application scenarios, and the bonding process capacity is limited.

[0004] In order to overcome the above-mentioned defects of the prior art, the art urgently needs a wafer bonding alignment method and device for realizing the alignment operation during wafer bonding through a predetermined algorithm, without the need to prepare additional alignment marks on the wafer, thereby simplifying the bonding process and improving the production efficiency of semiconductor product preparation.

[0005] Summary of the Invention

[0006] The following is a brief summary of one or more aspects to provide a basic understanding of these aspects. This summary is not an exhaustive overview of all conceivable aspects and is neither intended to identify key or critical elements of all aspects nor to define the scope of any or all aspects. Its sole purpose is to present some concepts of one or more aspects in a simplified form as a prelude to the more detailed description that will be provided later.

[0007] In order to overcome the above-mentioned defects in the prior art, the present invention provides an alignment method for wafer bonding, wherein multiple image acquisition devices are located on the same side of the wafers to be bonded and have the same acquisition direction, and the alignment method includes: after transferring a first wafer to a predetermined position of a first motion platform, fixing the first motion platform; causing the multiple image acquisition devices to focus and image the first wafer, and using a preset algorithm to determine the position coordinates of the first wafer; transferring a second wafer to a predetermined position of a second motion platform so that the first wafer and the second wafer are oriented oppositely, wherein the second motion platform is parallel to the position of the first motion platform; causing the multiple image acquisition devices to focus and image the second wafer, and using the preset algorithm to determine the position coordinates of the second wafer; based on the position coordinates of the first wafer and the second wafer, adjusting the second motion platform in a plane parallel to the wafers so that the positions of the second wafer and the first wafer are aligned and overlapped in the axial direction of the wafers; and adjusting the second motion platform along the axial direction of the wafer to bring the two wafers into close proximity for bonding.

[0008] In one embodiment, preferably, the position coordinates of the first wafer or the second wafer include the center position coordinates and the deflection angle of the wafer, and the preset algorithm includes: collecting the position coordinates of multiple edge points and preset grooves of the first wafer or the second wafer; and determining the center position coordinates and the deflection angle of the first wafer or the second wafer based on the multiple edge points and the position coordinates of the preset groove, respectively.

[0009] In one embodiment, preferably, the alignment method may further include: providing four image acquisition devices, wherein one image acquisition device is used to acquire the position coordinates of the preset cutting groove of the wafer, and the remaining three image acquisition devices are used to acquire the position coordinates of the edge point of the wafer.

[0010] In one embodiment, preferably, the second wafer is transferred to a predetermined position of the second motion platform so that the first wafer and the second wafer are oriented opposite to each other, and further includes: after the second wafer is transferred to the predetermined position of the second motion platform so that the two wafers are oriented opposite to each other, coarsely adjusting the second motion platform so that the distance between the first wafer and the second wafer does not exceed 500 μm.

[0011] In one embodiment, preferably, the axial direction of the wafer is a vertical direction, and the plane parallel to the wafer is a horizontal plane.

[0012] In one embodiment, preferably, transferring the second wafer to a predetermined position of the second motion platform so that the first wafer and the second wafer are oriented opposite to each other may include: transferring the second wafer to a predetermined position of the second motion platform so that the second wafer is located vertically above the first wafer and oriented opposite to the first wafer.

[0013] In one embodiment, preferably, the second motion platform is adjusted in a plane parallel to the wafer so that the positions of the second wafer and the first wafer are aligned and overlapped in the axial direction of the wafer, which may include: adjusting the second motion platform with a step movement accuracy of 50nm to ensure the alignment accuracy of the second wafer and the first wafer.

[0014] In one embodiment, preferably, the alignment method may further include: when the wafers to be bonded include more than two wafers, selecting single wafers one by one as the second wafer to sequentially perform alignment bonding between the multiple wafers.

[0015] Another aspect of the present invention further provides a wafer bonding alignment device, which may include: a memory; and a processor coupled to the memory, wherein the processor is configured to execute any of the wafer bonding alignment methods described above.

[0016] The present invention also provides a computer-readable medium having a computer program stored thereon, which, when executed by a processor, implements the wafer bonding alignment method as described in any one of the above items. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The above features and advantages of the present invention will be better understood after reading the detailed description of the embodiments of the present disclosure in conjunction with the following drawings. In the drawings, the components are not necessarily drawn to scale, and components with similar related properties or characteristics may have the same or similar reference numerals.

[0018] FIG1 is a schematic diagram of a method flow of a wafer bonding alignment method according to one aspect of the present invention;

[0019] 2A to 2F are schematic diagrams illustrating the operation steps of a wafer bonding alignment method according to an embodiment of the present invention;

[0020] FIG3 is a top view illustrating the arrangement of an image acquisition device in a wafer bonding alignment method according to an embodiment of the present invention; and

[0021] FIG. 4 is a schematic diagram illustrating the structure of an alignment device for wafer bonding according to another aspect of the present invention.

[0022] For the sake of clarity, a brief description of the reference numerals is given below: 201 Image acquisition device 202 First wafer 203 First motion platform 204 Second wafer 205 Second motion platform 301a, 301b, 301c, 301d Image acquisition device 302 Preset cutting groove DETAILED DESCRIPTION

[0023] The following specific embodiments illustrate the embodiments of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. Although the description of the present invention will be introduced in conjunction with the preferred embodiment, this does not mean that the features of this invention are limited to this embodiment. On the contrary, the purpose of introducing the invention in conjunction with the embodiment is to cover other options or modifications that may be extended based on the claims of the present invention. In order to provide a deep understanding of the present invention, the following description will include many specific details. The present invention can also be implemented without using these details. In addition, in order to avoid confusion or blurring the focus of the present invention, some specific details will be omitted in the description.

[0024] In the description of the present invention, it should be noted that, unless otherwise expressly specified or limited, the terms "mounted," "connected," and "connected" should be understood in a broad sense. For example, they may refer to fixed, detachable, or integral connections; mechanical or electrical connections; direct or indirect connections through an intermediate medium; and internal communication between two components. Those skilled in the art will understand the specific meanings of the above terms in the present invention based on the specific circumstances.

[0025] Furthermore, the terms "upper," "lower," "left," "right," "top," "bottom," "horizontal," and "vertical" used in the following description should be understood to refer to the orientations depicted in that section and the accompanying drawings. These relative terms are used solely for convenience of description and do not necessarily imply that the devices described herein must be manufactured or operated in a specific orientation. Therefore, they should not be construed as limiting the present invention.

[0026] It will be understood that although the terms "first," "second," "third," etc. may be used herein to describe various components, regions, layers, and / or portions, these components, regions, layers, and / or portions should not be limited by these terms, and these terms are merely used to distinguish different components, regions, layers, and / or portions. Thus, a first component, region, layer, and / or portion discussed below may be referred to as a second component, region, layer, and / or portion without departing from some embodiments of the present invention.

[0027] In order to overcome the above-mentioned defects of the prior art, the art urgently needs an alignment method and device for wafer bonding, which is used to collect the position coordinates of the wafer edge points and preset cutting grooves, so as to identify the center of the wafer and the deflection angle through a predetermined algorithm, and then realize the alignment operation during wafer bonding. There is no need to prepare additional alignment marks on the wafer, thereby simplifying the bonding process and improving the production efficiency of semiconductor product preparation.

[0028] FIG. 1 is a schematic flow chart of a wafer bonding alignment method according to one aspect of the present invention.

[0029] Referring to FIG. 1 , a wafer bonding alignment method 100 provided by the present invention may include:

[0030] Step 101: After transferring a first wafer to a predetermined position on a first motion platform, the first motion platform is fixed;

[0031] Step 102: enabling the plurality of image acquisition devices to focus and image the first wafer, and using a preset algorithm to determine the position coordinates of the first wafer;

[0032] Step 103: transferring the second wafer to a predetermined position of a second motion platform so that the first wafer and the second wafer face each other, wherein the second motion platform is parallel to the first motion platform;

[0033] Step 104: enabling the plurality of image acquisition devices to focus and image the second wafer, and using the preset algorithm to determine the position coordinates of the second wafer;

[0034] Step 105: Based on the position coordinates of the first wafer and the second wafer, adjust the second motion platform in a plane parallel to the wafers so that the positions of the second wafer and the first wafer are aligned and overlapped in the axial direction of the wafers; and

[0035] Step 106: Adjust the second motion platform along the axial direction of the wafer to bring the two wafers into close proximity for bonding.

[0036] 2A to 2F are schematic diagrams illustrating the operation steps of a wafer bonding alignment method according to an embodiment of the present invention, wherein the reference numerals for various components may refer to those in FIG. 2C .

[0037] The following describes steps 101 to 106 in detail with reference to FIG. 2A to FIG. 2F .

[0038] In the wafer bonding alignment method provided by the present invention, multiple image acquisition devices are located on the same side of the wafer to be bonded and have the same acquisition direction. As shown in Figures 2A to 2F, in this embodiment, multiple image acquisition devices 201 are all located above the wafer to be bonded, and the acquisition direction is from top to bottom. That is to say, the axial direction of the wafer is the vertical direction, and the plane parallel to the wafer is the horizontal plane. It should be noted that the bonding operation direction here is only for illustrative purposes and is not intended to limit the scope of protection of the present invention. Other similar schemes, such as placing the wafer vertically to perform bonding operations in the horizontal direction, can also be applied to the wafer bonding alignment method provided by the present invention, and should also be included in the scope of protection of the present invention.

[0039] In this embodiment, FIG. 2A may correspond to step 101 : after transferring the first wafer 202 to a predetermined position of the first motion platform 203 , the first motion platform 203 is fixed.

[0040] Next, FIG2B shows step 102 : enabling the plurality of image acquisition devices 201 to focus and image the first wafer 202 , and using a preset algorithm to determine the position coordinates of the first wafer 202 .

[0041] FIG2C corresponds to step 103: transferring the second wafer 204 to a predetermined position on the second motion platform 205 so that the first wafer 202 and the second wafer 204 face each other, wherein the second motion platform 205 is parallel to the first motion platform 203. More specifically, as shown in FIG2C , the second wafer 204 is transferred to a predetermined position on the second motion platform 205 so that the second wafer 204 is located vertically above the first wafer 202 and faces each other, in preparation for subsequent alignment and bonding operations.

[0042] It should be noted that the relative position relationship and fixed position sequence of the first wafer 202 and the second wafer 204 are only illustrative here, and are intended to illustrate the preferred implementation of the wafer bonding alignment method provided by the present invention, and are not intended to limit the scope of protection of the present invention. In fact, it can also be set specifically according to the specific equipment conditions and bonding process requirements. For example, the position of the upper wafer can be fixed first, and then the lower wafer can be moved for alignment and bonding. These similar variations can be applied to the wafer bonding alignment method of the present invention and should also be included in the scope of protection of the present invention.

[0043] In this embodiment, preferably, the second wafer is transferred to a predetermined position of the second motion platform so that the first wafer and the second wafer are oriented opposite to each other, and may also include: after the second wafer is transferred to the predetermined position of the second motion platform so that the two wafers are oriented opposite to each other, coarsely adjusting the second motion platform so that the distance between the first wafer and the second wafer does not exceed 500μm.

[0044] It can be understood that during the wafer bonding process, the lower wafer remains stationary and the upper wafer is pressed down. At this time, the upper wafer will inevitably undergo more or less displacement during the pressing process. The wafer bonding alignment method provided by the present invention first roughly adjusts the distance between the two wafers to be as small as possible, and then aligns them, thereby minimizing the amount of displacement that may occur during the final bonding process of the two wafers, thereby improving the accuracy of the alignment method of the present invention.

[0045] 2D may correspond to step 104 : enabling the multiple image acquisition devices 201 to focus and image the second wafer 204 , and using the preset algorithm to determine the position coordinates of the second wafer 204 .

[0046] 2E corresponds to step 105 : based on the position coordinates of the first wafer 202 and the second wafer 204 , the second motion platform 205 is adjusted in a plane parallel to the wafers so that the second wafer 204 and the first wafer 202 are aligned and overlapped in the axial direction of the wafers.

[0047] In one embodiment, preferably, adjusting the second motion platform within a plane parallel to the wafers so that the second wafer and the first wafer are aligned and overlapped in the axial direction of the wafers may include: adjusting the second motion platform with a stepping accuracy of 50 nm to ensure the alignment accuracy of the second wafer and the first wafer. The stepping accuracy reflects the control accuracy of the motion platform adjustment. That is, when the motion platform performs displacement adjustment according to the control instruction, on the one hand, it moves a predetermined distance based on the calculation result to achieve alignment, and on the other hand, it can also control the accuracy of the actual movement distance compared to the predetermined distance with a displacement accuracy of the order of 50 nm.

[0048] Finally, FIG. 2F corresponds to step 106 : adjusting the second motion platform 205 along the axial direction of the wafer to bring the two wafers close to each other for bonding, that is, moving the second motion platform 205 downward, thereby completing the entire alignment and bonding process.

[0049] In one embodiment, when the wafers to be bonded include more than two wafers, single wafers may be selected one by one as the second wafer, and the alignment and bonding between the multiple wafers may be performed sequentially using the above steps.

[0050] FIG3 is a top view illustrating the arrangement of an image acquisition device in a wafer bonding alignment method according to an embodiment of the present invention.

[0051] Please refer to Figure 3. In a preferred embodiment, the wafer bonding alignment method provided by the present invention may be provided with four image acquisition devices 301a, 301b, 301c, and 301d, wherein one image acquisition device 301d is used to acquire the position coordinates of the preset cutting groove 302 of the wafer, and the remaining three image acquisition devices 301a, 301b, and 301c are used to acquire the position coordinates of the edge point of the wafer.

[0052] In actual operation, three cameras can be used to detect the edge of the wafer to obtain the center coordinates of the wafer, and then the fourth camera can be used to image the preset groove to determine the deflection angle of the wafer.

[0053] At the same time, in one embodiment, the position coordinates of the first wafer or the second wafer include the center position coordinates and the deflection angle of the wafer, and the preset algorithm may include: collecting the position coordinates of multiple edge points and preset grooves of the first wafer or the second wafer; and determining the center position coordinates and the deflection angle of the first wafer or the second wafer based on the position coordinates of the multiple edge points and the preset groove, respectively.

[0054] Those skilled in the art will understand that before a silicon ingot is cut into wafers, a notch is typically ground into its cylindrical surface. This notch is a necessary step in the wafer manufacturing process. When the ingot is cut into wafer slices, the notch becomes the pre-set groove on each wafer. The wafer bonding alignment method provided by the present invention utilizes the inherent notch in the wafer preparation process as a basis for identifying the deflection angle, eliminating the need for additional positioning marks on the wafer and improving production efficiency.

[0055] For example, in combination with Figures 2A to 2F and steps 101 to 106, in step 102, the center coordinates (x1, y1) and the deflection angle θ1 of the first wafer 202 are first determined, and then in step 104, the center coordinates (x2, y2) and the deflection angle θ2 of the second wafer 204 are first determined. Then, in step 105, the center coordinates (x2, y2) and the deflection angle θ2 of the second wafer 204 are adjusted to the positions indicated by the center coordinates (x1, y1) and the deflection angle θ1, thereby completing the alignment of the second wafer 204 with the first wafer 202.

[0056] Using this alignment algorithm, the wafer bonding alignment method provided by the present invention can achieve micron-level alignment accuracy without requiring additional wafer markings, enabling efficient and rapid completion of bond alignment detection. Compared to existing techniques that transfer bonded wafers to a separate detection module for wafer bonding testing, the alignment method provided by the present invention integrates position detection within the bonding operation, minimizing wafer movement and significantly reducing position detection and alignment time, thereby improving production capacity.

[0057] It should be noted that in this embodiment, the wafer position determination algorithm that uses wafer edge detection to determine the center of the circle and groove detection to determine the deflection angle is only illustrative, and is intended to illustrate the preferred implementation method of the wafer bonding alignment method provided by the present invention, rather than to limit the scope of protection of the present invention. In fact, other similar algorithms that can determine the wafer position can also be applied to the alignment method provided by the present invention, and should also be included in the scope of protection of the present invention.

[0058] Although the above methods are illustrated and described as a series of acts for simplicity of explanation, it is to be understood and appreciated that these methods are not limited by the order of the acts, as some acts may occur in a different order and / or concurrently with other acts from those illustrated and described herein or not illustrated and described herein but understandable to those skilled in the art according to one or more embodiments.

[0059] FIG. 4 is a schematic diagram illustrating the structure of an alignment device for wafer bonding according to another aspect of the present invention.

[0060] According to another aspect of the present invention, an embodiment of an alignment device 400 for wafer bonding is also provided.

[0061] As shown in Fig. 4, the wafer bonding alignment device 400 provided in this embodiment may include a memory 401 and a processor 402 coupled to the memory 401. The processor 402 may be configured to implement any of the wafer bonding alignment methods described above.

[0062] According to another aspect of the present invention, an embodiment of a computer storage medium is also provided herein.

[0063] The computer storage medium stores a computer program, which, when executed by a processor, can implement the steps of any one of the above-mentioned wafer bonding alignment methods.

[0064] Those skilled in the art will further appreciate that the various illustrative logic blocks, modules, circuits, and algorithmic steps described in conjunction with the embodiments disclosed herein can be implemented as electronic hardware, computer software, or a combination of the two. To clearly illustrate this interchangeability of hardware and software, various illustrative components, blocks, modules, circuits, and steps are generally described above in terms of their functionality. Whether such functionality is implemented as hardware or software depends on the specific application and the design constraints imposed on the overall system. A skilled person may implement the described functionality in different ways for each specific application, but such implementation decisions should not be interpreted as resulting in a departure from the scope of the present invention.

[0065] The processor described in this case can be implemented using electronic hardware, computer software or any combination thereof. Whether such processors are implemented as hardware or software will depend on the specific application and the overall design constraints imposed on the system. As an example, the processor presented in this disclosure, any part of the processor, or any combination of processors can be implemented with a microprocessor, a microcontroller, a digital signal processor (DSP), a field programmable gate array (FPGA), a programmable logic device (PLD), a state machine, a gating logic, a discrete hardware circuit, and other suitable processing components configured to perform the various functions described throughout this disclosure. The functionality of the processor presented in this disclosure, any part of the processor, or any combination of processors can be implemented with software executed by a microprocessor, a microcontroller, a DSP or other suitable platform.

[0066] The steps of the methods or algorithms described in conjunction with the embodiments disclosed herein may be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. The software module may reside in RAM memory, flash memory, ROM memory, EPROM memory, EEPROM memory, registers, a hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art. An exemplary storage medium is coupled to the processor so that the processor can read and write information from / to the storage medium. In an alternative, the storage medium may be integrated into the processor. The processor and storage medium may reside in an ASIC. The ASIC may reside in a user terminal. In an alternative, the processor and storage medium may reside in a user terminal as discrete components.

[0067] The previous description of the disclosure is provided to enable any person skilled in the art to make or use the disclosure. Various modifications to the disclosure will be apparent to those skilled in the art, and the general principles defined herein may be applied to other variations without departing from the spirit or scope of the disclosure. Thus, the disclosure is not intended to be limited to the examples and designs described herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A wafer bonding alignment method, wherein: The plurality of image acquisition devices are located on the same side of the wafer to be bonded and have the same acquisition direction, and the alignment method comprises: After transferring the first wafer to a predetermined position of the first motion platform, fixing the first motion platform; Enable the multiple image acquisition devices to focus and image the first wafer, and use a preset algorithm to determine the position coordinates of the first wafer; Transferring the second wafer to a predetermined position of a second motion platform so that the first wafer and the second wafer face each other, wherein the second motion platform is parallel to the first motion platform; Enable the multiple image acquisition devices to focus and image the second wafer, and use the preset algorithm to determine the position coordinates of the second wafer; Based on the position coordinates of the first wafer and the second wafer, adjusting the second motion platform in a plane parallel to the wafers so that the positions of the second wafer and the first wafer are aligned and overlapped in the axial direction of the wafers; and The second motion platform is adjusted along the axial direction of the wafer to bring two wafers close to each other for bonding.

2. The alignment method according to claim 1, characterized in that: The position coordinates of the first wafer or the second wafer include the center position coordinates and the deflection angle of the wafer, and the preset algorithm includes: Collecting the position coordinates of a plurality of edge points and a preset groove of the first wafer or the second wafer; and The center position coordinates and the deflection angle of the first wafer or the second wafer are determined based on the plurality of edge points and the position coordinates of the preset grooves.

3. The alignment method according to claim 2, characterized in that: Also includes: Four image acquisition devices are provided, wherein one image acquisition device is used to acquire the position coordinates of the preset cutting groove of the wafer, and the remaining three image acquisition devices are used to acquire the position coordinates of the edge points of the wafer.

4. The alignment method according to claim 1, characterized in that: The transferring of the second wafer to a predetermined position of the second motion platform so that the first wafer and the second wafer face each other also includes: After the second wafer is transferred to a predetermined position of the second motion platform so that the two wafers face each other, the second motion platform is roughly adjusted so that the distance between the first wafer and the second wafer does not exceed 500 μm.

5. The alignment method according to claim 1, characterized in that: The axial direction of the wafer is a vertical direction, and the plane parallel to the wafer is a horizontal plane.

6. The alignment method according to claim 5, characterized in that: The step of transferring the second wafer to a predetermined position of the second motion platform so that the first wafer and the second wafer face each other includes: The second wafer is transferred to a predetermined position of the second motion platform so that the second wafer is located vertically above the first wafer and faces opposite to the first wafer.

7. The alignment method according to claim 1, characterized in that: The step of adjusting the second motion platform in a plane parallel to the wafer so that the positions of the second wafer and the first wafer are aligned and overlapped in the axial direction of the wafer comprises: The second motion platform is adjusted with a stepping movement accuracy of 50 nm to ensure the alignment accuracy of the second wafer with the first wafer.

8. The alignment method according to claim 1, characterized in that: Also includes: When the wafers to be bonded include more than two wafers, single wafers are selected one by one as the second wafer to sequentially perform alignment bonding between the multiple wafers.

9. A wafer bonding alignment device, comprising: Memory; as well as A processor coupled to the memory, wherein the processor is configured to execute the wafer bonding alignment method according to any one of claims 1 to 8.

10. A computer readable medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the wafer bonding alignment method according to any one of claims 1 to 8 is implemented.

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