Memory structure and manufacturing method therefor

Abstract

A memory structure and a manufacturing method therefor. The memory structure comprises: a substrate (10), which has a first surface and a second surface that are opposite to each other, wherein the substrate (10) comprises an array region and a logic region adjacent to the array region, there are a plurality of first conductive paths (20) penetrating from the first surface to the second surface in the array region, there is a second conductive path (30) penetrating from the first surface to the second surface in the logic region, and each first conductive path (20) is the same height as the second conductive path (30); a plurality of memory units (40), which are located on the first surface, wherein each memory unit (40) covers one first conductive path (20), and the plurality of memory units (40) correspond to the plurality of first conductive paths (20) on a one-to-one basis; at least one top electrode layer (50), which is located on the surface of the side of the plurality of memory units (40) that is away from the substrate (10); and a top metal wire layer (60), which is located on the side, on which there is the top electrode layer (50), of the substrate (10), wherein the top metal wire layer (60) is electrically connected to the at least one top electrode layer (50). By means of the present application, the manufacturing cost of the memory structure is reduced.

Description

Memory structure and manufacturing method thereof Technical Field

[0001] The present disclosure relates to the field of semiconductor memory technology, and in particular to a memory structure and a method for manufacturing the memory structure. Background Art

[0002] The MTJ of an MRAM memory cell is usually composed of three basic units: a ferromagnetic layer, an insulating tunneling layer, and a fixed layer. When the magnetic moments of the ferromagnetic layer and the fixed layer are in opposite directions, the memory device exhibits a high-resistance state Rap. When the magnetic moments of the two layers are in the same direction, it exhibits a low-resistance state Rp, which is used to store information "1" and "0". As a new type of memory, MRAM has huge advantages over traditional Flash storage in terms of read and write speed and device reliability.

[0003] However, when manufacturing memories in the industry today, a common integration solution is generally to first prepare bottom vias and memory cells in the memory array area, then prepare bottom vias in the non-memory array area, and then prepare a top metal layer common to both the memory area and the non-memory area, and electrically connect the top metal layer to multiple memory cells through the top vias. Therefore, the bottom vias in the memory array area, the bottom vias in the non-memory area, and the top vias on the memory cells need to be formed in multiple photolithography steps. Furthermore, since a mask is required for each photolithography process, a large number of mask layers are required, increasing manufacturing costs.

[0004] Summary of the Invention

[0005] The main purpose of the present disclosure is to provide a memory structure and a method for manufacturing the memory structure, so as to solve the problems of complex manufacturing process and high cost in the prior art.

[0006] To achieve the above-mentioned objectives, according to one aspect of the present disclosure, a memory structure is provided, comprising: a substrate having a first surface and a second surface relative to each other, and the substrate including an array area and a logic area adjacent to the array area, the array area having a plurality of first conductive paths extending from the first surface to the second surface, the logic area having a second conductive path extending from the first surface to the second surface, the first conductive path and the second conductive path having the same height; a plurality of memory cells located on the first surface, and each memory cell covering a first conductive path, the plurality of memory cells corresponding one-to-one to the plurality of first conductive paths; at least one top electrode layer located on a surface of the plurality of memory cells away from the substrate; and a top metal wiring layer located on a side of the substrate having the top electrode layer, and configured to electrically connect the top metal wiring layer to the at least one top electrode layer.

[0007] Furthermore, each memory cell has a first projection on the substrate, and at least one top electrode layer has a second projection on the substrate, wherein the first projection is located within the second projection.

[0008] Furthermore, the top electrode layer includes multiple top electrode layers, and the multiple top electrode layers correspond one-to-one to the multiple memory cells. The surface of the memory cell away from the first conductive path is the third surface. Each top electrode layer covers the third surface, and the top metal wiring layer electrically connects the multiple top electrode layers.

[0009] Furthermore, the memory structure further includes: a protection layer, wherein the protection layer at least covers the sidewalls of the memory unit.

[0010] Furthermore, the top metal wiring layer is also electrically connected to the second conductive path.

[0011] Furthermore, the memory cell includes one or more of a magnetic random access memory cell, a phase change random access memory cell, a resistive random access memory cell and a ferroelectric random access memory cell.

[0012] Furthermore, in the case where the memory cell is a magnetic random access memory cell, the at least one top electrode layer includes at least one layer.

[0013] Furthermore, the at least one top electrode layer includes multiple layers, and a material of at least one layer of the at least one top electrode layer is a ferromagnetic material.

[0014] To achieve the above-mentioned purpose, according to another aspect of the present disclosure, a method for manufacturing a memory structure is provided, comprising: providing a substrate having a first surface and a second surface relative to each other, and the substrate including an array area and a logic area adjacent to the array area, forming a plurality of first conductive paths and a second conductive path in the substrate using a single photolithography process, wherein the plurality of first conductive paths extend from the first surface corresponding to the array area to the second surface, and the second conductive paths extend from the first surface corresponding to the logic area to the second surface, and the first conductive paths and the second conductive paths have the same height in the extension direction; forming a plurality of memory cells on the first surface so that each memory cell covers a first conductive path, and the plurality of memory cells correspond one-to-one to the plurality of first conductive paths; forming at least one top electrode layer on a surface of the plurality of memory cells away from the substrate; and forming a top metal wiring layer on a side of the substrate having the top electrode layer so that the top metal wiring layer is electrically connected to the at least one top electrode layer.

[0015] Furthermore, the step of forming a top electrode layer includes: after the step of forming the memory cell, depositing a first insulating material and a second insulating material in sequence on a side of the substrate having the memory cell, so that the first insulating material covers the memory cell and the first surface, and the second insulating material covers the first insulating material; using chemical mechanical polishing to remove part of the first insulating material and part of the second insulating material to form a fourth surface exposing multiple memory cells; and forming a top electrode layer on the fourth surface.

[0016] By applying the technical solution disclosed in the present invention, a memory structure is provided, which includes a substrate, a plurality of memory cells, at least one top electrode layer and a top metal wiring layer. The substrate includes a plurality of first conductive paths located in an array area and a second conductive path located in a logic area. The plurality of memory cells are located on the plurality of first conductive paths to achieve electrical connection between each memory cell and each first conductive path. The at least one top electrode layer is located on a surface of the plurality of memory cells away from the substrate to achieve electrical connection between the top electrode layer and each memory cell. The top metal wiring layer is located on a side of the top electrode layer away from the substrate, and the top metal wiring layer is electrically connected to the at least one top electrode layer. Since the heights of the plurality of first conductive paths and the second conductive paths in the substrate of the memory structure provided by the present solution are consistent, the plurality of first conductive paths and the second conductive paths can be formed at one time using the same photolithography process, thereby reducing the number of masks when forming the first conductive paths and the second conductive paths. Subsequently, a plurality of memory cells and at least one top electrode layer covering the plurality of first conductive paths are formed on the first surface. After a top electrode layer, since the first conductive path serves as the bottom conductive path in the memory structure and the second conductive path serves as the top conductive path of the memory, when the heights of the first conductive path and the second conductive path are consistent, the heights of the multiple memory cells in the array area are higher than the height of the second conductive path. Therefore, a top metal wiring layer electrically connected to at least one top electrode layer can be directly formed on the side of the substrate having the top electrode layer, so that the top metal wiring layer can be electrically connected to the multiple memory cells. Compared with the prior art in which the total height of the bottom conductive path and the memory cells corresponding to the array area is lower than the top conductive path of the logic area, and a top conductive path needs to be formed again on the side of the memory cell away from the bottom conductive path so that the total height of the bottom conductive path and the memory cells corresponding to the array area is equal to the top conductive path of the logic area, the present application does not need to form an additional conductive path electrically connecting the multiple memory cells and the top metal wiring layer on the side of the memory cell away from the first conductive path, thereby further simplifying the process, reducing the number of photolithography steps, reducing the number of mask layers, and thus reducing the manufacturing cost of the memory structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The accompanying drawings, which constitute part of the present disclosure, are intended to provide a further understanding of the present disclosure. The exemplary embodiments of the present disclosure and their descriptions are intended to explain the present disclosure and do not constitute an improper limitation of the present disclosure. In the accompanying drawings:

[0018] FIG1 shows a schematic cross-sectional view of a memory structure according to an embodiment of the present disclosure;

[0019] FIG2 shows a schematic cross-sectional structure diagram of a substrate provided in a method for manufacturing a memory structure according to an embodiment of the present disclosure;

[0020] FIG3 is a schematic diagram showing a cross-sectional structure of a memory cell thin film deposited on the substrate shown in FIG2 ;

[0021] FIG4 is a schematic diagram showing a cross-sectional structure of a memory cell formed by etching the memory cell thin film shown in FIG3 ;

[0022] FIG5 is a schematic cross-sectional view showing a planarized surface formed after planarizing the upper surface of the memory cell shown in FIG4 ;

[0023] FIG6 is a schematic cross-sectional view showing a top electrode layer formed on the planarized surface shown in FIG5 ;

[0024] FIG7 is a schematic cross-sectional view showing a second insulating material deposited on a side of the top electrode layer shown in FIG6 away from the substrate;

[0025] FIG8 is a schematic cross-sectional view showing a structure in which a plurality of top electrode layers are formed on the planarized surface shown in FIG5 ;

[0026] FIG9 is a schematic cross-sectional view of the structure after a second insulating material is deposited on a side of the plurality of top electrode layers shown in FIG8 away from the substrate;

[0027] FIG10 is a schematic cross-sectional view showing a top metal wiring layer formed after removing part of the material in the structure shown in FIG9 ;

[0028] FIG11 shows a schematic cross-sectional view of depositing a second insulating material on the structure shown in FIG4 to form a fourth planarized surface;

[0029] FIG12 shows a schematic cross-sectional structure diagram after etching the fourth planarized surface shown in FIG11 and depositing a top electrode material;

[0030] FIG13 is a schematic cross-sectional view of the structure shown in FIG12 after etching to form a top electrode layer and depositing the second insulating material;

[0031] FIG14 is a schematic diagram showing a cross-sectional structure of a top metal wiring layer formed after removing part of the material in the structure shown in FIG13 .

[0032] Among them, the above-mentioned drawings include the following figure marks: 10, substrate; 20, first conductive path; 30, second conductive path; 40, memory cell; 401, lower electrode layer; 402, storage layer; 403, upper electrode layer; 50, top electrode layer; 60, top metal wiring layer; 70, protective layer; 80, insulating dielectric layer; 90, first metal wiring layer; 100, second metal wiring layer; 110, memory cell film; 111, lower electrode material layer; 112, storage material layer; 113, upper electrode material layer; 120, first insulating material; 130, second insulating material; 140, top electrode material; 150, etch stop layer. DETAILED DESCRIPTION

[0033] It should be noted that, in the absence of conflict, the embodiments and features of the embodiments in the present disclosure may be combined with each other. The present disclosure will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0034] In order to enable those skilled in the art to better understand the solutions of the present disclosure, the technical solutions in the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings in the embodiments of the present disclosure. Obviously, the embodiments described are only part of the embodiments of the present disclosure, not all of the embodiments. Based on the embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without making creative efforts should fall within the scope of protection of the present disclosure.

[0035] It should be noted that the terms "first," "second," and the like in the specification and claims of the present disclosure and the accompanying drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or precedence. It should be understood that the terms used in this manner are interchangeable where appropriate for the embodiments of the present disclosure described herein. In addition, the terms "including" and "having," and any variations thereof, are intended to cover non-exclusive inclusions. For example, a process, method, system, product, or apparatus comprising a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units that are not explicitly listed or inherent to these processes, methods, products, or apparatus.

[0036] As mentioned in the background art, when the industry manufactures memory, the general integration solution is generally to first prepare the bottom vias and memory cells in the memory array area, then prepare the bottom vias in the non-memory array area, and then prepare a top metal layer common to the memory area and the non-memory area, and make the top metal layer electrically connected to multiple memory cells through the top vias. Therefore, the bottom vias in the memory array area and the bottom vias in the non-memory area and the top vias on the memory cells need to be formed in multiple photolithography steps. Since a mask is required for each photolithography process, the number of mask layers is large, which increases the manufacturing cost. In order to solve the above technical problems, the inventors of this application provide a memory structure and a method for manufacturing a memory structure.

[0037] In some optional embodiments, a memory structure is provided, as shown in FIG1 , wherein the memory structure includes a substrate 10 having a first surface and a second surface opposite to each other, a plurality of memory cells 40 located on the first surface, at least one top electrode layer 50 located on the plurality of memory cells 40, and a top metal wiring layer 60 located on a side of the top electrode layer 50 away from the substrate 10. Specifically, the substrate 10 includes an array region and a logic region adjacent to the array region, the array region having a plurality of first conductive paths 20 extending from the first surface to the second surface, and the logic region having a second conductive path 30 extending from the first surface to the second surface. The first conductive path 20 and the second conductive path 30 have the same height; each of the plurality of memory cells 40 covers a different first conductive path 20, i.e., the number of the plurality of memory cells 40 can be the same as the number of the plurality of first conductive paths 20 in the substrate 10, and the plurality of memory cells 40 and the plurality of first conductive paths 20 correspond one to one; the at least one top electrode layer 50 is located on the surface of the plurality of memory cells 40 away from the substrate 10; the top metal wiring layer 60 is located on the side of the substrate 10 having the top electrode layer 50, and the top metal wiring layer 60 is electrically connected to the at least one top electrode layer 50. Optionally, the substrate 10 further comprises a first metal wiring layer 90 and a second metal wiring layer 100, wherein the first metal wiring layer 90 is disposed in contact with the side of the first conductive path 20 away from the memory cell 40, and the second metal wiring layer 100 is disposed in contact with the side of the second conductive path 30 away from the memory cell 40.

[0038] Specifically, the substrate 10 may include, but is not limited to, a silicon substrate, an epitaxial silicon substrate, a silicon germanium substrate, a silicon carbide substrate, and a silicon-on-insulator substrate, and those skilled in the art may make reasonable choices based on actual needs. The plurality of first conductive paths 20 and second conductive paths 30 may all be conductive paths formed of metal materials. Optionally, the metal materials in the first conductive paths 20 and second conductive paths 30 may include, but are not limited to, one metal or a combination of multiple metals selected from W, Cu, TaN, and TiN. Furthermore, any two adjacent first conductive paths 20 are spaced apart. Optionally, any first conductive path 20 and second conductive path 30 are spaced apart. It should be noted that the plurality of first conductive paths 20 and second conductive paths 30 in the substrate 10 are formed by etching and filling in a single photolithography process, and all extend from the first surface of the substrate 10 to the second surface. Therefore, the first conductive paths 20 and second conductive paths 30 have the same height in a direction perpendicular to the first surface.

[0039] Specifically, as shown in Figure 1, each memory cell 40 in the above-mentioned multiple memory cells 40 may include a lower electrode layer 401, a storage layer 402 and an upper electrode layer 403 stacked in sequence, and the above-mentioned lower electrode layer 401 is located between the storage layer 402 and the first surface of the substrate 10. Furthermore, the lower electrode layer 401 in each memory cell 40 covers a first conductive path 20, and any two adjacent lower electrode layers 401 in the multiple memory cells 40 are spaced apart, so that the multiple lower electrodes in the multiple memory cells 40 correspond one-to-one to the multiple first conductive paths 20, and the lower electrode layer 401, storage layer 402 and upper electrode layer 403 of each memory cell 40 in the multiple memory cells 40 correspond one-to-one, so that the multiple memory cells 40 correspond one-to-one to the multiple first conductive paths 20.

[0040] Specifically, the above-mentioned top electrode layer 50 may include one or more, and in the case where there is only one top electrode layer 50, the top electrode layer 50 is located on the side of the multiple memory cells 40 away from the substrate 10, and the surface of the multiple memory cells 40 away from the substrate 10 (i.e., the third surface) is completely covered by the above-mentioned top electrode layer 50, so that the multiple memory cells 40 share the above-mentioned top electrode layer 50; in the case where there are multiple top electrode layers 50, the surface of each memory cell 40 away from the substrate 10 is the third surface, and the multiple top electrode layers 50 correspond one-to-one to the multiple memory cells 40, that is, a top electrode layer 50 is provided on each of the above-mentioned third surfaces, so that any two adjacent top electrode layers 50 are arranged at intervals. Optionally, the top metal wiring layer 60 electrically connects the multiple top electrode layers 50.

[0041] Specifically, as shown in FIG1 , the top metal wiring layer 60 is used to electrically connect the plurality of memory cells 40 and interconnect the plurality of memory cells 40. In the case where the plurality of memory cells 40 have a top electrode layer 50 on the side away from the substrate 10, since the plurality of memory cells 40 are electrically connected via the top electrode layer 50, the top metal wiring layer 60 is disposed on the surface of the top electrode layer 50 on the side away from the substrate 10, thereby interconnecting the top metal wiring layer 60 and the plurality of memory cells 40. In the case where the plurality of memory cells 40 have multiple top electrode layers 50 on the side away from the substrate 10, and any two adjacent top electrode layers 50 are spaced apart, in order to form an interconnection structure between any two adjacent memory cells 40, the top metal wiring layer 60 is disposed on the surface of the multiple top electrode layers 50 on the side away from the substrate 10, and the top metal wiring layer 60 is electrically connected to the multiple top electrode layers 50.

[0042] Optionally, the materials of the upper and lower electrodes may include, but are not limited to, one or more metal materials such as Ti, TiN, Ta, TaN, and W, and the material of the top metal wiring layer 60 may include, but is not limited to, copper. Those skilled in the art can flexibly select the materials of the upper and lower electrodes according to actual needs.

[0043] In the above embodiment, since the heights of the multiple first conductive paths and the second conductive paths in the substrate of the memory structure provided by this solution are consistent, the multiple first conductive paths and the second conductive paths can be formed at one time using the same photolithography process, thereby reducing the number of masks when forming the first conductive paths and the second conductive paths. Subsequently, after multiple memory cells and at least one top electrode layer covering the multiple first conductive paths are formed on the above first surface, since the first conductive path serves as the bottom conductive path in the memory structure and the second conductive path serves as the top conductive path of the memory, when the heights of the first conductive path and the second conductive path are consistent, the heights of the multiple memory cells in the array area are higher than the height of the second conductive path. Therefore, it is possible to directly form the memory cells on the substrate having a plurality of first conductive paths. A top metal wiring layer electrically connected to at least one top electrode layer is formed on one side of the top electrode layer, so that the top metal wiring layer can be electrically connected to multiple memory cells. Compared with the prior art in which the total height of the bottom conductive path and the memory cell corresponding to the array area is lower than the top conductive path of the logic area, and it is necessary to form a top conductive path again on the side of the memory cell away from the bottom conductive path so that the total height of the bottom conductive path and the memory cell corresponding to the array area is equal to the top conductive path of the logic area, the present application does not need to form an additional conductive path electrically connecting multiple memory cells and the top metal wiring layer on the side of the memory cell away from the first conductive path, thereby further simplifying the process, reducing the number of photolithography steps, reducing the number of mask layers, and thereby reducing the manufacturing cost of the memory structure.

[0044] In some optional embodiments, each of the memory cells 40 has a first projection on the substrate 10 , and at least one of the top electrode layers 50 has a second projection on the substrate 10 , and the first projection is located within the second projection.

[0045] In the above embodiment, since the first projection of the memory cell 40 on the substrate 10 is located within the second projection of the top electrode layer 50 on the substrate 10, the size of the at least one top electrode layer 50 is larger than the size of the memory cell 40. Thus, during the back-end process steps of manufacturing the memory structure, the at least one top electrode layer 50 can protect the memory cell 40. Optionally, the memory cell 40 can be prevented from being over-etched.

[0046] Specifically, in the case where there is one top electrode layer 50, the projection of the top electrode layer 50 on the substrate 10 is the second projection, and the projections of the above-mentioned multiple memory cells 40 on the substrate 10 correspond to multiple first projections, so that the multiple first projections are all located in the above-mentioned second projection; specifically, in the case where there are multiple top electrode layers 50, the projection of each top electrode layer 50 in the multiple top electrode layers 50 on the substrate 10 is the second projection, and the projection of each memory cell 40 in the multiple memory cells 40 on the substrate 10 is the first projection, the multiple first projections correspond one-to-one to the multiple second projections, and each first projection is located in each corresponding second projection.

[0047] Since the top electrode layer 50 is located on the surface of the multiple memory cells 40 away from the above-mentioned substrate 10, the top electrode layer 50 is electrically connected to the memory cells 40. However, in the case where the top electrode layer 50 includes multiple top electrode layers, since any two adjacent top electrode layers 50 are electrically isolated, any two adjacent memory cells 40 are electrically isolated. In some optional embodiments, in order to form an electrical connection relationship between any two adjacent memory cells 40 when the top electrode layer 50 includes multiple top electrode layers, each of the above-mentioned top electrode layers 50 covers the surface of one of the above-mentioned memory cells 40 away from the above-mentioned first conductive path 20, and the above-mentioned top metal wiring layer 60 is electrically connected to the multiple above-mentioned top electrode layers 50, and the multiple above-mentioned top electrode layers 50 correspond one-to-one to the multiple above-mentioned memory cells 40.

[0048] In some optional embodiments, as shown in FIG1 , the memory structure further includes a protective layer 70, the protective layer 70 covering at least the sidewalls of the memory cells 40. Furthermore, the first surface corresponding to the array region includes an exposed surface other than that covered by the plurality of memory cells 40, and the protective layer 70 also covers the exposed surface. Furthermore, when the protective layer 70 also covers the exposed surface, the memory structure further includes an insulating dielectric layer 80. When there is only one top electrode layer 50, the insulating dielectric layer 80 is located between the protective layer 70 covering the exposed surface and the top electrode layer 50. When there are multiple top electrode layers 50, the insulating dielectric layer 80 is also located between the top metal wiring layer 60 and the protective layer 70.

[0049] In the above embodiment, in order to prevent water, oxygen, etc. from damaging the memory cells 40 in the memory structure, the protective layer 70 is provided around the four sides of the memory cells 40. Furthermore, in order to act as an etch stop layer in the memory structure, the protective layer 70 is located on a portion of the first surface of the substrate 10 corresponding to the array region (i.e., the exposed surface other than that covered by the plurality of memory cells 40). Optionally, the material of the protective layer 70 may include, but is not limited to, silicon nitride and aluminum oxide. Furthermore, the material of the insulating dielectric layer 80 may include, but is not limited to, any one or more of silicon dioxide, carbon oxide, fluorosilicate glass, phosphosilicate glass, borophosphosilicate glass, tetraethyl orthosilicate, Low-K dielectric, and Ultra-Low-K dielectric. It should be noted that there is a high etching selectivity between the protective layer 70 and the insulating dielectric layer 80.

[0050] Furthermore, in order to flatten the surface of the memory cell 40 away from the substrate 10, an insulating dielectric layer 80 is also provided on the side of the protective layer 70 away from the substrate 10, wherein the projection of the above-mentioned top electrode layer 50 on the substrate 10 and the projection of the insulating dielectric layer 80 on the substrate 10 at least partially overlap.

[0051] The multiple first conductive paths 20 in the array area of ​​the above-mentioned memory structure are electrically connected to the multiple memory cells 40, the above-mentioned multiple memory cells 40 are electrically connected to one or more top electrode layers 50, and the one or more top electrode layers 50 are electrically connected to the top metal wiring layer 60. Furthermore, in order to form an electrical connection between the array area and the logic area of ​​the memory structure, in some optional embodiments, the above-mentioned top metal wiring layer 60 is also electrically connected to the above-mentioned second conductive path 30.

[0052] Since the memory structure may include a magnetic random access memory structure, a phase change random access memory structure, a resistive random access memory structure and a ferroelectric random access memory structure, in some optional embodiments, the above-mentioned memory unit 40 includes one or more of a magnetic random access memory unit 40, a phase change random access memory unit 40, a resistive random access memory unit 40 and a ferroelectric random access memory unit 40.

[0053] In some optional embodiments, when the memory cell 40 is a magnetic random access memory cell 40, the at least one top electrode layer 50 includes at least one layer. Further, the at least one top electrode layer 50 includes multiple layers, and the material of at least one layer of the at least one top electrode layer 50 is a ferromagnetic material.

[0054] Optionally, the material of the at least one top electrode layer 50 may be a metal material, which may include but is not limited to non-magnetic materials such as TaN, TiN, and W. In the above embodiment, in order to significantly enhance the ability of the magnetic random access memory cell 40 to resist external magnetic field interference, the material of the at least one top electrode layer 50 may be a ferromagnetic material, which may include but is not limited to other ferromagnetic materials such as NiFe, CoFe, FeV, or any other metal material known to those skilled in the art that can be used as the top electrode layer 50, and their combinations. Furthermore, the at least one top electrode layer 50 may include multiple layers, wherein the material of the multiple top electrode layers 50 may all be non-magnetic materials, or the material of the multiple top electrode layers 50 may all be ferromagnetic materials, or the material of some layers in the multiple top electrode layers 50 may be non-magnetic materials, and the material of another part of the multiple top electrode layers 50 may be ferromagnetic materials.

[0055] It should be noted that, in the above-mentioned memory structure in this embodiment, the multiple magnetic random access memory cells 40 can be arranged side by side along one direction. When the top electrode layer 50 located on the surface of the multiple magnetic random access memory cells 40 away from the substrate 10 in the above-mentioned memory structure is a single layer, the extension direction of the top electrode layer 50 is the direction from one magnetic random access memory cell 40 to another magnetic random access memory cell 40, so that the top electrode layer 50 is a long strip structure in the extension direction, and the long strip structure is parallel to the routing direction of the bit line BL in the memory structure, thereby significantly enhancing the magnetic random access memory cell 40's ability to resist external magnetic field interference.

[0056] According to another aspect of the present disclosure, the inventors of the present application also provide a method for manufacturing a memory structure, which includes: providing a substrate having a first surface and a second surface relative to each other, and the substrate includes an array area and a logic area adjacent to the array area, and using a single photolithography process to form a plurality of first conductive paths and a second conductive path in the substrate, wherein the plurality of first conductive paths extend from the first surface corresponding to the array area to the second surface, and the second conductive paths extend from the first surface corresponding to the logic area to the second surface, and the first conductive paths and the second conductive paths have the same height in the extension direction; forming a plurality of memory cells on the first surface so that each of the memory cells covers one of the first conductive paths, and the plurality of memory cells correspond one-to-one to the plurality of first conductive paths; forming at least one top electrode layer on the surface of the plurality of memory cells away from the substrate; and forming a top metal wiring layer on the side of the substrate having the top electrode layer so that the top metal wiring layer is electrically connected to at least one of the top electrode layers.

[0057] In the above embodiment, a substrate having a first conductive path and a second conductive path is provided, and the first conductive path and the second conductive path in the substrate are highly consistent, that is, the above-mentioned multiple first conductive paths and second conductive paths are formed at one time using the same photolithography process, thereby reducing the number of masks when forming the first conductive path and the second conductive path, and then after multiple memory cells and at least one top electrode layer covering the multiple first conductive paths are formed on the above-mentioned first surface, a top metal wiring layer electrically connected to at least one top electrode layer is directly formed on the side of the substrate having the top electrode layer, so that the top metal wiring layer can be electrically connected to multiple memory cells. Compared with the prior art, the present application does not need to additionally form a conductive path electrically connecting multiple memory cells and the top metal wiring layer on the side of the memory cell away from the first conductive path, thereby further simplifying the process, reducing the photolithography steps, reducing the number of mask layers, and thereby reducing the manufacturing cost of the memory structure.

[0058] The following describes in more detail exemplary embodiments of methods for fabricating memory structures according to the present disclosure. However, these exemplary embodiments can be implemented in a variety of different forms and should not be construed as being limited to the embodiments described herein. It should be understood that these embodiments are provided to make the disclosure of this application thorough and complete, and to fully convey the concepts of these exemplary embodiments to those of ordinary skill in the art.

[0059] As shown in FIG2 , a substrate 10 is provided. The substrate 10 has opposing first and second surfaces, and includes an array region and a logic region adjacent to the array region. A first photomask covering the first surface is formed on the first surface of the substrate 10. The first photomask includes a plurality of first hollow regions corresponding to the array region and a second hollow region corresponding to the logic region. The plurality of first and second hollow regions are then etched to form a plurality of first through-holes extending from the first surface to the second surface in the array region and a plurality of second through-holes extending from the first surface to the second surface in the logic region. After removing the first photomask, a conductive material is deposited onto the first surface, filling the plurality of first and second through-holes with the conductive material. A planarization process can then be performed to remove the conductive material on the first surface, such that the remaining conductive material in the plurality of first through-holes forms a plurality of first conductive pathways 20, and the remaining conductive material in the second through-holes forms a plurality of second conductive pathways 30. Optionally, the planarization process can include a chemical mechanical polishing process. Optionally, the conductive material can include, but is not limited to, one or a combination of metals selected from the group consisting of W, Cu, TaN, and TiN. Optionally, the substrate further comprises a first metal wiring layer 90 and a second metal wiring layer 100 , the first conductive path 20 is located on the first metal wiring layer 90 , and the second conductive path 30 is located on the second metal wiring layer 100 .

[0060] Furthermore, as shown in FIG3 , a memory cell film 110 corresponding to the memory cell 40 is deposited on the substrate 10 shown in FIG2 . Specifically, the memory cell film 110 may include a lower electrode material layer 111, a storage material layer 112, and an upper electrode material layer 113, which are sequentially deposited. Optionally, the lower electrode material layer 111 and the upper electrode material layer 113 may include, but are not limited to, metal layers such as Ti, TiN, Ta, TaN, and W. Optionally, a hard mask material layer (not shown) may also be included on the upper electrode material layer 113. The hard mask material layer may include, but is not limited to, metal layers such as Ti, TiN, Ta, TaN, and W, or dielectric layers such as silicon oxide and silicon nitride. Optionally, the storage material layer 112 may include a free layer, a barrier layer, and a reference layer stacked sequentially. The free layer is disposed in contact with the lower electrode material layer 111, and the reference layer is disposed in contact with the upper electrode material layer 113.

[0061] Furthermore, first, a second mask is covered on one side of the memory cell film 110 shown in Figure 3, and the second mask has a plurality of memory cell patterns corresponding to the plurality of first conductive paths 20 in the array area, and then the memory cell film 110 is etched according to the above memory cell patterns (wherein, when the above memory cell film 110 is also covered with a hard mask material layer, it also includes sequentially etching the hard mask material layer and the above memory cell film 110), thereby removing the memory cell film 110 except for the portion covering the plurality of first conductive paths 20, so that the remaining memory cell film 110 forms a memory cell 40, as shown in Figure 4, and exposes part of the first surface. Optionally, the projection shape of the memory cell 40 on the above substrate 10 can be circular.

[0062] Furthermore, as shown in Figures 4 to 6, a top electrode layer 50 is formed on a side of the multiple memory cells away from the substrate 10, wherein, in some optional embodiments, the step of forming the above-mentioned top electrode layer 50 includes: after the step of forming the above-mentioned memory cells 40, depositing a first insulating material 120 and a second insulating material 130 in sequence on the side of the above-mentioned substrate 10 having the above-mentioned memory cells 40, so that the above-mentioned first insulating material 120 covers the above-mentioned memory cells 40 and the above-mentioned first surface, and the above-mentioned second insulating material 130 covers the above-mentioned first insulating material 120; using chemical mechanical polishing to remove part of the above-mentioned first insulating material 120 and part of the above-mentioned second insulating material 130 to form a fourth surface exposing the above-mentioned multiple memory cells 40; and forming the above-mentioned top electrode layer 50 on the above-mentioned fourth surface.

[0063] Specifically, as shown in FIG4 , after forming the memory cell 40, a first insulating material 120 is deposited on one side of the exposed first surface, such that the first insulating material 120 covers the exposed portion of the first surface and the exposed surface of the memory cell 40. Optionally, the first insulating material 120 may include, but is not limited to, silicon nitride and aluminum oxide. Those skilled in the art may reasonably select a first insulating material 120 used for protection in the prior art based on actual needs.

[0064] Furthermore, as shown in FIG5 , in the structure shown in FIG4 , in order to make the multiple memory cells 40 have a flat upper surface (i.e., the surface of each memory cell 40 away from the side of the substrate 10), a second insulating material 130 is first deposited so that the second insulating material 130 covers the first insulating material 120, and then chemical mechanical polishing can be used to remove part of the second insulating material 130 and the first insulating material 120 so that the upper surfaces of the multiple memory cells 40 are exposed to form a fourth surface, which is a planarized surface.

[0065] Furthermore, as shown in FIG6 , a top electrode material is deposited on the fourth surface (planarized surface) shown in FIG5 , so that the top electrode material covers the fourth surface (optionally, an etch stop material may also be deposited so that the etch stop material covers the surface of the top electrode material on the side away from the substrate 10). In order to form a top electrode layer 50 on the surface of the plurality of memory cells 40 away from the substrate 10, a third mask is formed on the fourth surface (or on the surface where the etch stop material is away from the top electrode material). The third mask covers the top electrode material (or etch stop material) corresponding to the array area and exposes the top electrode material corresponding to the logic area, so that the top electrode material (and etch stop material) corresponding to the logic area and part of the second insulating material 130 can be removed by etching to form a top electrode layer 50 (and an etch stop layer 150 corresponding to the etch stop material).

[0066] Furthermore, as shown in FIG7 , in order to flatten the surface of the top electrode layer 50 on the side away from the multiple memory cells 40, the second insulating material 130 is deposited again on the side of the top electrode layer 50 (and the etch stop layer 150 corresponding to the etch stop material) and the remaining second insulating material 130 away from the substrate 10 as shown in FIG6 .

[0067] Furthermore, a portion of the second insulating material 130 (and the etch stop layer 150 corresponding to the etch stop material) in the structure shown in FIG7 is removed by a chemical mechanical polishing process to expose the top electrode layer 50, and then a fourth mask is formed on the planarized surface of the exposed top electrode layer 50, so that the fourth mask covers the top electrode layer 50 and exposes the second insulating material 130 corresponding to the logic area, and then the second insulating material 130 not covered by the fourth mask is removed by etching, and with the first insulating material 120 serving as an etch barrier layer, the first insulating material 120 located in the logic area is removed, so that The second conductive path 30 is exposed, so that the logic area and the array area form a step structure, as shown in Figure 1, the remaining first insulating material forms a protective layer 70, and the remaining second insulating material forms an insulating dielectric layer 80, and then a top metal material is deposited on the exposed top electrode layer 50 and one side of the exposed second conductive path 30, so that the top metal material fills the above-mentioned step structure, and a chemical mechanical polishing process is used to flatten the top metal material, thereby forming a top metal wiring layer 60, which electrically connects the second conductive path 30 in the logic area and the multiple memory cells 40 in the array area.

[0068] Or illustratively, as shown in Figure 8, in other embodiments, a top electrode material is deposited on the fourth surface (planarized surface) shown in Figure 5, so that the top electrode material covers the above-mentioned fourth surface (optionally, an etch stop material can also be deposited so that the etch stop material covers the surface of the side of the above-mentioned top electrode material away from the substrate 10), and then in order to form multiple top electrode layers 50 on the surface of the multiple memory cells 40 away from the substrate 10, a fifth mask is formed on the fourth surface (and the surface of the etch stop material away from the top electrode material), and the fifth mask includes a plurality of mother-daughter boards arranged at intervals, and the plurality of mother-daughter boards cover portions of the top electrode material (and the etch stop material) corresponding to the multiple memory cells 40 in the array area, and leave the remaining top electrode material exposed, so that the top electrode material (and the etch stop material) except for the portions of the top electrode material (or the etch stop material) corresponding to the multiple memory cells 40 and a portion of the second insulating material 130 can be removed by etching to form multiple top electrode layers 50 (and the etch stop layer 150 formed by the remaining etch stop material). It can be understood that since the top electrode material between any two adjacent mother-substrates is exposed, after the etching process, part of the second insulating material 130 between any two adjacent top electrode layers 50 or any two adjacent memory cells 40 is also removed, thereby forming a pit between any two adjacent top electrode layers 50 or any two adjacent memory cells 40.

[0069] Furthermore, as shown in FIG9 , in order to flatten the surface of the top electrode layer 50 on the side away from the multiple memory cells 40, the second insulating material 130 is deposited again on the side away from the substrate 10 of the multiple top electrode layers 50 (and the etch stop layer 150 formed by the remaining etch stop material) and the remaining second insulating material 130 shown in FIG8 ; optionally, the second insulating material 130 fills the above-mentioned pits.

[0070] Furthermore, a portion of the second insulating material 130 (and the etching stop layer 150 formed by the remaining etching stop material) in the structure shown in FIG9 is removed by a chemical mechanical polishing process to expose the top electrode layer 50, and then a sixth mask is formed on the planarized surface of the exposed top electrode layer 50, so that the sixth mask covers the above-mentioned top electrode layer 50 and exposes the second insulating material 130 except for the top electrode layer 50. Then, the above-mentioned second insulating material 130 not covered by the sixth mask is removed by etching, and with the first insulating material 120 serving as an etching barrier layer, the first insulating material 120 located in the logic area is removed to expose the second conductive path 30, thereby forming a step structure between the logic area and the array area, and the portion located between any two adjacent memory cells 40 is exposed. Part of the second insulating material 130 is removed to form a groove, thereby exposing the side walls of any two adjacent top electrode layers 50, so that as shown in Figure 10, the remaining first insulating material forms a protective layer 70, and the remaining second insulating material forms an insulating dielectric layer 80, and then a top metal material is deposited on the exposed top electrode layer 50, on one side of the exposed second conductive path 30, and in the groove between any two adjacent top electrode layers 50, so that the top metal material fills the above-mentioned step structure, and after filling the groove, any two adjacent top electrode layers 50 are electrically connected, and then a chemical mechanical polishing process is used to flatten the top metal material, thereby forming a top metal wiring layer 60, which electrically connects the second conductive path 30 in the logic area and the multiple memory cells 40 in the array area.

[0071] Or illustratively, as shown in FIG11 , in some other embodiments, in the structure shown in FIG4 , in order to make the multiple memory cells 40 have a flat upper surface (i.e., the surface of each memory cell 40 away from the substrate 10), the second insulating material 130 is first deposited so that the second insulating material 130 covers the first insulating material 120, and then chemical mechanical polishing can be used to remove part of the second insulating material 130 so that the first insulating material 120 on the surface of the multiple memory cells 40 away from the substrate 10 is exposed, thereby forming a fourth planarized surface.

[0072] Furthermore, as shown in FIG12 , a seventh photomask is formed on the fourth planarized surface shown in FIG11 . The seventh photomask covers a portion of the fourth planarized surface corresponding to the logic region and exposes a portion of the fourth planarized surface corresponding to the array region. The exposed portion of the second insulating material 130 and the portion of the first insulating material 120 are then removed by etching, thereby exposing the upper surfaces of the plurality of memory cells 40 away from the substrate 10 . As a result, after removing the seventh photomask, a step structure is formed between the array region and the logic region (the height of the array region in a direction perpendicular to the first surface is lower than the height of the logic region). Thus, after depositing the top electrode material 140 on the step structure, a height difference still exists between the array region and the logic region.

[0073] Chemical mechanical polishing (CMP) is then used to planarize the top electrode material 140 in the structure shown in FIG12 to eliminate the height difference between the array region and the logic region. Since the array region is lower in height, all of the top electrode material 140 in the logic region is removed after planarization, leaving the second insulating material 130 exposed. As shown in FIG13 , the remaining top electrode material in the array region forms the top electrode layer 50 of the memory structure. Furthermore, as shown in FIG13 , to planarize the surface of the top electrode layer 50 facing away from the plurality of memory cells 40, the second insulating material 130 is re-deposited on the exposed surface of the top electrode layer 50 and on the side of the remaining second insulating material 130 facing away from the substrate 10.

[0074] Furthermore, a portion of the second insulating material 130 is removed by a chemical mechanical polishing process to expose the top electrode layer 50, and then an eighth mask is formed on the planarized surface of the exposed top electrode layer 50, so that the eighth mask covers the above-mentioned top electrode layer 50 and exposes the second insulating material 130 corresponding to the logic area. Then, the above-mentioned second insulating material 130 not covered by the eighth mask is removed by etching, and with the first insulating material 120 serving as an etching stop layer, the first insulating material 120 located in the logic area is removed, so that the second conductive path 30 is exposed, thereby The logic area and the array area form a step structure, so as to form a protective layer 70 and the remaining second insulating material forms an insulating dielectric layer 80 as shown in FIG14 , and then a top metal material is deposited on one side of the exposed top electrode layer 50 and the exposed second conductive path 30, so that the top metal material fills the above-mentioned step structure, and a chemical mechanical polishing process is used to flatten the top metal material, thereby forming a top metal wiring layer 60, which electrically connects the second conductive path 30 of the logic area and the multiple memory cells 40 of the array area.

[0075] From the above description, it can be seen that the above embodiments of the present disclosure achieve the following technical effects:

[0076] Since the heights of the multiple first conductive paths and the second conductive paths in the substrate of the memory structure provided by this solution are consistent, the multiple first conductive paths and the second conductive paths can be formed at one time using the same photolithography process, thereby reducing the number of masks when forming the first conductive paths and the second conductive paths. Subsequently, after multiple memory cells and at least one top electrode layer covering the multiple first conductive paths are formed on the above-mentioned first surface, since the first conductive path serves as the bottom conductive path in the memory structure and the second conductive path serves as the top conductive path of the memory, when the heights of the first conductive path and the second conductive path are consistent, the heights of the multiple memory cells in the array area are higher than the height of the second conductive path. Therefore, it is possible to directly form the memory cells by having a top electrode layer on the substrate. A top metal wiring layer electrically connected to at least one top electrode layer is formed on one side of the layer, so that the top metal wiring layer can be electrically connected to multiple memory cells. Compared with the prior art in which the total height of the bottom conductive path and the memory cell corresponding to the array area is lower than the top conductive path of the logic area, and it is necessary to form a top conductive path again on the side of the memory cell away from the bottom conductive path so that the total height of the bottom conductive path and the memory cell corresponding to the array area is equal to the top conductive path of the logic area, the present application does not need to form an additional conductive path electrically connecting multiple memory cells and the top metal wiring layer on the side of the memory cell away from the first conductive path, thereby further simplifying the process, reducing the number of photolithography steps, reducing the number of mask layers, and thus reducing the production cost of the memory structure.

[0077] The foregoing description is merely a preferred embodiment of the present disclosure and is not intended to limit the present disclosure. Those skilled in the art will readily appreciate that various modifications and variations are possible. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of the present disclosure shall be included within the scope of protection of the present disclosure.

Claims

1. A memory structure comprising: A substrate having a first surface and a second surface opposite to each other, and the substrate includes an array area and a logic area adjacent to the array area, wherein the array area has a plurality of first conductive paths extending from the first surface to the second surface, and the logic area has a second conductive path extending from the first surface to the second surface, and the first conductive path and the second conductive path have the same height; A plurality of memory cells are located on the first surface, and each of the memory cells covers one of the first conductive paths, and the plurality of memory cells correspond to the plurality of the first conductive paths one by one; at least one top electrode layer, located on a surface of the plurality of memory cells away from the substrate; The top metal wiring layer is located on the side of the substrate having the top electrode layer, and is configured to electrically connect the top metal wiring layer to at least one of the top electrode layers.

2. The memory structure according to claim 1, wherein: Each of the memory cells has a first projection on the substrate, and at least one of the top electrode layers has a second projection on the substrate, wherein the first projection is located within the second projection.

3. The memory structure according to claim 1, wherein: The top electrode layers include multiple top electrode layers, and the multiple top electrode layers correspond one-to-one to the multiple memory cells. The surface of the memory cell away from the first conductive path is the third surface. Each top electrode layer covers the third surface. The top metal wiring layer electrically connects the multiple top electrode layers.

4. The memory structure according to claim 1, wherein: The memory structure also includes: A protection layer at least covers a side wall of the memory cell.

5. The memory structure according to any one of claims 1 to 4, wherein: The top metal wiring layer is also electrically connected to the second conductive path.

6. The memory structure according to any one of claims 1 to 4, wherein: The memory unit includes one or more of a magnetic random access memory unit, a phase change random access memory unit, a resistive random access memory unit and a ferroelectric random access memory unit.

7. The memory structure according to claim 6, wherein: In the case where the memory cell is the magnetic random access memory cell, at least one of the top electrode layers includes at least one layer.

8. The memory structure according to claim 7, wherein: At least one of the top electrode layers comprises multiple layers, and a material of at least one layer of at least one of the top electrode layers is a ferromagnetic material.

9. A method for manufacturing a memory structure, comprising: Providing a substrate having a first surface and a second surface opposite to each other, and the substrate including an array area and a logic area adjacent to the array area, and forming a plurality of first conductive paths and a second conductive path in the substrate by a single photolithography process, wherein the plurality of first conductive paths extend from the first surface corresponding to the array area to the second surface, and the second conductive paths extend from the first surface corresponding to the logic area to the second surface, and the first conductive paths and the second conductive paths have the same height in the extension direction; forming a plurality of memory cells on the first surface so that each of the memory cells covers one of the first conductive paths, and the plurality of memory cells correspond to the plurality of the first conductive paths one by one; forming at least one top electrode layer on the surface of the plurality of memory cells away from the substrate; A top metal wiring layer is formed on a side of the substrate having the top electrode layer, so that the top metal wiring layer is electrically connected to at least one of the top electrode layers.

10. The method according to claim 9, wherein: The steps of forming the top electrode layer include: After the step of forming the memory cell, a first insulating material and a second insulating material are sequentially deposited on a side of the substrate having the memory cell, so that the first insulating material covers the memory cell and the first surface, and the second insulating material covers the first insulating material; removing a portion of the first insulating material and a portion of the second insulating material by chemical mechanical polishing to form a fourth surface exposing the plurality of memory cells; The top electrode layer is formed on the fourth surface.

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