Field-effect transistor

Abstract

The present invention suppresses recovery current in a field-effect transistor that has deep layers. A field-effect transistor according to the present invention is configured such that, when a semiconductor substrate is seen from above, each inter-trench region includes: a plurality of contact layers that are arranged with gaps therebetween in a specific direction that is parallel to a plurality of trenches; and a plurality of deep layers that are arranged with gaps therebetween in the specific direction. At each inter-trench region, each of the gaps between the contact layers is above a corresponding deep layer, and each of the gaps between the deep layers is below a corresponding contact layer.

Description

field-effect transistor

[0001] (Cross-reference to related applications) This application is a related application of Japanese Patent Application No. 2023-124922 filed on July 31, 2023, and claims priority based on this Japanese patent application, the entire contents of which are incorporated herein by reference.

[0002] The technology disclosed in this specification relates to a field effect transistor.

[0003] The field-effect transistor disclosed in Japanese Patent Laid-Open No. 2001-267570 has a trench-type gate electrode. This field-effect transistor also has a p-type deep layer (also called a base region) extending downward from a p-type body layer (also called a base region). The deep layer extends to a position below the bottom end of the trench. A p-type contact layer is provided above the deep layer, connecting the body layer and the source electrode. The contact layer is provided to stabilize the potential of the body layer. The deep layer is provided to reduce the electric field strength of the gate insulating film in the trench.

[0004] When the potential of the source electrode increases, a forward voltage is applied to the pn junction at the interface between the body layer and the drift layer. As a result, the diode formed by this pn junction turns on, and holes flow from the body layer into the drift layer. When the potential of the source electrode subsequently decreases, the holes in the drift layer flow to the source electrode via the deep layer, body layer, and contact layer. The current generated by the holes flowing to the source electrode in this way is called a recovery current. The flow of the recovery current generates a surge voltage in the field-effect transistor. The field-effect transistor disclosed in JP 2001-267570 A is prone to generating a high recovery current. This specification proposes a technology for suppressing the recovery current in a field-effect transistor having a deep layer.

[0005] The field-effect transistor disclosed in this specification includes a semiconductor substrate made of a compound semiconductor and having a plurality of trenches formed on its upper surface, a plurality of gate electrodes disposed in the corresponding trenches and insulated from the semiconductor substrate by gate insulating films, and a source electrode in contact with the upper surface of the semiconductor substrate. The semiconductor substrate includes a plurality of n-type source layers, a plurality of p-type contact layers, a p-type body layer, an n-type drift layer, and a plurality of p-type deep layers. Each semiconductor region of the semiconductor substrate located between the plurality of trenches is an inter-trench region. Each source layer is disposed in a corresponding inter-trench region and is in contact with the source electrode and the corresponding gate insulating film. Each contact layer is disposed in a corresponding inter-trench region and is in contact with the source electrode. A plurality of contact layers are provided in each inter-trench region. When the semiconductor substrate is viewed from above, the plurality of contact layers are disposed at intervals in each inter-trench region in a specific direction parallel to the plurality of trenches. The body layer has a lower p-type impurity concentration than the contact layers, is distributed across the inter-trench regions, is disposed below the source layers and the contact layers, and is in contact with the gate insulating film. The drift layer is distributed across the lower regions of the inter-trench regions, is in contact with the body layer from below in each inter-trench region, and is in contact with the gate insulating film. The deep layers extend from the body layer to a position below the lower end of each trench. When the semiconductor substrate is viewed from above, the deep layers are disposed in each inter-trench region with gaps in the specific direction. In each inter-trench region, each of the gaps in the contact layers is disposed above the corresponding deep layer. In each inter-trench region, each of the gaps in the deep layers is disposed below the corresponding contact layer.

[0006] In this field-effect transistor, the spacing portion of the contact layer is located above the deep layer, and the spacing portion of the deep layer is located below the contact layer. This reduces the area where the contact layer and the deep layer overlap in the vertical direction. As a result, the resistance of the path from the drift layer through the deep layer, body layer, and contact layer to the source electrode (i.e., the path through which the recovery current flows) is high. Therefore, this field-effect transistor can suppress the recovery current.

[0007] 1 is a perspective view showing the xz cross section and the yz cross section of a switching element; an xz cross section of a switching element at a position not including a deep layer; an xz cross section of a switching element at a position including a deep layer; a yz cross section of a switching element at a position not including a trench; a plan view of the upper surface of a semiconductor substrate as viewed from above; a graph showing impurity concentration distributions in a contact region, a body region, and a source region; a graph showing drain current and drain voltage during recovery operation; a graph showing the relationship between depth D and surge voltage; a plan view corresponding to FIG. 5 of a switching element of a first modified example; a graph showing the relationship between width W and a reduction rate of surge voltage; a plan view corresponding to FIG. 5 of a switching element of a second modified example; a plan view corresponding to FIG. 5 of a switching element of a third modified example; a plan view corresponding to FIG. 5 of a switching element of a fourth modified example; and a plan view corresponding to FIG. 5 of a switching element of a fifth modified example.

[0008] In one exemplary embodiment disclosed in the present specification, when the semiconductor substrate is viewed from above, the deep layers may intersect with the trenches.

[0009] This configuration can further reduce the electric field strength in the gate insulating film.

[0010] In an example embodiment disclosed in the present specification, the contact layers and the deep layers do not need to overlap when viewed from above the semiconductor substrate, and in this case, the width of the gaps in the contact layers can be wider than the width of the deep layers, and the width of the gaps in the deep layers can be wider than the width of the contact layers.

[0011] This configuration makes it possible to more effectively suppress the recovery current.

[0012] In one example embodiment disclosed in this specification, in each inter-trench region, the spacing of the deep layer may have a first spacing that overlaps with the contact layer when the semiconductor substrate is viewed from above, and a second spacing that does not overlap with the contact layer when the semiconductor substrate is viewed from above.

[0013] In one example embodiment disclosed in this specification, the lower ends of the contact layers may be located at the same position as or higher than the lower ends of the source layers in the thickness direction of the semiconductor substrate.

[0014] According to this configuration, depletion of the contact layer can be suppressed, and therefore the recovery current can be suppressed more effectively.

[0015] The MOSFET 10 (metal-oxide-semiconductor field effect transistor) of the embodiment shown in FIG. 1 has a semiconductor substrate 12. Hereinafter, the thickness direction of the semiconductor substrate 12 is referred to as the z-direction, a direction parallel to the top surface 12a of the semiconductor substrate 12 (a direction perpendicular to the z-direction) is referred to as the x-direction, and a direction perpendicular to the x-direction and z-direction is referred to as the y-direction. The semiconductor substrate 12 is made of silicon carbide (i.e., SiC). The semiconductor substrate 12 may also be made of other compound semiconductors such as gallium nitride or gallium oxide. A plurality of trenches 14 are provided in the top surface 12a of the semiconductor substrate 12. As shown in FIG. 5, the plurality of trenches 14 extend elongately along the y-direction on the top surface 12a. The plurality of trenches 14 are spaced apart in the x-direction. Hereinafter, each semiconductor region within a range sandwiched between the trenches 14 is referred to as an inter-trench region 50.

[0016] As shown in FIGS. 1 to 3 , the inner surface (i.e., the side and bottom surfaces) of each trench 14 is covered with a gate insulating film 16. A gate electrode 18 is disposed in each trench 14. Each gate electrode 18 is insulated from the semiconductor substrate 12 by the gate insulating film 16. The upper surface of each gate electrode 18 is covered with an interlayer insulating film 20. A source electrode 22 is provided on the upper part of the semiconductor substrate 12. The source electrode 22 covers each interlayer insulating film 20. The source electrode 22 is insulated from the gate electrode 18 by the interlayer insulating film 20. The source electrode 22 is in contact with the upper surface 12 a of the semiconductor substrate 12 at a position where the interlayer insulating film 20 is not present. A drain electrode 24 is disposed on the lower part of the semiconductor substrate 12. The drain electrode 24 is in contact with the entire lower surface 12 b of the semiconductor substrate 12.

[0017] The semiconductor substrate 12 has a plurality of source layers 30 , a plurality of contact layers 32 , a body layer 34 , a plurality of deep layers 36 , a plurality of trench lower layers 35 , a drift layer 38 , and a drain layer 40 .

[0018] Each contact layer 32 is a p-type layer having a high p-type impurity concentration. As shown in FIGS. 1, 2, 4, and 5, each contact layer 32 is disposed in an inter-trench region 50. Each contact layer 32 is disposed in an area including the upper surface 12a of the semiconductor substrate 12. Multiple contact layers 32 are provided in each inter-trench region 50. Each contact layer 32 is disposed in a position not in contact with the trench 14. In each inter-trench region 50, the multiple contact layers 32 are arranged at intervals along the y direction (i.e., the direction parallel to the trench 14 on the upper surface 12a). Hereinafter, the region between the contact layers 32 in the y direction will be referred to as a gap 33. Each contact layer 32 is in ohmic contact with the source electrode 22.

[0019] Each source layer 30 is an n-type layer having a high n-type impurity concentration. As shown in FIGS. 1 to 5 , each source layer 30 is disposed in the inter-trench region 50. Each source layer 30 is provided in a range including the upper surface 12a of the semiconductor substrate 12, in a range where the contact layer 32 is not provided. That is, each source layer 30 is provided in a region adjacent to the trench 14 and in the gap 33. The source layer 30 contacts the side surface of the contact layer 32. Each source layer 30 is in ohmic contact with the source electrode 22. Each source layer 30 contacts the gate insulating film 16 at the top of the side surface of the trench 14. Each source layer 30 faces the gate electrode 18 via the gate insulating film 16.

[0020] The body layer 34 is a p-type layer having a lower p-type impurity concentration than the contact layer 32. As shown in FIGS. 1 to 3 , the body layer 34 is distributed across the multiple inter-trench regions 50. The body layer 34 is disposed below the multiple source layers 30 and the multiple contact layers 32. The body layer 34 contacts the multiple source layers 30 and the multiple contact layers 32 from below. The body layer 34 contacts the gate insulating film 16 on the side surface of the trench 14 located below the source layer 30. The body layer 34 faces the gate electrode 18 with the gate insulating film 16 interposed therebetween.

[0021] As shown in FIGS. 1 and 4 , each deep layer 36 is a p-type layer that protrudes downward from the lower surface of the body layer 34. Each deep layer 36 extends from the lower surface of the body layer 34 to a position lower than the lower end of each trench 14. When the semiconductor substrate 12 is viewed from above as shown in FIG. 5 , each deep layer 36 extends elongatedly in the x direction and intersects with the trenches 14 at an angle of approximately 90 degrees. That is, each deep layer 36 is distributed across multiple inter-trench regions 50. When the semiconductor substrate 12 is viewed from above, the multiple deep layers 36 are spaced apart in the y direction. Hereinafter, the regions between the deep layers 36 in the y direction are referred to as gaps 37. As shown in FIG. 3 , each deep layer 36 contacts the gate insulating film 16 on the side surface of the trench 14 located below the body layer 34. Each deep layer 36 faces the gate electrode 18 via the gate insulating film 16.

[0022] 1 to 3 , each trench lower layer 35 is a p-type layer disposed in the lower portion of the corresponding trench 14. Each trench lower layer 35 extends longitudinally along the longitudinal direction (i.e., the y direction) of the corresponding trench 14 and intersects with each deep layer 36. Each trench lower layer 35 contacts the gate insulating film 16 at the bottom surface of the corresponding trench 14.

[0023] The drift layer 38 is an n-type layer having a lower n-type impurity concentration than the source layer 30. The drift layer 38 is distributed across the lower portions of the multiple inter-trench regions 50. The drift layer 38 contacts the multiple deep layers 36 and the multiple trench lower layers 35 from below. The drift layer 38 is distributed into each gap 37 between the multiple deep layers 36. In each gap 37, the drift layer 38 contacts the side surfaces of the multiple deep layers 36 and the side surfaces of the multiple trench lower layers 35. The drift layer 38 extends into each inter-trench region 50 through each gap 37. In each inter-trench region 50, the drift layer 38 contacts the body layer 34 from below. In each inter-trench region 50, the drift layer 38 contacts the gate insulating film 16. That is, the drift layer 38 contacts the gate insulating film 16 on the side surface of the trench 14 located below the body layer 34 .

[0024] The drain layer 40 is an n-type layer having a higher n-type impurity concentration than the drift layer 38. The drain layer 40 is in contact with the drift layer 38 from below. The drain layer 40 is disposed in an area including the lower surface 12b of the semiconductor substrate 12. The drain layer 40 is in ohmic contact with the drain electrode 24.

[0025] 5 shows the positional relationship between the contact layer 32 and the deep layer 36 when the semiconductor substrate 12 is viewed from above. In each inter-trench region 50, the spacing portions 33 of the contact layer 32 are disposed above the corresponding deep layer 36. Also, in each inter-trench region 50, the spacing portions 37 of the deep layer 36 are disposed below the corresponding contact layer 32. Each contact layer 32 is disposed at a position that does not overlap with the deep layer 36 when the semiconductor substrate 12 is viewed from above.

[0026] As shown in FIG. 2 , the lower end 32 a of the contact layer 32 is located above the lower end 30 a of the source layer 30. FIG. 6 shows the impurity concentration distribution in the z-direction within the source layer 30, contact layer 32, and body layer 34. The lower end 30 a of the source layer 30 is defined as the position where the n-type impurity concentration and the p-type impurity concentration are the same. In the body layer 34 (i.e., the p-type region below the source layer 30), the p-type impurity concentration is distributed in a normal distribution with a peak value P1. In this specification, the contact layer 32 is defined as a p-type layer having a p-type impurity concentration higher than the peak value P1. Therefore, the lower end 32 a of the contact layer 32 is defined as the position where the p-type impurity concentration is the same as the peak value P1. As shown in FIG. 6 , the lower end 32 a of the contact layer 32 is located above the lower end 30 a of the source layer 30.

[0027] Next, the operation of the MOSFET 10 will be described. When a potential equal to or greater than the gate threshold is applied to each gate electrode 18, a channel is formed in the body layer 34 near the gate insulating film 16. The channel connects the source layer 30 and the drift layer 38. When the potential of the drain electrode 24 is higher than the potential of the source electrode 22, electrons flow from the source layer 30 to the drain layer 40 via the channel and the drift layer 38. In other words, the MOSFET 10 is turned on. When the potential of each gate electrode 18 is reduced to a value less than the gate threshold, the channel disappears and the flow of electrons stops. In other words, the MOSFET 10 is turned off. When the MOSFET 10 is turned off, a depletion layer extends from the body layer 34 to the drift layer 38. In addition, a depletion layer also extends from the deep layer 36 and the trench lower layer 35 to the drift layer 38. The depletion layer extending from the deep layer 36 and the trench lower layer 35 promotes depletion in the semiconductor region around the bottom end of the trench 14. Therefore, the concentration of the electric field on the gate insulating film 16 is suppressed.

[0028] Furthermore, a higher potential may be applied to the source electrode 22 than to the drain electrode 24. When a higher potential is applied to the source electrode 22 than to the drain electrode 24, a diode formed by a pn junction at the interface between the p-type layer (i.e., a p-type layer composed of the body layer 34, the trench lower layer 35, and the deep layer 36) and the drift layer 38 turns on. That is, holes flow from the p-type layer to the drift layer 38, and electrons flow from the drift layer 38 to the p-type layer. When the voltage applied to the MOSFET 10 is subsequently changed and the potential of the source electrode 22 becomes lower than the potential of the drain electrode 24, a recovery operation occurs in the diode. FIG. 7 shows the changes in the drain-source voltage Vds and the drain current Ids during the recovery operation. During the recovery operation, a depletion layer develops from the pn junction at the interface between the p-type layer and the drift layer 38 into the drift layer, and holes in the drift layer 38 are discharged to the source electrode 22 via the p-type layer. This causes a recovery current IR to flow, as shown in FIG. 7. As a result, a surge voltage Vak is generated between the source electrode 22 and the drain electrode 24. In this embodiment, the deep layer 36 protrudes toward the drift layer 38, so holes easily flow from the drift layer 38 into the deep layer 36 during recovery operation. Therefore, as shown by arrow 100 in FIG. 4 , holes are discharged from the drift layer 38 to the source electrode 22 via the deep layer 36, the body layer 34, and the contact layer 32. In this embodiment, since the contact layer 32 does not exist above the deep layer 36, holes that pass through the deep layer 36 move laterally within the body layer 34 before flowing to the contact layer 32. Therefore, the resistance of the path through which holes flow is high. Therefore, the recovery current IR is suppressed, and the surge voltage Vak is suppressed.

[0029] Furthermore, during recovery operation, a depletion layer extends from the pn junction into the p-type layer. Holes discharged from the depleted p-type layer to the source electrode 22 also constitute the recovery current. Within the body layer 34, the depletion layer extends upward from the pn junction. When the depletion layer reaches the lower end 30a of the source layer 30, its extension upward stops. In this embodiment, the lower end 32a of the contact layer 32 is located above the lower end 30a of the source layer 30, preventing the depletion layer from extending into the contact layer 32. This prevents the high-concentration holes in the contact layer 32 from being discharged to the source electrode 22 as a recovery current. This further suppresses the recovery current and the surge voltage. FIG. 8 shows the relationship between the depth D of the contact layer 32 and the surge voltage Vak. In FIG. 8, the depth D refers to the relative position in the z direction of the lower end 32a of the contact layer 32 with respect to the lower end 30a of the source layer 30. A positive depth D means that the lower end 32a of the contact layer 32 is located higher than the lower end 30a of the source layer 30. As shown in Fig. 8, the greater the depth D (i.e., the higher the lower end 32a of the contact layer 32 is located), the more the surge voltage Vak is suppressed.

[0030] As described above, the MOSFET 10 of the embodiment can suppress the recovery current.

[0031] In the above embodiment, the lower end 32a of the contact layer 32 is located above the lower end 30a of the source layer 30. However, the lower end 32a of the contact layer 32 may be located at the same position as the lower end 30a of the source layer 30 in the thickness direction of the semiconductor substrate 12. In other words, the depth D may be zero. As shown in FIG. 8 , even when the depth D is zero, the surge voltage Vak is suppressed more effectively than when the depth D is negative.

[0032] In the above embodiment, the contact layer 32 is not located above the deep layer 36. However, as shown in FIG. 9 , a portion 32x of the contact layer 32 may be located above the deep layer 36. That is, when the semiconductor substrate 12 is viewed from above, the portion 32x of the contact layer 32 may overlap the deep layer 36. FIG. 10 shows the relationship between the width W (see FIG. 9 ) of the overlapping portion between the contact layer 32 and the deep layer 36 and the reduction rate of the surge voltage Vak. A negative width W means that the contact layer 32 and the deep layer 36 do not overlap. In addition, in FIG. 10 , the width Wd means the width of the deep layer 36 in the y direction (see FIG. 9 ). W=½Wd means that the spacing portion 33 does not exist. As shown in FIG. 10 , even when the width W is positive, the surge voltage Vak decreases as the width W decreases from ½Wd. In this way, even if a portion 32x of the contact layer 32 overlaps with the deep layer 36, the spacing portion 33 is disposed above the deep layer 36, thereby increasing the resistance of the recovery current path and suppressing the recovery current.

[0033] In the above embodiment, the contact layer 32 is provided for each gap 37 of the deep layer 36. However, as shown in Fig. 11 , the number of contact layers 32 may be fewer than the number of gaps 37 in each inter-trench region 50. That is, in Fig. 11 , the gap 37 has a first gap 37a that overlaps with the contact layer 32 when the semiconductor substrate 12 is viewed from above, and a second gap 37b that does not overlap with the contact layer 32 when the semiconductor substrate 12 is viewed from above. In this case, the contact layers 32 may be disposed in an evenly dispersed manner.

[0034] In the above embodiment, the source layer 30 is provided in the entire surface region near the top surface 12a where the contact layer 32 is not present. However, the distribution range of the source layer 30 may be narrower. FIGS. 12 and 13 show an example in which the distribution range of the source layer 30 is narrower than that shown in FIG. 5. In FIGS. 12 and 13, the hatched region R indicates a region on the top surface 12a where neither the contact layer 32 nor the source layer 30 is provided. Within region R, the body layer 34 is in contact with the source electrode 22 on the top surface 12a. In FIG. 12, the source layer 30 is provided only in a region adjacent to the trench 14. In FIG. 13, the body layer 34 (i.e., region R) is provided in a region adjacent to the end of the contact layer 32 in the x-direction, and the source layer 30 is provided in the remaining region.

[0035] In the above embodiment, each deep layer 36 extends elongately in the x direction when the semiconductor substrate 12 is viewed from above. However, as shown in FIG. 14 , each deep layer 36 may be provided dispersedly in the x direction when the semiconductor substrate 12 is viewed from above. In FIG. 14 , the deep layers 36 are provided dispersedly in the x direction so that each deep layer 36 is present in each inter-trench region 50. Within each inter-trench region 50, the deep layers 36 are arranged at intervals in the y direction. The configuration in FIG. 14 can also suppress the recovery current.

[0036] The configurations of the technology disclosed in this specification are listed below. (Configuration 1) A field effect transistor comprising: a semiconductor substrate made of a compound semiconductor and having a plurality of trenches provided on its upper surface; a plurality of gate electrodes each disposed in a corresponding one of the trenches and insulated from the semiconductor substrate by a gate insulating film; and a source electrode in contact with the upper surface of the semiconductor substrate; the semiconductor substrate having a plurality of n-type source layers, a plurality of p-type contact layers, a p-type body layer, an n-type drift layer, and a plurality of p-type deep layers; each semiconductor region of the semiconductor substrate located between the plurality of trenches is an inter-trench region; each source layer is disposed in a corresponding one of the inter-trench regions and in contact with the source electrode and the corresponding gate insulating film; each contact layer is disposed in a corresponding one of the inter-trench regions and in contact with the source electrode; a plurality of the contact layers are provided in each of the inter-trench regions; when the semiconductor substrate is viewed from above, the plurality of contact layers are disposed at intervals in each of the inter-trench regions in a specific direction parallel to the plurality of trenches; a body layer having a p-type impurity concentration lower than that of each of the contact layers, distributed across the plurality of inter-trench regions, disposed below each of the source layers and each of the contact layers, and in contact with the gate insulating film; a drift layer distributed across lower regions of the plurality of inter-trench regions, in contact with the body layer from below in each of the inter-trench regions, and in contact with the gate insulating film; each of the deep layers extending from the body layer to a position lower than the lower end of each of the trenches; when the semiconductor substrate is viewed from above, the plurality of deep layers are disposed in each of the inter-trench regions with gaps in the specific direction; and in each of the inter-trench regions, each of the gaps in the contact layers is disposed above a corresponding one of the deep layers; and in each of the inter-trench regions, each of the gaps in the deep layers is disposed below a corresponding one of the contact layers.(Structure 2) The field-effect transistor according to Structure 1, wherein each of the deep layers intersects with each of the trenches when the semiconductor substrate is viewed from above. (Structure 3) The field-effect transistor according to Structure 1 or 2, wherein each of the contact layers does not overlap with each of the deep layers when the semiconductor substrate is viewed from above. (Structure 4) The field-effect transistor according to any of Structures 1 to 3, wherein, in each inter-trench region, the spacing portion of the deep layer has a first spacing portion that overlaps with the contact layer when the semiconductor substrate is viewed from above, and a second spacing portion that does not overlap with the contact layer when the semiconductor substrate is viewed from above. (Structure 5) The field-effect transistor according to any of Structures 1 to 4, wherein, in the thickness direction of the semiconductor substrate, a lower end of each of the contact layers is located at the same position as or higher than a lower end of each of the source layers.

[0037] Although the embodiments have been described in detail above, these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and variations of the specific examples exemplified above. The technical elements described in this specification or drawings exhibit technical utility alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. Furthermore, the technology exemplified in this specification or drawings simultaneously achieves multiple objectives, and achieving one of these objectives itself has technical utility.

Claims

1. A field effect transistor comprising: a semiconductor substrate (12) made of a compound semiconductor and having a plurality of trenches (14) on an upper surface thereof; a plurality of gate electrodes (18) each disposed in a corresponding one of the trenches and insulated from the semiconductor substrate by a gate insulating film; and a source electrode (22) in contact with an upper surface of the semiconductor substrate; the semiconductor substrate has a plurality of n-type source layers (30), a plurality of p-type contact layers (32), a p-type body layer (34), an n-type drift layer (38), and a plurality of p-type deep layers (36); each semiconductor region located between the plurality of trenches in the semiconductor substrate is an inter-trench region (50); each of the source layers is disposed in a corresponding one of the inter-trench regions, is in contact with the source electrode, and is in contact with a corresponding one of the gate insulating films; each of the contact layers is disposed in a corresponding one of the inter-trench regions, and is in contact with the source electrode; and a plurality of the contact layers are provided in each of the inter-trench regions; When the semiconductor substrate is viewed from above, in each of the inter-trench regions, the contact layers are arranged with gaps (33) in a specific direction parallel to the trenches; the body layer has a lower p-type impurity concentration than each of the contact layers, is distributed across the inter-trench regions, is disposed below each of the source layers and each of the contact layers, and is in contact with the gate insulating film; the drift layer is distributed across a lower region of the inter-trench regions, is in contact with the body layer from below in each of the inter-trench regions, and is in contact with the gate insulating film; each of the deep layers extends from the body layer to a position lower than the lower end of each of the trenches; when the semiconductor substrate is viewed from above, the deep layers are arranged with gaps (37) in the specific direction in each of the inter-trench regions; in each of the inter-trench regions, each of the gaps of the contact layers is disposed above the corresponding deep layer; and in each of the inter-trench regions, each of the gaps of the deep layers is disposed below the corresponding contact layer. Field effect transistor.

2. The field effect transistor according to claim 1, wherein each of said deep layers intersects each of said trenches when said semiconductor substrate is viewed from above.

3. The field effect transistor according to claim 1 or 2, wherein the contact layers and the deep layers do not overlap each other when the semiconductor substrate is viewed from above.

4. A field effect transistor as described in claim 1 or 2, wherein in each inter-trench region, the gap of the deep layer has a first gap (37a) that overlaps with the contact layer when the semiconductor substrate is viewed from above, and a second gap (37b) that does not overlap with the contact layer when the semiconductor substrate is viewed from above.

5. A field effect transistor according to claim 1 or 2, wherein, in the thickness direction of the semiconductor substrate, the lower ends (32a) of the contact layers are located at the same position as or higher than the lower ends (30a) of the source layers.

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