Array antenna device

Abstract

An array antenna device (100) is provided with: a first layer (10) in which a plurality of antenna elements (11) are arranged in a grid shape; and a second layer (20) that overlaps the first layer (10). The second layer (20) has: an IF signal main line (21) and an LO signal main line (22) that extend in the orthogonal direction to each other; an IF signal branch line (23) and an LO signal branch line (24) that extend in the orthogonal direction of the IF signal main line (21) and the LO signal main line (22); and a plurality of mixers (29) that are arranged in the same grid shape as the plurality of antenna elements (11) at the intersections of the branch lines (23, 24), and electrically connected to the branch lines (23, 24) and the antenna elements (11). Phase shifters (25, 26, 27, 28) are provided between the connection points of the branch lines (23, 24) in the main lines (21, 22) and / or between the connection points of the mixers (29) in the branch lines (23, 24). The first layer (10) and the second layer (20) vertically overlap such that the arrangement region (110) of the plurality of antenna elements (11) in the first layer (10) and the arrangement region (290) of the plurality of mixers (29) in the second layer (20) overlap in a plan view.

Description

Array Antenna Device

[0001] The present invention relates to a wireless device equipped with an array antenna, and more particularly to an array antenna device suitable for a transceiver using the 300 GHz band.

[0002] Figure 7 is a graph showing the relationship between frequency band and S / N ratio for each received power of radio waves. The horizontal axis of the graph is frequency band, and the vertical axis is S / N ratio. The graph plots the relationship between frequency band and S / N ratio when the received power Pr is 0.1 μW (equivalent to -40 dBm), 1 μW (equivalent to -30 dBm), and 10 μW (equivalent to -20 dBm). As can be seen from this graph, the S / N ratio decreases as the frequency band increases, regardless of the magnitude of Pr.

[0003] The graph shows the results of modulation schemes QPSK (Quadrature Phase Shift Keying), 16QAM (16 Quadrature Amplitude Modulation), and 64QAM (64 Quadrature Amplitude Modulation) with a BER (Bit Error Rate) of less than 10 －３ An auxiliary line is drawn to indicate the S / N ratio required to achieve this. According to this, if the frequency band is 25 GHz, communication is possible using any of the modulation methods QPSK, 16QAM, and 64QAM with a Pr of 0.1 μW or more, but if the frequency band is 50 GHz, a Pr of 0.1 μW will make the S / N ratio too small, making QPSK communication difficult. Furthermore, to perform stable QPSK communication at an even higher frequency band of around 100 GHz, a receiving power of 1 μW or more is required.

[0004] The sixth-generation mobile communication system (6G) aims to achieve data rates of 100 Gb / s or more using the 300 GHz band, which is even higher than the fifth-generation mobile communication system (5G). Therefore, in next-generation mobile communication systems, which will continue to operate at higher frequencies and higher data rates, it is necessary to increase the transmitter output power to maintain high reception power. Previous approaches to increasing the output power of transceivers using the 300 GHz band have included using lenses or horns to increase antenna gain, or using rat-race power combiners to combine multiple RF (radio frequency) signals to increase the output power of a single transceiver (see, for example, Patent Document 1).

[0005] International Publication No. 2020 / 110814

[0006] When evaluating the received power from the perspective of EIPR (equivalent isotropically radiated power), the received power is Pr = EIRP · Ar / 4πd, where d is the distance from the transmitter to the receiver and Ar is the antenna area of ​​the receiver. ２ That is, the magnitude of the received power is determined by the antenna area Ar of the receiver regardless of the frequency band, and the larger the antenna area, the larger the antenna gain and the greater the received power.

[0007] An effective way to increase antenna gain is to use an array antenna with multiple antenna elements. Furthermore, using a phased array antenna enables the use of beamforming technology, which adjusts the signal phase of each antenna element to transmit radio waves in a specific direction or receive radio waves from a specific direction, as well as beam sweep, which allows the beam direction to be freely changed. This allows for a wider beam control angle than using lenses or horns, and also makes beamforming easier.

[0008] In an array antenna, antenna elements are arranged at a pitch of half the wavelength of the radio wave. In the 300 GHz band, antenna elements must be arranged at a pitch of approximately 500 μm. Therefore, if an array antenna in which antenna elements are arranged in a two-dimensional grid pattern is to be adopted in a transceiver using the 300 GHz band, the transceiver circuitry must be packed into an area of ​​approximately 500 μm square. Although transistor size can be reduced through miniaturization of semiconductor processes, passive elements such as inductance elements and capacitance elements are difficult to miniaturize, making it difficult to pack a circuit such as that disclosed in Patent Document 1 into such a narrow area. Thus, it is difficult to adopt an array antenna in a transceiver using the 300 GHz band due to the constraints on circuit layout area.

[0009] In view of the above problems, an object of the present invention is to provide an array antenna device that can be used in the 300 GHz band.

[0010] According to one aspect of the present invention, a radio frequency antenna includes a first layer on which a plurality of antenna elements are arranged in a grid pattern, and a second layer overlapping the first layer, wherein the second layer includes an IF (intermediate frequency) signal main line and an LO (local oscillation frequency) signal main line extending in mutually orthogonal directions, a plurality of IF signal branch lines and a plurality of LO signal branch lines extending in respective orthogonal directions to the IF signal main line and the LO signal main line, and a plurality of mixers arranged in the same grid pattern as the plurality of antenna elements at each intersection of the plurality of IF signal branch lines and the plurality of LO signal branch lines, and electrically connected to each of the plurality of IF signal branch lines, the plurality of LO signal branch lines, and the plurality of antenna elements. a first phase shifter is provided at least one between each connection point of the plurality of IF signal branch lines in the IF signal main line and between each connection point of the plurality of mixers in the plurality of LO signal branch lines, and a second phase shifter is provided at least one between each connection point of the plurality of LO signal branch lines in the LO signal main line and between each connection point of the plurality of mixers in the plurality of IF signal branch lines, and the first layer and the second layer are stacked vertically so that the arrangement area of ​​the plurality of antenna elements in the first layer and the arrangement area of ​​the plurality of mixers in the second layer overlap in a planar view.

[0011] According to the present invention, an array antenna can transmit and receive radio waves in the 300 GHz band, which makes it possible to easily increase antenna gain in the 300 GHz band.

[0012] Figure 4 is a schematic planar configuration diagram of an array antenna device according to an embodiment of the present invention. Figure 5 is a diagram showing an example of a circuit of a 300 GHz silicon CMOS transmitter mounted on a semiconductor substrate of the array antenna device of Figure 1. Figure 6 is a diagram showing an example of a chiplet configuration of the transmitter circuit of Figure 2. Figure 7 is a diagram showing an example of a circuit of a 300 GHz silicon CMOS receiver mounted on a semiconductor substrate of the array antenna device of Figure 1. Figure 8 is a diagram showing an example of a chiplet configuration of the receiver circuit of Figure 4. Figure 9 is a diagram showing an example of a circuit of a transceiver mounted on a semiconductor substrate of the array antenna device of Figure 1. Figure 10 is a graph showing the relationship between frequency band and S / N ratio for each received power of radio waves.

[0013] Hereinafter, embodiments will be described in detail with reference to the drawings as appropriate. However, more detailed description than necessary may be omitted. For example, detailed description of well-known matters or redundant description of substantially identical configurations may be omitted. This is to avoid unnecessary redundancy in the following description and to facilitate understanding by those skilled in the art. Note that the inventors provide the accompanying drawings and the following description to enable those skilled in the art to fully understand the present invention, and are not intended to limit the subject matter described in the claims. Furthermore, the dimensions of each component depicted in the drawings, the detailed shapes of the details, and the like may differ from the actual ones.

[0014] 1 is a schematic plan view of an array antenna device according to one embodiment of the present invention. The array antenna device 100 according to this embodiment is a 300 GHz band silicon CMOS radio in which a printed circuit board 10 and a semiconductor substrate 20 are stacked one above the other. For convenience, the plan views of the printed circuit board 10 and the semiconductor substrate 20 are drawn side by side in Fig. 1, but in reality they are stacked one above the other and electrically connected by flip-chip bonding.

[0015] Antenna elements 11, such as rectangular microstrip patch antennas, are arranged in a 4x4 grid in an antenna element arrangement region 110 of a printed circuit board 10. Considering that the desired RF frequency of the array antenna device 100 is 252 to 296 GHz (wavelength of approximately 1000 to 1200 μm), for example, the sum of the lengths of the two sides of the antenna elements 11 is 300 to 350 μm, which is one-quarter wavelength of the RF signal with some margin, and the arrangement pitch of the antenna elements 11 in the row and column directions (corresponding to the horizontal and vertical directions in FIG. 1 ) is 600 to 700 μm, which is one-half wavelength of the RF signal with some margin.

[0016] 1, power lines and ground lines are laid out in a grid pattern between the antenna elements 11 on the printed circuit board 10. These power lines and ground lines provide operating power to the circuit elements on the semiconductor substrate 20 by flip-chip bonding.

[0017] The semiconductor substrate 20 is mounted with circuits for a 300 GHz-band transmitter and / or receiver, which will be described later. Generally, a transmitter inputs an IF signal and an LO signal to a mixer, upconverts the IF signal with the LO signal to generate an RF signal, amplifies the RF signal with a power amplifier, and transmits the signal from an antenna. Meanwhile, a receiver amplifies an RF signal received by an antenna with a low-noise amplifier, inputs the RF signal and the LO signal to a mixer, and downconverts the RF signal with the LO signal to generate an IF signal. However, when RF signals reach the 300 GHz band, due to the operating limits of CMOS transistors, it becomes difficult to place a power amplifier in the final stage of a transmitter or a low-noise amplifier in the first stage of a receiver. Therefore, for high-frequency bands such as the 300 GHz band, transmitters with a mixer-first configuration, in which a mixer is placed in the final stage, and receivers with a mixer-first configuration, in which a mixer is placed in the first stage, are used.

[0018] In the mixer placement region 290 of the semiconductor substrate 20, the mixers 29 are arranged in a 4x4 grid pattern with the same arrangement pitch as the antenna elements 11. There is a one-to-one correspondence between the mixers 29 and the antenna elements 11, and each mixer 29 is electrically connected to the corresponding antenna element 11 on the printed circuit board 10 via a bump (not shown). In other words, if the printed circuit board 10 is the upper layer and the semiconductor substrate 20 is the lower layer, the antenna element placement region 110 and the mixer placement region 290 overlap in whole or in part in a plan view. Each of these mixers 29 is a mixer for the above-mentioned mixer-first configuration transmitter or mixer-first configuration receiver, and the array antenna device 100 is configured as a collection of multiple mixer-first configuration transmitters, a collection of multiple mixer-first configuration receivers, or a combination of these.

[0019] In the semiconductor substrate 20, the IF signal main line 21 and the LO signal main line 22 extend in directions perpendicular to each other outside the mixer placement region 290. Furthermore, a plurality of IF signal branch lines 23 extend from the IF signal main line 21 in a direction perpendicular to the IF signal main line 21, i.e., parallel to the LO signal main line 22, at the same placement pitch as the mixers 29, i.e., at intervals of 600 to 700 μm, which is the same as the placement pitch of the antenna elements 11. In this embodiment, there are four IF signal branch lines 23. Similarly, a plurality of LO signal branch lines 24 extend from the LO signal main line 22 in a direction perpendicular to the LO signal main line 22, i.e., parallel to the IF signal main line 21, at the same placement pitch as the mixers 29, i.e., at intervals of 600 to 700 μm, which is the same as the placement pitch of the antenna elements 11. In this embodiment, there are four LO signal branch lines 24. The IF signal main line 21 and the IF signal branch line 23 are lines that supply an IF signal to the mixer 29 in the transmitter, and are lines that acquire the IF signal from the mixer 29 and power couple it in the receiver. The LO signal main line 22 and the LO signal branch line 24 are lines that supply an LO signal to the mixer 29. Each mixer 29 is disposed at each intersection of the multiple IF signal branch lines 22 and the multiple LO signal branch lines 24, and is connected to the nearest IF signal branch line 22 and LO signal branch line 24.

[0020] Phase shifters (not shown) are inserted in each of the IF signal main line 21, the LO signal main line 22, the IF signal branch line 23, and the LO signal branch line 24, and the phases of the IF signals and LO signals input to and output from each mixer 29 can be adjusted to sweep the RF signals transmitted from the array antenna device 100 or the RF signals received by the array antenna device in two dimensions, vertically and horizontally. This will be described below with reference to specific circuit examples.

[0021] The area in which each mixer 29 is arranged is a narrow area with a side length of 600 to 700 μm, so it is not possible to arrange many circuit elements in such an area. Therefore, all circuits that are of a certain size, such as an LO signal oscillator (not shown) that supplies an LO signal to the main LO signal line 21 and a controller (not shown) that controls each of the phase shifters described above, are arranged outside the mixer arrangement area 290.

[0022] --Transmitter Circuit Example-- Figure 2 is a diagram showing an example circuit of a 300 GHz silicon CMOS transmitter mounted on the semiconductor substrate 20 of the array antenna device 100 of Figure 1. In the transmitter circuit 201, mixers 29 are arranged in a 4x4 grid. Each mixer 29 is composed of, for example, one or more transistors and one or more passive elements. Each mixer 29 is electrically connected to a corresponding antenna element 11 (see Figure 1) on the printed circuit board 10 via an RF signal terminal 30 by flip-chip bonding. Note that the terminals on both sides of the RF signal terminal 30 in the figure represent ground terminals. Furthermore, a power supply terminal 31 and a ground terminal 32 provided corresponding to each mixer 29 are electrically connected to the power line and ground line on the printed circuit board 10, and each mixer 29 operates by receiving the power supply.

[0023] In the transmitter circuit 201, the IF signal main line 21 and the LO signal main line 22 extend in mutually orthogonal directions outside the mixers 29 arranged in a grid pattern. Furthermore, four IF signal branch lines 23 extend from the IF signal main line 21 via buffers at the same arrangement pitch as the mixers 29 in a direction orthogonal to the IF signal main line 21, i.e., parallel to the LO signal main line 22. Similarly, multiple LO signal branch lines 24 extend from the LO signal main line 22 via buffers at the same arrangement pitch as the mixers 29 in a direction orthogonal to the LO signal main line 22, i.e., parallel to the IF signal main line 21. Each mixer 29 is arranged at each intersection of the multiple IF signal branch lines 22 and the multiple LO signal branch lines 24, and is connected to the nearest IF signal branch line 22 and LO signal branch line 24 via a buffer. For example, each mixer 29 mixes a 50 GHz IF signal supplied from the IF signal branch line 22 with a 225 GHz LO signal supplied from the LO signal branch line 24 to output a 275 GHz RF signal.

[0024] In the IF signal main line 21, a signal phase is set to φ between each connection point of the IF signal branch line 23. １ Delay by φ １ A phase shifter 25 is inserted. Furthermore, the signal phase is adjusted by φ between each connection point of the mixer 29 in the IF signal branch line 23. ４ Delay by φ ４A phase shifter 27 is inserted. That is, the IF signal input to the IF signal terminal 41 is φ １ Phase shifter 25 and φ ４ The signal is input to each mixer 29 with a phase delay each time it passes through a phase shifter 27. １ Phase shifter 25 and φ ４ The phasers 27 are controlled through respective common control lines, but for simplicity these control lines and controllers are not shown.

[0025] In the LO signal main line 22, a signal phase φ is set between each connection point of the LO signal branch line 24. ３ Delay by φ ３ A phase shifter 26 is inserted. Furthermore, the signal phase is adjusted by φ between each connection point of the mixer 29 in the LO signal branch line 24. ２ Delay by φ ２ The phase shifter 28 is inserted. That is, the LO signal input to the LO signal terminal 42 is φ ３ Phase shifter 26 and φ ２ The signal is input to each mixer 29 with a phase delay each time it passes through a phase shifter 28. ３ Phase shifter 26 and φ ２ The phasers 28 are controlled through respective common control lines, but for convenience these control lines and controllers are not shown.

[0026] 2, with the upper left corner as the base point, the row direction to the right is the x direction, and the column direction to the bottom is the y direction, the arrangement position of each mixer 29 is represented by natural numbers (x, y), the maximum value of x is n, the maximum value of y is m, and the IF signal terminal 41 and the LO signal terminal 42 are reference phases, the IF signal phase and LO signal phase input to the mixer 29 at arrangement position (x, y) and the RF signal phase output are respectively expressed as follows: IF signal phase: (m-y)φ １ +(x-1)φ ４ LO signal phase: (n-x)φ ３ +(y-1)φ ２ RF signal phase: (my)φ １ +(x-1)φ ４ +(n-x)φ ３ +(y-1)φ ２

[0027] where φ １ =φ ２ , φ ３ =φ ４ Then, the RF signal phase is (m-1)φ １ +(n-1)φ ３ That is, RF signals of the same phase are output from all mixers 29 regardless of the arrangement position of the mixers 29. This means that the RF signals sent from the array antenna device 100 are beamformed directly ahead, that is, in the normal direction of the printed circuit board 10.

[0028] Conversely, φ １ ≠φ ２ In this case, the beam direction of the RF signal is shifted in the column direction from the normal direction of the printed circuit board 10, and φ ３ ≠φ ４ In this case, the beam direction of the RF signal is shifted in the row direction from the normal direction of the printed circuit board 10. １ Phase shifter 25 and φ ２ The phase shifter 28 is appropriately controlled to change φ １ and φ ２ and adjust the relative relationship of φ ３ Phase shifter 26 and φ ４ The phase shifter 27 is appropriately controlled to set φ ３ and φ ４ By adjusting the relative relationship between the two, it is possible to freely sweep the beam of the transmission RF signal in the column direction and the row direction.

[0029] The transmitter circuit 201 can be configured monolithically on a single semiconductor substrate 20, or alternatively, can be configured as a chiplet in which each circuit element is divided into multiple chips and these chips are connected together. FIG. 3 is a diagram showing an example of a chiplet configuration of the transmitter circuit 201. For example, the transmitter circuit 201 can be divided into three types of chips. Chip 2A is a chip for the IF signal line portion. In addition to the IF signal main line 21, chip 2A has two IF signal branch lines 23 and two φ １ The chip 2B is a chip for the LO signal line portion. In addition to the LO signal main line 22, the chip 2B also includes two LO signal branch lines 24 and two φ ３The chip 2C is a chip for the mixer portion. In addition to the four mixers 29, the chip 2C includes two IF signal branches 23, two LO signal branches 24, and four φ ４ Phase shifter 27 and four φ ２ It includes a phase shifter 28. In each chip, pads are arranged at the ends of each signal line for connection to signal lines of other chips.

[0030] By connecting a plurality of chips 2A and a plurality of chips 2B in series, the IF signal main line 21 and the LO signal main line 22 can be extended as desired. Furthermore, by connecting a plurality of chips 2C vertically and horizontally, the number of mixers 29 can be increased and the IF signal branch line 23 and the LO signal branch line 24 can be extended as desired. The transmitter circuit 201 can be configured by connecting two chips 2A in series, connecting two chips 2B in series, and connecting four chips 2C vertically and horizontally and joining them together.

[0031] --Receiver Circuit Example-- Figure 4 is a diagram showing an example of a 300 GHz silicon CMOS receiver circuit mounted on the semiconductor substrate 20 of the array antenna device 100 of Figure 1. In the receiver circuit 202, mixers 29 are arranged in a 4x4 grid. Each mixer 29 is composed of, for example, one or more transistors and one or more passive elements. Each mixer 29 is electrically connected to a corresponding antenna element 11 (see Figure 1) on the printed circuit board 10 via an RF signal terminal 30 by flip-chip bonding. Note that the terminals on both sides of the RF signal terminal 30 in the figure represent ground terminals. Furthermore, a power supply terminal 31 and a ground terminal 32 provided corresponding to each mixer 29 are electrically connected to the power line and ground line on the printed circuit board 10, and each mixer 29 operates by receiving the power supply.

[0032] In the receiving circuit 202, the IF signal main line 21 and the LO signal main line 22 extend in mutually orthogonal directions outside the mixers 29 arranged in a grid pattern. Furthermore, four IF signal branch lines 23 extend from the IF signal main line 21 via buffers at the same arrangement pitch as the mixers 29 in a direction orthogonal to the IF signal main line 21, i.e., parallel to the LO signal main line 22. Similarly, multiple LO signal branch lines 24 extend from the LO signal main line 22 via buffers at the same arrangement pitch as the mixers 29 in a direction orthogonal to the LO signal main line 22, i.e., parallel to the IF signal main line 21. Each mixer 29 is arranged at each intersection of the multiple IF signal branch lines 22 and the multiple LO signal branch lines 24, and is connected to the nearest IF signal branch line 22 and LO signal branch line 24 via a buffer. For example, each mixer 29 mixes a 275 GHz RF signal supplied from the RF signal terminal 30 with a 225 GHz LO signal supplied from the LO signal branch line 24 and outputs an approximately 50 GHz IF signal to the IF signal branch line 22 .

[0033] In the IF signal main line 21, a signal phase is set to φ between each connection point of the IF signal branch line 23. １ Delay by φ １ A phase shifter 25 is inserted. Furthermore, the signal phase is adjusted by φ between each connection point of the mixer 29 in the IF signal branch line 23. ４ Delay by φ ４ The phase shifter 27 is inserted. That is, when the phase of the IF signal terminal 43 is considered as a reference, the IF signal output from each mixer 29 is shifted by φ from the reference phase. １ Phase shifter 25 and φ ４ The phase is advanced by the amount that passes through the phase shifter 27. １ Phase shifter 25 and φ ４ The phasers 27 are controlled through respective common control lines, but for simplicity these control lines and controllers are not shown.

[0034] In the LO signal main line 22, a signal phase φ is set between each connection point of the LO signal branch line 24. ３ Delay by φ ３ A phase shifter 26 is inserted. Furthermore, the signal phase is adjusted by φ between each connection point of the mixer 29 in the LO signal branch line 24. ２ Delay by φ ２The phase shifter 28 is inserted. That is, the LO signal input to the LO signal terminal 42 is φ ３ Phase shifter 26 and φ ２ The signal is input to each mixer 29 with a phase delay each time it passes through a phase shifter 28. ３ Phase shifter 26 and φ ２ The phasers 28 are controlled through respective common control lines, but for convenience these control lines and controllers are not shown.

[0035] 4, with the upper left corner as the base point, the row direction to the right is the x direction, and the column direction to the bottom is the y direction, the arrangement position of each mixer 29 is represented by natural numbers (x, y), the maximum value of x is n, the maximum value of y is m, and the IF signal terminal 43 and the LO signal terminal 42 are reference phases, the IF signal phase output from the mixer 29 at arrangement position (x, y) and the LO signal phase and RF signal phase input thereto are respectively expressed as follows: IF signal phase: (m-y)φ １ +(n-x)φ ４ LO signal phase: (x-1)φ ３ +(y-1)φ ２ RF signal phase: (my)φ １ +(n-x)φ ４ +(x-1)φ ３ +(y-1)φ ２

[0036] where φ １ =φ ２ , φ ３ =φ ４ Then, the RF signal phase is (m-1)φ １ +(n-1)φ ３ That is, an RF signal of the same phase is input to each mixer 29 regardless of the position of the mixer 29. This means that the RF signal received by the array antenna device 100 is beamformed directly ahead, that is, in the normal direction of the printed circuit board 10.

[0037] Conversely, φ １ ≠φ ２ In this case, the beam direction of the RF signal is shifted in the column direction from the normal direction of the printed circuit board 10, and φ ３ ≠φ ４In this case, the beam direction of the RF signal is shifted in the row direction from the normal direction of the printed circuit board 10. １ Phase shifter 25 and φ ２ The phase shifter 28 is appropriately controlled to change φ １ and φ ２ and adjust the relative relationship of φ ３ Phase shifter 26 and φ ４ The phase shifter 27 is appropriately controlled to set φ ３ and φ ４ By adjusting the relative relationship between the two, it is possible to freely sweep the beam of the received RF signal in the column direction and the row direction.

[0038] The receiver circuit 202 can be configured monolithically on a single semiconductor substrate 20, or alternatively, can be configured as a chiplet in which each circuit element is divided into multiple chips and these chips are connected together. FIG. 5 is a diagram showing an example of the receiver circuit 202 configured as a chiplet. For example, the receiver circuit 202 can be divided into three types of chips. Chip 2D is the chip for the IF signal line portion. In addition to the IF signal main line 21, chip 2D has two IF signal branch lines 23 and two φ １ The chip 2E is a chip for the LO signal line portion. In addition to the LO signal main line 22, the chip 2E also includes two LO signal branch lines 24 and two φ ３ The chip 2F includes a phase shifter 26. The chip 2F is a chip for the mixer portion. In addition to the four mixers 29, the chip 2F includes two IF signal branches 23, two LO signal branches 24, and four φ ４ Phase shifter 27 and four φ ２ It includes a phase shifter 28. In each chip, pads are arranged at the ends of each signal line for connection to signal lines of other chips.

[0039] By connecting a plurality of chips 2D and a plurality of chips 2E in series, the IF signal main line 21 and the LO signal main line 22 can be extended as desired. Furthermore, by connecting a plurality of chips 2F vertically and horizontally, the number of mixers 29 can be increased and the IF signal branch line 23 and the LO signal branch line 24 can be extended as desired. The receiving circuit 202 can be configured by connecting two chips 2D in series, connecting two chips 2E in series, and connecting four chips 2F vertically and horizontally and joining them together.

[0040] 4 and 5, the IF signal main line 21 and the LO signal main line 22 are １ Phase shifter 25 and φ ３ The insertion position of the phase shifter 26 is different, but this is due to the layout of the chip 2D and the chip 2E, and the receiving circuits 202 in FIGS. 4 and 5 operate in exactly the same way.

[0041] --Example of a Transmitter / Receiver Circuit-- Because an LO signal is input to the mixer in both the transmitter and receiver, a transmitter and receiver can be configured with a common LO signal line. Figure 6 is a diagram showing an example of a transmitter / receiver circuit mounted on the semiconductor substrate of the array antenna device of Figure 1. Note that for each transmitter / receiver, a corresponding number of transmitting and receiving antenna elements 11 must be arranged on the printed circuit board 10.

[0042] The transmitting / receiving circuit 203 is composed of a transmitting circuit 201 and a receiving circuit 202. The transmitting circuit 201 is the same as the transmitting circuit 201 in Fig. 2, and the receiving circuit 202 is a left-right inverted version of the receiving circuit 203 in Fig. 4. In the transmitting / receiving circuit 203, the LO signal main line 22 and the LO signal branch line 24 are shared by the transmitting circuit 201 and the receiving circuit 202. In this way, the transceiver can be easily configured.

[0043] <<Effects>> As described above, according to this embodiment, the use of array antennas in a 300 GHz silicon CMOS transmitter and receiver can increase transmission power and reception power. Furthermore, by appropriately controlling the phase shifters inserted at various points in the IF signal main line and branch line and the LO signal main line and branch line, the transmission RF signal and reception RF signal can be freely swept in two dimensions, vertically and horizontally. In addition, beam squint can be easily mitigated.

[0044] Furthermore, by arranging the mixer, LO signal generator, controller, etc. on the same layer of the semiconductor substrate 20, heat generated from the various circuit elements is less likely to be trapped and is easier to dissipate than when they are arranged in a stacked configuration, which makes it possible to prevent performance degradation of the transmitter circuit 201, receiver circuit 202, and transmitter / receiver circuit 203 due to heat generated by the semiconductor substrate 20.

[0045] Furthermore, the transmitter and receiver circuits employed in this embodiment have a circuit topology that is easy to convert into chiplets. Therefore, by configuring these circuits as chiplets, the array size can be easily made scalable according to the required transmission and reception power.

[0046] The mixers 29 do not need to be arranged in an orderly grid pattern, but may be arranged in a staggered pattern, for example. The IF signal branch lines 23 and the LO signal branch lines 24 do not need to be arranged in an orderly manner at equal intervals, either. For example, two IF signal branch lines 23 may be arranged between adjacent rows of mixers 29, or two LO signal branch lines 24 may be arranged between adjacent columns of mixers 29.

[0047] The antenna elements 11 may be mounted on the redistribution layer (RDL) of the semiconductor substrate 20 instead of on the printed circuit board 10. In this way, an array antenna device can be realized on a single chip.

[0048] Needless to say, the number of antenna elements 11 is not limited to 16 (4 × 4). The antenna gain can be increased by increasing the number of antenna elements 11. For example, by increasing the number of antenna elements 11 to 1024 (32 × 32), the antenna gain is 64 times greater than when there are 16 antenna elements 11. When the number of antenna elements 11 is large, the length of the IF signal main line and branch line and the LO signal main line and branch line increases, which may result in significant signal attenuation at the end of the signal line. Therefore, a buffer circuit may be provided at an appropriate point along the signal line to enable transmission of a signal of a certain magnitude or greater to the end.

[0049] In addition, when using a chiplet configuration, the chips for the IF signal part and the LO signal part each have a larger φ １ Phase shifter 25 and φ ３ A phase shifter 26 may be included, and more mixers 29, IF signal branch 23, LO signal branch 24, φ may be included on the chip of the mixer section. ４ Phase shifter 27 and φ ２ A phaser 28 may also be included.

[0050] The antenna elements 11 may be mounted on the redistribution layer (RDL) of the semiconductor substrate 20 instead of on the printed circuit board 10. In this way, an array antenna device can be realized on a single chip.

[0051] φ １ Phase shifter 25 and φ ２ Either one of the phase shifters 28 and / or φ ３ Phase shifter 26 and φ ４ Either one of the phase shifters 27 may be omitted or replaced with a phase shifter with a fixed phase amount. ２ Phase shifter 28 and φ ４ The phase shifter 27 must be placed in a narrow area, and in some cases it may not be possible to place it there. １ Phase shifter 25 and φ ３ The phase shifter 26 remains the same, and φ ２ Phase shifter 28 and φ ４The phase shifter 27 may be replaced with a phase shifter with a fixed phase amount such as meander wiring, etc. In this case, the beam sweep range is reduced, but the beam sweep itself is still possible.

[0052] The semiconductor substrate 20 may be constructed of a compound semiconductor such as GaAs, InP, or InGaAlP, or a bipolar CMOS such as SiGe-BiCMOS. Because compound semiconductors and BiCMOS have excellent high-frequency characteristics, it is possible to provide a power amplifier for amplifying the 300 GHz RF signal output from the mixer 29 downstream of the mixer 29, i.e., between the antenna element 11 and the mixer 29, in the transmitter. Also, it is possible to provide a low-noise amplifier 62 for amplifying the weak 300 GHz RF signal received by the antenna element 11 upstream of the mixer 29, i.e., between the antenna element 11 and the mixer 29, in the receiver. Although compound semiconductors and BiCMOS are more expensive to manufacture than silicon CMOS, they can increase the transmission and reception power per antenna element 11, thereby reducing the number of transmitters and receivers required to ensure the required transmission and reception power. In other words, compound semiconductors and BiCMOS can achieve greater transmission and reception power with a smaller circuit scale than silicon CMOS, thereby overcoming the problem of increased manufacturing costs.

[0053] As described above, the embodiments have been described as examples of the technology of the present invention. For this purpose, the accompanying drawings and detailed description have been provided. Therefore, the components described in the accompanying drawings and detailed description may include not only components essential for solving the problem, but also components that are not essential for solving the problem in order to exemplify the above technology. Therefore, the fact that these non-essential components are described in the accompanying drawings or detailed description should not be interpreted as immediately indicating that these non-essential components are essential. Furthermore, because the above-described embodiments are intended to exemplify the technology of the present invention, various modifications, substitutions, additions, omissions, etc. may be made within the scope of the claims or their equivalents.

[0054] The array antenna device according to the present invention can be widely used as a wireless communication device or wireless sensor that uses not only the 300 GHz band but also the terahertz band of 100 GHz or more.

[0055] REFERENCE SIGNS LIST 100 Array antenna device 10 Printed circuit board (first layer) 11 Antenna element 110 Antenna element arrangement area (arrangement area for a plurality of antenna elements) 20 Semiconductor substrate (second layer) 21 IF signal main line 22 LO signal main line 23 IF signal branch line 24 LO signal branch line 25 φ １ Phase shifter (first phase shifter) 26 φ ２ Phase shifter (fourth phase shifter, first phase shifter, third phase shifter) 27 φ ３ Phase shifter (second phase shifter) 28 φ ４ Phase shifter (third phase shifter, second phase shifter, third phase shifter) 29 Mixer 290 Mixer placement area (placement area of ​​multiple mixers) 2A, 2D Chip (first chip) 2B, 2E Chip (second chip) 2C, 2F Chip (third chip)

Claims

1. A antenna element array comprising: a first layer having a plurality of antenna elements arranged in a grid pattern; and a second layer overlapping the first layer, wherein the second layer has: an IF (intermediate frequency) signal main line and an LO (local oscillator frequency) signal main line extending in mutually orthogonal directions; a plurality of IF signal branch lines and a plurality of LO signal branch lines extending in respective orthogonal directions to the IF signal main line and the LO signal main line; and a plurality of mixers arranged in the same grid pattern as the plurality of antenna elements at each intersection of the plurality of IF signal branch lines and the plurality of LO signal branch lines and electrically connected to the plurality of IF signal branch lines, the plurality of LO signal branch lines, and the plurality of antenna elements, wherein a first phase shifter is provided at least either between each connection point of the plurality of IF signal branch lines in the IF signal main line or between each connection point of the plurality of mixers in the plurality of LO signal branch lines, An array antenna device characterized in that a second phase shifter is provided at least either between each connection point of the multiple LO signal branch lines in the LO signal main line or between each connection point of the multiple mixers in the multiple IF signal branch lines, and the first layer and the second layer are stacked vertically so that the arrangement area of ​​the multiple antenna elements in the first layer and the arrangement area of ​​the multiple mixers in the second layer overlap in a planar view.

2. The array antenna device as described in claim 1, wherein the first phase shifter is provided between each connection point of the multiple IF signal branch lines in the IF signal main line, and a third phase shifter or meander wiring is provided between each connection point of the multiple mixers in the multiple LO signal branch lines.

3. The array antenna device as described in claim 1, wherein the second phase shifter is provided between each connection point of the multiple LO signal branch lines in the LO signal main line, and a third phase shifter or meander wiring is provided between each connection point of the multiple mixers in the multiple IF signal branch lines.

4. The array antenna device as described in claim 1, wherein the first phase shifter is provided between each connection point of the multiple IF signal branch lines in the IF signal main line, the second phase shifter is provided between each connection point of the multiple LO signal branch lines in the LO signal main line, a third phase shifter or meander wiring is provided between each connection point of the multiple mixers in the multiple IF signal branch lines, and a fourth phase shifter or meander wiring is provided between each connection point of the multiple mixers in the multiple LO signal branch lines.

5. The array antenna device as described in claim 4, wherein the IF signal main line and the first phase shifter are implemented on a first chip, the LO signal main line and the second phase shifter are implemented on a second chip, the multiple mixers, the multiple IF signal branches, the multiple LO signal branches, the third phase shifter or its alternative meander wiring, and the fourth phase shifter or its alternative meander wiring are implemented on a third chip, and the first chip and the second chip are connected to the third chip to form the second layer.

6. The array antenna device of claim 5, wherein a plurality of the first chips are connected in series to extend the IF signal main line, a plurality of the second chips are connected in series to extend the LO signal main line, a plurality of the third chips are connected vertically and horizontally to extend the plurality of IF signal branch lines and the plurality of LO signal branch lines, respectively, and the plurality of the first chips connected in series and the plurality of the second chips connected in series are connected to the plurality of the third chips connected vertically and horizontally to form the second layer.

7. An array antenna device according to any one of claims 1 to 6, wherein at least one of the plurality of IF signal branches and the plurality of LO signal branches are arranged in parallel at the same pitch as the plurality of antenna elements.

8. An array antenna device according to any one of claims 1 to 6, wherein the first layer is a printed circuit board, and the second layer is a semiconductor substrate.

9. The array antenna device according to claim 7, wherein the first layer is a printed circuit board, and the second layer is a semiconductor substrate.

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