Transistor device comprising emitter based on metalloid material of two-dimensional structure, driving method thereof, and manufacturing method thereof

Abstract

This transistor device may comprise: an emitter which is located on a substrate including a dielectric material, made of a metalloid material of a two-dimensional structure, and configured to selectively emit electrons; a source electrode which is electrically in contact with one region of the emitter; a drain electrode which is located on the substrate spaced apart from the emitter and electrically separated from the source electrode; and a gate structure which is located on the emitter and configured to apply, to the emitter, a gate voltage for controlling electron emission by the emitter by modulating a work function of the emitter. The transistor device may be a three-terminal or four-terminal field effect transistor including a vacuum region as a moving path of emission electrons and configured to adjust an emission current by changing the Fermi level of an emitter front end of a two-dimensional metalloid material by applying a gate voltage.

Description

Transistor device including an emitter based on a two-dimensional metalloid material, and a driving method and manufacturing method thereof

[0001] The embodiments relate to transistor devices, and particularly to transistor devices using a vacuum channel. More specifically, the embodiments relate to a technique for enabling modulation of the amount of current passing through and across a vacuum channel by applying a gate voltage to change the Fermi level and work function of the emitter in a transistor device using a vacuum as a channel, the transistor device including an emitter based on a semi-metallic material having a two-dimensional structure and high conductivity.

[0002] In a field effect transistor (FET) device, the channel is primarily composed of a solid semiconductor material. For example, Korean Patent Publication No. 10-0973124 discloses a prior art FET having a channel comprising an oxide semiconductor material containing indium and zinc.

[0003] The high-frequency performance of FETs with solid-state channels is limited by the velocity limitations of charge carriers (i.e., electrons and holes) in the semiconductor material forming the channel, which in turn imposes limitations on device design, such as the distance between the source and drain regions and the length of the gate electrode. For example, reducing the distance between the source and drain regions (i.e., channel length) to allow the FET to operate at higher frequencies reduces the maximum allowable source-drain voltage and increases the capacitance of the gate dielectric, which ultimately limits the output power, gain, and efficiency of the device.

[0004] Therefore, in conventional high-frequency power devices based on solid-state channels, the carrier mobility cannot exceed the saturation velocity due to scattering effects within the solid channel. If the channel length is reduced to compensate for this, other parameters, such as output impedance and capacitance, deteriorate, leading to a decrease in output power.

[0005] Meanwhile, the speed of electrons, which are charge carriers, can increase significantly in a vacuum. Since all scattering components except electron-electron scattering are reduced in a vacuum, electrons passing through a vacuum channel can move at much faster speeds than when passing through a solid-state channel. For example, the speed of an electron accelerated to a kinetic energy of several hundred eV is about 10 9 cm / s, whereas in a solid channel it is 10 7 The speed is limited to a saturation speed of about cm / s.

[0006] To utilize a vacuum as a path for charge carriers, electrons must be emitted from the emitter into the space. Methods for emitting electrons include electron emission using thermal energy, electron emission using optical energy, and electron emission using the quantum mechanical tunneling effect of microscopic particles by applying an electric field. Among these, electron-emitting devices utilizing the electric field effect based on tunneling can be sufficiently manufactured using a top-down planar lithography method.

[0007] In order to induce field emission, a large electric field must exist near the tip of the emitter where electron emission occurs. However, if the tip of the emitter has a sharp geometric structure, the charge distribution inside the emitter tip is reorganized to compensate for the externally applied electric field, locally increasing the charge density, thereby inducing a local field enhancement effect. In addition, the local field enhancement effect induced by the geometric shape of the emitter tip can also be achieved at the edge of a two-dimensional material with high conductivity.

[0008] However, there has been no transistor device configured to emit electrons through quantum mechanical tunneling by utilizing the field enhancement effect that occurs at the edge of a two-dimensional material with such high conductivity. In addition, in existing vacuum devices, the gate electrode that controls electron emission must be located between the drain electrode and the emitter. In this case, the gap between the drain electrode and the emitter increases, which causes damage in terms of the applied voltage for device operation and the movement speed of electrons, and there is a problem that the operating speed of the device is limited.

[0009] According to one aspect of the present invention for solving the problems of the above-mentioned prior art, a transistor device can be provided in which an emitter is formed of a semi-metal material having a two-dimensional structure and high conductivity, a voltage is applied to the emitter by a gate structure to change the Fermi level and work function of the emitter, thereby modulating the amount of current to perform a switching operation and a rectifying function, and a driving method and a manufacturing method of such a transistor device.

[0010] A transistor device according to one aspect of the present invention comprises: an emitter positioned on a substrate including a dielectric material, the emitter being made of a two-dimensional metalloid material and configured to selectively emit electrons; a source electrode in electrical contact with a region of the emitter; a drain electrode positioned on the substrate and spaced apart from the emitter and electrically isolated from the source electrode; and a gate structure positioned on the emitter and configured to apply a gate voltage to the emitter to control electron emission by the emitter by modulating a work function of the emitter.

[0011] A transistor device according to one embodiment is configured such that when a gate voltage and a drain voltage are applied to the emitter so that the emitter emits electrons, a vacuum channel through which electrons can move is formed between a tip of the emitter facing the drain electrode and the drain electrode.

[0012] In one embodiment, the distance between the gate structure and the drain electrode is greater than or equal to the distance between the tip of the emitter and the drain electrode.

[0013] In one embodiment, the tip of the emitter is positioned to protrude in a direction toward the drain electrode relative to the gate structure, and the shortest distance between the tip of the emitter and the gate structure is 40 nm or less.

[0014] In one embodiment, the two-dimensional structure of the semi-metallic material is parallel to the surface of the substrate, such that the emitter is configured to emit electrons from a tip of the emitter in a direction parallel to the surface of the substrate.

[0015] In one embodiment, the tip of the emitter has a radius of curvature less than a preset value such that a field enhancement effect is induced at the tip of the emitter by a voltage between the source electrode and the drain electrode.

[0016] In one embodiment, the emitter comprises one or more layers of graphene or reduced graphene oxide.

[0017] In one embodiment, the gate structure includes a gate insulating film positioned on the emitter; and a gate electrode positioned on the gate insulating film and configured to apply the gate voltage.

[0018] In one embodiment, the gate electrode is configured to apply a first voltage to the emitter, the magnitude of the first voltage being determined based on a quantum capacitance of the emitter, which is determined by a voltage between the source electrode and the drain electrode.

[0019] In one embodiment, a second voltage is applied between the source electrode and the drain electrode. At this time, the magnitude of the first voltage is greater than or equal to -10 V and less than 0 V or greater than 0 V and less than or equal to 10 V, and the magnitude of the second voltage is greater than 0 V and less than or equal to 200 V.

[0020] A field effect transistor according to one aspect of the present invention comprises a transistor device according to any one of the above-described embodiments, configured to operate in a vacuum; and a conductive lead electrically connected to the source electrode, the gate structure, and the drain electrode of the transistor device.

[0021] A method of operating a transistor device according to one aspect of the present invention comprises the steps of preparing a source electrode positioned on a substrate including a dielectric material, and an emitter positioned on the substrate and electrically connected to the source electrode and made of a two-dimensional metalloid material; modulating a work function of the emitter by applying a gate voltage to the emitter by a gate structure positioned on the emitter; and emitting electrons from a tip portion of the emitter to which the gate voltage and drain voltage are applied in the direction of a drain electrode electrically separated from the source electrode and spaced apart from the emitter.

[0022] In one embodiment, the step of emitting electrons comprises emitting electrons from the emitter into a vacuum region between a tip of the emitter and the drain electrode.

[0023] In one embodiment, the step of modulating the work function of the emitter includes the steps of applying a first voltage to a tip of the emitter by the gate electrode; and determining a magnitude of the first voltage based on a quantum capacitance of the emitter determined by a voltage between the source electrode and the drain electrode.

[0024] A method of operating a transistor device according to one embodiment further includes the step of applying a second voltage between the source electrode and the drain electrode. At this time, the first voltage is greater than or equal to -10 V and less than 0 V or greater than 0 V and less than or equal to 10 V, and the second voltage is greater than 0 V and less than or equal to 200 V.

[0025] A method for manufacturing a transistor device according to one aspect of the present invention comprises the steps of forming an emitter having a two-dimensional structure made of a semi-metallic material on a substrate including a dielectric material; forming a gate insulating film on the semi-metallic material layer; forming a gate electrode on the gate insulating film; partially removing the dielectric material; and forming a source electrode electrically connected to a region of the emitter and a drain electrode positioned apart from the emitter. At this time, the gate electrode is positioned between the source electrode and the drain electrode.

[0026] The step of partially removing the genetic material includes the step of forming an undercut below the semi-metal material layer.

[0027] In one embodiment, the step of forming the gate insulating film includes the step of forming an insulating layer with a thickness less than or equal to a distance between the gate electrode and the emitter, such that a voltage applied by the gate electrode can modulate a work function of the emitter.

[0028] In one embodiment, the step of forming the emitter comprises the steps of forming a two-dimensional structured metalloid material layer on another substrate, the edge of which has a radius of curvature less than a preset value; and the step of transferring the metalloid material layer onto the substrate.

[0029] A transistor device according to another aspect of the present invention comprises: a first transistor element; and a second transistor element opposite to the first transistor element.

[0030] At this time, each of the first transistor element and the second transistor element comprises: an emitter positioned on a substrate including a dielectric material, the emitter being made of a two-dimensional metalloid material and configured to selectively emit electrons; a source electrode in electrical contact with a region of the emitter; a drain electrode positioned on the substrate and spaced apart from the emitter and electrically separated from the source electrode; and a gate structure positioned on the emitter and configured to apply a gate voltage to the emitter to control electron emission by the emitter by modulating a work function of the emitter.

[0031] Additionally, the first transistor element and the second transistor element are arranged so that the emission directions of electrons from the emitter toward the drain electrode are opposite to each other.

[0032] In one embodiment, the drain electrode of the first transistor element and the drain electrode of the second transistor device are formed integrally with each other.

[0033] In one embodiment, the drain electrode of each of the first transistor element and the second transistor element is formed on the substrate at a height lower than the upper surface of the emitter.

[0034] A transistor device according to one aspect of the present invention utilizes a vacuum region as a channel and a two-dimensional semi-metallic material as an emitter, and is configured to induce quantum tunneling of electrons by a field enhancement effect at the edge of the emitter. In this transistor device, unlike conventional solid-channel-based transistors, electrons emitted through quantum tunneling can move quickly without being affected by lattice scattering or the like, and thus has the advantage of being able to operate efficiently under high-frequency conditions.

[0035] A transistor device according to one aspect of the present invention can be implemented as a three-terminal or four-terminal field effect transistor. In addition, in the transistor device according to one aspect of the present invention, the gate electrode is not positioned between the emitter and drain electrodes as in the prior art, but is positioned in the channel portion of the emitter, so there is no physical limitation in reducing the length of the vacuum channel, which has the advantage of improving the operating frequency of the transistor.

[0036] For example, conventional high-frequency devices that utilize solid semiconductor materials as channels have a problem in that the output power decreases to less than several μW under high-frequency conditions of 300 GHz or more, and the output power continues to decrease as the operating frequency increases. On the other hand, a transistor device according to one aspect of the present invention has a cutoff frequency of about 0.41 to 1.72 THz and a maximum oscillation frequency of about 6.4×10 under conditions where the source-drain voltage is 90 to 100 V. 2 1.9×10 4 As for THz, it has the advantage of being able to operate without deterioration of device performance even in the terahertz (THz) band.

[0037] FIG. 1 is a perspective view of a transistor device using a two-dimensional metalloid material as an emitter according to one embodiment.

[0038] Figure 2 is a cross-sectional view of the transistor device illustrated in Figure 1.

[0039] FIG. 3 is a flowchart showing each step of a method for driving a transistor device according to one embodiment.

[0040] FIG. 4 is a conceptual diagram for explaining the operation of a transistor device according to one embodiment.

[0041] FIG. 5 is a diagram schematically showing an equivalent circuit structure of a transistor device according to one embodiment.

[0042] FIG. 6 is a graph showing the current-voltage characteristics of a transistor device according to one embodiment.

[0043] FIGS. 7a and 7b are graphs showing changes in the band structure of each region of the emitter according to voltage conditions applied to each of the source electrode, drain electrode, and gate electrode in a transistor device according to one embodiment.

[0044] FIGS. 8A and 8B are graphs showing potential distributions in an area of ​​a device and an adjacent space according to voltage conditions applied to each of a source electrode, a drain electrode, and a gate electrode in a transistor device according to one embodiment.

[0045] FIG. 9 is a graph showing the change in transconductance according to the change in gate voltage for each source-drain voltage condition in a transistor device according to one embodiment.

[0046] FIG. 10a is a graph showing the change in cutoff frequency according to the change in gate voltage for each source-drain voltage condition in a transistor device according to one embodiment.

[0047] FIG. 10b is a graph showing the change in maximum vibration frequency according to the change in gate voltage for each source-drain voltage condition in a transistor device according to one embodiment.

[0048] FIG. 11 is a graph showing changes in the work function of the emitter tip according to changes in the shortest distance between the gate electrode and the emitter tip, source-drain voltage conditions, and gate voltage modulation in a transistor device according to one embodiment.

[0049] FIG. 12 is a graph showing the current-voltage characteristics when the length of the vacuum channel is changed in a transistor device according to one embodiment.

[0050] FIG. 13 is a cross-sectional view of a transistor device using a two-dimensional metalloid material as an emitter according to another embodiment.

[0051] FIGS. 14a and 14b are graphs comparing current-voltage characteristics according to voltage conditions applied to the source electrode, drain electrode, and gate electrode in the transistor device illustrated in FIG. 13.

[0052] FIGS. 15a to 15c are graphs showing changes in the band structure of each region of the emitter according to voltage conditions applied to each of the source electrode, drain electrode, and gate electrode in the transistor device illustrated in FIG. 13.

[0053] Fig. 16 is a graph showing the change in transconductance according to the change in gate voltage under each source-drain voltage condition in the transistor device illustrated in Fig. 13.

[0054] Fig. 17 is a flowchart showing each step of a method for manufacturing a transistor device according to one embodiment.

[0055] FIG. 18a is a cross-sectional view of a transistor device according to another embodiment.

[0056] Figure 18b is a plan view of the transistor device illustrated in Figure 18a.

[0057] FIG. 19 is an optical microscope photograph of a transistor device manufactured according to the embodiment illustrated in FIGS. 18a and 18b.

[0058] FIGS. 20A and 20B are graphs showing emission current characteristics of a transistor device according to the embodiment illustrated in FIGS. 18A and 18B.

[0059] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

[0060] In describing the embodiments of this specification, if a detailed description of a known configuration or function is judged to obscure the gist of the embodiments of this specification, a detailed description thereof will be omitted. In addition, parts of the drawings that are not related to the description of the embodiments of this specification have been omitted, and similar parts have been designated with similar drawing reference numerals.

[0061] In the embodiments of this specification, when a component is said to be "connected," "coupled," or "connected" to another component, this may include not only a direct connection, but also an indirect connection in which another component exists in between. Furthermore, when a component is said to "include" or "have" another component, unless otherwise specifically stated, this does not exclude the other component, but rather implies that the other component may be included.

[0062] In the embodiments of this specification, the terms first, second, etc. are used only for the purpose of distinguishing one component from another component, and do not limit the order or importance between components unless specifically stated otherwise. Therefore, within the scope of the embodiments of this specification, a first component in an embodiment may be referred to as a second component in another embodiment, and similarly, a second component in an embodiment may be referred to as a first component in another embodiment.

[0063] Unless otherwise defined, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. Terms defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology, and will not be interpreted in an idealized or overly formal sense unless explicitly defined herein.

[0064] When a layer is referred to herein as being "on" another layer or substrate, it may be formed directly on the other layer or substrate, or a third layer may be interposed therebetween. Furthermore, directional expressions such as "upper," "upper," and "top" in this specification may be interpreted to mean "lower," "lower," and "bottom," depending on the reference. In other words, expressions of spatial direction should be understood as relative directions and should not be construed as limiting them to mean absolute directions.

[0065] FIG. 1 is a perspective view of a transistor device using a two-dimensional metalloid material as an emitter according to one embodiment, and FIG. 2 is a cross-sectional view of the transistor device illustrated in FIG. 1.

[0066] Referring to FIGS. 1 and 2, a transistor device according to one embodiment includes a source electrode (10), an emitter (40) made of a two-dimensional metalloid material, a gate structure (20, 50) configured to apply a voltage to the emitter (40), and a drain electrode (30) electrically separated from the source electrode (10) and positioned apart from the emitter (40).

[0067] A transistor device according to embodiments may be positioned on a substrate (100) having a surface made of a dielectric material. In the present specification, the transistor device or a component thereof being positioned on the substrate (100) may mean that the transistor device or a component thereof is in direct contact with the substrate (100), or may mean that the transistor device or a component thereof is indirectly disposed on the substrate (100) with one or more other material layers interposed therebetween.

[0068] The substrate (100) having a surface made of a dielectric material may be entirely made of the dielectric material, or may have a form in which a dielectric material layer thick enough to prevent insulation breakdown during operation of the transistor device is formed on a base member made of another material. In addition, it is preferable that the surface of the substrate (100) have high thermal conductivity in order to improve the performance of the transistor device.

[0069] The source electrode (10) and the drain electrode (30) are made of metal or any other conductive material. The source electrode (10) is in electrical contact with the emitter (40), and the drain electrode (30) is electrically separated from the source electrode (10) and the emitter (40). A gate structure (20, 50) is positioned on a region of the emitter (40) between the source electrode (10) and the drain electrode (30). That is, the gate structure (20, 50) is positioned closer to the source electrode (10) than to the drain electrode (50) in comparison with the drain electrode (50). In addition, in the transistor device according to the embodiments, the source electrode (10), the gate electrode (20), and the drain electrode (30) are not in electrical contact with each other.

[0070] In this specification, being electrically contacted means that charge carriers are physically interfered with or controlled so that they can move from one part to another through direct physical contact with another medium. For example, in FIGS. 1 and 2, the source electrode (10) is disposed on the substrate (100) and is in electrical contact with the emitter (40), but the gate electrode (20) and the drain electrode (30) are not in electrical contact with the emitter (40).

[0071] The drain electrode (40) is disposed on the substrate (100), but is disposed apart from the emitter (40) for the purpose of designing the operation of the device. A vacuum region exists between the tip (B) of the emitter (40) and the drain electrode (30) in the space between the gate electrode (20) and the drain electrode (30) to serve as a vacuum channel. The tip (B) of the emitter (40) does not come into contact with other components of the transistor device (e.g., the gate electrode (20), the drain electrode (30), etc.) other than the vacuum channel.

[0072] Meanwhile, other regions of the emitter (40) excluding the tip (B) may be in contact with the gate insulating film (50), the source electrode (10), the substrate (100), etc. of the gate structure. In Fig. 1, region (A) represents a conductive contact region between the source electrode (10) and the emitter (40) in a cross-section, and a conductive contact may be formed in a form in which region (A) is extended two-dimensionally along the surface of the emitter (40) having a two-dimensional structure.

[0073] The positional relationship between the source electrode (10), the emitter (40), the gate structure (20, 50), and the drain electrode (30) in the transistor device according to the embodiments is configured so that a path for the emission electrons to move from the source electrode (10) through the gate structure (20, 50), the tip (B) of the emitter (40), and the vacuum channel toward the drain electrode (30) can be secured.

[0074] The emitter (40) is electrically connected to the source electrode (10) at the conductive contact area (A) and is made of a semi-metallic material having a two-dimensional structure. Here, the two-dimensional structure means a shape that is overall a smooth flat plate shape and in which the tip (B) of the emitter (40) has a radius of curvature less than a preset value so as to induce a field enhancement effect. For example, the two-dimensional structure may refer to a collection of planar molecules with an atomic-scale thickness, but this is exemplary and does not mean that all atoms constituting the emitter (40) are on the same perfect geometric plane.

[0075] The conductive contact area (A) of the emitter (40) may be made of a different conductive material from the semi-metallic material forming the other portion of the emitter (40), or may simply refer to a portion where the emitter (40) made of the semi-metallic material contacts the source electrode (10). In addition, the tip (B) of the emitter (40) facing the drain electrode (30) and the drain electrode (30) are spaced apart from each other, so that a vacuum region is located between the emitter (40) and the drain electrode (30).

[0076] In this specification, the semi-metallic material constituting the emitter (40) refers to a material having a high electrical conductivity that allows electrons to be emitted from the tip (B) of the emitter (40) through quantum tunneling when a predetermined gate voltage is applied to the emitter (40) and the emitted electrons to traverse a vacuum channel by an electric field. In the transistor according to the embodiments, the semi-metallic material constituting the emitter (40) includes graphene, but is not limited thereto. In addition, in this specification, graphene may include graphene-based composites such as reduced graphene oxide in addition to pure graphene.

[0077] Additionally, in this specification, the term "vacuum region" refers to a region that functions as a channel for the movement of charge carriers when the gas density is relatively low compared to normal atmospheric conditions. The transistor device according to the embodiments may be configured to operate in a vacuum.

[0078] When a transistor operates in a vacuum state, when a gate voltage is applied to the semi-metallic material of the emitter (40) through the gate structure (20, 50), electrons can be emitted from the tip (B), which is the edge of the emitter (40), by quantum tunneling. The transistor device according to the embodiments is configured to control the Fermi level and work function of the semi-metallic material through the gate voltage, thereby controlling the number of emitted electrons, i.e., the amount of emission current crossing the vacuum channel. Such a transistor device can be implemented as, for example, a three-terminal or four-terminal field effect transistor (FET).

[0079] In one embodiment, the semi-metallic material of the emitter (40) has a two-dimensional structure composed of a single layer or multiple layers. For example, the emitter (40) may be a flat plate having a thin and sharp edge. When the tip (B) of the emitter (40) has a sharp and sharp geometric structure, the charge distribution of the tip (B) is reorganized to compensate for an externally applied electric field, thereby locally increasing the charge density, thereby inducing a local electric field enhancement effect. This electric field enhancement effect plays a role in inducing quantum tunneling of electrons from the emitter (40) to the vacuum channel even when a relatively low gate voltage is applied.

[0080] The field enhancement effect is induced by a structure having a radius of curvature less than a preset value, and for example, the field enhancement effect can occur at the edge of a two-dimensional material having a thickness of less than a nanometer. Therefore, a strong field enhancement effect can be obtained by using a material having high conductivity, such as graphene, as an emitter (40) of a two-dimensional structure. Under the condition of applying the same current density, the electric field in the region adjacent to the tip (B) of the graphene emitter (40) is larger than that of conventional emitters having a larger radius of curvature, which increases charge accumulation and the Fermi level at the tip (B) of the graphene emitter (40), thereby increasing the emission current.

[0081] In one embodiment, the edge of the emitter (40) may be processed into a tapered shape in which the thickness of the emitter (40) becomes thinner toward the end thereof. However, the shape of the emitter (40) is not limited thereto, and the two-dimensional shape of the emitter (40) in the present specification may refer to a sheet shape in which the thickness is smaller than a certain level compared to the length and width thereof, so that the radius of curvature of the edge is sufficiently small.

[0082] In conventional transistor devices, a flat-plate-shaped emitter has the disadvantage of being difficult to generate a high electric field compared to a structure with a sharp tip-shaped tip. In contrast, embodiments of the present invention overcome this problem by utilizing the edge of a two-dimensional semi-metallic material as the tip (B) of the emitter (40).

[0083] According to embodiments, when a FET is implemented by using the edge of a planar graphene as the tip (B) of an emitter (40), since graphene is mechanically strong, there is an advantage in that the emitter (40) is not destroyed or excessively distorted in shape due to Coulomb stress when a voltage is applied between the source electrode (10) and the channel. In addition, since graphene is chemically inactive, molecules such as water and hydrocarbons that can be easily adsorbed in the atmosphere at low temperatures do not easily form strong chemical bonds with graphene, and such bonds can be removed through a process of heating to a certain temperature (e.g., 300°C or higher) in a vacuum. In addition, graphene has very high electrical conductivity, allowing a large current to flow without causing excessive power dissipation.

[0084] In addition, the graphene forming the emitter (40) has high electrical conductivity when floating in a vacuum, resulting in high field emission current and transconductance, and has very high thermal conductivity, which can minimize temperature rise of the emitter (40) due to field emission, and when combined with the two-dimensional structural characteristics due to high heat release, heat loss due to thermal radiation is relatively large, which can efficiently reduce the temperature difference with the nearby medium forming surface contact.

[0085] At this time, due to the two-dimensional structure of the graphene emitter, the electric field applied to the emitter tip decreases within a similar interval corresponding to the radius of curvature of the emitter tip. For example, the radius of curvature of single-layer graphene (approximately 0.14 nm) is much smaller than the tunneling distance of electrons (approximately 1 nm), so the electric field can be dramatically reduced within the interval where the Fermi level of the graphene emitter tip becomes equal to the vacuum level.

[0086] In addition, the potential barrier for electron emission at the tip of the graphene emitter increases rapidly with the angle with respect to the propagation direction of the emitted electrons, which reduces the ratio of the emission current generated at a large angle with respect to the graphene plane to the total emission current. The total energy of electrons inside the graphene is equal to the sum of the transverse energy and the longitudinal energy, but only the longitudinal component can be converted into RF power. In the transistor device according to the embodiments, the emitted electrons contain little transverse energy, which is advantageous for the operating efficiency of the transistor.

[0087] Furthermore, in graphene emitters with a two-dimensional structure, electrons above the Fermi level have a much higher probability of quantum tunneling compared to emitters with a larger radius of curvature, while electrons below the Fermi level have a much lower probability of quantum tunneling. This increase and decrease in tunneling probability depending on the energy level induces cooling of electron emission from the emitter due to the emission of high-energy electrons and reduces the temperature increase due to electron emission below the Fermi level. As a result, the crossover temperature, where the energy of field emission transitions from heating to cooling, is significantly reduced. The crossover temperature is a factor that greatly determines the temperature of the emitter, and when graphene is used as an emitter, the reduced crossover temperature can prevent the durability of the emitter from deteriorating due to excessive temperature.

[0088] In one embodiment, the edge of the emitter (40) may be parallel to the surface of the substrate (100). In the cross-sectional view illustrated in FIG. 2, the region connecting the tip (B) of the emitter (40) and the conductive contact between the emitter (40) and the source electrode (10), i.e., the emitter (40) channel region, may be a straight line parallel to the substrate (100). However, this is exemplary, and the emitter (40) may be curved in any direction as long as it matches the shape of the gate electrode (20).

[0089] In one embodiment, the tip (B) of the emitter (40) is positioned to protrude in the direction toward the drain electrode (30) compared to the gate structures (20, 50). In addition, the tip (B) of the emitter (40) is positioned within a vacuum channel region formed by partially removing the surface of the substrate (100), and thus does not come into contact with other components of the transistor device, such as the substrate (100), the gate insulating film (50), and the gate electrode (20). The position of the emitter (40) minimizes the possibility that electrons emitted from the tip (B) come into contact with other components. However, if the tip (B) is too far from the gate electrode (20), the shielding effect for the gate voltage is aggravated, making it difficult to control the emission current. Therefore, the position may be appropriately determined so that a desired frequency response characteristic can be implemented by applying a gate voltage.

[0090] However, in another embodiment, the tip (B) of the emitter (40) may be positioned at the same distance from the drain electrode (30) as compared to the gate structure (20, 50).

[0091] Since the channel between the tip (B) of the two-dimensional emitter (40) and the drain electrode (30) is made of vacuum, even if a gate voltage is applied to the emitter (40) to induce a field emission effect, no insulation breakdown occurs, making it suitable as a medium for transmitting emitted electrons. This is different from conventional solid-channel based transistors, which can use only a small number of dielectric materials capable of withstanding high electric fields as channel materials.

[0092] The gate structure (20, 50) refers to a structure for controlling electron emission by the emitter (40) by modulating the work function of the emitter (40) by applying a gate voltage, and may include, for example, a gate insulating film (50) on the emitter (40) and a gate electrode (20) on the gate insulating film (50). The gate insulating film (50) may be made of various dielectric materials such as oxides. The gate electrode (20) can efficiently modulate the Fermi level of the emitter (40) by applying a gate voltage having a voltage range in which dielectric breakdown of the gate insulating film (50) does not occur to the contact region (i.e., the emitter channel region) between the gate insulating film (50) and the emitter (40). Depending on the shape of the gate insulating film (50), the shape of the emitter channel region may be flat, curved, or any other arbitrary shape.

[0093] The drain electrode (30) is positioned apart from the emitter (40). For example, the drain electrode (30) may be positioned at a position displaced in a horizontal direction from the tip (B) of the emitter (40) to the surface of the substrate (100). The surface of the drain electrode (30) onto which the current emitted from the emitter (40) is incident may or may not be formed in a completely vertical direction with respect to the surface of the substrate (100).

[0094] In one embodiment, the tip (B) of the emitter (40) may be positioned to protrude toward the drain electrode (30) by a distance (d2) compared to the gate structure (20, 50). Accordingly, the minimum distance (d2, d3) between the gate structure (20, 50) and the drain electrode (30) is greater than the distance (d3) between the tip (B) of the emitter (40) and the drain electrode (30). In addition, at this time, the distance (d3) between the tip (B) of the emitter (40) and the drain electrode (30) may be greater than the shortest distance (d2) between the tip (B) of the emitter (40) and the gate structure (20, 50).

[0095] For example, the distance (d3) between the tip (B) of the emitter (40) and the drain electrode (30) may be 300 nm, and the shortest distance (d2) between the tip (B) of the emitter (40) and the gate structure (20, 50) may be 100 nm. In addition, in one embodiment, the shortest distance (d2) between the tip (B) of the emitter (40) and the gate structure (20, 50) may be 40 nm or less.

[0096] However, in another embodiment, the tip (B) of the emitter (40) does not protrude toward the drain electrode (30) compared to the gate structure (20, 50), and the minimum distance between the gate structure (20, 50) and the drain electrode (30) may be equal to the distance (d3) between the tip (B) of the emitter (40) and the drain electrode (30).

[0097] Also, in one embodiment, the length (l1) of the source electrode (10) and the length (l3) of the drain electrode (30) may be 400 nm, the length (l2) of the gate electrode (20) may be 100 nm, and the length (L) of the emitter (40) may be 1300 nm. Also, the width (W) of the source electrode (10), the gate electrode (20), and the drain electrode (30) may be 1300 nm. In the present specification, the length refers to the size of each component along the direction of movement of charge carriers through the channel, and the width of each electrode refers to the size of each component along the direction orthogonal to this length direction. Also, in one embodiment, the shortest distance (d1) between the source electrode (20) and the gate structure (20, 50) may be 700 nm.

[0098] The thickness (t) of the gate insulating film (50) of the gate structure can be determined based on the distance between the gate electrode (20) and the emitter (40) at which the voltage applied by the gate electrode (20) on the gate insulating film (50) can modulate the work function of the emitter (40). For example, in one embodiment, the thickness (t) of the gate insulating film (50) can be 10 nm or less.

[0099] However, the dimensions related to each component of the transistor device described in this specification are exemplary, and the dimensions related to each component constituting the transistor device may be appropriately determined according to operating conditions such as changes in input power or phase for the transistor.

[0100] In one embodiment, the transistor device according to the embodiments may be sealed to maintain a vacuum state. Sealing of the transistor device may be performed using any known or future developed technology, and for example, but not limited to, sealing the transistor device in a vacuum state using a getter (not shown) such as titanium or barium. The transistor device having a vacuum channel may operate in a vacuum-sealed state, and the vacuum level required for operation may be appropriately determined based on the mean free path of electrons in the gas within the space where the emitted electrons move and the chemical reaction that may occur through interaction with the gas or physical adsorption on the emitter (40).

[0101] In addition, in one embodiment, the transistor device according to the embodiments may further include conductive leads (not shown) for each of the source electrode (10), the gate electrode (20), and the drain electrode (30). The transistor device can be connected to a circuit capable of applying a voltage using the leads electrically connected to each electrode of the vacuum-sealed device, and can be operated as a vacuum channel FET. During operation, electrons are emitted from the emitter (40) to which a gate voltage is applied, traverse the vacuum channel by quantum tunneling, and then are incident on the drain electrode (30).

[0102] FIG. 3 is a flowchart illustrating each step of a method for driving a transistor device according to one embodiment. For convenience of explanation, the method for driving a transistor device according to the present embodiment will be described with reference to FIGS. 2 and 3.

[0103] First, as in the embodiments described above, a transistor device including a source electrode (10) and an emitter (40) made of a two-dimensional metalloid material is prepared (S1), and by applying a gate voltage to the emitter (40) via a gate electrode (20), the work function of the tip (B) of the emitter (40) can be changed (S12). As the work function of the tip (B) of the emitter (40) is changed, current is emitted from the tip (B) of the emitter (40) by quantum tunneling (S13), and the emitted current can traverse the vacuum channel between the tip (B) of the emitter (40) and the drain electrode (30) and be incident on the drain electrode (30).

[0104] The operation of the transistor device described above is different from the operation method of a conventional FET in which the gate electrode is positioned between the emitter and drain electrodes in that it can be performed without introducing a field plate electrode to shield and interfere with the electric field applied between the source electrode (10) and the drain electrode (30).

[0105] In one embodiment, the magnitude of the voltage applied by the gate electrode (20) to the emitter (40) to cause quantum tunneling of electrons varies depending on the quantum capacitance of the emitter (40), and the quantum capacitance of the emitter (40) is determined based on the voltage applied between the source electrode (10) and the drain electrode (30). Therefore, the magnitude of the gate voltage for controlling the emission current of the emitter (40) can be determined by considering the magnitude of the source-drain voltage.

[0106] In one embodiment, the magnitude of the gate voltage applied by the gate electrode (20) may be greater than 0 V and less than or equal to 10 V. Also, in one embodiment, the magnitude of the gate voltage may be greater than 0 V and less than or equal to 7 V. Furthermore, in one embodiment, the magnitude of the gate voltage may be greater than 0 V and less than or equal to 5 V. Meanwhile, the gate voltage applied by the gate electrode (20) may have a negative (-) value, for example, may be greater than or equal to -10 V and less than 0 V.

[0107] In one embodiment, the magnitude of the source-drain voltage may be greater than 0 V and less than or equal to 200 V. Also, in one embodiment, the magnitude of the source-drain voltage may be greater than 0 V and less than or equal to 100 V. Further, in one embodiment, the magnitude of the source-drain voltage may be between 90 and 100 V.

[0108] According to the operating method of the transistor device according to the embodiments discussed above, by inducing a local electric field enhancement effect on the potential distribution in the nearby space at the tip (B) of the emitter (40) made of a two-dimensional metal material, quantum tunneling of electrons to the vacuum channel can be efficiently induced even when a relatively low voltage is applied.

[0109] In the transistor device according to the embodiments, the electrons emitted through quantum tunneling do not experience effects such as lattice scattering, which can occur in a solid-material-based channel, within the vacuum channel traversed by the electric field, so that the velocity of the emitted electrons does not saturate. In addition, due to the high electrical conductivity of the emitter (40) made of a semi-metallic material and the two-dimensional structure thereof, it is possible to realize a transistor device capable of normal operation even under high-frequency conditions exceeding 100 GHz, thanks to the remarkable quantum capacitance.

[0110] In addition, in the transistor device according to the embodiments, the source-drain distance can be made smaller than in a conventional transistor device without a field plate electrode or the like for shielding and interfering with the electric field applied between the source electrode (10) and the drain electrode (30), and thus excellent operating performance can be realized at a higher frequency.

[0111] FIG. 4 is a conceptual diagram for explaining the operation of a transistor device according to one embodiment.

[0112] Referring to Figure 4, graphene constituting the emitter has a characteristic in which the valence band and the conduction band meet at the charge neutral point, resulting in a density of states of 0. However, when a positive potential is applied to the graphene, electrons accumulate in the graphene, causing the Fermi level to rise to the conduction band. This locally reduces the potential barrier through quantum tunneling at the graphene tip, enabling current emission through a vacuum channel.

[0113] More specifically, the Fermi velocity is 10 6 m / s to υ F , Planck constant 6.58Х10 -16 If eV·s is h and charge density is ρ, the Fermi energy E of graphene F is defined by the following mathematical formula 1.

[0114] [Mathematical Formula 1]

[0115]

[0116]

[0117] The Fermi energy defined by Equation 1 rises very quickly and steeply near the edges of graphene, and more charges accumulate at the edges of graphene due to the two-dimensional structure.

[0118] In particular, the transistor device according to the embodiments can operate by utilizing Fowler-Nordheim tunneling, in which a local field enhancement effect is induced near the emitter tip by a voltage applied to the drain electrode, and the allowable band for emitted electrons within the vacuum channel is bent, thereby dramatically increasing the probability of quantum tunneling. The probability of such quantum tunneling depends on the thickness of the potential barrier, and the width of the potential barrier from the perspective of emitted electrons depends on the position of the Fermi level at the emitter tip.

[0119] Therefore, by applying a gate voltage, the Fermi level at the emitter tip can be indirectly changed through the gate insulator, thereby controlling the probability of quantum tunneling, and consequently, the tunneling current, i.e., the emission current. The current emitted from the graphene tip by quantum tunneling can take the form of a type of sheet electron beam.

[0120] FIG. 5 is a diagram schematically showing an equivalent circuit structure of a vacuum channel FET in which a transistor device according to one embodiment is implemented.

[0121] In the equivalent circuit shown in Fig. 5, V S , V G and V D represents the contact points of the source electrode, gate electrode, and drain electrode, respectively, and the connection between the emitter made of graphene and each electrode is the electric capacitance (C T and C GD ), resistance (R G , R DS ) and transconductance (g m ) was expressed equivalently as a small signal model including .

[0122] The inventors performed calculations for the equivalent circuit assuming that the width of all elements is 1 mm for convenience of calculation, and assuming that palladium is used as the electrode material of the gate electrode, the gate resistance (R G ) is 3.51×10 -6 Ω. In this case, the thickness of the gate electrode is assumed to be 1 nm and the length is assumed to be 30 nm. The above assumptions regarding parameters and materials are only exemplary. In addition, a similar estimation method can be applied when the gate electrode is made of other materials such as gold (Au), platinum (Pt), copper (Cu), aluminum (Al), tungsten (W), titanium (Ti), and silver (Ag).

[0123] Output resistance between source and drain (R DS ) is the inverse of the output conductance (the small change in emission current due to the drain voltage), and the source-drain output resistance (R DS ) and transconductance (g m ) varies depending on the gate voltage, as the value of the emission current can change depending on the gate voltage. In the numerical assumptions of each element mentioned above, the electric capacitance (C) of the gate insulating film GD ) is 1.7071×10 -14 F becomes. Also, the total capacitance (C T ) is a value that takes into account the quantum capacitance value of graphene, and the capacitance of the gate insulating film (C GS ) and quantum capacitance (C) of graphene Q ) can be simulated by a serial connection and can be calculated by the following mathematical formula 2.

[0124] [Equation 2]

[0125]

[0126]

[0127] For example, if hafnium oxide (HfO2) is used as the gate insulator, and the height of the gate electrode is 5 nm, and the length of the gate electrode is 30 nm, the electric capacitance (C) of the gate insulator isGS ) is 1.32813×10 -12 F. In addition, the quantum capacitance of graphene depends on the gate voltage and the source-drain voltage, and on the Dirac level (ε) in the band structure of graphene. D ) from the Fermi level (ε F ) is determined by the displacement of the capacitor and consequently changes according to each voltage condition. In one embodiment, the total capacitance (C) calculated by the numerical assumptions mentioned above T ) is 10 -12 10 inland -13 It can have values ​​of magnitude F.

[0128] Fig. 6 is a graph showing the current-voltage characteristics of a transistor device according to one embodiment, showing the change in emission current according to the gate voltage as the source-drain voltage is changed from 0 V to 100 V. At this time, the gate voltage was increased from 0 V to 7 V in 1 V intervals, and the emission current density according to the drain voltage was shown as a separate graph for each gate voltage. That is, eight graphs (601 to 608) show the emission current density when the gate voltage is 0 V, 1 V, 2 V, 3 V, 4 V, 5 V, 6 V, and 7 V, respectively.

[0129] As illustrated in Figure 6, the emission current of a transistor device tends to increase exponentially with changes in the source-drain voltage, while the emission current can be controlled by varying the gate voltage. Furthermore, the variation in the emission current is also influenced by factors such as the length of the vacuum channel, which is the medium through which the emitted electrons move, and the distance from the gate structure of the tip of the graphene emitter.

[0130] FIGS. 7a and 7b are graphs showing changes in the band structure of each region of the emitter according to voltage conditions applied to each of the source electrode, drain electrode, and gate electrode in a transistor device according to one embodiment.

[0131] Figure 7a shows the energy at the surface of a graphene emitter according to the position from the source electrode, with the conductive contact point between the source electrode and the graphene emitter serving as a reference point for the position. Area (401) on the graph represents a graphene emitter channel area where charge carriers move along the graphene, area (402) represents a graphene emitter channel area located below the gate structure, and area (403) represents the edge of the graphene emitter.

[0132] At this time, Fig. 7a shows the Dirac level (ε) of each region of the emitter with the potential of the source electrode as the reference potential. D ) and Fermi level (ε F ) distribution of the gate voltage (V G ) are shown by size. Graphs (701, 702) each show the gate voltage (V G ) is the Fermi level (ε) when it is 0 V F ) and Dirac level (ε D ) and graphs (711, 712) represent the gate voltage (V G ) Fermi level (ε) when the voltage is 5 V F ) and Dirac level (ε D ) is indicated.

[0133] Figure 7b shows the energy distribution shown in Figure 7a at the Dirac level (ε D ) from the Fermi level (ε F ) is expressed as a displacement of the gate voltage (V), and graphs (721, 722) are respectively G ) represents the displacement when it is 0 V and 5 V. Fermi level (ε F ) and Dirac level (ε D ) can be used to determine the dominant charge carriers that dominate the graphene emitter channel through their relationship with each other on the energy levels.

[0134] As can be seen in Figures 7a and 7b, the concentration of charge carriers induced in the graphene emitter channel is determined by the potential difference between the graphene emitter channel and the gate electrode. The source-drain voltage (V DS ) is applied with 100 V and the gate voltage (V G ) is applied as 0 V, the gate voltage (V G ) within the graphene emitter channel beneath the gate insulator, which is affected by the Fermi level (ε F ) is the Dirac level (ε D ) remain at a lower energy level. In this case, the charge carriers induced within the graphene emitter channel are mainly composed of holes.

[0135] On the other hand, under the same conditions, the gate voltage (V G ) when 5 V is applied, the Fermi level (ε F ) is the Dirac level (ε D ) remain at a higher energy level, and the charge carriers induced within the graphene emitter channel are mainly composed of electrons. The gate voltage (V G ) on the graphene emitter tip is partially shielded by the charge carriers induced as described above. The gate voltage (V) through the shielding G ) is influenced by the Fermi level (ε) of the graphene emitter tip. F ) and consequently, by applying a gate voltage, the Fermi level (ε) of the graphene emitter is affected. F ) can be adjusted to modulate the emission current from the emitter.

[0136] FIGS. 8A and 8B are graphs showing potential distributions in an area of ​​a device and an adjacent space according to voltage conditions applied to each of a source electrode, a drain electrode, and a gate electrode in a transistor device according to one embodiment.

[0137] The potential distributions illustrated in Figs. 8a and 8b represent a state in which a source-drain voltage of 25 V is applied, with Fig. 8a representing a case in which a gate voltage of 0 V is applied, and Fig. 8b representing a case in which a gate voltage of 5 V is applied. As illustrated, the electric field formed within the vacuum channel by the source-drain voltage is formed so that the emitted electrons can move completely to the drain electrode.

[0138] The transistor device according to the embodiments has an advantage in that, unlike a conventional vacuum channel transistor, the gate electrode does not exist within the vacuum channel, and thus electrons emitted from the emitter can be fundamentally prevented from entering the gate electrode and flowing out.

[0139] FIG. 9 is a graph showing the change in transconductance according to the change in gate voltage for each source-drain voltage condition in a transistor device according to one embodiment, and the source-drain voltage (V DS ) shows the transconductance value according to the gate voltage size while changing the source-drain voltage (V DS ) represents the transconductance values ​​when the voltage is 90 V, 95 V, and 100 V.

[0140] Referring to Figure 9, the transconductance of the graphene emitter, like the emission current, depends on the source-drain voltage (V DS ) changes exponentially. In addition, the gate voltage (V G ) also changes the transconductance, which depends on the concentration of charge carriers induced by the gate voltage.

[0141] The point at which the transconductance value is minimum is the applied gate voltage (V G) is the point where the Fermi level displaced by the Dirac level of the graphene emitter channel matches the point where the concentration of induced charge carriers becomes 0 (charge neutrality point). The smaller the degree of separation of the Fermi level from the Dirac level, the smaller the quantum capacitance, and the smaller the gate voltage (V G ) also reduces the degree to which the Fermi level of the graphene emitter channel is shifted by the gate voltage (V G ) changes from 0 V to 5 V, the transconductance takes a minimum value and then increases again. This change pattern also depends on the source-drain voltage (V DS ) is affected by the concentration of charge carriers induced by the electron transport mechanism.

[0142] Figure 10a shows the cutoff frequency (f) according to the change in gate voltage for each source-drain voltage condition in a transistor device according to one embodiment. T ) is a graph showing the changing pattern.

[0143] If the transistor device according to this embodiment is matched to the equivalent circuit described above with reference to FIG. 5, the cutoff frequency (f T ) is the transconductance (g m ), gate dielectric capacitance (C GD ) and total capacitance (C T ) can be calculated as in mathematical formula 3 below.

[0144] [Equation 3]

[0145]

[0146]

[0147] The graphs (1001 to 1003) of Fig. 10a each represent the source-drain voltage (V DS ) is the cutoff frequency (f) when the voltage is 90 V, 95 V and 100 V. T ) is shown. The gate voltage (V) shown in Fig. 10a G ) according to the cutoff frequency (f T) changes in a similar manner to the transconductance value described above with reference to Fig. 9. For example, the source-drain voltage (V DS ) is 90 V, the cutoff frequency is 3.66×10 -3 1.44×10 -2 It is THz. The source-drain voltage (V DS ) is 95 V, the cutoff frequency is 4.8×10 -2 1.96×10 -1 It is THz. The source-drain voltage (V DS ) is 100 V, the cutoff frequency is 4.1×10 -1 is 1.72 THz. This cutoff frequency (f T ) values ​​are substantially larger than those of conventional transistor devices that transport charge carriers through solid-state channels.

[0148] FIG. 10b is a graph showing the change in maximum vibration frequency according to the change in gate voltage for each source-drain voltage condition in a transistor device according to one embodiment.

[0149] If the transistor device according to this embodiment is matched to the equivalent circuit described above with reference to FIG. 5, the maximum vibration frequency (f max ) is the transconductance (g m ), gate dielectric capacitance (C GD ), total capacitance (C T ), gate resistance (R G ), source-drain output resistance (R DS ) can be calculated as in mathematical equation 4 below.

[0150] [Equation 4]

[0151]

[0152]

[0153] The graphs (1011 to 1013) of Fig. 10b each represent the source-drain voltage (V DS ) is the maximum vibration frequency (f) when the voltage is 90 V, 95 V and 100 V.max ) is shown. The gate voltage (V) shown in Fig. 10b G ) according to the maximum vibration frequency (f max ) changes in a similar manner to the transconductance value described above with reference to Fig. 9. For example, the source-drain voltage (V DS ) is 90 V, the maximum vibration frequency (f max ) is 99 to 201 THz. The source-drain voltage (V DS ) is 95 V, the maximum vibration frequency (f max ) is 230 to 661 THz. The source-drain voltage (V DS ) is 100 V, the maximum vibration frequency (f max ) is 641 to 1940 THz. This maximum vibration frequency (f max ) values ​​are substantially larger than those of conventional transistor devices that transport charge carriers through solid-state channels.

[0154] FIG. 11 is a graph showing changes in the work function of the emitter tip according to changes in the shortest distance between the gate electrode and the emitter tip, source-drain voltage conditions, and gate voltage modulation in a transistor device according to one embodiment.

[0155] In the transistor device according to the embodiments, the shielding effect by charge carriers induced in the graphene emitter channel affects the operation of the device. This shielding effect also affects the charge carriers induced by the gate voltage and the source-drain voltage (V DS ) is determined by the charge carriers induced by the gate structure, and the shielding effect increases as the tip of the graphene emitter from which electrons are emitted is further away from the gate structure, increasing the total charge existing between the two regions.

[0156] As a result, as shown in Fig. 11, the length (L) from the source electrode to the emitter tip tip) increases, the work function change (ΔΦ) of the graphene emitter tip according to the change in gate voltage gr ) is dramatically reduced. Also, the source-drain voltage (V DS ) changes in the work function of the graphene emitter tip (ΔΦ) gr ) The difference in width depends on the change in quantum capacitance within the graphene emitter channel.

[0157] Source-drain voltage (V DS ) is small, the degree of displacement of the Fermi level of the graphene emitter tip is small, so the quantum capacitance of the emitter is small, and therefore the change in work function of the graphene emitter tip due to the gate voltage (ΔΦ gr ) increases. Conversely, the source-drain voltage (V DS ) is large, the degree of displacement of the Fermi level of the graphene emitter tip is large, which increases the quantum capacitance, and therefore the change in work function of the graphene emitter tip due to the gate voltage (ΔΦ gr ) the width becomes relatively smaller.

[0158] FIG. 12 is a graph showing the current-voltage characteristics when the length of the vacuum channel is changed in a transistor device according to one embodiment.

[0159] Figure 12 shows the current-voltage characteristics of a transistor device when the length of the vacuum channel (VC) in the same device structure is changed to 50 nm, 100 nm, 150 nm, and 200 nm, respectively. At this time, the source-drain voltage (V DS ) is 100 V, and the solid lines in the graph represent the emission current density when the gate voltage is 5 V in the vacuum channel having each length, and the dotted lines represent the change in the emission current value when the gate voltage is 0 V in the vacuum channel having each length.

[0160] As shown in Fig. 12, as the length of the vacuum channel (VC) increases, the source-drain voltage (V DS) reduces the electric field applied to the edge of the graphene emitter. Therefore, for the same source-drain voltage (V DS ) is applied, the emission current value decreases exponentially as the length of the vacuum channel (VC) increases.

[0161] Furthermore, the threshold voltage at which the emission current increases exponentially also varies depending on the length of the vacuum channel (VC). Furthermore, as the length of the vacuum channel (VC) increases, the electrical influence on charge carriers induced within the graphene emitter channel decreases, and the concentration of charge carriers induced by changes in the gate voltage increases relatively. Consequently, it can be confirmed that the difference in emission current when the gate voltage is turned on and off increases as the length of the vacuum channel (VC) increases.

[0162] FIG. 13 is a cross-sectional view of a transistor device using a two-dimensional metalloid material as an emitter according to another embodiment.

[0163] The transistor device according to the embodiment illustrated in FIG. 13 differs from the embodiment described above with reference to FIGS. 1 and 2 in that the emitter (40) is composed of a double layer (41, 42) of graphene, and therefore, to avoid duplication of explanation, descriptions of components other than the emitter (40) are omitted. As illustrated, in the present embodiment, the emitter (40) includes a first layer (41) and a second layer (42) made of graphene or reduced graphene oxide. The second layer (42) may be positioned on a substrate (100), the first layer (41) may be positioned on the second layer (42), and a gate structure including a gate insulating film (50) and a gate electrode (20) may be positioned on the first layer (41).

[0164] Figures 14a and 14b are graphs comparing the current-voltage characteristics according to the voltage conditions applied to the source electrode, drain electrode, and gate electrode in the transistor device illustrated in Figure 13. Figure 14a shows the gate voltage (V G ) is 0 V, the source-drain voltage (V DS ) shows the emission current density according to the change in the gate voltage (V), and the graph (1401) of Fig. 14 shows the emission current density of the first and second graphene layers, the graph (1402) shows the emission current density of the entire graphene bilayer, and the graph (1403) shows the emission current density of the graphene monolayer. Fig. 14b shows the emission current density according to the change in the gate voltage (V G ) when the source-drain voltage (V DS ) shows the emission current density according to the change in the graphene layer. In Fig. 14b, graphs (1411, 1412) show the emission current density of the first and second graphene layers, respectively, graph (1413) shows the emission current density of the entire graphene bilayer, and graph (1414) shows the emission current density of the graphene monolayer.

[0165] Referring to Figures 14a and 14b, it can be seen that the emission current density value is reduced when a graphene bilayer is used as an emitter compared to when a graphene monolayer is used as an emitter. This is because the source-drain voltage (V) is reduced due to the shielding effect between the two graphene layers in the graphene bilayer forming the emitter. DS ) and gate voltage (V G ) is relatively reduced, which leads to a decrease in the emission current.

[0166] Specifically, the gate voltage (V) in the emitter containing the graphene bilayer G) is applied, charge carriers are induced in both layers of the graphene bilayer by the externally applied voltage. At this time, the concentration of charge carriers induced in the graphene layer (the second layer (42); FIG. 13) in contact with the substrate is relatively reduced due to the shielding effect of the charge carriers induced in the graphene layer (the first layer (41); FIG. 13) in contact with the gate insulating film. Therefore, when the gate voltage (V G ) and the change in charge carrier concentration and the resulting change in emission current within the graphene bilayer are different in each layer (41, 42; Fig. 13) that constitutes the bilayer.

[0167] However, even when the emitter consists of a graphene bilayer, the emission current is dependent on the source-drain voltage (V DS ) tends to increase exponentially as the gate voltage (V G ) can be adjusted according to the change in the emission current. This specification shows embodiments including emitters composed of single layers and double layers, but depending on the embodiment, the emitter may be composed of three or more layers.

[0168] FIGS. 15a to 15c are graphs showing changes in the band structure of each region of the emitter according to voltage conditions applied to each of the source electrode, drain electrode, and gate electrode in the transistor device illustrated in FIG. 13.

[0169] Figure 15a shows the source-drain voltage (V DS ) is applied with 100 V and the gate voltage (V G ) represents the energy band when 0 V is applied, and graphs (1501, 1502) represent the Fermi level (ε) of the first layer of graphene, respectively. F ) and Dirac level (ε D ) and graphs (1511, 1512) represent the Fermi level (ε) of the second layer of graphene, respectively. F ) and Dirac level (ε D) is shown. Also, Fig. 15b shows the source-drain voltage (V DS ) is applied with 100 V and the gate voltage (V G ) represents the energy band when 5 V is applied, and graphs (1521, 1522) represent the Fermi level (ε) of the first layer of graphene, respectively. F ) and Dirac level (ε D ) and graphs (1531, 1532) represent the Fermi level (ε) of the second layer of graphene, respectively. F ) and Dirac level (ε D ) is indicated.

[0170] Figure 15c shows the gate voltage (V G ) at 0 V and 5 V, the Dirac level (ε) in each graphene layer constituting the emitter (i.e., the first layer (41) and the second layer (42); Fig. 13) D ) from the Fermi level (ε F ) shows how much displacement has occurred. Graphs (1541, 1542) show the gate voltage (V G ) at 0 V, the Dirac levels (ε) in each of the first and second layers of graphene D ) from the Fermi level (ε F ) represents the displacement of the gate voltage (V G ) at 5 V, the Dirac levels (ε) in the first and second layers of graphene, respectively. D ) from the Fermi level (ε F ) represents the displacement.

[0171] As illustrated in Fig. 15c, the polarity and concentration of charge carriers induced in the graphene emitter channel are determined by the potential difference between the graphene emitter channel and the gate electrode. The gate voltage (V G ) is 0 V, the Fermi level (ε) within the graphene bilayer channel under the gate insulator F ) is the Dirac level (ε D) remains at a lower energy level. At this time, the charge carriers induced in the graphene emitter channel are mainly composed of holes. On the other hand, the gate voltage (V G ) when 5 V is applied, the Fermi level (ε F ) is the Dirac level (ε D ) and the charge carriers induced within the graphene emitter channel are mainly composed of electrons.

[0172] Also, a relatively large gate voltage (V G ) is applied, the concentration of charge carriers induced in the lower layer of the graphene bilayer (i.e., the second layer (42) adjacent to the substrate; FIG. 13) is relatively lower than the concentration of charge carriers induced in the upper layer of the graphene bilayer adjacent to the gate insulating film (i.e., the first layer (41) adjacent to the gate insulating film; FIG. 13). This is due to the shielding effect of the charge carriers induced in the upper layer.

[0173] Figure 16 shows each source-drain voltage (V) in the transistor device illustrated in Figure 13. DS ) condition, the gate voltage (V G ) Transconductance (g) according to change in m ) is a graph showing the changing pattern.

[0174] For performance comparison of frequency characteristics, the transconductance values ​​when using a graphene single-layer emitter are also shown. Source-drain voltage (V DS ) was increased from 90 V to 100 V in 1 V steps, and the gate voltage (V G ) is 5 V. When the emitter is composed of a double layer of graphene, the transconductance (g) is higher than when using a single layer of graphene. m) can be confirmed to be low. This means that in an emitter composed of a double layer, the shielding effect between each layer of the double layer not only affects the amount of emission current, but also the frequency characteristics of the emitter.

[0175] Fig. 17 is a flowchart showing each step of a method for manufacturing a transistor device according to one embodiment.

[0176] The transistor device according to the embodiments can be manufactured by forming a layered structure by forming the gate insulating film, gate electrode, emitter, source electrode, drain electrode, etc. described above in an appropriate order on a substrate with reference to FIGS. 1, 2, and 13. In addition, during the manufacturing process of the transistor device according to the embodiments, part or all of the layered structure can be removed by a method such as etching in order to implement a structure and characteristics for achieving the function of the transistor device.

[0177] Referring to FIG. 17, in a method for manufacturing a transistor device according to one embodiment, a two-dimensional metalloid material may first be formed on a substrate having a surface composed of a dielectric material (S21). In the present specification, forming any material or layer is intended to include both directly forming the material on a substrate by a method such as deposition or growth, and forming the material or layer on a separate substrate and then transferring it. For example, a graphene emitter may be formed by depositing it on a separate substrate so that molecules in an appropriate direction (e.g., the edge of an armchair structure, etc.) become tips, and then transferring it, but is not limited to this method.

[0178] In the above step (S21), the substrate may be formed of an optically flat and smooth dielectric material, such as silicon nitride (Si3N4), or may include such a dielectric material on its surface. In one embodiment, the dielectric material forming the substrate or provided on the substrate is preferably a material having low reactivity with a material that etches a gate insulating film material (e.g., hafnium oxide (HfO2)) to be formed in the future. Similarly, the gate insulating film is preferably formed of a material that has low reactivity with a material that etches the dielectric material of the substrate.

[0179] Next, an insulating layer made of a dielectric material for forming a gate insulating film on a semi-metallic material layer is formed by any method such as growth or deposition (S22), and the semi-metallic material layer and the insulating layer can be patterned to form an emitter and a gate insulating film (S23). The method for patterning the material layer can be performed by a conventional lithography method in which a photoresist is coated on top of the semi-metallic material and the insulating layer, and then only the necessary area is left through an exposure and development process, and unnecessary parts are removed by etching, etc., and finally the photoresist is removed.

[0180] In Fig. 17, it is described that the semi-metal material layer and the insulating layer are patterned in one step (S23), but this is an example for convenience of explanation, and each layer may be patterned separately depending on what the material or process conditions of the corresponding layer require.

[0181] Next, an electrode material layer may be formed on top of the gate insulating film by a known process such as photoresist coating, exposure, and development, and the electrode material layer may be patterned to form a gate electrode (S24). For example, the electrode material layer for forming the gate electrode may be formed by removing unnecessary photoresist and metal layers through a lift-off process after forming the electrode material layer, leaving only the gate electrode, but is not limited thereto.

[0182] Next, etching of the dielectric material may be performed to form a vacuum channel (S25). In FIG. 17, it was described that the semi-metal material layer is patterned first in step (S23), but in another embodiment, the semi-metal material layer may be patterned together in the etching step (S25) of the dielectric material for forming a vacuum channel. At this time, the etching of the dielectric material may be performed in a manner of inducing an undercut in the semi-metal material so that the tip of the semi-metal material layer protrudes and is positioned within the vacuum channel. In step (S25), in order to prevent the shape of the semi-metal material having a two-dimensional structure from being distorted and sticking to the substrate, the etching of the dielectric material may be performed by gas-phase etching, wet etching using a critical point dryer, or any other arbitrary etching method.

[0183] Next, by forming and patterning an electrode material layer on the substrate, a source electrode in contact with the semi-metal material layer and a drain electrode spaced apart from the tip of the semi-metal material with a vacuum channel therebetween can be formed (S26). For example, the source electrode and the drain electrode may be formed by a method of depositing an electrode material layer such as palladium (Pd) in a vertical direction directly below the substrate surface using an electron beam deposition method or a thermal evaporation method, but the present invention is not limited to this method. At this time, due to the undercut formed in the step (S25), the drain electrode does not physically and electrically contact the tip of the semi-metal material layer. In addition, the drain electrode is formed at a height from the substrate surface that can be at the same height as the tip of the semi-metal material layer.

[0184] FIG. 18a is a cross-sectional view of a transistor device according to another embodiment, and FIG. 18b is a plan view of the transistor device illustrated in FIG. 18a.

[0185] Referring to FIGS. 18a and 18b, the transistor device of the present embodiment has a configuration in which a pair of transistor devices according to the above-described embodiment with reference to FIGS. 1 and 2 are arranged facing each other so that their electron emission directions are opposite to each other. In the description of the transistor device according to the present embodiment, each transistor including an emitter, a source electrode, a drain electrode, and a gate structure is referred to as a "transistor element" for the sake of distinction, and a structure in which a plurality of such transistor elements are combined is referred to as a "transistor device" according to the present embodiment.

[0186] A first transistor element (1) of a transistor device includes an emitter (140), a source electrode (110), a drain electrode (130), and a gate electrode (120). The first transistor element (1) may be manufactured on a first substrate (100). Similarly, a second transistor element (2) includes an emitter (240), a source electrode (210), a drain electrode (130), and a gate electrode (220). The second transistor element (2) may be manufactured on a second substrate (200). A gate insulating film may be positioned between each of the gate electrodes (120, 220) and the substrate. Additionally, a conductive lead (301) may be electrically connected to the source electrode (110, 210), a conductive lead (302) may be electrically connected to the gate electrode (120, 220), and a conductive lead (303) may also be electrically connected to the drain electrode (130, 230).

[0187] The detailed configuration of each transistor element (1, 2) can be easily understood from the above-described embodiments, so a detailed description thereof is omitted.

[0188] A pair of transistor elements (1, 2) are arranged facing each other so that the electron emission direction, i.e., the direction from each emitter (140, 240) toward the drain electrode (130, 230), is opposite to each other. The drain electrode (130) of the first transistor element (1) and the drain electrode (230) of the second transistor element (2) are arranged adjacent to each other, and may be positioned with a slight gap therebetween or in complete contact with each other. In one embodiment, the drain electrode (130) of the first transistor element (1) and the drain electrode (230) of the second transistor element (2) may be formed as a single integrated drain electrode (30). Also, in one embodiment, the gate electrode (120) of the first transistor element (1) and the gate electrode (220) of the second transistor element (2) may be formed as a single integrated electrode.

[0189] In one embodiment, the size and arrangement of each transistor element (1, 2) can be determined so that the shortest distance (D1) between the end of the emitter (140) of the first transistor element (1) and the end of the emitter (240) of the second transistor element (2) is on the order of several micrometers.

[0190] Additionally, in one embodiment, the gap (D2) between the edge of each emitter (140, 240) and the drain electrode (130, 230) can be controlled by controlling the speed at which the drain electrode (130, 230) is formed on each substrate (100, 200). For example, the drain electrode (130, 230) on each substrate (100, 200) can be formed at a lower height (h) than the upper surface of each emitter (140, 240). For example, the height (h) of the drain electrode (130, 230) can be determined such that the upper surface of the drain electrode (130, 230) is positioned 0 to 100 nm lower than the upper surface of the emitter (140, 240).

[0191] As the height (h) of the drain electrode (130, 230) from the substrate (100, 200) decreases, the gap (D2) between the edge of each emitter (140, 240) and the drain electrode (130, 230) will increase. Therefore, by finely controlling the vertical formation speed of the drain electrode (130, 230) at the angstrom level, a vacuum channel of a desired length can be formed, and in this case, the horizontal dimension of the drain electrode (130, 230) (e.g., length (l3) in FIG. 1) can be more finely controlled, which has the advantage of allowing for more precise control.

[0192] In the transistor device according to the embodiment illustrated in FIGS. 18a and 18b, since a pair of transistor elements (1, 2) are arranged in opposite directions, if the structures of both transistor elements (1, 2) are completely symmetrical, the resultant electromagnetic force applied to the drain electrodes (130, 230) becomes 0. In addition, even if both transistor elements (1, 2) are not completely symmetrical, the physical force acting on the drain electrodes (130, 230) is significantly canceled out due to the arrangement of both transistor elements (1, 2) facing each other. Therefore, in the transistor device according to the present embodiment, the phenomenon of the drain electrodes (130, 230) being peeled off due to the electromagnetic force can be prevented.

[0193] Fig. 19 is an optical microscope photograph of a transistor device manufactured according to the embodiment illustrated in Figs. 18a and 18b. The inventors formed a gate electrode (120, 220) and a drain electrode (30) by depositing 10 nm of chromium and then 140 nm of copper, and formed a vacuum channel by etching the substrate using tetrafluoromethane (CF4) gas. At this time, the gap portion (A) between the graphene-based emitter (140, 240) and the drain electrode (30) is the region where electron emission occurs.

[0194] FIGS. 20A and 20B are graphs showing the results of measuring the emission current by applying a voltage between the source electrode and the drain electrode after fabricating a transistor device according to the embodiment illustrated in FIGS. 18A and 18B. FIG. 20A shows that the emission current turns on after exceeding the threshold voltage, and the current begins to increase exponentially. FIG. 20B is a graph showing the current-voltage change of FIG. 20A on an exponential scale along the y-axis. This comparison is commonly used to clearly show that the current is a result of field emission due to the quantum tunneling effect. As shown in the two graphs, the change in current based on the quantum tunneling effect, rather than the current change due to resistive properties, was confirmed through the graphs. Therefore, it can be confirmed that a transistor device can be implemented by utilizing the edge of a semi-metal material such as graphene as the tip of the emitter while forming a transistor device in a structure parallel to the substrate according to the embodiments of the present invention.

[0195] While the present invention has been described above with reference to the embodiments illustrated in the drawings, these are merely exemplary, and those skilled in the art will appreciate that various modifications and variations of the embodiments are possible. However, such modifications should be considered within the technical protection scope of the present invention. Therefore, the true technical protection scope of the present invention should be determined by the technical spirit of the appended claims.

[0196] The embodiments relate to transistor devices, and particularly to transistor devices using a vacuum channel. More specifically, the embodiments relate to a technique for enabling modulation of the amount of current passing through and across a vacuum channel by applying a gate voltage to change the Fermi level and work function of the emitter in a transistor device using a vacuum as a channel, the transistor device including an emitter based on a semi-metallic material having a two-dimensional structure and high conductivity.

Claims

1. An emitter positioned on a substrate containing a dielectric material, made of a two-dimensional semi-metallic material, and configured to selectively emit electrons; A source electrode in electrical contact with one region of the above emitter; A drain electrode positioned on the substrate and spaced apart from the emitter and electrically separated from the source electrode; and A transistor device comprising a gate structure positioned on the emitter and configured to apply a gate voltage to the emitter to control electron emission by the emitter by modulating a work function of the emitter.

2. In paragraph 1, A transistor device in which, when a gate voltage and a drain voltage are applied to the emitter so that the emitter emits electrons, a vacuum channel through which electrons can move is formed between a tip of the emitter facing the drain electrode and the drain electrode.

3. In paragraph 2, A transistor device in which the distance between the gate structure and the drain electrode is greater than or equal to the distance between the tip of the emitter and the drain electrode.

4. In paragraph 3, The tip of the above emitter is arranged to protrude in a direction toward the drain electrode compared to the above gate structure, A transistor device wherein the shortest distance between the tip of the emitter and the gate structure is 40 nm or less.

5. In paragraph 2, The two-dimensional structure of the above semi-metallic material is parallel to the surface of the substrate, A transistor device wherein the emitter is configured to emit electrons in a direction parallel to the surface of the substrate from a tip of the emitter.

6. In paragraph 2, A transistor device in which the tip of the emitter has a radius of curvature less than a preset value so that an electric field enhancement effect is induced at the tip of the emitter by a voltage between the source electrode and the drain electrode.

7. In paragraph 1, A transistor device wherein the emitter comprises one or more layers of graphene or reduced graphene oxide.

8. In paragraph 1, The above gate structure is, a gate insulating film positioned on the emitter; and A transistor device comprising a gate electrode positioned on the gate insulating film and configured to apply the gate voltage.

9. In paragraph 8, The above gate electrode is configured to apply a first voltage to the emitter, A transistor device in which the magnitude of the first voltage is determined based on the quantum capacitance of the emitter, which is determined by the voltage between the source electrode and the drain electrode.

10. In paragraph 9, A second voltage is applied between the source electrode and the drain electrode, The magnitude of the first voltage is -10 V or more and less than 0 V or more than 0 V and less than 10 V, A transistor device in which the magnitude of the second voltage is greater than 0 V and less than or equal to 200 V.

11. A transistor device configured to operate in a vacuum and according to any one of claims 1 to 10; and A field effect transistor comprising a conductive lead electrically connected to the source electrode, the gate structure and the drain electrode of the transistor device.

12. A step of preparing a source electrode positioned on a substrate including a dielectric material, and an emitter positioned on the substrate and electrically connected to the source electrode and made of a two-dimensional metalloid material; A step of modulating the work function of the emitter by applying a gate voltage to the emitter through a gate structure positioned on the emitter; and A driving method of a transistor device, comprising a step of emitting electrons from a tip of the emitter to which the gate voltage and drain voltage are applied, toward a drain electrode electrically separated from the source electrode and spaced apart from the emitter.

13. In paragraph 12, A method for driving a transistor device, wherein the step of emitting electrons includes a step of emitting electrons from the emitter into a vacuum region between a tip of the emitter and the drain electrode.

14. In paragraph 12, The step of modulating the work function of the above emitter is: A step of applying a first voltage to the tip of the emitter by the gate electrode; and A driving method of a transistor device, comprising the step of determining the magnitude of the first voltage based on the quantum capacitance of the emitter determined by the voltage between the source electrode and the drain electrode.

15. In paragraph 12, Further comprising a step of applying a second voltage between the source electrode and the drain electrode, The above first voltage is -10 V or more and less than 0 V or more than 0 V and less than 10 V, A method for driving a transistor device wherein the second voltage is greater than 0 V and less than or equal to 200 V.

16. A step of forming an emitter having a two-dimensional structure made of a semi-metallic material on a substrate including a dielectric material; A step of forming a gate insulating film on the semi-metal material layer; A step of forming a gate electrode on the gate insulating film; a step of partially removing the genetic material; and Comprising the step of forming a source electrode electrically connected to one region of the emitter and a drain electrode positioned spaced apart from the emitter, The gate electrode is located between the source electrode and the drain electrode, The step of partially removing the genetic material is as follows: A method for manufacturing a transistor device, comprising the step of forming an undercut below the semi-metal material layer.

17. In paragraph 16, A method for manufacturing a transistor device, wherein the step of forming the gate insulating film includes the step of forming an insulating layer with a thickness less than or equal to a distance between the gate electrode and the emitter, such that a voltage applied by the gate electrode can modulate the work function of the emitter.

18. In paragraph 16, The step of forming the above emitter is: A step of forming a two-dimensional structured semi-metallic material layer having an edge having a radius of curvature less than a preset value on another substrate; and A method for manufacturing a transistor device, comprising the step of transferring the semi-metal material layer onto the substrate.

19. First transistor element; and A transistor device comprising a second transistor element opposite to the first transistor element, Each of the first transistor element and the second transistor element, An emitter positioned on a substrate containing a dielectric material, made of a two-dimensional semi-metallic material, and configured to selectively emit electrons; A source electrode in electrical contact with one region of the above emitter; A drain electrode positioned on the substrate and spaced apart from the emitter and electrically separated from the source electrode; and A gate structure positioned on the emitter and configured to apply a gate voltage to the emitter to control electron emission by the emitter by modulating a work function of the emitter, A transistor device in which the first transistor element and the second transistor element are arranged so that the emission directions of electrons from the emitter toward the drain electrode are opposite to each other.

20. In paragraph 19, A transistor device in which the drain electrode of the first transistor element and the drain electrode of the second transistor device are formed integrally with each other.

21. In paragraph 19, A transistor device in which the drain electrode of each of the first transistor element and the second transistor element is formed at a height lower than the upper surface of the emitter on the substrate.

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