Semiconductor device and manufacturing method therefor, and electronic device

Abstract

A semiconductor device and a manufacturing method therefor, and an electronic device. The semiconductor device comprises: a plurality of transistors distributed in different layers and stacked in a direction perpendicular to a substrate (1); and word lines (40) passing through the different layers and extending in the direction perpendicular to the substrate (1). Each transistor comprises a first electrode (51), a gate insulating layer (24), a semiconductor layer (23) surrounding the side walls of the word lines (40), and a protective layer (32) arranged between the semiconductor layer (23) and the side wall of the gate insulating layer (24), wherein the first electrode (51) is arranged in a first groove of the semiconductor layer (23).

Description

Semiconductor device and manufacturing method thereof, and electronic device

[0001] This application claims priority to the Chinese patent application filed on August 8, 2023, with application number 202310986429.1, and invention name “A semiconductor, a method for manufacturing the same, and an electronic device”, the contents of which should be understood as incorporated into this application by reference. Technical Field

[0002] The embodiments of the present disclosure relate to, but are not limited to, device design and manufacturing of semiconductor technology, and in particular to a semiconductor device and a manufacturing method thereof, and an electronic device. Background Art

[0003] Semiconductor storage can be divided into volatile memory (RAM, including DRAM and SRAM, etc.) and non-volatile memory (ROM and non-ROM) based on application.

[0004] Taking DRAM as an example, conventional DRAM has multiple repetitive "memory cells," each containing a capacitor and a transistor. A capacitor can store one bit of data. After charging and discharging, the amount of charge stored in the capacitor corresponds to the binary data "1" and "0," respectively. The transistor acts as a switch that controls the charging and discharging of the capacitor.

[0005] To minimize product costs, people hope to create as many memory cells as possible on a limited substrate. Since the advent of Moore's Law, the industry has proposed various semiconductor structure designs and process optimizations to meet people's current product needs.

[0006] Summary of the Invention

[0007] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0008] An embodiment of the present disclosure provides a semiconductor device, including:

[0009] Multiple transistors are distributed in different layers and stacked vertically along the substrate;

[0010] A word line, extending through the different layers in a direction perpendicular to the substrate;

[0011] The transistor includes a semiconductor layer with a first electrode surrounding the sidewalls of the word line, a gate insulating layer disposed between the sidewalls of the word line and the semiconductor layer, and a protective layer disposed between the semiconductor layer and the gate insulating layer. The semiconductor layer includes a first recess opening away from the word line, and the first electrode is located within the first recess and connected to the semiconductor layer. In some embodiments, the semiconductor layers of multiple transistors arranged in the same column along a direction perpendicular to the substrate are spaced apart.

[0012] In some embodiments, multiple protection layers of multiple transistors in the same column distributed along a direction perpendicular to the substrate are arranged at intervals.

[0013] In some embodiments, an orthographic projection of the protection layer on the substrate is outside an orthographic projection of the gate insulation layer on the substrate.

[0014] In some embodiments, the transistor also includes a second electrode connected to the semiconductor layer, and the semiconductor device also includes: a plurality of bit lines distributed in different layers and respectively connected to the second electrodes of the plurality of transistors, extending along a second direction parallel to the substrate; the semiconductor layer of the transistor also surrounds the side walls of the bit lines to which the transistor is connected.

[0015] In some embodiments, the semiconductor layer of the transistor is further in contact with one end surface of a bit line to which the transistor is connected.

[0016] In some embodiments, the second electrode and the bit line are connected to form an integral structure.

[0017] In some embodiments, gate insulation layers of a plurality of transistors in the same column distributed along a direction perpendicular to the substrate are connected to form an integrated structure.

[0018] In some embodiments, the semiconductor device further comprises:

[0019] Insulating layers and conductive layers are alternately distributed from bottom to top in a direction perpendicular to the substrate, wherein the conductive layer includes the first electrode and the second electrode;

[0020] A through hole is formed through each of the insulating layers and each of the conductive layers, wherein the word line, the gate insulating layer surrounding the sidewall of the word line, and the protection layer surrounding the sidewall of the gate insulating layer are sequentially distributed in the through hole from inside to outside.

[0021] In some embodiments, the first electrode includes a second groove opening away from the word line.

[0022] In some embodiments, the semiconductor device further includes: a second capacitor electrode filling the second groove, and a dielectric layer disposed between the second capacitor electrode and the first electrode.

[0023] An embodiment of the present disclosure provides an electronic device, comprising the semiconductor device described in any of the above embodiments.

[0024] An embodiment of the present disclosure provides a method for manufacturing a semiconductor device, wherein the semiconductor device includes a plurality of transistors distributed in different layers and stacked along a direction perpendicular to a substrate, and word lines and bit lines extending in a direction perpendicular to the substrate; the transistors include a first electrode, a second electrode, and a semiconductor layer surrounding the sidewalls of the word lines and insulated from the word lines; the method for manufacturing the semiconductor device includes:

[0025] Providing a substrate, and alternately depositing a first insulating film and a sacrificial layer film on the substrate to form a stacked structure including multiple insulating layers and multiple sacrificial layers;

[0026] forming a through hole penetrating the stacked structure in a direction perpendicular to the substrate, with the sidewall of the through hole exposing each of the sacrificial layers; forming a protective layer, the protective layer covering the sidewall of the sacrificial layer facing the through hole, and sequentially depositing a gate insulating film and a gate electrode film filling the through hole in the through hole to form a multi-layer gate insulating layer and word line of the transistor;

[0027] The stacked structure is patterned so that the sacrificial layer forms a predetermined pattern, the predetermined pattern including a first sub-portion and a second sub-portion connected to the first sub-portion, the orthographic projection of the through hole on the substrate is located within an outer contour of the orthographic projection of the predetermined pattern on the substrate, the first sub-portion extends along a first direction, the second sub-portion extends along a second direction, and the first direction intersects the second direction;

[0028] The first sub-portion and the second sub-portion are etched to form a first semiconductor sub-layer and a first electrode in the area where the first sub-portion is located, and a second semiconductor sub-layer and a bit line are formed in the area where the second sub-portion is located, wherein the first semiconductor sub-layer and the second semiconductor sub-layer constitute a semiconductor layer of the transistor, the semiconductor layer surrounds the side wall of the word line, the semiconductor layer includes a first groove with an opening facing away from the word line, and the first electrode is located in the first groove and is connected to the semiconductor layer.

[0029] In some embodiments, forming a protection layer in the through hole to prevent the sacrificial layer from being exposed includes:

[0030] Depositing a protective layer film in the through hole to form the protective layer;

[0031] Alternatively, the end surface of the sacrificial layer exposed on the side wall of the through hole and a region with a distance from the end surface less than or equal to a preset distance are oxidized to form the protective layer.

[0032] In some embodiments, etching the first sub-portion and etching the second sub-portion to form a first semiconductor sub-layer and a first electrode in the area where the first sub-portion is located, and forming a second semiconductor sub-portion and a second electrode in the area where the second sub-portion is located includes:

[0033] etching and removing the first sub-portion and the second sub-portion by a single wet etching process;

[0034] A semiconductor film and a conductive film are sequentially deposited in the area where the first sub-section is located and the area where the second sub-section is located to form a semiconductor layer including the first semiconductor sub-layer and the second semiconductor sub-layer, a first electrode, and a bit line.

[0035] In some embodiments, etching the first sub-portion and etching the second sub-portion to form a first semiconductor sub-layer and a first electrode in the area where the first sub-portion is located, and forming a second semiconductor sub-portion and a second electrode in the area where the second sub-portion is located includes:

[0036] Etching to remove the first sub-portion, and sequentially depositing a first semiconductor film and a first conductive film in the area where the first sub-portion is located to form the first semiconductor sub-layer and the first electrode;

[0037] The second sub-portion is removed by etching, and a second semiconductor film and a second conductive film filling the area where the second sub-portion is located are sequentially deposited in the area where the second sub-portion is located to form the second semiconductor sub-layer and the bit line.

[0038] In some embodiments, depositing a first conductive film in the area where the first sub-portion is located includes:

[0039] After depositing a first semiconductor film in the area where the first sub-section is located, depositing a first conductive film on the first semiconductor film to fill the area where the first sub-section is located;

[0040] Alternatively, after depositing a first semiconductor film in the area where the first sub-portion is located, a first conductive film is deposited on the first semiconductor film with a preset thickness, so that the first conductive film forms a second groove with an opening away from the word line.

[0041] Other features and advantages of the present disclosure will be described in the following description, and in part will become apparent from the description, or will be understood by practicing the present disclosure. The objects and advantages of the present disclosure can be realized and obtained through the structures particularly pointed out in the description and the drawings.

[0042] Still other aspects will become apparent upon reading and understanding the accompanying drawings and detailed description.

[0043] Summary of the Figures

[0044] The accompanying drawings are used to provide a further understanding of the technical solution of the present disclosure and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the technical solution and do not constitute a limitation to the technical solution.

[0045] FIG1A is a cross-sectional view taken along the aa' direction in FIG1E ; FIG1B is a cross-sectional view taken along the bb' direction in FIG1E ; FIG1C is a cross-sectional view taken along the cc' direction in FIG1E ; FIG1D is a cross-sectional view taken along the dd' direction in FIG1E ; FIG1E is a cross-sectional view of a semiconductor device provided by an exemplary embodiment along a direction parallel to the substrate;

[0046] FIG2A is a cross-sectional view taken along the aa' direction after forming a stack structure according to an exemplary embodiment; FIG2B is a cross-sectional view taken along the bb' direction after forming a stack structure according to an exemplary embodiment; FIG2C is a cross-sectional view taken along the cc' direction after forming a stack structure according to an exemplary embodiment; FIG2D is a cross-sectional view taken along the dd' direction after forming a stack structure according to an exemplary embodiment;

[0047] FIG3A is a cross-sectional view taken along the aa' direction in FIG3E; FIG3B is a cross-sectional view taken along the bb' direction in FIG3E; FIG3C is a cross-sectional view taken along the cc' direction in FIG3E; FIG3D is a cross-sectional view taken along the dd' direction in FIG3E; FIG3E is a cross-sectional view taken along a direction parallel to the substrate after forming a through hole, provided by an exemplary embodiment;

[0048] FIG4A is a cross-sectional view taken along the aa' direction after forming a protective layer according to an exemplary embodiment; FIG4B is a cross-sectional view taken along the bb' direction after forming a protective layer according to an exemplary embodiment; FIG4C is a cross-sectional view taken along the cc' direction after forming a protective layer according to an exemplary embodiment; FIG4D is a cross-sectional view taken along the dd' direction after forming a protective layer according to an exemplary embodiment; FIG4E is a cross-sectional view taken along the aa' direction after forming a protective layer according to another exemplary embodiment; and FIG4F is a cross-sectional view taken along the cc' direction after forming a protective layer according to another exemplary embodiment;

[0049] 5A is a cross-sectional view taken along the aa' direction after forming a gate insulating layer and a gate electrode according to an exemplary embodiment; FIG. 5B is a cross-sectional view taken along the bb' direction after forming a gate insulating layer and a gate electrode according to an exemplary embodiment; FIG. 5C is a cross-sectional view taken along the cc' direction after forming a gate insulating layer and a gate electrode according to an exemplary embodiment; and FIG. 5D is a cross-sectional view taken along the dd' direction after forming a gate insulating layer and a gate electrode according to an exemplary embodiment;

[0050] 6A is a cross-sectional view taken along the aa' direction in FIG. 6E ; FIG. 6B is a cross-sectional view taken along the bb' direction in FIG. 6E ; FIG. 6C is a cross-sectional view taken along the cc' direction in FIG. 6E ; FIG. 6D is a cross-sectional view taken along the dd' direction in FIG. 6E ; FIG. 6E is a cross-sectional view taken along a direction parallel to the substrate after forming a first insulating layer and a sacrificial layer, provided in accordance with an exemplary embodiment;

[0051] 7A is a cross-sectional view taken along the aa' direction after forming the third insulating layer according to an exemplary embodiment; FIG. 7B is a cross-sectional view taken along the bb' direction after forming the third insulating layer according to an exemplary embodiment; FIG. 7C is a cross-sectional view taken along the cc' direction after forming the third insulating layer according to an exemplary embodiment; FIG. 7D is a cross-sectional view taken along the dd' direction after forming the third insulating layer according to an exemplary embodiment;

[0052] FIG8A is a cross-sectional view taken along the aa' direction after the capacitor region is exposed according to an exemplary embodiment; FIG8B is a cross-sectional view taken along the bb' direction after the capacitor region is exposed according to an exemplary embodiment; FIG8C is a cross-sectional view taken along the cc' direction after the capacitor region is exposed according to an exemplary embodiment; FIG8D is a cross-sectional view taken along the dd' direction after the capacitor region is exposed according to an exemplary embodiment;

[0053] FIG9A is a cross-sectional view along the aa' direction after etching the sacrificial layer according to an exemplary embodiment; FIG9B is a cross-sectional view along the bb' direction after etching the sacrificial layer according to an exemplary embodiment; FIG9C is a cross-sectional view along the cc' direction after etching the sacrificial layer according to an exemplary embodiment; FIG9D is a cross-sectional view along the dd' direction after etching the sacrificial layer according to an exemplary embodiment;

[0054] 10A is a cross-sectional view taken along the aa' direction in FIG. 10E ; FIG. 10B is a cross-sectional view taken along the bb' direction in FIG. 10E ; FIG. 10C is a cross-sectional view taken along the cc' direction in FIG. 10E ; FIG. 10D is a cross-sectional view taken along the dd' direction in FIG. 10E ; FIG. 10E is a cross-sectional view taken along a direction parallel to the substrate after forming a semiconductor layer, a first electrode, a second electrode, and a bit line, provided in accordance with an exemplary embodiment;

[0055] FIG11A is a cross-sectional view taken along the aa' direction after forming a dielectric layer and a second capacitor electrode according to an exemplary embodiment; FIG11B is a cross-sectional view taken along the bb' direction after forming a dielectric layer and a second capacitor electrode according to an exemplary embodiment; FIG11C is a cross-sectional view taken along the cc' direction after forming a dielectric layer and a second capacitor electrode according to an exemplary embodiment; FIG11D is a cross-sectional view taken along the dd' direction after forming a dielectric layer and a second capacitor electrode according to an exemplary embodiment; FIG11E is a cross-sectional view taken along a direction parallel to the substrate after forming a dielectric layer and a second capacitor electrode according to an exemplary embodiment;

[0056] 12A is a cross-sectional view taken along the aa' direction in FIG. 12E ; FIG. 12B is a cross-sectional view taken along the bb' direction in FIG. 12E ; FIG. 12C is a cross-sectional view taken along the cc' direction in FIG. 12E ; FIG. 12D is a cross-sectional view taken along the dd' direction in FIG. 12E ; and FIG. 12E is a cross-sectional view of a semiconductor device provided in a direction parallel to the substrate according to another exemplary embodiment;

[0057] FIG13A is a cross-sectional view taken along the aa' direction after the first sub-portion is removed, provided by an exemplary embodiment; FIG13B is a cross-sectional view taken along the bb' direction after the first sub-portion is removed, provided by an exemplary embodiment; FIG13C is a cross-sectional view taken along the cc' direction after the first sub-portion is removed, provided by an exemplary embodiment; FIG13D is a cross-sectional view taken along the dd' direction after the first sub-portion is removed, provided by an exemplary embodiment;

[0058] FIG14A is a cross-sectional view taken along the aa' direction after forming the first semiconductor sublayer and the first electrode according to an exemplary embodiment; FIG14B is a cross-sectional view taken along the bb' direction after forming the first semiconductor sublayer and the first electrode according to an exemplary embodiment; FIG14C is a cross-sectional view taken along the cc' direction after forming the first semiconductor sublayer and the first electrode according to an exemplary embodiment; FIG14D is a cross-sectional view taken along the dd' direction after forming the first semiconductor sublayer and the first electrode according to an exemplary embodiment;

[0059] FIG15A is a cross-sectional view along the aa' direction after the semiconductor film and the conductive film located in the capacitor region are removed, according to an exemplary embodiment; FIG15B is a cross-sectional view along the bb' direction after the semiconductor film and the conductive film located in the capacitor region are removed, according to an exemplary embodiment; FIG15C is a cross-sectional view along the cc' direction after the semiconductor film and the conductive film located in the capacitor region are removed, according to an exemplary embodiment; FIG15D is a cross-sectional view along the dd' direction after the semiconductor film and the conductive film located in the capacitor region are removed, according to an exemplary embodiment;

[0060] FIG16A is a cross-sectional view taken along the aa' direction in FIG16E; FIG16B is a cross-sectional view taken along the bb' direction in FIG16E; FIG16C is a cross-sectional view taken along the cc' direction in FIG16E; FIG16D is a cross-sectional view taken along the dd' direction in FIG16E; FIG16E is a cross-sectional view along a direction parallel to the substrate after forming a dielectric layer and a second capacitor electrode, provided in an exemplary embodiment;

[0061] FIG17A is a cross-sectional view along the aa' direction after the second sub-portion is removed, provided by an exemplary embodiment; FIG17B is a cross-sectional view along the bb' direction after the second sub-portion is removed, provided by an exemplary embodiment; FIG17C is a cross-sectional view along the cc' direction after the second sub-portion is removed, provided by an exemplary embodiment; FIG17D is a cross-sectional view along the dd' direction after the second sub-portion is removed, provided by an exemplary embodiment;

[0062] Figure 18A is a cross-sectional view along the aa' direction in Figure 18E; Figure 18B is a cross-sectional view along the bb' direction in Figure 18E; Figure 18C is a cross-sectional view along the cc' direction in Figure 18E; Figure 18D is a cross-sectional view along the dd' direction in Figure 18E; Figure 18E is a cross-sectional view along a direction parallel to the substrate after forming a second semiconductor sublayer and a bit line provided by an exemplary embodiment.

[0063] Details

[0064] The embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. Unless there is a conflict, the embodiments of the present disclosure and the features therein may be combined with each other in any manner.

[0065] Unless otherwise defined, technical or scientific terms used in the present disclosure should have the same meaning as commonly understood by a person having ordinary skills in the field to which the present disclosure belongs.

[0066] The embodiments of the present disclosure are not necessarily limited to the dimensions shown in the drawings, and the shapes and sizes of the components in the drawings do not reflect the true proportions. In addition, the drawings schematically illustrate ideal examples, and the embodiments of the present disclosure are not limited to the shapes or values ​​shown in the drawings.

[0067] In the present disclosure, ordinal numbers such as “first”, “second” and “third” are provided to avoid confusion among constituent elements and do not indicate any order, quantity or importance.

[0068] In this disclosure, for convenience, words and phrases indicating orientation or positional relationships, such as "middle," "upper," "lower," "front," "back," "vertical," "horizontal," "top," "bottom," "inside," and "outside," are used to illustrate the positional relationships of constituent elements with reference to the accompanying drawings. This is merely for the convenience of describing this specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation. Therefore, it should not be understood as a limitation of this disclosure. The positional relationships of constituent elements may be appropriately changed according to the direction in which each constituent element is described. Therefore, the words and phrases described in this disclosure are not limited and may be appropriately replaced according to the circumstances.

[0069] In this disclosure, unless otherwise expressly specified or limited, the terms "mounted," "connected," and "connected" should be interpreted broadly. For example, they can refer to fixed connections, removable connections, or integral connections; physical connections or electrical signal connections; direct connections, indirect connections through intermediaries, or internal communication between two components. Those skilled in the art will understand the specific meanings of these terms in this disclosure based on the specific circumstances.

[0070] In this disclosure, a transistor refers to an element comprising at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. In this disclosure, the channel region refers to the region through which current primarily flows.

[0071] In the present disclosure, the first electrode may be a drain electrode and the second electrode may be a source electrode, or vice versa. The functions of the "source electrode" and "drain electrode" may be reversed when using transistors with opposite polarities or when the direction of current changes during circuit operation. Therefore, in the present disclosure, the terms "source electrode" and "drain electrode" may be reversed.

[0072] In this disclosure, "connection" includes the connection of components via an element having some electrical function. There are no particular limitations on the "element having some electrical function" as long as it enables the transfer of electrical signals between the connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with various functions.

[0073] In this disclosure, "parallel" means approximately parallel or nearly parallel. For example, the angle formed by two straight lines is greater than -10° and less than 10°, and thus also includes the angle of greater than -5° and less than 5°. In addition, "perpendicular" means approximately perpendicular. For example, the angle formed by two straight lines is greater than 80° and less than 100°, and thus also includes the angle of greater than 85° and less than 95°.

[0074] The phrase "A and B disposed in the same layer" in this disclosure encompasses layers formed of the same material or different materials located on the same film layer. For example, A and B are formed by forming the same film layer from the same material and then undergoing the same patterning process or different patterning processes. A and B disposed in the same layer can be located on the same horizontal plane, but not necessarily on the same film layer, or located in different regions of the same film layer, but not necessarily on the same horizontal plane.

[0075] In the embodiments of the present disclosure, "A and B are an integrated structure" may mean that there are no distinct microstructural boundaries, such as gaps or discontinuities. Generally, a film layer patterned to form a connection is considered integrated. For example, A and B may be formed using the same material into a single film layer and simultaneously formed into a connected structure through the same patterning process.

[0076] Figure 1A is a cross-sectional view taken along the aa' direction in Figure 1E, Figure 1B is a cross-sectional view taken along the bb' direction in Figure 1E, Figure 1C is a cross-sectional view taken along the cc' direction in Figure 1E, and Figure 1D is a cross-sectional view taken along the dd' direction in Figure 1E. Figure 1E is a cross-sectional view of a semiconductor device provided by an exemplary embodiment along a direction parallel to substrate 1. The semiconductor device may be a transistor, a memory cell including a transistor, a memory cell array including a memory cell, a 3D stacked structure including a memory cell array, or a memory including a transistor or a memory cell array.

[0077] As shown in FIG. 1A to FIG. 1E , an embodiment of the present disclosure provides a semiconductor device, which may include:

[0078] Multiple transistors are distributed in different layers and stacked along a direction perpendicular to the substrate 1;

[0079] A word line 40 passes through the different layers and extends in a direction perpendicular to the substrate 1;

[0080] The transistor includes a first electrode 51, a second electrode 52, a semiconductor layer 23 surrounding the sidewalls of the word line 40, a gate insulating layer 24 disposed between the sidewalls of the word line 40 and the semiconductor layer 23, and a protective layer 32 disposed between the semiconductor layer 23 and the gate insulating layer 24. The semiconductor layer 23 includes a first groove with an opening facing away from the word line 40. The first electrode 51 is located in the first groove and connected to the semiconductor layer 23. In other words, the first electrode 51 includes an end surface facing the word line 40 and a sidewall connected to the end surface. The semiconductor layer 23 is connected to the end surface and surrounds the sidewalls of the first electrode 51.

[0081] In the solution provided in this embodiment, the first electrode 51 is disposed within the first recess of the semiconductor layer 23. When manufacturing a transistor stacked structure, a conductive film can be omitted. Instead, the conductive film can be deposited to form the first electrode after etching the stacked structure to form the word lines. This allows the conductive film to be replaced with a layer that is easily etched, making etching easier to control and facilitating the replacement of a different conductive film as the first electrode without changing the process, thus facilitating iterative upgrades of the device. Furthermore, the protective layer can protect the gate insulation layer during the manufacturing process.

[0082] In some embodiments, the transistor may further include a gate electrode 26, and the gate electrode 26 of transistors in different layers may be a portion of the word line 40. It is understandable that before and after the word line 40 is formed, there is no need to separately fabricate the gate electrode 26. After the word line 40 is fabricated, a portion of the word line 40 functions as the gate electrode 26. The local morphology of the word line 40 is not limited here, and the word line 40 as a whole extends in a direction perpendicular to the substrate 1. Locally, corresponding to each transistor, the gate electrode 26 in this region may extend in both the horizontal and vertical directions, but the semiconductor layer 23 is formed on the sidewall of the word line 40, and the region of the sidewall of the word line 40 wrapped with the semiconductor layer 23 may be a region where the main surface of the film layer includes an extension in a direction perpendicular to the substrate 1, or includes an area extending in a horizontal direction in addition to an area extending vertically.

[0083] In some embodiments, the gate electrode 26 can be linear and extend only in a direction perpendicular to the substrate 1. The word line 40 formed by the gate electrode 26 or multiple gate electrodes 26 includes a side surface adjacent to the sidewall of the hole in which the word line 40 is located. The side surface is generally perpendicular to the substrate 1. Specifically, the portion of the sidewall corresponding to the semiconductor layer 23 that functions as the gate electrode control layer is perpendicular to the substrate 1. Regions that may be locally curved during actual product manufacturing are also included in the aforementioned aspects of this application.

[0084] Here, "surrounding" can be understood as partially or completely surrounding the gate electrode 26. In some embodiments, the surrounding can be completely surrounding, and the cross-section of the semiconductor layer 23 after the surrounding is a closed ring. The cross-section is intercepted along a direction parallel to the substrate 1. In some embodiments, the surrounding can be partially surrounding, and the cross-section after the surrounding is not closed, but has a ring shape. For example, a ring with an opening.

[0085] In an exemplary embodiment, the material composition of different regions of the word line 40 extending in a direction perpendicular to the substrate 1 is the same, which can be understood as being formed using the same deposition process. The same material composition can be understood as the same main elements tested in the material, for example, all are made of metals, alloys, metal nitrides, metal oxides (such as ITO, IZO, etc.), and metal silicides, but the atomic number ratio of different regions of the word line 40 is not limited.

[0086] In some embodiments, the cross section of the gate electrode 26 along the direction parallel to the substrate 1 is, for example, a square structure, but the embodiments of the present disclosure are not limited thereto and may be other shapes, such as a circle.

[0087] In some embodiments, the first electrode 51 and the second electrode 52 of the same transistor may be located at the same horizontal plane.

[0088] In some embodiments, the first electrode 51 and the second electrode 52 may be provided in the same layer, that is, the first electrode 51 and the second electrode 52 may be formed simultaneously through the same process, but the embodiments of the present disclosure are not limited thereto, and the first electrode 51 and the second electrode 52 may be manufactured separately through different processes.

[0089] In some embodiments, the first electrode 51 may extend along a first direction X.

[0090] In some embodiments, the first direction X may be parallel to the substrate 1 .

[0091] In some embodiments, stacked transistors in different layers may share a word line 40 extending in a direction perpendicular to the substrate 1 .

[0092] In some embodiments, the semiconductor layers 23 of the transistors may be spaced apart, for example, physically disconnected. That is, the semiconductor layers 23 of different layers are not connected, thereby eliminating parasitic transistors and preventing leakage between transistors. The transistors may be arranged in the same column perpendicular to the substrate 1.

[0093] In some embodiments, the plurality of protection layers 32 of the plurality of transistors may be spaced apart, for example, physically disconnected, but the present disclosure is not limited thereto, and the plurality of protection layers 32 of the plurality of transistors may form an integrated structure.

[0094] In some embodiments, the protection layer 32 may surround the sidewall of the gate insulating layer 24 so that the semiconductor layer 23 is not in contact with the gate insulating layer 24 .

[0095] In some embodiments, the orthographic projection of the protective layer 32 on the substrate 1 may be located outside the orthographic projection of the gate insulating layer 24 on the substrate 1. In this embodiment, during the manufacturing process of the semiconductor device, the protective layer 32 can provide support when removing the sacrificial layer film occupying the area where the first electrode 51 and the second electrode 52 are located.

[0096] In some embodiments, the semiconductor device may further include: a plurality of bit lines 30 respectively connected to the second electrodes 52 of the plurality of transistors and extending along the second direction Y; the semiconductor layer 23 of the transistor further surrounds the sidewalls of the bit lines 30 connected to the transistors. The bit lines 30 may extend along the second direction Y, and the sidewalls of the bit lines 30 are surfaces of the bit lines 30 extending along the second direction Y.

[0097] In some embodiments, the second direction Y may be parallel to the substrate 1 .

[0098] In some embodiments, the second direction Y and the first direction X may intersect.

[0099] In some embodiments, the first direction X and the second direction Y are perpendicular.

[0100] In some embodiments, the second electrode 52 and the bit line 30 can be connected to form an integral structure. For example, the bit line 30 can be a straight line with its sidewalls connected to the semiconductor layer 23. Alternatively, the bit line 30 can have an integrally designed branch connected to the semiconductor layer 23, wherein the branch extends in a direction that intersects, such as approximately perpendicular to, the direction of extension of the bit line 30. The branches can be multiple branches on one sidewall of the bit line 30, or multiple branches on both sidewalls, each branch corresponding to a transistor or a memory cell.

[0101] In some embodiments, the semiconductor layer 23 may further contact an end surface of the bit line 30 , which is perpendicular to an extending direction of the bit line 30 .

[0102] The shape of the bit line 30 shown in FIG. 1E is merely an example, and the shape of the bit line 30 is not limited thereto and may be other shapes.

[0103] In some embodiments, the gate insulation layers 24 of multiple transistors in the same column distributed along a direction perpendicular to the substrate 1 may be connected to form an integrated structure.

[0104] In some embodiments, transistors in different layers may share a ring-shaped gate insulating layer 24 extending in a direction perpendicular to the substrate 1 .

[0105] In some embodiments, the semiconductor device may further include:

[0106] Insulating layers and conductive layers are alternately distributed from bottom to top along a direction perpendicular to the substrate 1 , wherein the conductive layer includes the first electrode 51 and the second electrode 52 ;

[0107] Through holes are formed through each insulating layer and each conductive layer. Distributed in order from the inside to the outside of the through holes are the word lines 40, the gate insulating layer 24 surrounding the sidewalls of the word lines 40, and the protective layer 32 surrounding the sidewalls of the gate insulating layer 24. This simplifies the process by forming the word lines 40 and gate insulating layer 24 of the multi-layer transistor by etching and then depositing film layers separately.

[0108] In some embodiments, as shown in FIG1E , the cross-section of the first electrode 51 parallel to the substrate 1 may be square. The surface of the first electrode 51 away from the word line 40 may be perpendicular to the substrate 1. The semiconductor device may further include a second capacitor electrode 42 and a dielectric layer 43 disposed between the second capacitor electrode 42 and the first electrode 51. The contact surface between the dielectric layer 43 and the first electrode 51 may be perpendicular to the substrate 1. In this embodiment, the first electrode 51 may be a solid structure without an opening.

[0109] In some embodiments, an opening may be provided on a side of the first electrode 51 away from the word line 40, that is, the first electrode 51 includes a second groove with an opening facing away from the word line 40. In this embodiment, when the first electrode 51 serves as an electrode of a capacitor, providing the second groove can increase the area of ​​the first electrode 51, thereby increasing the capacitance value.

[0110] In some embodiments, the cross-section of the second groove can be U-shaped along a direction parallel to the opening of the second groove and perpendicular to the substrate 1, and the cross-section of the second groove can be U-shaped along a direction parallel to the substrate 1. Subsequently, a dielectric layer 43 and a second capacitor electrode 42 are deposited in the second groove, and the first electrode 51, the dielectric layer 43, and the second capacitor electrode 42 form a capacitor. The embodiments of the present disclosure are not limited to this, and the second groove of the first electrode 51 can have other shapes.

[0111] In some embodiments, as shown in FIG1E , the memory cells in the same layer form an array distributed along a first direction X and a second direction Y, respectively. Each layer of memory cells may further include a bit line 30 connected to the second electrode 52 of the transistor in the same layer and column. FIG1E illustrates that each layer includes three rows and two columns of memory cells, but the disclosed embodiments are not limited thereto. Each layer may include memory cells of other numbers of rows and columns, for example, only one memory cell. In some embodiments, the semiconductor device may further include a data storage element.

[0112] The stacked transistors described above can be applied in a variety of memory applications, such as traditional 1T and 2T structures, with or without capacitors, in DRAM applications. Alternatively, they can be used in 4T or 6T memory cell applications in SRAM.

[0113] In some embodiments, the data storage element is, for example, a capacitor, forming a 1T1C storage structure. However, the present disclosure is not limited thereto, and other transistors can be used to form a 2T0C storage structure, and so on.

[0114] In some embodiments, the capacitor may include a first capacitor electrode 41 and a second capacitor electrode 42 , and the first capacitor electrode 41 is connected to the first electrode 51 .

[0115] In some embodiments, the first capacitor electrode 41 and the first electrode 51 may be an integrated structure, that is, the same electrode is reused as the first capacitor electrode 41 and the first electrode 51 .

[0116] In some embodiments, as shown in FIG. 1A to FIG. 1E , the second capacitor electrode 42 may be a planar electrode extending in a direction perpendicular to the substrate 1 .

[0117] In some embodiments, as shown in FIG. 1A to FIG. 1E , the dielectric layer 43 may be a planar film layer extending in a direction perpendicular to the substrate 1 .

[0118] In some embodiments, the semiconductor device may further include: a second capacitor electrode 42 filling the second groove, and a dielectric layer 43 disposed between the second capacitor electrode 42 and the first electrode 51 .

[0119] Figures 12A to 12E are schematic diagrams of a semiconductor device provided by another exemplary embodiment, wherein Figure 12A is a cross-sectional view along the aa' direction in Figure 12E, Figure 12B is a cross-sectional view along the bb' direction in Figure 12E, Figure 12C is a cross-sectional view along the cc' direction in Figure 12E, and Figure 12D is a cross-sectional view along the dd' direction in Figure 12E. Figure 12E is a cross-sectional view of a semiconductor device provided by an exemplary embodiment along a direction parallel to the substrate 1. As shown in Figures 12A to 12E, in this embodiment, the first electrode 51 has a second groove, the opening direction of the second groove facing away from the word line 40. Accordingly, the second capacitor electrode 42 may include a vertical portion extending in a direction perpendicular to the substrate 1 and a raised portion extending from the vertical portion into the second groove. The raised portion fills the second groove (filling the area remaining in the second groove after the dielectric layer 43 occupies the remaining area). The first electrode 51 and the second capacitor electrode 42 are insulated by a dielectric layer 43 disposed therebetween. The solution provided by this embodiment can increase the electrode area of ​​the capacitor and increase the capacitance value.

[0120] In some embodiments, the second capacitor electrodes 42 of the capacitors connected to the same column of transistors in different layers can be connected as an integrated structure. As shown in Figure 1A, the main surface of the second capacitor electrode 42 of the capacitors in the first column of different layers extends in a direction perpendicular to the substrate 1 to form a plate shape. As shown in Figure 12A, the main surface of the second capacitor electrode 42 of the capacitors in the first column of different layers extends in a direction perpendicular to the substrate 1 to form a plate shape, and a protrusion is provided on the plate-shaped film layer to fill the opening of the first electrode 51 to form a capacitor with the first electrode 51.

[0121] In some embodiments, the second capacitor electrodes 42 of the capacitors connected to transistors in the same layer and the same column may be connected into an integrated structure.

[0122] In some embodiments, the projections of the first electrodes 51 of adjacent transistors along a direction perpendicular to the substrate 1 in a direction parallel to the substrate 1 may overlap, the projections of the second electrodes 52 in a direction parallel to the substrate 1 may overlap, and the projections of the gate electrodes 26 in a direction parallel to the substrate 1 may overlap. The solution provided in this embodiment allows the regions where the multi-layer stacked first and second electrodes are located to be formed using a single mask patterning process, simplifying the process. Furthermore, the semiconductor device structure can be made more compact.

[0123] In some embodiments, the semiconductor device may further include an insulating film layer filled between different transistors.

[0124] The technical solution of this embodiment will be further illustrated below using the manufacturing process of the semiconductor device of this embodiment. The "patterning process" referred to in this embodiment includes film deposition, photoresist coating, mask exposure, development, etching, and photoresist stripping, and is a mature manufacturing process in the relevant art. The "photolithography process" referred to in this embodiment includes film coating, mask exposure, and development, and is a mature manufacturing process in the relevant art. Deposition can be achieved using known processes such as sputtering, evaporation, and chemical vapor deposition; coating can be achieved using known coating processes; and etching can be achieved using known methods, without specific limitations here. In the description of this embodiment, it should be understood that a "thin film" refers to a thin film of a certain material formed on a substrate using a deposition or coating process. If the "thin film" does not require patterning or photolithography during the entire manufacturing process, it can also be referred to as a "layer." If the "thin film" also requires patterning or photolithography during the entire manufacturing process, the "thin film" before patterning is referred to as a "thin film" and the "layer" after patterning is referred to as a "layer." The "layer" after patterning or photolithography contains at least one "pattern."

[0125] In some embodiments, a semiconductor device manufacturing process may include:

[0126] 101) A first insulating film 9 and a sacrificial layer film 11 are alternately deposited on a substrate 1 to form a stacked structure, as shown in FIG2A, FIG2B, FIG2C and FIG2D, wherein FIG2A is a cross-sectional view along the aa' direction, FIG2B is a cross-sectional view along the bb' direction, FIG2C is a cross-sectional view along the cc' direction, and FIG2D is a cross-sectional view along the dd' direction.

[0127] In some embodiments, the first insulating film 9 may be a low-K dielectric layer, ie, a dielectric layer with a dielectric constant K<3.9, including but not limited to silicon oxide, such as silicon dioxide (SiO 2 ).

[0128] In some embodiments, the sacrificial layer film 11 may include a film layer having a relatively large etching selectivity compared to the first insulating film 9, including but not limited to SiN (silicon nitride). In this embodiment, no conductive film is deposited when manufacturing the stacked structure. When etching the stacked structure in the subsequent process, it is easier to form a smooth vertical surface than etching the stacked structure formed by the insulating film and the conductive film, thereby better controlling the device structure and achieving more stable device performance.

[0129] The stacked structure shown in FIG. 2A to FIG. 2D includes four layers of first insulating films 9 and three layers of sacrificial layer films 11 , which is only an example. In other embodiments, the stacked structure may include more or fewer layers of first insulating films 9 and sacrificial layer films 11 that are alternately arranged.

[0130] 102) forming a through hole K1;

[0131] The forming of the through hole K1 may include:

[0132] The stacked structure is etched to form a plurality of through holes K1 penetrating the stacked structure, as shown in Figures 3A, 3B, 3C, 3D and 3E, wherein Figure 3A is a cross-sectional view along the aa' direction, Figure 3B is a cross-sectional view along the bb' direction, Figure 3C is a cross-sectional view along the cc' direction, Figure 3D is a cross-sectional view along the dd' direction, and Figure 3E is a cross-sectional view along a direction parallel to the substrate 1 after the through hole K1 is formed.

[0133] In some embodiments, the stacked structure may be dry-etched.

[0134] In some embodiments, the through hole K1 may extend in a direction perpendicular to the substrate 1 .

[0135] In some embodiments, the orthographic projection of the through hole K1 on a plane parallel to the substrate 1 may be a square, but the embodiments of the present disclosure are not limited thereto, and the through hole K1 may be a circle, an ellipse, or the like.

[0136] 103) forming a protective layer 32;

[0137] The forming of the protective layer 32 may include:

[0138] A protective layer thin film is deposited on the substrate 1 having the aforementioned structure to form a protective layer 32 covering the sidewalls of the through hole K1, as shown in Figures 4A, 4B, 4C, and 4D. Figure 4A is a cross-sectional view along the aa' direction, Figure 4B is a cross-sectional view along the bb' direction, Figure 4C is a cross-sectional view along the cc' direction, and Figure 4D is a cross-sectional view along the dd' direction. The protective layer 32 can protect the film layer in the through hole K1 in subsequent processes.

[0139] In another exemplary embodiment, a portion of the sacrificial layer film 11 near the through hole K1 can be oxidized to form a protective sublayer 32', as shown in Figures 4E and 4F, where Figure 4E is a cross-sectional view along the aa' direction, and Figure 4F is a cross-sectional view along the cc' direction. The protective sublayer 32' can protect the film layer in the through hole K1 in subsequent processes. In this embodiment, the protective layer 32 can be omitted, that is, the protective sublayer 32' serves as the protective layer.

[0140] In some embodiments, the protective layer film includes but is not limited to silicon oxide, such as silicon dioxide (SiO2).

[0141] 104) forming a gate insulating layer 24 and a gate electrode 26;

[0142] The formation of the gate insulating layer 24 and the gate electrode 26 may include: sequentially depositing a gate insulating film and a gate electrode film filling the through hole K1 in the through hole K1 to form the gate insulating layer 24 and the gate electrode 26, as shown in Figures 5A, 5B, 5C and 5D, wherein Figure 5A is a cross-sectional view along the aa' direction, Figure 5B is a cross-sectional view along the bb' direction, Figure 5C is a cross-sectional view along the cc' direction, and Figure 5D is a cross-sectional view along the dd' direction.

[0143] In some embodiments, gate electrodes 26 of transistors at the same location in different layers are connected to form a word line 40 .

[0144] In some embodiments, the gate electrode 26 extends in a direction perpendicular to the substrate 1 . The gate insulating layer 24 surrounds the sidewalls of the gate electrode 26 .

[0145] In an exemplary embodiment of the present disclosure, the material of the gate insulating layer 24 may include one or more layers of a High-K dielectric material, such as a dielectric material with a dielectric constant K>3.9. In some embodiments, the gate insulating layer 24 may include one or more oxides of hafnium, aluminum, lanthanum, zirconium, etc. Exemplary, for example, it may include but is not limited to at least one of the following: hafnium oxide (HfO2), aluminum oxide (Al2O3), hafnium aluminum oxide (HfAlO), hafnium lanthanum oxide (HfLaO), zirconium oxide (ZrO2), and other high-K materials.

[0146] In an exemplary embodiment, the gate electrode film may be made of one or more of the following different types of materials:

[0147] For example, it may contain metals such as tungsten, aluminum, titanium, copper, nickel, platinum, ruthenium, molybdenum, gold, iridium, rhodium, tantalum, and cobalt; or it may be a metal alloy containing the aforementioned metals;

[0148] Alternatively, it may be a metal oxide, metal nitride, metal silicide, metal carbide, etc., such as metal oxide materials with high conductivity such as indium tin oxide (ITO), indium zinc oxide (IZO), indium oxide (InO); for example, metal nitride materials such as titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), titanium aluminum nitride (TiAlN);

[0149] Alternatively, it may be polysilicon material, conductive doped semiconductor material, etc., such as conductive doped silicon, conductive doped germanium, conductive doped silicon germanium, etc.; other materials that exhibit conductivity, etc.

[0150] 105) The first insulating film 9 and the sacrificial layer film 11 are patterned to form a first insulating layer 10 and a sacrificial layer 12, as shown in Figures 6A, 6B, 6C, 6D, and 6E. Figure 6A is a cross-sectional view along the aa' direction, Figure 6B is a cross-sectional view along the bb' direction, Figure 6C is a cross-sectional view along the cc' direction, and Figure 6D is a cross-sectional view along the dd' direction. Figure 6E is a cross-sectional view parallel to the substrate 1 (the film layer where the sacrificial layer 12 is located). The dotted line in Figure 6E indicates the boundary of the sacrificial layer film 11 when it is not etched.

[0151] In this step, the shape of the sacrificial layer 12 can be determined based on the shapes of the first electrode 51, the second electrode 52, and the bit line 30 of the transistor. In some embodiments, in a cross section parallel to the substrate 1, the shape of the sacrificial layer 12 can be as shown in FIG6E . After the sacrificial layer 12 is subsequently removed, the semiconductor layer 23, the first electrode 51, the second electrode 52, and the bit line 30 of the transistor can be formed in the area where the sacrificial layer 12 was located.

[0152] In this embodiment, the sacrificial layer 12 may include a first sub-portion 121 extending along the first direction X and a second sub-portion 122 extending along the second direction Y; the area where the first sub-portion 121 is located will subsequently form the first electrode 51 of the transistor, and the area where the second sub-portion 122 is located may subsequently form the second electrode 52 of the transistor, as well as forming the bit line 30.

[0153] In some embodiments, the stacked structure may be etched in a direction perpendicular to the substrate 1 using a dry etching method to form the first insulating layer 10 and the sacrificial layer 12 .

[0154] 106) forming a third insulating layer 33;

[0155] The formation of the third insulating layer 33 includes: depositing a third insulating film on the substrate 1 forming the aforementioned structure and then grinding it flat to form a third insulating layer 33, the third insulating layer 33 filling the area where the first insulating film 9 and the sacrificial layer film 11 etched away in step 104 are located, and covering the stacked structure, as shown in Figures 7A, 7B, 7C and 7D, wherein Figure 7A is a cross-sectional view along the aa' direction, Figure 7B is a cross-sectional view along the bb' direction, Figure 7C is a cross-sectional view along the cc' direction, and Figure 7D is a cross-sectional view along the dd' direction.

[0156] In some embodiments, the third insulating film includes but is not limited to silicon oxide, such as silicon dioxide (SiO 2 ).

[0157] 107) exposing the capacitor region 100;

[0158] Exposing the capacitor region 100 may include: patterning the stacked structure, etching away the film layer located in the capacitor region 100, and forming a first trench T1, as shown in Figures 8A, 8B, 8C, and 8D, wherein Figure 8A is a cross-sectional view along the aa' direction, Figure 8B is a cross-sectional view along the bb' direction, Figure 8C is a cross-sectional view along the cc' direction, and Figure 8D is a cross-sectional view along the dd' direction. Capacitors can be subsequently formed in the capacitor region 100. Capacitor regions 100 can be provided on both sides of the stacked structure to form capacitors connected to different transistors. The first trench T1 extends along the second direction Y.

[0159] In some embodiments, the stacked structure may be etched from the top layer to the bottom layer by dry etching to expose the capacitor region 100 .

[0160] 108) etching the sacrificial layer 12;

[0161] Etching the sacrificial layer 12 may include removing the entire sacrificial layer 12 by wet lateral etching based on the first trench T1; as shown in FIG9A , FIG9B , FIG9C , and FIG9D , where FIG9A is a cross-sectional view along the aa' direction, FIG9B is a cross-sectional view along the bb' direction, FIG9C is a cross-sectional view along the cc' direction, and FIG9D is a cross-sectional view along the dd' direction. It can be seen that the entire sacrificial layer 12 has been removed.

[0162] 109) forming a semiconductor layer 23, a first electrode 51, a second electrode 52 and a bit line 30;

[0163] The formation of the semiconductor layer 23, the first electrode 51, the second electrode 52, and the bit line 30 may include: sequentially depositing a semiconductor film and a conductive film on the substrate 1 forming the aforementioned structure to form the semiconductor layer 23, the first electrode 51, the second electrode 52, and the bit line 30, as shown in Figures 10A, 10B, 10C, 10D, and 10E, wherein Figure 10A is a cross-sectional view along the aa' direction, Figure 10B is a cross-sectional view along the bb' direction, Figure 10C is a cross-sectional view along the cc' direction, Figure 10D is a cross-sectional view along the dd' direction, and Figure 10E is a cross-sectional view along a direction parallel to the substrate 1 (a cross-sectional view of the area where the original sacrificial layer 12 is located). The second electrode 52 and the bit line 30 may be connected to form an integrated structure. The conductive film fills the area where the sacrificial layer 12 is etched away in step 108.

[0164] In an exemplary embodiment of the present disclosure, the material of the semiconductor layer 23 may be silicon or polysilicon with a band gap less than 1.65 eV, or a wide band gap material, such as a metal oxide material with a band gap greater than 1.65 eV.

[0165] For example, the material of the metal oxide semiconductor layer or channel may include a metal oxide of at least one of the following metals: indium, gallium, zinc, tin, tungsten, magnesium, zirconium, aluminum, hafnium, etc. Of course, the metal oxide may also contain compounds of other elements, such as nitrogen and silicon, or contain other small amounts of doping elements.

[0166] In some embodiments, the material of the metal oxide semiconductor layer or the channel may include one or more of the following: indium gallium zinc oxide (InGaZnO), indium zinc oxide (InZnO), indium gallium oxide (InGaO), indium tin oxide (InSnO), indium gallium tin oxide (InGaSnO), indium gallium zinc tin oxide (InGaZnSnO), indium oxide (InO), tin oxide (SnO), zinc tin oxide (ZnSnO, ZTO), indium aluminum zinc gold oxide (InAlZnO), zinc oxide (ZnO), indium gallium silicon oxide (InGaSiO), indium tungsten oxide (InWO , IWO), titanium oxide (TiO), zinc oxynitride (ZnON), magnesium zinc oxide (MgZnO), zirconium indium zinc oxide (ZrInZnO), hafnium indium zinc oxide (HfInZnO), tin indium zinc oxide (SnInZnO), aluminum tin indium zinc oxide (AlSnInZnO), silicon indium zinc oxide (SiInZnO), aluminum zinc tin oxide (AlZnSnO), gallium zinc tin oxide (GaZnSnO), zirconium zinc tin oxide (ZrZnSnO) and other materials. As long as the leakage current of the transistor can meet the requirements, the specific adjustment can be made according to the actual situation.

[0167] These materials have a wide band gap and low leakage current. For example, when the metal oxide material is IGZO, the leakage current of the transistor is less than or equal to 10 -15 A, thereby improving the working performance of dynamic memory.

[0168] The material of the metal oxide semiconductor layer or channel only emphasizes the element type of the material, and does not emphasize the atomic ratio in the material and the film quality of the material.

[0169] In some embodiments, the conductive film may be one or more of the following different types of materials:

[0170] For example, it may contain metals such as tungsten, aluminum, titanium, copper, nickel, platinum, ruthenium, molybdenum, gold, iridium, rhodium, tantalum, and cobalt; or it may be a metal alloy containing the aforementioned metals;

[0171] Alternatively, it may be a metal oxide, metal nitride, metal silicide, metal carbide, etc., such as metal oxide materials with high conductivity such as indium tin oxide (ITO), indium zinc oxide (IZO), indium oxide (InO); for example, metal nitride materials such as titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), titanium aluminum nitride (TiAlN);

[0172] Alternatively, it may be polysilicon material, conductive doped semiconductor material, etc., such as conductive doped silicon, conductive doped germanium, conductive doped silicon germanium, etc.; other materials that exhibit conductivity, etc.

[0173] The solution provided in this embodiment is that when different types of conductive films are used to manufacture semiconductor devices, the process before depositing the conductive film remains unchanged, and only the corresponding conductive film needs to be replaced when depositing the conductive film. This facilitates the manufacture of transistors using different conductive films without changing the manufacturing process, thereby reducing costs.

[0174] 110) forming a dielectric layer 43 and a second capacitor electrode 42;

[0175] The forming of the dielectric layer 43 and the second capacitor electrode 42 may include:

[0176] The semiconductor film and the conductive film located in the capacitor region 100 are etched and removed; this step can disconnect the first electrodes 51 of transistors in different layers; that is, the semiconductor film and the conductive film in the first trench T1 are etched and removed;

[0177] A dielectric film and a conductor film are sequentially deposited on the substrate 1 forming the above structure to form a dielectric layer 43 and a second capacitor electrode 42, respectively. The dielectric layer 43 covers the side wall of the first electrode 51 away from the bit line 30, isolating the first electrode 51 and the second capacitor electrode 42. The first electrode 51 also serves as the first capacitor electrode 41 of the capacitor, as shown in Figures 11A, 11B, 11C, 11D and 11E, wherein Figure 11A is a cross-sectional view along the aa' direction, Figure 11B is a cross-sectional view along the bb' direction, Figure 11C is a cross-sectional view along the cc' direction, Figure 11D is a cross-sectional view along the dd' direction, and Figure 11E is a cross-sectional view along a direction parallel to the substrate 1.

[0178] The dielectric layer 43 serves as a medium between the capacitor electrodes, the second capacitor electrode 42 serves as one electrode of the capacitor, and the first electrode 51 serves as the other electrode of the capacitor, namely, the first capacitor electrode 41 .

[0179] In some embodiments, the dielectric film and the conductor film may be deposited by atomic layer deposition (ALD).

[0180] In an exemplary embodiment, the dielectric layer 43 may be a Low-K material, such as silicon oxide. Alternatively, it may be a High-K material, such as a dielectric material with a dielectric constant K ≥ 3.9. In some embodiments, it may include one or more oxides of hafnium, aluminum, lanthanum, zirconium, etc. Exemplary, for example, it may include but is not limited to at least one of the following: hafnium oxide (HfO2), aluminum oxide (Al2O3), hafnium aluminum oxide (HfAlO), hafnium lanthanum oxide (HfLaO), zirconium oxide (ZrO2), and other high-K materials.

[0181] In an exemplary embodiment, the conductive film includes but is not limited to at least one of the following or a combination thereof:

[0182] Metals or alloys, for example, metals containing tungsten, aluminum, titanium, copper, nickel, platinum, ruthenium, molybdenum, gold, iridium, rhodium, tantalum, cobalt, etc., and metal alloys containing the aforementioned metals;

[0183] Alternatively, it can be a metal oxide, metal nitride, metal silicide, metal carbide, etc., such as tin-doped indium oxide (ITO), indium-doped zinc oxide (IZO), indium oxide (InO), aluminum-doped zinc oxide (Al-doped ZnO, AZO), iridium oxide (IrOx), ruthenium oxide (RuOx) and other metal oxide conductive materials; for example, titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), titanium aluminum nitride (TiAlN) and other metal nitride materials.

[0184] In another exemplary embodiment, a process for manufacturing a semiconductor device may include:

[0185] 201) to 207), the same as steps 101) to 107), forming the structure shown in Figures 8A, 8B, 8C and 8D.

[0186] 208) etching a portion of the sacrificial layer 12;

[0187] Etching a portion of the sacrificial layer 12 may include: removing the first sub-portion 121 by transverse etching based on the first trench T1, retaining the second sub-portion 122, and forming a first transverse groove A1 in the area where the first sub-portion 121 is located after the first sub-portion 121 is etched away. As shown in Figures 13A, 13B, 13C, and 13D, Figure 13A is a cross-sectional view along the aa' direction, Figure 13B is a cross-sectional view along the bb' direction, Figure 13C is a cross-sectional view along the cc' direction, and Figure 13D is a cross-sectional view along the dd' direction.

[0188] In some embodiments, the portion of the sacrificial layer 12 may be etched by wet etching.

[0189] 209) forming a first semiconductor sublayer 231 and a first electrode 51;

[0190] The formation of the first semiconductor sublayer 231 and the first electrode 51 may include: depositing a first semiconductor film and a first conductive film in sequence on the substrate 1 forming the aforementioned structure to form the first semiconductor sublayer 231 and the first electrode 51, as shown in Figures 14A, 14B, 14C, and 14D, wherein Figure 14A is a cross-sectional view along the aa' direction, Figure 14B is a cross-sectional view along the bb' direction, Figure 14C is a cross-sectional view along the cc' direction, and Figure 14D is a cross-sectional view along the dd' direction. In this step, only a portion of the semiconductor layer 23 is formed, and the other portion of the semiconductor layer 23 is manufactured subsequently. The first conductive film does not completely fill the area where the first sub-portion 121 etched in step 208 is located, that is, the first conductive film does not completely fill the first lateral groove A1.

[0191] 210) The first semiconductor film and the first conductive film located in the capacitor region 100 are etched and removed; that is, the first semiconductor film and the first conductive film in the first trench T1 are etched and removed, and the first semiconductor film and the first conductive film in the first lateral groove A1 are retained, as shown in Figures 15A, 15B, 15C, and 15D, wherein Figure 15A is a cross-sectional view along the aa' direction, Figure 15B is a cross-sectional view along the bb' direction, Figure 15C is a cross-sectional view along the cc' direction, and Figure 15D is a cross-sectional view along the dd' direction.

[0192] This step can disconnect the first electrodes 51 of transistors in different layers. In this embodiment, the cross-section of the first electrode 51 in the direction perpendicular to the substrate 1 is U-shaped, that is, the first electrode 51 has a second groove facing the side away from the bit line 30. The first electrode 51 serves as the first capacitor electrode of the capacitor. The first electrode 51 has a second groove that has no opening compared to the first electrode 51, which can increase the capacitor electrode area and increase the capacitance value.

[0193] 211) forming a dielectric layer 43 and a second capacitor electrode 42;

[0194] The forming of the dielectric layer 43 and the second capacitor electrode 42 may include:

[0195] A dielectric film and a conductive film are sequentially deposited on the substrate 1 having the above structure, forming a dielectric layer 43 and a second capacitor electrode 42, respectively. The conductive film fills the first transverse groove A1, and the dielectric layer 43 covers the sidewall of the first electrode 51 away from the bit line 30, isolating the first electrode 51 from the second capacitor electrode 42. The first electrode 51 also serves as the first capacitor electrode 41 of the capacitor, as shown in Figures 16A, 16B, 16C, 16D, and 16E. Figure 16A is a cross-sectional view along the aa' direction, Figure 16B is a cross-sectional view along the bb' direction, Figure 16C is a cross-sectional view along the cc' direction, Figure 16D is a cross-sectional view along the dd' direction, and Figure 16E is a cross-sectional view parallel to the substrate 1 (a cross-sectional view of the region where the sacrificial layer 12 is located). In this embodiment, the second capacitor electrode 42 fills the second groove of the first electrode 51, and the first electrode 51 is separated from the second capacitor electrode 42 by the dielectric layer 43.

[0196] 212) removing the second subsection 122;

[0197] The removing of the second sub-portion 122 may include: removing the second sub-portion 122 by wet lateral etching to form a second lateral groove A2, as shown in Figures 17A, 17B, 17C, and 17D, wherein Figure 17A is a cross-sectional view along the aa' direction, Figure 17B is a cross-sectional view along the bb' direction, Figure 17C is a cross-sectional view along the cc' direction, and Figure 17D is a cross-sectional view along the dd' direction.

[0198] 213) forming a second semiconductor sublayer 232 and a bit line 30;

[0199] The formation of the second semiconductor sublayer 232 and the bit line 30 may include: sequentially depositing a second semiconductor film and a second conductive film on the substrate 1 forming the aforementioned structure to form the second semiconductor sublayer 232 and the bit line 30, as shown in Figures 18A, 18B, 18C, 18D, and 18E, wherein Figure 18A is a cross-sectional view along the aa' direction, Figure 18B is a cross-sectional view along the bb' direction, Figure 18C is a cross-sectional view along the cc' direction, Figure 18D is a cross-sectional view along the dd' direction, and Figure 18E is a cross-sectional view along a direction parallel to the substrate 1 (a cross-sectional view of the film layer where the bit line 30 is located). The first semiconductor sublayer 231 and the second semiconductor sublayer 232 constitute the semiconductor layer 23. The second conductive film fills the second lateral groove A2.

[0200] The solution provided in this embodiment is that when different types of conductive films are used to manufacture semiconductor devices, the process other than depositing the conductive film remains unchanged. It is only necessary to replace the conductive film with a conductive film of the corresponding material when depositing the conductive film. This facilitates the manufacture of transistors using conductive films of different materials without changing the manufacturing process, thereby reducing costs.

[0201] The present disclosure also provides an electronic device comprising the semiconductor device described in any of the preceding embodiments. The electronic device may be a storage device, a smartphone, a computer, a tablet computer, an artificial intelligence device, a wearable device, or a mobile power bank. The storage device may include, but is not limited to, computer memory.

[0202] An embodiment of the present disclosure provides a method for manufacturing a semiconductor device, wherein the semiconductor device includes a plurality of transistors distributed in different layers and stacked along a direction perpendicular to a substrate, and word lines and bit lines extending in a direction perpendicular to the substrate; the transistors include a first electrode, a second electrode, and a semiconductor layer surrounding the sidewalls of the word lines and insulated from the word lines; the method for manufacturing the semiconductor device may include:

[0203] Providing a substrate, and alternately depositing a first insulating film and a sacrificial layer film on the substrate to form a stacked structure including multiple insulating layers and multiple sacrificial layers;

[0204] forming a through hole penetrating the stacked structure in a direction perpendicular to the substrate, with the sidewall of the through hole exposing each of the sacrificial layers; forming a protective layer, the protective layer covering the sidewall of the sacrificial layer facing the through hole, and sequentially depositing a gate insulating film and a gate electrode film filling the through hole in the through hole to form a multi-layer gate insulating layer and word line of the transistor;

[0205] The stacked structure is patterned so that the sacrificial layer forms a predetermined pattern, the predetermined pattern including a first sub-portion and a second sub-portion connected to the first sub-portion, the orthographic projection of the through hole on the substrate is located within an outer contour of the orthographic projection of the predetermined pattern on the substrate, the first sub-portion extends along a first direction, the second sub-portion extends along a second direction, and the first direction intersects the second direction;

[0206] The first sub-portion and the second sub-portion are etched to form a first semiconductor sub-layer and a first electrode in the area where the first sub-portion is located, and a second semiconductor sub-layer and a bit line are formed in the area where the second sub-portion is located, wherein the first semiconductor sub-layer and the second semiconductor sub-layer constitute a semiconductor layer of the transistor, the semiconductor layer surrounds the side wall of the word line, the semiconductor layer includes a first groove with an opening facing away from the word line, and the first electrode is located in the first groove and is connected to the semiconductor layer.

[0207] In some embodiments, forming a protection layer in the through hole to prevent the sacrificial layer from being exposed includes:

[0208] Depositing a protective layer film in the through hole to form the protective layer;

[0209] Alternatively, the sacrificial layer film exposed on the sidewall of the through hole is oxidized to form the protection layer.

[0210] In some embodiments, etching the first sub-portion and etching the second sub-portion to form a first semiconductor sub-layer and a first electrode in the area where the first sub-portion is located, and forming a second semiconductor sub-portion and a second electrode in the area where the second sub-portion is located includes:

[0211] etching and removing the first sub-portion and the second sub-portion by a single wet etching process;

[0212] A semiconductor film and a conductive film are sequentially deposited in the area where the first sub-section is located and the area where the second sub-section is located to form a semiconductor layer including the first semiconductor sub-layer and the second semiconductor sub-layer, a first electrode, and a bit line.

[0213] In some embodiments, etching the first sub-portion and etching the second sub-portion to form a first semiconductor sub-layer and a first electrode in the area where the first sub-portion is located, and forming a second semiconductor sub-portion and a second electrode in the area where the second sub-portion is located includes:

[0214] Etching to remove the first sub-portion, and sequentially depositing a first semiconductor film and a first conductive film in the area where the first sub-portion is located to form the first semiconductor sub-layer and the first electrode;

[0215] The second sub-portion is removed by etching, and a second semiconductor film and a second conductive film filling the area where the second sub-portion is located are sequentially deposited in the area where the second sub-portion is located to form the second semiconductor sub-layer and the bit line.

[0216] In some embodiments, depositing a first conductive film in the area where the first sub-portion is located includes:

[0217] After depositing a first semiconductor film in the area where the first sub-section is located, depositing a first conductive film on the first semiconductor film to fill the area where the first sub-section is located;

[0218] Alternatively, after depositing a first semiconductor film in the area where the first sub-portion is located, a first conductive film is deposited on the first semiconductor film with a preset thickness, so that the first conductive film forms a second groove with an opening away from the word line.

[0219] Although the embodiments disclosed herein are as described above, the contents described herein are merely embodiments for facilitating understanding of the present invention and are not intended to limit the present invention. Any person skilled in the art may make any modifications and variations in the form and details of the embodiments without departing from the spirit and scope of the present invention. However, the scope of patent protection of the present invention shall remain subject to the scope defined by the appended claims.

Claims

1. A semiconductor device, comprising: Multiple transistors are distributed in different layers and stacked along the direction perpendicular to the substrate; A word line, extending through the different layers in a direction perpendicular to the substrate; The transistor comprises a first electrode, a semiconductor layer surrounding the sidewall of the word line, a gate insulating layer arranged between the sidewall of the word line and the semiconductor layer, and a protection layer arranged between the semiconductor layer and the gate insulating layer; The semiconductor layer includes a first groove with an opening facing away from the word line. The first electrode is located in the first groove and connected to the semiconductor layer.

2. The semiconductor device according to claim 1, wherein A plurality of semiconductor layers of a plurality of transistors in the same column distributed along a direction perpendicular to the substrate are arranged at intervals.

3. The semiconductor device according to claim 1, wherein A plurality of protection layers of a plurality of transistors in the same column distributed along a direction perpendicular to the substrate are arranged at intervals.

4. The semiconductor device according to claim 1, wherein: The orthographic projection of the protection layer on the substrate is located outside the orthographic projection of the gate insulation layer on the substrate.

5. The semiconductor device according to claim 1, wherein The transistor also includes a second electrode connected to the semiconductor layer, and the semiconductor device also includes: a plurality of bit lines distributed in different layers and respectively connected to the second electrodes of the plurality of transistors and extending along a second direction parallel to the substrate; the semiconductor layer of the transistor also surrounds the side walls of the bit lines connected to the transistor.

6. The semiconductor device according to claim 1, wherein The semiconductor layer of the transistor is also connected to one end surface of a bit line to which the transistor is connected.

7. The semiconductor device according to claim 5, wherein: The second electrode and the bit line are connected to form an integrated structure.

8. The semiconductor device according to any one of claims 1 to 7, wherein: The gate insulating layers of a plurality of transistors in the same column distributed along a direction perpendicular to the substrate are connected to form an integrated structure.

9. The semiconductor device according to claim 5 or 7, wherein: The semiconductor device further comprises: Insulating layers and conductive layers are alternately distributed from bottom to top in a direction vertical to the substrate, wherein the conductive layer includes the first electrode and the second electrode; A through hole penetrates each of the insulating layers and each of the conductive layers, wherein the word line, the gate insulating layer surrounding the side wall of the word line, and the protection layer surrounding the side wall of the gate insulating layer are sequentially distributed in the through hole from inside to outside.

10. The semiconductor device according to any one of claims 1 to 7, wherein: The first electrode includes a second groove opening away from the word line.

11. The semiconductor device according to claim 10, wherein: The semiconductor device further includes: a second capacitor electrode filling the second groove, and a dielectric layer disposed between the second capacitor electrode and the first electrode.

12. The semiconductor device according to any one of claims 1 to 7, wherein: The semiconductor device further includes: a second capacitor electrode, and a dielectric layer disposed between the second capacitor electrode and the first electrode, wherein a contact surface between the dielectric layer and the first electrode is perpendicular to the substrate.

13. An electronic device comprising the semiconductor device according to any one of claims 1 to 12.

14. A method for manufacturing a semiconductor device, the semiconductor device comprising a plurality of transistors distributed in different layers and stacked along a direction perpendicular to a substrate, a word line and a bit line extending along a direction perpendicular to the substrate; the transistor comprising a first electrode, a second electrode, and a semiconductor layer surrounding a side wall of the word line and insulated from the word line; The method for manufacturing the semiconductor device comprises: Providing a substrate, and alternately depositing a first insulating film and a sacrificial layer film on the substrate in sequence to form a stacked structure including a plurality of insulating layers and a plurality of sacrificial layers; Forming a through hole penetrating the stacked structure in a direction perpendicular to the substrate, wherein the sidewall of the through hole exposes each of the sacrificial layers; forming a protective layer, wherein the protective layer covers the sidewall of the sacrificial layer facing the through hole, and sequentially depositing a gate insulating film and a gate electrode film filling the through hole in the through hole to form a multi-layer gate insulating layer and a word line of the transistor; The stacked structure is patterned so that the sacrificial layer forms a preset pattern, the preset pattern includes a first sub-portion and a second sub-portion connected to the first sub-portion, the orthographic projection of the through hole on the substrate is located within the outer contour of the orthographic projection of the preset pattern on the substrate, the first sub-portion extends along a first direction, the second sub-portion extends along a second direction, and the first direction intersects the second direction; The first sub-portion and the second sub-portion are etched to form a first semiconductor sub-layer and a first electrode in the area where the first sub-portion is located, and a second semiconductor sub-layer and a bit line are formed in the area where the second sub-portion is located, the first semiconductor sub-layer and the second semiconductor sub-layer constitute a semiconductor layer of the transistor, the semiconductor layer surrounds the side wall of the word line, the semiconductor layer includes a first groove with an opening facing away from the word line, and the first electrode is located in the first groove and connected to the semiconductor layer.

15. The method for manufacturing a semiconductor device according to claim 14, wherein: The forming of the protective layer comprises: Depositing a protective layer film in the through hole to form the protective layer; Alternatively, the end surface of the sacrificial layer exposed on the side wall of the through hole and a region whose distance from the end surface is less than or equal to a preset distance are oxidized to form the protective layer.

16. The method for manufacturing a semiconductor device according to claim 14, wherein: The etching of the first sub-portion and the etching of the second sub-portion to form a first semiconductor sub-layer and a first electrode in the region where the first sub-portion is located, and forming a second semiconductor sub-portion and a second electrode in the region where the second sub-portion is located comprises: etching and removing the first sub-portion and the second sub-portion by a single wet etching process; A semiconductor film and a conductive film are sequentially deposited in the region where the first sub-portion is located and the region where the second sub-portion is located to form a semiconductor layer including the first semiconductor sub-layer and the second semiconductor sub-layer, a first electrode, and a bit line.

17. The method for manufacturing a semiconductor device according to claim 14, wherein: The etching of the first sub-portion and the etching of the second sub-portion to form a first semiconductor sub-layer and a first electrode in the region where the first sub-portion is located, and forming a second semiconductor sub-portion and a second electrode in the region where the second sub-portion is located comprises: The first sub-portion is removed by etching, and a first semiconductor film and a first conductive film are sequentially deposited in the region where the first sub-portion is located to form the first semiconductor sub-layer and the first electrode; The second sub-portion is removed by etching, and a second semiconductor film and a second conductive film filling the area where the second sub-portion is located are sequentially deposited in the area where the second sub-portion is located to form the second semiconductor sub-layer and the bit line.

18. The method for manufacturing a semiconductor device according to claim 17, wherein: Depositing a first conductive film in the area where the first sub-portion is located comprises: After depositing a first semiconductor film in the area where the first sub-portion is located, depositing a first conductive film on the first semiconductor film to fill the area where the first sub-portion is located; Alternatively, after depositing a first semiconductor film in the region where the first sub-section is located, depositing a The first conductive film is deposited to a preset thickness so that the first conductive film forms a second groove having an opening facing away from the word line.

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