Semiconductor device and method for manufacturing semiconductor device

Abstract

Provided is a semiconductor device that can be miniaturized or highly integrated. This semiconductor device is provided with a memory cell having first to third vertical transistors. The first to third vertical transistors are provided stacked from the bottom in the given order. The first vertical transistor has a gate electrode between a lower electrode and an upper electrode, and the gate electrode surrounds a semiconductor layer. An insulating layer is embedded inside the semiconductor layer, and an upper surface of the insulating layer is positioned above an upper surface of the semiconductor layer in a region overlapping the upper electrode. The second and third vertical transistors have a gate electrode further inward than the semiconductor layer. A lower electrode of the second vertical transistor is positioned on the insulating layer and is in contact with the semiconductor layer of the first vertical transistor. The conductive layer used for the gate electrode of the second vertical transistor and the conductive layer used for a lower electrode of the third vertical transistor are the same.

Description

Semiconductor device and method for manufacturing the same

[0001] 1. Field of the Invention One embodiment of the present invention relates to a semiconductor device, a memory device, a display device, and an electronic device. Another embodiment of the present invention relates to a manufacturing method of a semiconductor device.

[0002] One embodiment of the present invention is not limited to the above technical field, and examples of the technical field of one embodiment of the present invention include semiconductor devices, display devices, light-emitting devices, power storage devices, memory devices, electronic devices, lighting devices, input devices (e.g., touch sensors), input / output devices (e.g., touch panels), driving methods thereof, and manufacturing methods thereof.

[0003] In this specification and the like, a semiconductor device is a device that utilizes semiconductor characteristics, and refers to a circuit including a semiconductor element (transistor, diode, photodiode, etc.), a device having such a circuit, etc. Also, it refers to any device that can function by utilizing semiconductor characteristics. For example, an integrated circuit, a chip including an integrated circuit, and an electronic component in which a chip is housed in a package are examples of semiconductor devices. Furthermore, a memory device, a display device, a light-emitting device, a lighting device, and an electronic device may themselves be semiconductor devices and each may have a semiconductor device.

[0004] In recent years, semiconductor devices have been developed, and semiconductor devices mainly use LSIs (Large Scale Integration), CPUs (Central Processing Units), memories, etc. A CPU is an aggregate of semiconductor elements that have semiconductor integrated circuits (at least transistors and memories) formed into chips by processing a semiconductor wafer and on which electrodes serving as connection terminals are formed.

[0005] 2. Description of the Related Art Semiconductor circuits (IC chips) such as LSIs, CPUs, and memories are mounted on circuit boards, such as printed wiring boards, and are used as components of various electronic devices.

[0006] Furthermore, a technique for constructing a transistor using a semiconductor thin film formed on a substrate having an insulating surface has been attracting attention. Such transistors are widely applied to electronic devices such as integrated circuits (ICs) and display devices. While silicon-based semiconductor materials are widely known as semiconductor thin films applicable to transistors, oxide semiconductors have also been attracting attention as other materials.

[0007] Furthermore, it is known that a transistor using an oxide semiconductor has an extremely small leakage current in an off state. For example, Patent Document 1 discloses a CPU with low power consumption that utilizes the property of a transistor using an oxide semiconductor that has a small leakage current. Furthermore, Patent Document 2 discloses a memory device that can retain stored data for a long period of time by utilizing the property of a transistor using an oxide semiconductor that has a small leakage current.

[0008] In addition, with the recent trend toward smaller and lighter electronic devices, there is an increasing demand for higher density integrated circuits. There is also a demand for improved productivity of semiconductor devices including integrated circuits. For example, Patent Document 3 and Non-Patent Document 1 disclose a technique for increasing the density of integrated circuits by stacking a first transistor using an oxide semiconductor film and a second transistor using an oxide semiconductor film to provide multiple memory cells in an overlapping manner. Patent Document 4 discloses a technique for increasing the density of integrated circuits by vertically arranging the channel of a transistor using an oxide semiconductor film.

[0009] JP 2012-257187 A JP 2011-151383 A WO 2021 / 053473 JP 2013-211537 A

[0010] M. Oota et. al, “3D-Stacked CAAC-In-Ga-Zn Oxide FETs with Gate Length of 72nm”, IEDM Tech. Dig. , 2019, pp. 50-53

[0011] An object of one embodiment of the present invention is to provide a semiconductor device that can be miniaturized or highly integrated, and a manufacturing method thereof. Another object of one embodiment of the present invention is to provide a highly reliable semiconductor device and a manufacturing method thereof. Another object of one embodiment of the present invention is to provide a semiconductor device that operates at high speed, and a manufacturing method thereof. Another object of one embodiment of the present invention is to provide a semiconductor device that consumes low power, and a manufacturing method thereof. Another object of one embodiment of the present invention is to provide a manufacturing method of a semiconductor device with a high yield. Another object of one embodiment of the present invention is to provide a novel semiconductor device, and a manufacturing method thereof.

[0012] Note that the description of these problems does not preclude the existence of other problems. One embodiment of the present invention does not necessarily have to solve all of these problems. Problems other than these can be extracted from the description in the specification, drawings, and claims.

[0013] One embodiment of the present invention includes a first semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, a first insulating layer, a second insulating layer, a third insulating layer, a fourth insulating layer, and a fifth insulating layer, wherein the first insulating layer is located on the first conductive layer, the second conductive layer is located on the first insulating layer, the second insulating layer is located on the second conductive layer and on the first insulating layer, and the third conductive layer is located on the second insulating layer, the first insulating layer, the second conductive layer, the second insulating layer, and the third conductive layer have a first opening that reaches the first conductive layer, and the third insulating layer is in contact with a side surface of the second conductive layer inside the first opening, and the first semiconductor layer a first semiconductor layer in contact with a first conductive layer, the first semiconductor layer in contact with an upper surface of the third conductive layer, the first semiconductor layer having a first region facing the second conductive layer within the first opening with the third insulating layer sandwiched therebetween, at least a portion of the first region in contact with the third insulating layer, a fourth insulating layer being located inside the first opening relative to the first semiconductor layer, a fifth insulating layer being provided inside the fourth insulating layer to fill the first opening and being planarized, the first semiconductor layer having a second region overlapping with the third conductive layer, and an upper surface of the fifth insulating layer being located higher than an upper surface of the second region of the first semiconductor layer.

[0014] Alternatively, in the above aspect, there may be a sixth insulating layer and a seventh insulating layer, the sixth insulating layer covering the side of the third conductive layer opposite to the side on the first opening side, and the seventh insulating layer being located on the sixth insulating layer.

[0015] Alternatively, in the above aspect, the semiconductor device may have a second semiconductor layer, a fourth conductive layer, a fifth conductive layer, a sixth conductive layer, a sixth insulating layer, and a seventh insulating layer, wherein the fourth conductive layer is located on the fifth insulating layer and the fourth conductive layer is in contact with the second region, the sixth insulating layer is located on the fourth conductive layer, and the fifth conductive layer is located on the sixth insulating layer, the sixth insulating layer and the fifth conductive layer have a second opening that reaches the fourth conductive layer, the second semiconductor layer has a region that is in contact with the fourth conductive layer and the fifth conductive layer and is located inside the second opening, the seventh insulating layer is located on the second semiconductor layer and is located inside the second opening, and the sixth conductive layer is located on the seventh insulating layer and is located inside the second opening.

[0016] Alternatively, in the above aspect, the semiconductor device may have a third semiconductor layer, a seventh conductive layer, an eighth conductive layer, an eighth insulating layer, and a ninth insulating layer, wherein the eighth insulating layer is located on the sixth conductive layer, the seventh conductive layer is located on the eighth insulating layer, the eighth insulating layer and the seventh conductive layer have a third opening that reaches the sixth conductive layer, the third semiconductor layer has a region that is in contact with the sixth conductive layer and the seventh conductive layer and is located inside the third opening, the ninth insulating layer is located on the third semiconductor layer and is located inside the third opening, and the eighth conductive layer is located on the ninth insulating layer and is located inside the third opening.

[0017] Alternatively, in the above aspect, the semiconductor device may have a ninth conductive layer and a tenth insulating layer, the eighth insulating layer has an eleventh insulating layer and a twelfth insulating layer on the eleventh insulating layer, the ninth conductive layer is located on the eleventh insulating layer, the twelfth insulating layer is located on the ninth conductive layer and on the eleventh insulating layer, the eleventh insulating layer, the ninth conductive layer, and the twelfth insulating layer have a third opening, the tenth insulating layer contacts a side surface of the ninth conductive layer inside the third opening, the third semiconductor layer contacts the tenth insulating layer inside the third opening, and the third semiconductor layer may have a third region that faces the eighth conductive layer across the ninth insulating layer and that faces the ninth conductive layer across the tenth insulating layer.

[0018] Alternatively, in the above-described embodiment, a metal oxide is used for each of the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer, and the metal oxide has two or three elements selected from indium, the element M, and zinc, and the element M may be one or more elements selected from aluminum, gallium, tin, yttrium, titanium, vanadium, chromium, manganese, iron, cobalt, nickel, zirconium, molybdenum, hafnium, tantalum, tungsten, lanthanum, cerium, neodymium, magnesium, calcium, strontium, barium, boron, silicon, germanium, and antimony.

[0019] Alternatively, one embodiment of the present invention includes forming a first conductive layer, forming a first insulating layer over the first conductive layer, forming a second conductive layer over the first insulating layer, forming a second insulating layer over the second conductive layer and the first insulating layer, forming a third conductive layer over the second insulating layer, forming a first opening that reaches the first conductive layer in the third conductive layer, the second insulating layer, the second conductive layer, and the first insulating layer, forming the third insulating layer to cover the first opening, and processing the third insulating layer by anisotropic etching to expose a top surface of the third conductive layer and the first conductive layer, forming a first semiconductor layer to cover the third insulating layer and to be in contact with the top surface of the third conductive layer and the first conductive layer, forming a fourth insulating layer to cover the first semiconductor layer, and forming a fifth insulating layer over the fourth insulating layer to have a region located inside the first opening, until at least a part of a top surface of the fourth insulating layer is exposed. a sixth insulating layer having a region located inside the first opening by performing planarization treatment on the fifth insulating layer; a seventh insulating layer having a region located inside the first opening by removing part of the fourth insulating layer; at least a part of a top surface of the first semiconductor layer is exposed; a fourth conductive layer is formed to be in contact with a top surface of the sixth insulating layer and a top surface of the first semiconductor layer; an eighth insulating layer is formed on the fourth conductive layer; a fifth conductive layer is formed on the eighth insulating layer; a second opening is formed in the fifth conductive layer and the eighth insulating layer, reaching the fourth conductive layer; a second semiconductor layer is formed to cover the second opening and to be in contact with the fourth conductive layer and the fifth conductive layer; a ninth insulating layer is formed to cover the second semiconductor layer; and a sixth conductive layer is formed on the ninth insulating layer to have a region located inside the second opening.

[0020] Alternatively, in the above aspect, a tenth insulating layer may be formed on the sixth conductive layer, a seventh conductive layer may be formed on the tenth insulating layer, a third opening that reaches the sixth conductive layer may be formed in the seventh conductive layer and the tenth insulating layer, a third semiconductor layer may be formed to cover the third opening and to be in contact with the sixth conductive layer and the seventh conductive layer, an eleventh insulating layer may be formed to cover the third semiconductor layer, and an eighth conductive layer may be formed on the eleventh insulating layer to have a region located inside the third opening.

[0021] Alternatively, in the above aspect, a tenth insulating layer may be formed on the sixth conductive layer, a seventh conductive layer may be formed on the tenth insulating layer, an eleventh insulating layer may be formed on the seventh conductive layer and the tenth insulating layer, an eighth conductive layer may be formed on the eleventh insulating layer, a third opening reaching the sixth conductive layer may be formed in the eighth conductive layer, the eleventh insulating layer, the seventh conductive layer, and the tenth insulating layer, a twelfth insulating layer may be formed to cover the third opening, and the twelfth insulating layer may be processed by anisotropic etching to expose an upper surface of the eighth conductive layer and the sixth conductive layer, a third semiconductor layer may be formed to cover the twelfth insulating layer and to be in contact with the upper surface of the eighth conductive layer and the sixth conductive layer, a thirteenth insulating layer may be formed to cover the third semiconductor layer, and a ninth conductive layer may be formed on the thirteenth insulating layer to have a region located inside the third opening.

[0022] Alternatively, in the above embodiment, after performing a planarization treatment on the fifth insulating layer, the fourth insulating layer may be processed to remove at least a portion of the region of the fourth insulating layer that does not overlap with the sixth insulating layer.

[0023] Alternatively, in the above embodiment, a fourth opening that overlaps with the first semiconductor layer may be formed in the fifth insulating layer by performing a planarization treatment on the fifth insulating layer, and the fourth insulating layer may be processed to remove a region of the fourth insulating layer that does not overlap with either the fifth insulating layer or the sixth insulating layer.

[0024] According to one embodiment of the present invention, a semiconductor device that can be miniaturized or highly integrated and a manufacturing method thereof can be provided. Alternatively, according to one embodiment of the present invention, a highly reliable semiconductor device and a manufacturing method thereof can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device that operates at high speed and a manufacturing method thereof can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device that consumes low power and a manufacturing method thereof can be provided. Alternatively, according to one embodiment of the present invention, a manufacturing method of a semiconductor device with high yield can be provided. Alternatively, according to one embodiment of the present invention, a novel semiconductor device and a manufacturing method thereof can be provided.

[0025] Note that the description of these effects does not preclude the existence of other effects. One embodiment of the present invention does not necessarily have all of these effects. Effects other than these can be extracted from the description in the specification, drawings, and claims.

[0026] FIG. 1A is a circuit diagram showing an example of the configuration of a memory cell. FIGS. 1B to 1D are plan views showing an example of the configuration of a semiconductor device. FIGS. 2A and 2B are cross-sectional views showing an example of the configuration of a semiconductor device. FIGS. 3A to 3D are plan views showing an example of the configuration of a semiconductor device. FIGS. 4A and 4B are cross-sectional views showing an example of the configuration of a semiconductor device. FIGS. 5A and 5B are plan views showing an example of the configuration of a semiconductor device. FIGS. 5C and 5D are cross-sectional views showing an example of the configuration of a semiconductor device. FIGS. 6A and 6B are cross-sectional views showing an example of the configuration of a semiconductor device. FIG. 7A is a circuit diagram showing an example of the configuration of a memory cell. FIG. 7B is a plan view showing an example of the configuration of a semiconductor device. FIGS. 7C and 7D are cross-sectional views showing an example of the configuration of a semiconductor device. FIGS. 8A and 8B are cross-sectional views showing an example of the configuration of a semiconductor device. FIGS. 9A and 9B are cross-sectional views showing an example of the configuration of a semiconductor device. FIGS. 10A and 10B are cross-sectional views showing an example of the configuration of a semiconductor device. FIGS. 11A and 11B are cross-sectional views showing an example of the configuration of a semiconductor device. FIGS. 12A and 12B are cross-sectional views showing a structural example of a semiconductor device. FIGS. 13A and 13B are cross-sectional views showing a structural example of a semiconductor device. FIGS. 14A and 14B are cross-sectional views showing a structural example of a semiconductor device. FIGS. 15A and 15B are cross-sectional views showing a structural example of a semiconductor device. FIGS. 16A and 16B are cross-sectional views showing a structural example of a semiconductor device. FIGS. 17A to 17D are cross-sectional views showing a manufacturing method example of a semiconductor device. FIGS. 18A to 18C are cross-sectional views showing a manufacturing method example of a semiconductor device. FIGS. 19A to 19C are cross-sectional views showing a manufacturing method example of a semiconductor device. FIGS. 20A and 20B are cross-sectional views showing a manufacturing method example of a semiconductor device. FIGS. 21A and 21B are cross-sectional views showing a manufacturing method example of a semiconductor device. FIG. 22 is a cross-sectional view showing a manufacturing method example of a semiconductor device. FIG. 23 is a cross-sectional view showing a manufacturing method example of a semiconductor device. FIG. 24 is a cross-sectional view showing a manufacturing method example of a semiconductor device. FIGS. 25A to 25D are cross-sectional views showing a method for forming a metal oxide film. 26A to 26D are cross-sectional views showing a method for forming a metal oxide film, Fig. 27 is a cross-sectional view showing an example of the configuration of a semiconductor device, and Fig. 28 is a cross-sectional view showing an example of the configuration of a semiconductor device.Fig. 29 is a block diagram showing an example of the configuration of a semiconductor device. Figs. 30A and 30B are perspective views showing an example of the configuration of a semiconductor device. Fig. 31 is a block diagram explaining a CPU. Figs. 32A and 32B are perspective views showing an example of the configuration of a semiconductor device. Figs. 33A and 33B are perspective views showing an example of the configuration of a semiconductor device. Figs. 34A and 34B are views showing the hierarchy of a storage device. Figs. 35A and 35B are views showing an example of electronic components. Figs. 36A to 36C are views showing an example of a mainframe computer. Fig. 36D is a view showing an example of space equipment. Fig. 36E is a view showing an example of a storage system applicable to a data center.

[0027] The embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it will be readily understood by those skilled in the art that various changes can be made in form and detail without departing from the spirit and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the description of the embodiments shown below.

[0028] In the configuration of the invention described below, the same parts or parts having similar functions are denoted by the same reference numerals in different drawings, and repeated explanations thereof will be omitted. Furthermore, when referring to similar functions, the same hatching pattern may be used and no particular reference numeral may be assigned.

[0029] Furthermore, for ease of understanding, the position, size, range, etc. of each component shown in the drawings may not represent the actual position, size, range, etc. Therefore, the disclosed invention is not necessarily limited to the position, size, range, etc. disclosed in the drawings.

[0030] In this specification, the ordinal numbers such as "first" and "second" are used for convenience and do not limit the number of components or the order of the components (for example, the order of processes or the order of stacking). Furthermore, the ordinal numbers assigned to components in one part of this specification may not match the ordinal numbers assigned to the same components in other parts of this specification or in the claims.

[0031] A transistor is a type of semiconductor element that can perform functions such as amplifying current or voltage and performing a switching operation to control conduction or non-conduction. The term "transistor" used in this specification includes an insulated gate field effect transistor (IGFET) and a thin film transistor (TFT).

[0032] In this specification and the like, a transistor using an oxide semiconductor or a metal oxide for a semiconductor layer and a transistor having an oxide semiconductor or a metal oxide for a channel formation region may be referred to as an OS transistor. A transistor having silicon for a channel formation region may be referred to as a Si transistor.

[0033] In this specification and the like, a transistor is an element having at least three terminals including a gate, a drain, and a source. A transistor has a region (also referred to as a channel formation region) where a channel is formed between the drain (drain terminal, drain region, or drain electrode) and the source (source terminal, source region, or source electrode), and current can flow between the source and the drain through the channel formation region. Note that in this specification and the like, the channel formation region refers to a region through which current mainly flows.

[0034] Furthermore, the functions of "source" and "drain" may be interchanged when transistors of different polarities are used, or when the direction of current flow changes during circuit operation, etc. Therefore, in this specification, the terms "source" and "drain" may be used interchangeably.

[0035] Note that impurities in a semiconductor refer to, for example, elements other than the main components constituting the semiconductor. For example, an element with a concentration of less than 0.1 atomic % can be considered an impurity. The presence of impurities may increase the density of defect states in the semiconductor or reduce the crystallinity, for example. When the semiconductor is an oxide semiconductor, impurities that change the characteristics of the semiconductor include, for example, Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, Group 15 elements, and transition metals other than the main components of the oxide semiconductor. Specific examples include hydrogen, lithium, sodium, silicon, boron, phosphorus, carbon, and nitrogen. Note that water may also function as an impurity. For example, the inclusion of impurities may cause oxygen deficiency (V) in the oxide semiconductor. Ｏ In some cases, a nucleus (also referred to as a nucleus) may be formed.

[0036] In this specification and the like, an oxynitride refers to a material having a composition in which oxygen is contained in a larger amount than nitrogen, and a nitride oxide refers to a material having a composition in which nitrogen is contained in a larger amount than oxygen.

[0037] To analyze the content of elements such as hydrogen, oxygen, carbon, or nitrogen contained in a film, for example, secondary ion mass spectrometry (SIMS) or X-ray photoelectron spectroscopy (XPS) can be used. XPS is suitable when the content of the target element is high (e.g., 0.5 atomic% or more, or 1 atomic% or more). On the other hand, SIMS is suitable when the content of the target element is low (e.g., 0.5 atomic% or less, or 1 atomic% or less). When comparing the content of elements, it is more preferable to perform a combined analysis using both SIMS and XPS analytical techniques.

[0038] It should be noted that the terms "film" and "layer" can be interchangeable depending on the circumstances. For example, the term "conductive layer" can be changed to the term "conductive film." Or, for example, the term "insulating film" can be changed to the term "insulating layer."

[0039] Furthermore, in this specification, "parallel" refers to a state in which two straight lines are arranged at an angle of -10 degrees or more and 10 degrees or less. Therefore, it also includes cases in which the angle is -5 degrees or more and 5 degrees or less. Furthermore, "substantially parallel" refers to a state in which two straight lines are arranged at an angle of -20 degrees or more and 20 degrees or less. Furthermore, "perpendicular" refers to a state in which two straight lines are arranged at an angle of 80 degrees or more and 100 degrees or less. Therefore, it also includes cases in which the angle is 85 degrees or more and 95 degrees or less. Furthermore, "substantially perpendicular" refers to a state in which two straight lines are arranged at an angle of 70 degrees or more and 110 degrees or less.

[0040] In this specification, "electrically connected" includes a connection via "something that has some kind of electrical function." Here, "something that has some kind of electrical function" is not particularly limited as long as it allows electrical signals to be transmitted and received between the connected objects. For example, "something that has some kind of electrical function" includes electrodes or wiring, as well as switching elements such as transistors, resistive elements, coils, and other elements with various functions.

[0041] In this specification and the like, unless otherwise specified, the off-state current refers to the leakage current between the source and drain when the transistor is in an off state (also referred to as a non-conducting state or a cut-off state). Unless otherwise specified, the off-state current refers to the leakage current between the source and the gate when the voltage V ｇｓ is the threshold voltage V ｔｈ (For p-channel transistors, V ｔｈ This refers to a state of being (higher than)

[0042] In this specification, the term "normally-on" refers to a state in which a channel exists and a current flows through a transistor even when no voltage is applied to the gate, whereas the term "normally-off" refers to a state in which no current flows through a transistor when no potential is applied to the gate or when a ground potential is applied to the gate.

[0043] In this specification and the like, a tapered shape refers to a shape in which at least a portion of the side surface of a structure is inclined with respect to the substrate surface or the surface to be formed. For example, it is preferable to have a region in which the angle (also called the taper angle) between the inclined side surface and the substrate surface or the surface to be formed is greater than 0 degrees and less than 90 degrees. Note that the side surface of the structure, the substrate surface, and the surface to be formed do not necessarily need to be completely flat, and may be approximately planar with a slight curvature or approximately planar with a slight unevenness.

[0044] In this specification, when it is stated that A is located on B, at least a portion of A is located on B. Therefore, for example, it can be rephrased as "A has a region located on B." Similarly, when it is stated that A contacts B or A overlaps B, at least a portion of A contacts B or overlaps B. Therefore, it can be rephrased as "A has a region contacting B" or "A has a region overlapping B," respectively. Similarly, in this specification, when it is stated that A covers B, at least a portion of A covers B. Therefore, for example, it can be rephrased as "A has a region covering B."

[0045] In this specification and the like, a step disconnection refers to a phenomenon in which a layer, a film, or an electrode is separated due to the shape of the surface on which it is formed (for example, a step or the like).

[0046] In addition, for example, in the drawings related to this specification, arrows indicating the X direction, Y direction, and Z direction may be added. In this specification, etc., the "X direction" refers to the direction along the X axis, and there may be no distinction between the forward direction and the reverse direction unless explicitly stated. The same applies to the "Y direction" and the "Z direction." Furthermore, the X direction, Y direction, and Z direction are directions that intersect with each other. For example, the X direction, Y direction, and Z direction are directions that are perpendicular to each other.

[0047] Embodiment 1 In this embodiment, a semiconductor device according to one embodiment of the present invention and a manufacturing method thereof will be described.

[0048] One embodiment of the present invention relates to a semiconductor device including a memory cell including a first transistor, a second transistor, and a third transistor, the first transistor, the second transistor, and the third transistor being stacked in this order from the bottom up, and the first transistor, the second transistor, and the third transistor having overlapping regions.

[0049] In this specification and the like, a semiconductor device provided with memory cells is also referred to as a memory device.

[0050] In the first to third transistors, the source electrode and the drain electrode are located at different heights, and current flowing through the semiconductor layer flows in the height direction (vertical direction). In other words, it can be said that the channel length direction has a height component. Therefore, the first to third transistors can be called VFETs (Vertical Field Effect Transistors), vertical transistors, vertical channel transistors, or vertical channel transistors. Here, in a vertical transistor, the electrode located on the lower side of the source electrode and the drain electrode is called the lower electrode, and the electrode located on the upper side is called the upper electrode. In a vertical transistor, the source electrode, the semiconductor layer, and the drain electrode can be provided overlapping each other.

[0051] The upper electrode of the first transistor and the lower electrode of the second transistor can be formed using the same conductive layer. The gate electrode of the second transistor and the lower electrode of the third transistor can be formed using the same conductive layer. As described above, the first to third transistors are vertical transistors and are stacked, and the other of the source and drain of the first transistor can be electrically connected to one of the source and drain of the second transistor. Furthermore, the gate of the second transistor can be electrically connected to one of the source and drain of the third transistor.

[0052] As a result, the area occupied by the memory cell can be reduced compared to when, for example, two or three of the first, second, and third transistors are formed on the same formation surface and the first to third transistors are so-called planar transistors. As a result, a semiconductor device that can be miniaturized or highly integrated can be realized.

[0053] Here, the gate electrode of the first transistor is provided between the lower electrode of the first transistor and the upper electrode of the first transistor. The gate electrode of the first transistor is provided to surround the semiconductor layer of the first transistor. The semiconductor layer of the first transistor has a recess overlapping with the lower electrode of the first transistor. An insulating layer is filled in the recess. A conductive layer serving as both the upper electrode of the first transistor and the lower electrode of the second transistor is provided on the insulating layer. This allows the first transistor and the second transistor to be vertical transistors and be stacked, while electrically connecting the other of the source and drain of the first transistor to one of the source and drain of the second transistor.

[0054] By providing an insulating layer in the recess of the semiconductor layer of the first transistor, the conductive layer can be prevented from contacting the channel formation region of the first transistor. Furthermore, by providing an insulating layer so as to fill the recess of the semiconductor layer of the first transistor, the conductive layer can be prevented from entering the recess, and therefore the electric field of the conductive layer can be prevented from being applied to the channel formation region of the first transistor. As a result, a highly reliable semiconductor device can be realized.

[0055] <Structural Example 1 of Semiconductor Device> A structural example of a semiconductor device of one embodiment of the present invention will be described below. Specifically, a structural example of a memory cell included in the semiconductor device of one embodiment of the present invention and a structural example of a transistor included in the memory cell will be described.

[0056] 1A is a circuit diagram showing an example of the configuration of a memory cell 10. The memory cell 10 includes a transistor 100, a transistor 200, and a transistor 300.

[0057] One of the source and drain of the transistor 100 is electrically connected to a wiring RBL. The other of the source and drain of the transistor 100 is electrically connected to one of the source and drain of the transistor 200. The gate of the transistor 100 is electrically connected to a wiring RWL. The other of the source and drain of the transistor 200 is electrically connected to a wiring PL. The gate of the transistor 200 is electrically connected to one of the source and drain of the transistor 300. The other of the source and drain of the transistor 300 is electrically connected to a wiring WBL.

[0058] The transistor 300 can be a dual-gate transistor having two gates (a first gate and a second gate). In this case, the first gate of the transistor 300 can be referred to as a front gate or simply as a gate, and the second gate can be referred to as a back gate. Note that the first gate can be referred to as a back gate, and the second gate can be referred to as a front gate or simply as a gate. In the example shown in FIG. 1A , the gate of the transistor 300 is electrically connected to a wiring WWL, and the back gate is electrically connected to a wiring BGL.

[0059] The wirings WWL and RWL function as word lines. A signal for controlling the on / off state of the transistor 300 is supplied to the wiring WWL. A signal for controlling the on / off state of the transistor 100 is supplied to the wiring RWL.

[0060] The wiring WBL functions as a bit line. A data signal to be supplied to the memory cell 10 is supplied to the wiring WBL. When the transistor 300 is in an on state, data corresponding to the potential of the wiring WBL is written to the memory cell 10. When the transistor 300 is in an off state, the data written to the memory cell 10 is retained. Specifically, the gate potential of the transistor 200 is retained. As described above, the wiring WWL to which a signal for controlling the on / off of the transistor 300 is supplied can be referred to as a write word line, and the wiring WBL can be referred to as a write bit line.

[0061] The wiring RBL functions as a bit line. The wiring PL functions as a power supply line and is supplied with a power supply potential. As described above, when data is written to the memory cell 10, the gate potential of the transistor 200 becomes a potential corresponding to the data. In this state, when the transistor 100 is turned on, a current having a magnitude corresponding to the gate potential of the transistor 200 flows between the wiring RBL and the wiring PL. As a result, the potential of the wiring RBL becomes a potential corresponding to the data stored in the memory cell 10. Therefore, the data stored in the memory cell 10 can be read. This reading can be non-destructive. As described above, the wiring RWL, to which a signal for controlling the on / off of the transistor 100 is supplied, can be referred to as a read word line, and the wiring RBL can be referred to as a read bit line.

[0062] The threshold voltage of the transistor 300 can be controlled by controlling the potential of the wiring BGL electrically connected to the back gate of the transistor 300. For example, by supplying a potential lower than or equal to the source potential or a potential lower than or equal to 0 V (preferably a negative potential) to the wiring BGL, the threshold voltage of the transistor 300 can be shifted in the positive direction, resulting in a normally-off characteristic. This allows the gate potential of the transistor 200 to be held for a long period of time. Therefore, data written to the memory cell 10 can be held for a long period of time.

[0063] FIG. 1B is a plan view showing a configuration example of a transistor 100. FIG. 1C is a plan view showing a configuration example of a transistor 200. FIG. 1D is a plan view showing a configuration example of a transistor 300. Note that in the plan views of FIGS. 1B to 1D, some elements are omitted for clarity. Some elements will also be omitted in the subsequent plan views.

[0064] Fig. 2A is a cross-sectional view taken along dashed dotted lines A1-A2 shown in Fig. 1B to Fig. 1D. Fig. 2B is a cross-sectional view taken along dashed dotted lines B1-B2 shown in Fig. 1B to Fig. 1D. Fig. 2A and Fig. 2B show an example of the configuration of a memory cell 10.

[0065] The memory cell 10 includes an insulating layer 110 on a substrate (not shown), a transistor 100, an insulating layer 180a, and an insulating layer 181 on the insulating layer 110, an insulating layer 180b on the insulating layer 180a, an insulating layer 181A on the insulating layer 180b, an insulating layer 183 on the insulating layer 181, an insulating layer 183A on the insulating layer 181A, a transistor 200 on the transistor 100, an insulating layer 280 on the transistor 100 and on the insulating layer 183A, a transistor 300 on the transistor 200, an insulating layer 380a on the transistor 200 and on the insulating layer 280, and an insulating layer 380b on the insulating layer 380a. That is, the transistor 100, the transistor 200, and the transistor 300 are stacked in this order from the bottom up. The transistors 100, 200, and 300 are provided so as to have overlapping regions with each other.

[0066] Note that the memory cell 10 may have a capacitor. For example, the conductive layer 320 or another conductive layer electrically connected to the conductive layer 320 can be used as one electrode of the capacitor. Alternatively, for example, a conductive layer provided on the same formation surface as the conductive layer 320 or a conductive layer provided on the same formation surface as the conductive layer 355 can be used as the other electrode of the capacitor. In this case, one electrode of the capacitor is electrically connected to the gate of the transistor 200 and one of the source and drain of the transistor 300. For example, a power supply potential can be supplied to the other electrode of the capacitor.

[0067] The insulating layer 180a, the insulating layer 180b, the insulating layer 280, the insulating layer 380a, and the insulating layer 380b function as interlayer films. Here, the insulating layer 180a and the insulating layer 180b are collectively referred to as the insulating layer 180, and the insulating layer 380a and the insulating layer 380b are collectively referred to as the insulating layer 380.

[0068] The transistor 100 includes a conductive layer 120a, a conductive layer 120b over the conductive layer 120a, a conductive layer 155 over the insulating layer 180a, a conductive layer 140a over the insulating layer 180b, a conductive layer 140b over the conductive layer 140a, an insulating layer 135, a semiconductor layer 130, a conductive layer 220a over the semiconductor layer 130, and a conductive layer 220b over the conductive layer 220a. Here, the conductive layers 120a and 120b are collectively referred to as the conductive layer 120, the conductive layers 140a and 140b are collectively referred to as the conductive layer 140, and the conductive layers 220a and 220b are collectively referred to as the conductive layer 220.

[0069] The transistor 200 includes a conductive layer 220a, a conductive layer 220b over the conductive layer 220a, a conductive layer 240a over the insulating layer 280, a conductive layer 240b over the conductive layer 240a, a semiconductor layer 230, an insulating layer 250 over the semiconductor layer 230, a conductive layer 320a over the insulating layer 250, and a conductive layer 320b over the conductive layer 320a. Here, the conductive layers 240a and 240b are collectively referred to as the conductive layer 240, and the conductive layers 320a and 320b are collectively referred to as the conductive layer 320.

[0070] The transistor 300 includes a conductive layer 320a, a conductive layer 320b over the conductive layer 320a, a conductive layer 355 over the insulating layer 380a, a conductive layer 340a over the insulating layer 380b, a conductive layer 340b over the conductive layer 340a, an insulating layer 335, a semiconductor layer 330, an insulating layer 350 over the semiconductor layer 330, a conductive layer 365a over the insulating layer 350, and a conductive layer 365b over the conductive layer 365a. Here, the conductive layers 340a and 340b are collectively referred to as the conductive layer 340, and the conductive layers 365a and 365b are collectively referred to as the conductive layer 365.

[0071] 2A and 2B, the conductive layer 155 and the conductive layer 355 have a single-layer structure, but the conductive layer 155 and the conductive layer 355 may have a stacked structure of two or more layers.

[0072] In the transistor 100, the conductive layer 120 functions as one of a source electrode and a drain electrode, the conductive layer 140 and the conductive layer 220 function as the other of the source electrode and the drain electrode, the conductive layer 155 functions as a gate electrode, and the insulating layer 135 functions as a gate insulating layer. Note that the conductive layer 220 does not necessarily have to be included as a component of the transistor 100.

[0073] In the transistor 200, the conductive layer 220 functions as one of a source electrode and a drain electrode, the conductive layer 240 functions as the other of the source electrode and the drain electrode, the conductive layer 320 functions as a gate electrode, and the insulating layer 250 functions as a gate insulating layer. In the transistor 300, the conductive layer 320 functions as one of the source electrode and the drain electrode, the conductive layer 340 functions as the other of the source electrode and the drain electrode, the conductive layer 365 functions as a first gate electrode, the conductive layer 355 functions as a second gate electrode, the insulating layer 350 functions as a first gate insulating layer, and the insulating layer 335 functions as a second gate insulating layer. That is, the transistor 300 can be a dual-gate transistor. Here, the conductive layer 365 also functions as a gate wiring.

[0074] For example, the conductive layer 365 can function as a gate electrode, and the conductive layer 355 can function as a back gate electrode. In this case, the insulating layer 350 functions as a gate insulating layer, and the insulating layer 335 functions as a back gate insulating layer. Note that the conductive layer 365 may function as a back gate electrode, and the conductive layer 355 may function as a gate electrode. In this case, the insulating layer 350 can function as a back gate insulating layer, and the insulating layer 335 can function as a gate insulating layer.

[0075] As described above, the other of the source electrode and drain electrode of the transistor 100 and one of the source electrode and drain electrode of the transistor 200 can be formed using the same conductive layer 220. This allows the other of the source and drain of the transistor 100 to be electrically connected to one of the source and drain of the transistor 200. Furthermore, the same conductive layer 320 can be used for the gate electrode of the transistor 200 and one of the source and drain electrodes of the transistor 300. This allows the gate of the transistor 200 to be electrically connected to one of the source and drain of the transistor 300.

[0076] At least a portion of the conductive layer 120 functions as the wiring RBL shown in FIG. 1A. At least a portion of the conductive layer 155 functions as the wiring RWL shown in FIG. 1A. At least a portion of the conductive layer 240 functions as the wiring PL shown in FIG. 1A. At least a portion of the conductive layer 355 functions as the wiring BGL shown in FIG. 1A. At least a portion of the conductive layer 340 functions as the wiring WBL shown in FIG. 1A. At least a portion of the conductive layer 365 functions as the wiring WWL shown in FIG. 1A.

[0077] The insulating layer 180a is located on the conductive layer 120 and the insulating layer 110. The insulating layer 180a is provided to cover the upper surface of the conductive layer 120b, the side surfaces of the conductive layer 120b, the side surfaces of the conductive layer 120a, and the upper surface of the insulating layer 110.

[0078] The conductive layer 155 is located on the insulating layer 180a. The insulating layer 180b is located on the conductive layer 155 and on the insulating layer 180a. The insulating layer 180b is provided to cover the top surface of the conductive layer 155, the side surfaces of the conductive layer 155, and the top surface of the insulating layer 180a.

[0079] The conductive layer 140 is located over the insulating layer 180b. As described above, the insulating layer 180b is located over the insulating layer 180a, and the insulating layer 180a is located over the conductive layer 120. As described above, the insulating layer 180a and the insulating layer 180b functioning as interlayer films are provided between the conductive layer 120 and the conductive layer 140.

[0080] The conductive layer 140 and the conductive layer 220, which function as the other of the source and drain electrodes of the transistor 100, are located above the conductive layer 120, which functions as one of the source and drain electrodes of the transistor 100. Thus, the conductive layer 120 can be referred to as a lower electrode of the transistor 100, and the conductive layer 140 and the conductive layer 220 can be referred to as an upper electrode of the transistor 100.

[0081] The insulating layer 180a, the conductive layer 155, the insulating layer 180b, and the conductive layer 140 have an opening 190 that reaches the conductive layer 120. As described above, the conductive layer 120 has a conductive layer 120a and a conductive layer 120b on the conductive layer 120a. 2A and 2B show an example in which the conductive layer 120b has a recess that overlaps with the opening 190. In other words, the conductive layer 120 has a recess, the bottom surface of which corresponds to the bottom surface of the recess in the conductive layer 120b, and the side surface of which corresponds to the side surface of the recess in the conductive layer 120b. Here, the bottom of the opening 190 includes the bottom surface of the recess in the conductive layer 120b. The sidewalls of the opening 190 include the side surfaces of the recess of the conductive layer 120b, the side surfaces of the insulating layer 180a, the side surfaces of the conductive layer 155, the side surfaces of the insulating layer 180b, the side surfaces of the conductive layer 140a, and the side surfaces of the conductive layer 140b.

[0082] 2A and 2B show an example in which the conductive layer 120b has a first recess and a second recess that is located outside the first recess and has a shallower depth. When forming the opening 190, the second recess is provided in the conductive layer 120b, and then, when processing the insulating layer 135, the first recess is provided in the conductive layer 120b. Therefore, in FIGS. 2A and 2B, the side surface of the first recess in the conductive layer 120b is aligned with the surface of the insulating layer 135 facing the semiconductor layer 130. Furthermore, the side surface of the second recess in the conductive layer 120b is aligned with, for example, the side surface of the insulating layer 180a facing the opening 190. Hereinafter, the first recess and the second recess may be collectively referred to as recesses.

[0083] The opening 190 includes an opening in the insulating layer 180a, an opening in the conductive layer 155, an opening in the insulating layer 180b, an opening in the conductive layer 140a, and an opening in the conductive layer 140b. In other words, the opening in the region where the insulating layer 180a overlaps with the conductive layer 120a is part of the opening 190, the opening in the region where the conductive layer 155 overlaps with the conductive layer 120a is another part of the opening 190, the opening in the region where the insulating layer 180b overlaps with the conductive layer 120a is another part of the opening 190, the opening in the region where the conductive layer 140a overlaps with the conductive layer 120a is another part of the opening 190, and the opening in the region where the conductive layer 140b overlaps with the conductive layer 120a is another part of the opening 190. The shape and size of the opening 190 in a plan view may differ depending on the layer. When the shape of the opening 190 in a plan view is circular, the openings in each layer may or may not be concentric. For example, the center of at least one of the openings in each layer may not overlap with the center of the openings in the other layers.

[0084] At least some of the components of the transistor 100 are disposed inside the opening 190. Specifically, the insulating layer 135 and the semiconductor layer 130 are disposed such that at least some of them are located inside the opening 190.

[0085] The insulating layer 135 has at least a region located between the semiconductor layer 130 and the conductive layer 155. The insulating layer 135 contacts the side surface of the conductive layer 155 inside the opening 190. As will be described in detail later, the insulating layer 135 is formed after the opening 190 is formed so as to cover the opening 190 and have a region located on the conductive layer 140. The insulating layer 135 is then processed by, for example, anisotropic etching until the top surface of the conductive layer 140 is exposed. This removes the region of the insulating layer 135 located on the top surface of the conductive layer 140 and the region located on the bottom surface of the opening 190, leaving the insulating layer 135 only on the side surface inside the opening 190.

[0086] Here, by forming the insulating layer 135 after forming the conductive layer 140, it is possible to suppress the continuation of anisotropic etching of the insulating layer 135 even after the region of the insulating layer 135 located outside the opening 190 is removed, compared to when the insulating layer 135 is formed without forming the conductive layer 140. Therefore, for example, the side surface of the conductive layer 155 on the opening 190 side can be prevented from being exposed. Therefore, for example, contact between the conductive layer 155 and the semiconductor layer 130 can be prevented. As a result, a highly reliable semiconductor device can be realized. Note that the transistor 100 does not necessarily have to include the conductive layer 140. In this case, the number of manufacturing steps for the transistor 100 can be reduced.

[0087] 2A and 2B , the insulating layer 135 contacts the bottom and side surfaces of the recess (specifically, the second recess) in the conductive layer 120b, and also contacts the side surfaces of the insulating layer 180a, the conductive layer 155, the insulating layer 180b, the conductive layer 140a, and the conductive layer 140b inside the opening 190. The semiconductor layer 130 contacts the bottom and side surfaces of the recess (specifically, the first recess) in the conductive layer 120b, the insulating layer 135, and the top surface of the conductive layer 140b. The conductive layer 120b has a recess, which increases the area in which the semiconductor layer 130 contacts the conductive layer 120b. Therefore, the contact resistance between the semiconductor layer 130 and the conductive layer 120b can be reduced.

[0088] The insulating layer 135 is provided along at least a part of the sidewall of the opening 190. The semiconductor layer 130 has a region inside the opening 190 that faces the conductive layer 155 with the insulating layer 135 sandwiched therebetween. At least a part of this region of the semiconductor layer 130 is in contact with the insulating layer 135. The conductive layer 155 is provided to surround the semiconductor layer 130 with the insulating layer 135 sandwiched therebetween.

[0089] As described above, the conductive layer 155 functions as the gate electrode of the transistor 100, and the insulating layer 135 functions as the gate insulating layer of the transistor 100. As described above, the region of the semiconductor layer 130 facing the conductive layer 155 with the insulating layer 135 sandwiched therebetween functions as a channel formation region of the transistor 100. A region of the semiconductor layer 130 in contact with the conductive layer 120 functions as one of the source region and the drain region of the transistor 100. A region of the semiconductor layer 130 in contact with at least one of the conductive layer 140 and the conductive layer 220 functions as the other of the source region and the drain region of the transistor 100. In other words, the channel formation region of the transistor 100 is sandwiched between the source region and the drain region.

[0090] The portion of the semiconductor layer 130 that is disposed inside the opening 190 is provided to reflect the shape of the opening 190. Specifically, the semiconductor layer 130 is provided along the bottom and sidewalls of the opening 190. As a result, a recess is provided in the semiconductor layer 130 at a position that overlaps with the opening 190.

[0091] The insulating layer 181 is located inside the opening 190 and more inward than the semiconductor layer 130. The insulating layer 183 is located inside the opening 190 and more inward than the insulating layer 181. The insulating layer 183 is located on the insulating layer 181. The insulating layer 181 is provided along the semiconductor layer 130. As described above, a recess is provided in the semiconductor layer 130 at a position overlapping the opening 190. As described above, a recess is also provided in the insulating layer 181 at a position overlapping the opening 190. The insulating layer 183 is provided inside the insulating layer 181 so as to fill the opening 190. Specifically, the insulating layer 183 is provided so as to fill the recess in the insulating layer 181. The insulating layer 183 is a planarized layer.

[0092] The conductive layer 220 is located on the insulating layer 183. The conductive layer 220 is in contact with a region of the semiconductor layer 130 that overlaps with the conductive layer 140.

[0093] The insulating layer 181 can prevent the conductive layer 220 from contacting the channel formation region of the semiconductor layer 130. Furthermore, the insulating layer 183 can prevent the conductive layer 220 from entering the opening 190. This can prevent the electric field of the conductive layer 220 from being applied to the channel formation region of the transistor 100. Therefore, the threshold voltage of the transistor 100 can be prevented from varying depending on the potential of the conductive layer 220. Furthermore, the transistor 100 can be prevented from being turned on during periods other than the period in which data stored in the memory cell 10 is read. Furthermore, the transistor 100 can be prevented from being turned off during the period in which data stored in the memory cell 10 is read. As described above, a semiconductor device including the memory cell 10 can be a highly reliable semiconductor device.

[0094] The upper surface of the insulating layer 183 is located higher than the upper surface of the semiconductor layer 130 in the region overlapping with the conductive layer 140. The upper surface of the insulating layer 183 can be located at a position higher than the upper surface of the semiconductor layer 130 in the region overlapping with the conductive layer 140, for example, by the thickness of the insulating layer 181. In other words, the difference between the height of the upper surface of the insulating layer 183 from the reference plane and the height of the upper surface of the semiconductor layer 130 in the region overlapping with the conductive layer 140 can be set to, for example, the thickness of the insulating layer 181 or a value close to that. Similarly, the upper surface of the insulating layer 183A is located higher than the upper surface of the semiconductor layer 130 in the region overlapping with the conductive layer 140.

[0095] The reference plane may be, for example, the surface of the substrate or the upper surface of an interlayer film such as the insulating layer 110. The same applies to the following description.

[0096] As will be described later in detail, when manufacturing the memory cell 10, after forming the semiconductor layer 130, a first insulating film to be the insulating layer 181 and a second insulating film to be the insulating layer 183 are formed on the first insulating film. Subsequently, the second insulating film is subjected to planarization treatment until at least a portion of the top surface of the first insulating film is exposed, thereby forming the insulating layer 183. As the planarization treatment, planarization treatment (also referred to as CMP treatment) using a chemical mechanical polishing (CMP) method is preferable. Then, the first insulating film is processed. For example, a region of the first insulating film that does not overlap with either the insulating layer 183 or the conductive layer 140 is removed. As a result, the insulating layer 181 is formed to overlap with the insulating layer 183, and the region of the semiconductor layer 130 that overlaps with the conductive layer 140 is exposed.

[0097] Here, if the above-described first insulating film is not formed, and the above-described second insulating film is formed, and then a planarization process is performed on the second insulating film until at least a portion of the top surface of the semiconductor layer 130 is exposed, for example, the planarization process may be performed on not only the second insulating film but also the semiconductor layer 130. As a result, the region of the semiconductor layer 130 that contacts the conductive layer 140 may be removed. Furthermore, it becomes difficult to control the film thickness of the region of the semiconductor layer 130 that overlaps with the conductive layer 140. As a result, the reliability of the semiconductor device may be reduced.

[0098] Therefore, by forming the second insulating film after the first insulating film and then performing a planarization process on the second insulating film until at least a portion of the upper surface of the first insulating film is exposed, it is possible to prevent the planarization process from being performed on the semiconductor layer 130. Therefore, a highly reliable semiconductor device can be realized. When the planarization process is performed on the second insulating film until at least a portion of the upper surface of the first insulating film is exposed, the upper surface of the insulating layer 183 is located at a position higher than the upper surface of the semiconductor layer 130 in the region overlapping with the conductive layer 140, for example, by the thickness of the insulating layer 181. Note that the upper surface of the insulating layer 183A is located at a position higher than the upper surface of the semiconductor layer 130 in the region overlapping with the conductive layer 140, for example, by the thickness of the insulating layer 181A.

[0099] Note that, for example, the shortest distance from the top surface of the insulating layer 110 to the top surface of the conductive layer 120b that is in contact with the insulating layer 180a is preferably longer than the shortest distance from the top surface of the insulating layer 110 to the bottom surface of the insulating layer 181 inside the opening 190. This can increase the contact area between the side surface of the conductive layer 120b and the semiconductor layer 130, thereby reducing the contact resistance between the conductive layer 120b and the semiconductor layer 130. Therefore, the on-current of the transistor 100 can be increased.

[0100] FIG. 3A is a plan view showing an example of the configuration of the semiconductor layer 130, the conductive layer 140, the insulating layer 181, the insulating layer 183, the insulating layer 181A, and the insulating layer 183A. FIG. 3B is a plan view in which the semiconductor layer 130 is omitted from FIG. 3A . As shown in FIGS. 3A and 3B , the insulating layer 181A and the insulating layer 183A located on the insulating layer 181A are provided so as to surround the semiconductor layer 130 and the conductive layer 140. Specifically, the insulating layer 181A and the insulating layer 183A are provided so as to surround, in a plan view, the side surface of the semiconductor layer 130 located outside the opening 190 and the side surface of the conductive layer 140 opposite to the side surface on the opening 190 side. The insulating layer 181A is provided, for example, to contact the side surface of the semiconductor layer 130 located outside the opening 190 and the side surface of the conductive layer 140 opposite to the side surface on the opening 190 side.

[0101] 3A, the insulating layer 181A and the insulating layer 183A can be considered to have an opening 191 that overlaps with the semiconductor layer 130. As shown in FIG. 3B, the insulating layer 181A and the insulating layer 183A can be considered to have an opening 191 that overlaps with the conductive layer 140 and the opening 190. The opening 191 can be considered to include an island-shaped insulating layer 181 and an insulating layer 183 on the insulating layer 181.

[0102] In this specification and the like, an island-shaped layer refers to a layer that is provided so as to be surrounded by an opening in a plan view. For example, insulating layer 181 and insulating layer 183 can be called island-shaped layers because they are provided so as to be surrounded by opening 191 in a plan view.

[0103] Opening 191 includes an opening in insulating layer 181A and an opening in insulating layer 183A. In other words, the opening in the region where insulating layer 181A overlaps with semiconductor layer 130 is a part of opening 191, and the opening in the region where insulating layer 183A overlaps with semiconductor layer 130 is another part of opening 191. Note that the shape and size of opening 191 in a plan view may differ depending on the layer.

[0104] By configuring the memory cell 10 to include the insulating layer 181A and the insulating layer 183A, the insulating layer 181 and the insulating layer 183 can be formed without using photolithography, as will be described in detail later. Therefore, by configuring the memory cell 10 to include the insulating layer 181A and the insulating layer 183A, the number of manufacturing steps for the semiconductor device can be reduced compared to when the memory cell 10 does not include the insulating layer 181A and the insulating layer 183A. Therefore, the manufacturing cost of the semiconductor device can be reduced, and a low-cost semiconductor device can be provided.

[0105] Although the details will be described later, the insulating layer 181 and the insulating layer 181A can be layers formed in the same process using the same material. Also, the insulating layer 183 and the insulating layer 183A can be layers formed in the same process using the same material.

[0106] As described above, the conductive layer 220 is located on the insulating layer 183. The conductive layer 220 is provided so as to cover the top surface of the insulating layer 183 and the side surface of the insulating layer 183 located outside the opening 190. The conductive layer 220 is in contact with a region of the semiconductor layer 130 that overlaps with the conductive layer 140.

[0107] The insulating layer 280 is located on the conductive layer 220 and the insulating layer 180b. Specifically, the insulating layer 280 is located on the conductive layer 220, the conductive layer 140, the semiconductor layer 130, the insulating layer 181A, and the insulating layer 183A. The insulating layer 280 is provided so as to cover the top surface of the conductive layer 220b, the side surfaces of the conductive layer 220b, the side surfaces of the conductive layer 220a, the top surface of the semiconductor layer 130, the side surfaces of the insulating layer 181A, and the top surface of the insulating layer 183A.

[0108] The conductive layer 240 is located over the insulating layer 280. As described above, the insulating layer 280 is located over the conductive layer 220. As described above, the insulating layer 280, which functions as an interlayer film, is provided between the conductive layer 220 and the conductive layer 240.

[0109] The conductive layer 240, which functions as the other of the source electrode and the drain electrode of the transistor 200, is located above the conductive layer 220, which functions as one of the source electrode and the drain electrode of the transistor 200. Thus, the conductive layer 220 can be referred to as a lower electrode of the transistor 200, and the conductive layer 240 can be referred to as an upper electrode of the transistor 200.

[0110] The insulating layer 280 and the conductive layer 240 have an opening 290 that reaches the conductive layer 220. As described above, the conductive layer 220 includes a conductive layer 220a and a conductive layer 220b on the conductive layer 220a. FIGS. 2A and 2B illustrate an example in which the conductive layer 220b has a recess that overlaps the opening 290. In other words, the conductive layer 220 has a recess, the bottom of which corresponds to the bottom of the recess in the conductive layer 220b, and the side of which corresponds to the side of the recess in the conductive layer 220b. Here, the bottom of the opening 290 includes the bottom of the recess in the conductive layer 220b. Furthermore, the sidewall of the opening 290 includes the side of the recess in the conductive layer 220b, the side of the insulating layer 280, the side of the conductive layer 240a, and the side of the conductive layer 240b. Note that FIGS. 2A and 2B illustrate an example in which the opening 290 overlaps the opening 190.

[0111] The opening 290 includes an opening in the insulating layer 280 and an opening in the conductive layer 240. In other words, the opening in the region where the insulating layer 280 overlaps with the conductive layer 220a is one part of the opening 290, the opening in the region where the conductive layer 240a overlaps with the conductive layer 220a is another part of the opening 290, and the opening in the region where the conductive layer 240b overlaps with the conductive layer 220a is another part of the opening 290. The shape and size of the openings 290 in a planar view may differ depending on the layer. Furthermore, when the shape of the opening 290 in a planar view is circular, the openings in each layer may or may not be concentric. For example, at least one of the centers of the openings in each layer may not overlap with the centers of the openings in the other layers.

[0112] At least some of the components of the transistor 200 are disposed inside the opening 290. Specifically, the semiconductor layer 230 and the insulating layer 250 are disposed such that at least some of them are located inside the opening 290.

[0113] The semiconductor layer 230 contacts the bottom and side surfaces of the recessed portion of the conductive layer 220, the insulating layer 280, the side surfaces of the conductive layer 240a and the conductive layer 240b on the opening 290 side, and the top surface of the conductive layer 240b. The conductive layer 220b has a recessed portion, which can increase the area where the semiconductor layer 230 contacts the conductive layer 220b. Therefore, the contact resistance between the semiconductor layer 230 and the conductive layer 220b can be reduced.

[0114] Here, for example, the shortest distance from the top surface of the insulating layer 110 to the top surface of the conductive layer 220b that contacts the insulating layer 280 is preferably longer than the shortest distance from the top surface of the insulating layer 110 to the bottom surface of the insulating layer 250 inside the opening 290. This increases the contact area between the side surface of the conductive layer 220b and the semiconductor layer 230, thereby reducing the contact resistance between the conductive layer 220b and the semiconductor layer 230. Therefore, the on-current of the transistor 200 can be increased.

[0115] For example, the shortest distance from the top surface of the insulating layer 110 to the top surface of the conductive layer 220b that is in contact with the insulating layer 280 is preferably equal to or greater than the shortest distance from the top surface of the insulating layer 110 to the bottom surface of the conductive layer 320a inside the opening 290, and is even more preferably longer than this shortest distance. This makes it easier to apply a gate electric field to the channel formation region of the semiconductor layer 230, thereby improving the electrical characteristics of the transistor 200. Furthermore, since a gate electric field is also easier to apply to the region of the semiconductor layer 230 that is in contact with the conductive layer 220b, the on-state current of the transistor 200 can be increased. Furthermore, whether the conductive layer 220 or the conductive layer 240 is used as the drain electrode, the electrical characteristics of the transistor 200 can be improved.

[0116] The portion of the semiconductor layer 230 that is disposed inside the opening 290 is provided to reflect the shape of the opening 290. Specifically, the semiconductor layer 230 is provided along the bottom and sidewalls of the opening 290. As a result, a recess is provided in the semiconductor layer 230 at a position that overlaps with the opening 290.

[0117] The insulating layer 250 is located on the semiconductor layer 230 and on the insulating layer 280. The insulating layer 250 is located inside the opening 290 and more inward than the semiconductor layer 230. The insulating layer 250 is provided so as to cover the top and side surfaces of the semiconductor layer 230, the side surfaces of the conductive layer 240b, the side surfaces of the conductive layer 240a, and the top surface of the insulating layer 280. The insulating layer 250 may have a region in contact with the semiconductor layer 230. The insulating layer 250 may have a region in contact with the semiconductor layer 230, for example, inside the opening 290.

[0118] The insulating layer 250 is provided along the semiconductor layer 230. As described above, a recess is provided in the semiconductor layer 230 at a position overlapping the opening 290. As described above, a recess is also provided in the insulating layer 250 at a position overlapping the opening 290.

[0119] The conductive layer 320 is located on the insulating layer 250. The conductive layer 320 is located inside the opening 290 and on the inner side of the insulating layer 250. The conductive layer 320 is provided so as to fill the opening 290 on the inner side of the insulating layer 250. Specifically, the conductive layer 320 is provided so as to fill the recessed portion of the insulating layer 250. FIGS. 2A and 2B show an example in which the conductive layer 320a is planarized.

[0120] The conductive layer 320 has a region inside the opening 290 that faces the semiconductor layer 230 with the insulating layer 250 sandwiched therebetween. This region functions as a channel formation region of the transistor 200. A region of the semiconductor layer 230 in contact with the conductive layer 220 functions as one of the source region and the drain region of the transistor 200. A region of the semiconductor layer 230 in contact with the conductive layer 240 functions as the other of the source region and the drain region of the transistor 200. That is, the channel formation region of the transistor 200 is sandwiched between the source region and the drain region, similar to the channel formation region of the transistor 100.

[0121] At least one layer constituting the conductive layer 320 is provided in the opening 290. When the conductive layer 320 has a stacked structure, as the transistor 200 is miniaturized and the diameter of the opening 290 becomes smaller, it becomes more difficult to arrange all of the layers constituting the conductive layer 320 in the opening 290. In FIGS. 2A and 2B , an example is shown in which the conductive layer 320 has a two-layer structure, in which only the conductive layer 320a is provided in the opening 290, and the conductive layer 320b on the conductive layer 320a is provided in a position overlapping with the opening 290. Note that depending on the diameter of the opening 290, the thickness of the conductive layer 320a, and the like, both the conductive layer 320a and the conductive layer 320b may be located in the opening 290.

[0122] The insulating layer 380a is located on the conductive layer 320 and the insulating layer 250. The insulating layer 380a is provided to cover the upper surface of the conductive layer 320b, the side surfaces of the conductive layer 320b, the side surfaces of the conductive layer 320a, and the upper surface of the insulating layer 250.

[0123] The conductive layer 355 is located over the insulating layer 380a. The insulating layer 380b is located over the conductive layer 355 and the insulating layer 380a. The insulating layer 380b is provided to cover a top surface of the conductive layer 355, side surfaces of the conductive layer 355, and a top surface of the insulating layer 380a.

[0124] The conductive layer 340 is located over the insulating layer 380b. As described above, the insulating layer 380b is located over the insulating layer 380a, and the insulating layer 380a is located over the conductive layer 320. As described above, the insulating layer 380a and the insulating layer 380b functioning as interlayer films are provided between the conductive layer 320 and the conductive layer 340.

[0125] The conductive layer 340, which functions as the other of the source and drain electrodes of the transistor 300, is located above the conductive layer 320, which functions as one of the source and drain electrodes of the transistor 300. Thus, the conductive layer 320 can be referred to as a lower electrode of the transistor 300, and the conductive layer 340 can be referred to as an upper electrode of the transistor 300.

[0126] The insulating layer 380a, the conductive layer 355, the insulating layer 380b, and the conductive layer 340 have an opening 390 that reaches the conductive layer 320. As described above, the conductive layer 320 has a conductive layer 320a and a conductive layer 320b on the conductive layer 320a. 2A and 2B show an example in which the conductive layer 320b has a recess that overlaps the opening 390. In other words, the conductive layer 320 has a recess, the bottom surface of which corresponds to the bottom surface of the recess in the conductive layer 320b, and the side surface of which corresponds to the side surface of the recess in the conductive layer 320b. Here, the bottom of the opening 390 includes the bottom surface of the recess in the conductive layer 320b. 2A and 2B show an example in which the opening 390 overlaps with the opening 190 and the opening 290.

[0127] 2A and 2B show an example in which the conductive layer 320b has a first recess and a second recess that is located outside the first recess and has a shallower depth. When forming the opening 390, the second recess is provided in the conductive layer 320b, and then when processing the insulating layer 335, the first recess is provided in the conductive layer 320b. Therefore, in FIGS. 2A and 2B, the side surface of the first recess in the conductive layer 320b is aligned with the surface of the insulating layer 335 facing the semiconductor layer 330. Furthermore, the side surface of the second recess in the conductive layer 320b is aligned with, for example, the side surface of the insulating layer 380a facing the opening 390.

[0128] The opening 390 includes an opening in the insulating layer 380a, an opening in the conductive layer 355, an opening in the insulating layer 380b, an opening in the conductive layer 340a, and an opening in the conductive layer 340b. In other words, the opening in the region where the insulating layer 380a overlaps with the conductive layer 320a is part of the opening 390, the opening in the region where the conductive layer 355 overlaps with the conductive layer 320a is another part of the opening 390, the opening in the region where the insulating layer 380b overlaps with the conductive layer 320a is another part of the opening 390, the opening in the region where the conductive layer 340a overlaps with the conductive layer 320a is another part of the opening 390, and the opening in the region where the conductive layer 340b overlaps with the conductive layer 320a is another part of the opening 390. The shape and size of the opening 390 in a plan view may differ depending on the layer. Furthermore, when the shape of the opening 390 in a plan view is circular, the openings in each layer may or may not be concentric. For example, the center of at least one of the openings in each layer may not overlap with the center of the openings in the other layers.

[0129] At least some of the components of the transistor 300 are disposed inside the opening 390. Specifically, the insulating layer 335, the semiconductor layer 330, the insulating layer 350, and the conductive layer 365 are disposed such that at least some of them are located inside the opening 390.

[0130] The insulating layer 335 has a region located between the semiconductor layer 330 and the conductive layer 355. The insulating layer 335 contacts the side surface of the conductive layer 355 inside the opening 390.

[0131] 2A and 2B , the insulating layer 335 contacts the bottom and side surfaces of the recess (specifically, the second recess) of the conductive layer 320b, and also contacts the side surfaces of the insulating layer 380a, the conductive layer 355, the insulating layer 380b, the conductive layer 340a, and the conductive layer 340b inside the opening 390. The semiconductor layer 330 contacts the bottom and side surfaces of the recess (specifically, the first recess) of the conductive layer 320b, the insulating layer 335, and the top surface of the conductive layer 340b. The conductive layer 320b has a recess, which increases the area of ​​contact between the semiconductor layer 330 and the conductive layer 320b. Therefore, the contact resistance between the semiconductor layer 330 and the conductive layer 320b can be reduced.

[0132] Here, for example, the shortest distance from the top surface of the insulating layer 110 to the top surface of the conductive layer 320b that contacts the insulating layer 380a is preferably longer than the shortest distance from the top surface of the insulating layer 110 to the bottom surface of the insulating layer 350 inside the opening 390. This increases the contact area between the side surface of the conductive layer 320b and the semiconductor layer 330, thereby reducing the contact resistance between the conductive layer 320b and the semiconductor layer 330. Therefore, the on-current of the transistor 300 can be increased.

[0133] For example, the shortest distance from the top surface of the insulating layer 110 to the top surface of the conductive layer 320b that is in contact with the insulating layer 380 is preferably equal to or greater than the shortest distance from the top surface of the insulating layer 110 to the bottom surface of the conductive layer 365a inside the opening 390, and is even more preferably longer than this shortest distance. This makes it easier to apply a gate electric field to the channel formation region of the semiconductor layer 330, thereby improving the electrical characteristics of the transistor 300. Furthermore, since a gate electric field is also easier to apply to the region of the semiconductor layer 330 that is in contact with the conductive layer 320b, the on-state current of the transistor 200 can be increased. Furthermore, whether the conductive layer 320 or the conductive layer 340 is used as the drain electrode, the electrical characteristics of the transistor 300 can be improved.

[0134] The insulating layer 335 is provided along at least a part of a sidewall of the opening 390. The semiconductor layer 330 has a region inside the opening 390 that faces the conductive layer 355 with the insulating layer 335 sandwiched therebetween. At least a part of this region of the semiconductor layer 330 is in contact with the insulating layer 335. The conductive layer 355 is provided to surround the semiconductor layer 330 with the insulating layer 335 sandwiched therebetween.

[0135] The insulating layer 350 is located on the semiconductor layer 330 and on the insulating layer 380b. The insulating layer 350 is located inside the opening 390 and more inward than the semiconductor layer 330. The insulating layer 350 is provided so as to cover the top and side surfaces of the semiconductor layer 330, the side surfaces of the conductive layer 340b, the side surfaces of the conductive layer 340a, and the top surface of the insulating layer 380b. The insulating layer 350 may have a region in contact with the semiconductor layer 330. The insulating layer 350 may have a region in contact with the semiconductor layer 330, for example, inside the opening 390.

[0136] The insulating layer 350 is provided along the semiconductor layer 330. As described above, a recess is provided in the semiconductor layer 330 at a position overlapping the opening 390. As described above, a recess is also provided in the insulating layer 350 at a position overlapping the opening 390.

[0137] The conductive layer 365 is located on the insulating layer 350. The conductive layer 365 is located inside the opening 390 and on the inner side of the insulating layer 350. The conductive layer 365 is provided so as to fill the opening 390 on the inner side of the insulating layer 350. Specifically, the conductive layer 365 is provided so as to fill the recessed portion of the insulating layer 350.

[0138] The conductive layer 365 has a region inside the opening 390 that faces the semiconductor layer 330 with the insulating layer 350 sandwiched therebetween. This region functions as a channel formation region of the transistor 300. A region of the semiconductor layer 330 in contact with the conductive layer 320 functions as one of the source region and the drain region of the transistor 300. A region of the semiconductor layer 330 in contact with the conductive layer 340 functions as the other of the source region and the drain region of the transistor 300. That is, the channel formation region of the transistor 300 is sandwiched between the source region and the drain region, similar to the channel formation regions of the transistors 100 and 200.

[0139] The conductive layer 355 is provided to face the conductive layer 365 functioning as a gate electrode of the transistor 300, with the insulating layer 335, the semiconductor layer 330, and the insulating layer 350 sandwiched therebetween. Thus, the semiconductor layer 330 has a region facing the conductive layer 365 with the insulating layer 350 sandwiched therebetween and a region facing the conductive layer 355 with the insulating layer 335 sandwiched therebetween.

[0140] The conductive layer 355 is provided to surround at least a part of the channel formation region of the transistor 300 with the insulating layer 335 sandwiched therebetween. As described above, the conductive layer 355 functions as a backgate electrode of the transistor 300. Therefore, the threshold voltage of the transistor 300 can be controlled by controlling the potential of the conductive layer 355. By supplying the conductive layer 355 with a potential lower than or equal to the source potential or a potential lower than or equal to 0 V (preferably a negative potential), for example, the threshold voltage of the transistor 300 can be shifted in the positive direction, thereby achieving normally-off characteristics. This allows the gate potential of the transistor 200 to be held for a long period of time, as described above. Therefore, data written to the memory cell 10 can be held for a long period of time.

[0141] At least one layer constituting the conductive layer 365 is provided in the opening 390. When the conductive layer 365 has a stacked structure, it becomes more difficult to arrange all of the layers constituting the conductive layer 365 in the opening 390 as the transistor 300 is miniaturized and the diameter of the opening 390 becomes smaller. In FIGS. 2A and 2B , an example is shown in which the conductive layer 365 has a two-layer structure, in which only the conductive layer 365a is provided in the opening 390, and the conductive layer 365b on the conductive layer 365a is provided so as to overlap with the opening 390. Note that depending on the diameter of the opening 390, the thickness of the conductive layer 365a, and the like, both the conductive layer 365a and the conductive layer 365b may be located in the opening 390.

[0142] The semiconductor layer 130 including the channel formation region of the transistor 100, the semiconductor layer 230 including the channel formation region of the transistor 200, and the semiconductor layer 330 including the channel formation region of the transistor 300 can each include a metal oxide (also referred to as an oxide semiconductor) that functions as a semiconductor. In this case, the transistor 100, the transistor 200, and the transistor 300 can be said to be OS transistors.

[0143] An OS transistor has an oxygen vacancy (V Ｏ ) and impurities, the electrical characteristics are likely to fluctuate, and reliability may be reduced. In addition, hydrogen in the vicinity of the oxygen vacancy may become a defect in which hydrogen enters the oxygen vacancy (hereinafter referred to as V Ｏ H) and generate electrons that serve as carriers. Therefore, if oxygen vacancies are present in the channel formation region of the oxide semiconductor, the OS transistor is likely to have normally-on characteristics. Therefore, it is preferable that oxygen vacancies and impurities are reduced as much as possible in the channel formation region of the oxide semiconductor. In other words, it is preferable that the carrier concentration of the channel formation region of the oxide semiconductor is reduced and the channel formation region of the oxide semiconductor is made i-type (intrinsic) or substantially i-type.

[0144] On the other hand, the source and drain regions of an OS transistor have more oxygen vacancies than the channel formation region. Ｏ The source and drain regions of an OS transistor preferably have a high carrier concentration and low resistance compared to the channel formation region, due to a high concentration of H or an impurity such as hydrogen, nitrogen, or a metal element.

[0145] When the transistor 100 is an OS transistor, the conductive layers 120b and 140b are preferably formed using a conductive material containing oxygen. This can reduce the contact resistance between the semiconductor layer 130 and the conductive layer 120b and the contact resistance between the semiconductor layer 130 and the conductive layer 140b. Similarly, when the transistor 200 is an OS transistor, the conductive layers 220b and 240b are preferably formed using a conductive material containing oxygen. When the transistor 300 is an OS transistor, the conductive layers 320b and 340b are preferably formed using a conductive material containing oxygen.

[0146] When the conductive layer 120 and the conductive layer 140 have a stacked structure, it is preferable to use a conductive material containing oxygen for a layer in the stacked structure that has the largest contact area with the semiconductor layer 130, because this can reduce the contact resistance with the semiconductor layer 130. For this reason, it is preferable to use a conductive material containing oxygen for the conductive layer 120b and the conductive layer 140b, for example. The same applies to the conductive layer 220, the conductive layer 240, the conductive layer 320, and the conductive layer 340.

[0147] Alternatively, when the conductive layer 120 and the conductive layer 140 have a stacked structure, a conductive material containing oxygen is used for a layer of the stacked structure that is closest to the channel formation region, thereby reducing the contact resistance with the semiconductor layer 130. This shortens the current path between the source and the drain, thereby increasing the on-state current of the transistor 100. For this reason, for example, a conductive material containing oxygen is preferably used for the conductive layer 120b and the conductive layer 140a. The same applies to the conductive layer 220, the conductive layer 240, the conductive layer 320, and the conductive layer 340. Specifically, a conductive material containing oxygen is preferably used for the conductive layer 220b, the conductive layer 240a, the conductive layer 320b, and the conductive layer 340a.

[0148] As the conductive material containing oxygen, it is preferable to use a metal oxide having conductivity (also called an oxide conductor).

[0149] 2A and 2B show a structure in which the end portions of the conductive layer 140a, the conductive layer 140b, and the semiconductor layer 130 are aligned outside the opening 190. Also, FIGS. 2A and 2B show a structure in which the end portions of the conductive layer 240a, the conductive layer 240b, and the semiconductor layer 230 are aligned outside the opening 290. Furthermore, FIGS. 2A and 2B show a structure in which the end portions of the conductive layer 340a, the conductive layer 340b, and the semiconductor layer 330 are aligned outside the opening 390. By processing the conductive layer 140a, the conductive layer 140b, and the semiconductor layer 130 using the same mask as in a manufacturing method example described later, the end portions can have the structures shown in FIGS. 2A and 2B . Furthermore, by processing the conductive layer 240a, the conductive layer 240b, and the semiconductor layer 230 using the same mask, the end portions thereof can be formed as shown in FIGS. 2A and 2B . Furthermore, by processing the conductive layer 340a, the conductive layer 340b, and the semiconductor layer 330 using the same mask, the end portions thereof can be formed as shown in FIGS. 2A and 2B . As described above, the number of masks required for manufacturing a semiconductor device can be reduced, which is preferable. Note that the present invention is not limited to this. For example, in the X direction or Y direction, any one of the end portions of the semiconductor layer 130, the end portion of the conductive layer 140a, and the end portion of the conductive layer 140b may be located more inward or more outward than the other end portions. Similarly, in the X direction or Y direction, any one of the end portions of the semiconductor layer 230, the end portion of the conductive layer 240a, and the end portion of the conductive layer 240b may be located more inward or more outward than the other end portions. Furthermore, any one of the end of the semiconductor layer 330, the end of the conductive layer 340a, and the end of the conductive layer 340b may be located inside or outside the others.

[0150] The conductive layer 140 has an opening 190 in a region overlapping with the conductive layer 120. Furthermore, it is preferable that the conductive layer 140 is not located inside the opening 190 of the insulating layer 180b, for example. That is, it is preferable that the conductive layer 140 does not have a region in contact with the side surface of the insulating layer 180b inside the opening 190. With this configuration, the opening 190 can be formed simultaneously in the conductive layer 140, the insulating layer 180b, the conductive layer 155, and the insulating layer 180a. Furthermore, if the side surfaces of the conductive layer 140, the insulating layer 180b, the conductive layer 155, and the insulating layer 180a are aligned inside the opening 190, the film thickness distribution of the insulating layer 135, the semiconductor layer 130, and the like provided inside the opening 190 can be made uniform. Furthermore, it is possible to prevent the insulating layer 135, the semiconductor layer 130, and the like from being separated by a step or the like between the conductive layer 140 and the insulating layer 180b.

[0151] The above also applies to the conductive layer 240 and the conductive layer 340. Specifically, the conductive layer 240 has an opening 290 in a region overlapping with the conductive layer 220, and preferably is not located inside the opening 290 of the insulating layer 280, for example. The conductive layer 340 has an opening 390 in a region overlapping with the conductive layer 320, and preferably is not located inside the opening 390 of the insulating layer 380b, for example.

[0152] 2A and 2B show a configuration in which the side surface of the conductive layer 140 inside the opening 190 and the side surface of the insulating layer 180b inside the opening 190 are flush (or may be said to be aligned or approximately aligned), but the present invention is not limited to this. For example, the side surface of the conductive layer 140 inside the opening 190 and the side surface of the insulating layer 180b inside the opening 190 may be discontinuous. Furthermore, the inclination of the side surface of the conductive layer 140 inside the opening 190 and the inclination of the side surface of the insulating layer 180b inside the opening 190 may differ from each other. In this case, for example, it is preferable that the taper angle of the side surface of the conductive layer 140 inside the opening 190 is smaller than the taper angle of the side surface of the insulating layer 180b inside the opening 190. This configuration improves the coverage of the semiconductor layer 130 on the side surface of the conductive layer 140 inside the opening 190 and reduces defects such as voids. Furthermore, when insulating layer 180a and insulating layer 180b each have a stacked structure, the inclination of the side surface of each layer may be different inside opening 190. Similarly, when conductive layer 140 has a stacked structure, the inclination of the side surface of each layer may be different inside opening 190. The same applies to the inclination of the side surface of each layer inside opening 290 and the inclination of the side surface of each layer inside opening 390.

[0153] The transistor 100, the transistor 200, and the transistor 300 are each vertical transistors. In a vertical transistor, a source electrode, a semiconductor layer, and a drain electrode can be provided overlapping one another. Specifically, as shown in FIGS. 2A and 2B , a conductive layer 120, a semiconductor layer 130, and a conductive layer 140 can be provided overlapping one another. A conductive layer 220, a semiconductor layer 230, and a conductive layer 240 can be provided overlapping one another. A conductive layer 320, a semiconductor layer 330, and a conductive layer 340 can be provided overlapping one another. For example, the conductive layer 120, the semiconductor layer 130, the conductive layer 140, the conductive layer 220, the semiconductor layer 230, the conductive layer 240, the conductive layer 320, the semiconductor layer 330, and the conductive layer 340 can be provided overlapping one another.

[0154] As described above, the memory cell 10 can include a stack of the transistors 100, 200, and 300. As described above, the transistors 100, 200, and 300 can each be vertical transistors, and the source electrode, the semiconductor layer, and the drain electrode can be stacked. By stacking the vertical transistors 100, 200, and 300 in this order from the bottom, the other of the source and drain electrodes of the transistor 100 and one of the source and drain electrodes of the transistor 200 can be formed using the same conductive layer. Furthermore, the gate electrode of the transistor 200 and one of the source and drain electrodes of the transistor 300 can be formed using the same conductive layer.

[0155] As described above, in the memory cell 10, the transistors 100, 200, and 300 are vertical transistors and are stacked, and the other of the source and drain of the transistor 100 can be electrically connected to one of the source and drain of the transistor 200. In addition, the gate of the transistor 200 can be electrically connected to one of the source and drain of the transistor 300.

[0156] Therefore, the area occupied by the memory cell can be made smaller than when, for example, two or three of the transistors 100, 200, and 300 are formed on the same formation surface and the transistors 100, 200, and 300 are so-called planar transistors. Therefore, a semiconductor device that can be miniaturized or highly integrated can be realized.

[0157] Fig. 3C is a plan view including a cross section taken along dashed-dotted lines A3-A4 in Fig. 2A and a cross section taken along dashed-dotted lines B3-B4 in Fig. 2B. Fig. 3D is a plan view including a cross section taken along dashed-dotted lines A5-A6 in Fig. 2A and a cross section taken along dashed-dotted lines B5-B6 in Fig. 2B. Figs. 3C and 3D can be considered plan views of the XY plane. Fig. 4A is an enlarged view of a region including transistor 100 shown in Fig. 2B. Fig. 4B is an enlarged view of a region including transistor 300 shown in Fig. 2B.

[0158] As shown in FIG. 3C , an opening 190 is provided in the conductive layer 155 that functions as the gate electrode of the transistor 100. The insulating layer 183, the insulating layer 181, the semiconductor layer 130, and the insulating layer 135 are concentrically formed in the opening 190, in this order from the inside. This allows the entire periphery of the semiconductor layer 130 to be a channel formation region in a plan view. As shown in FIG. 3D , an opening 390 is provided in the conductive layer 355 that functions as the backgate electrode of the transistor 300. The conductive layer 365a, the insulating layer 350, the semiconductor layer 330, and the insulating layer 335 are concentrically formed in the opening 390, in this order from the inside. Therefore, the side surface of the conductive layer 365a, which is provided in the center, faces the side surface of the semiconductor layer 330, with the insulating layer 350 sandwiched therebetween. Therefore, the entire periphery of the semiconductor layer 330 becomes a channel formation region in a plan view.

[0159] As described above, for example, the channel width of the transistor 100 is determined by the perimeter of the semiconductor layer 130, and the channel width of the transistor 300 is determined by the perimeter of the semiconductor layer 330. In other words, the channel width of the transistor 100 can be determined by the width of the opening 190 (or the diameter if the opening 190 is circular in plan view). Similarly, the channel width of the transistor 300 can be determined by the width of the opening 390 (or the diameter if the opening 390 is circular in plan view). FIG. 3C shows the width D1 of the opening 190 and the channel width W1 of the transistor 100. FIG. 3D also shows the width D2 of the opening 390 and the channel width W2 of the transistor 300. Furthermore, FIG. 4A also shows the width D1 of the opening 190, and FIG. 4B also shows the width D2 of the opening 390.

[0160] The width D1 of the opening 190 and the width D2 of the opening 390 may vary in the depth direction (e.g., the Z direction). The shortest distance between the two side surfaces of the conductive layer 155 on the opening 190 side in a cross-sectional view can be used as the width D1 of the opening 190. In other words, the minimum width of the opening 190 in the conductive layer 155 can be used as the width D1 of the opening 190. Alternatively, the width of the opening 190 at the highest position in the conductive layer 155, the width of the opening 190 at the lowest position, the width of the opening 190 at the midpoint between these, or the average value of these three widths may be used as the width D1. Here, an example is shown in which the width D1 is determined using the width of the opening 190 in the conductive layer 155, but the method for determining the width D1 is not particularly limited. The shortest distance between the two side surfaces of the insulating layer 180a, the insulating layer 180b, the conductive layer 140a, or the conductive layer 140b on the opening 190 side can be used as the width D1. Alternatively, the width of the opening 190 at the highest position, the width of the opening 190 at the lowest position, the width of the opening 190 at the midpoint between these positions, or the average of these three widths may be used as the width D1. Here, for the width D2, the description of the width D1 can be referenced by replacing the conductive layer 155, the opening 190, the insulating layer 180a, the insulating layer 180b, the conductive layer 140a, and the conductive layer 140b with the conductive layer 355, the opening 390, the insulating layer 380a, the insulating layer 380b, the conductive layer 340a, and the conductive layer 340b, respectively.

[0161] When the openings 190 and 390 are formed using photolithography, the width D1 of the openings 190 and the width D2 of the openings 390 are limited by the exposure limit of photolithography, making further miniaturization difficult. Furthermore, the width D1 of the openings 190 is set by the film thicknesses of the insulating layer 135, the semiconductor layer 130, the insulating layer 181, and the insulating layer 183 provided inside the opening 190. The width D2 of the opening 390 is determined by the film thicknesses of the insulating layer 335, the semiconductor layer 330, the insulating layer 350, and the conductive layer 365a provided inside the opening 390. The width D1 of the openings 190 and the width D2 of the openings 390 are, for example, 5 nm to 100 nm, preferably 5 nm to 60 nm, more preferably 10 nm to 50 nm, more preferably 10 nm to 40 nm, and even more preferably 20 nm to 30 nm. When opening 190 is circular in plan view, width D1 of opening 190 corresponds to the diameter of opening 190, and channel width W1 can be calculated as "D1 × π." Similarly, when opening 390 is circular in plan view, width D2 of opening 390 corresponds to the diameter of opening 390, and channel width W2 can be calculated as "D2 × π."

[0162] For the channel width of the transistor 200 and the width of the opening 290, the above description of the channel width W2 of the transistor 300 and the width D2 of the opening 390 can be referred to. Here, the width of the opening 290 can be the shortest distance between two side surfaces of the insulating layer 280 on the opening 290 side in a cross-sectional view. In other words, the minimum width of the opening 290 in the insulating layer 280 can be used as the width of the opening 290. Alternatively, the width of the opening 290 at the highest position, the width of the opening 290 at the lowest position, the width of the opening 290 at the midpoint between these positions, or the average value of these three widths in the insulating layer 280 can be used as the width of the opening 290. Alternatively, the shortest distance between two side surfaces of the insulating layer 280, the conductive layer 240a, or the conductive layer 240b on the opening 290 side can be used as the width of the opening 290. In addition, the width of the opening 290 may be the width of the opening 290 at the highest position in the insulating layer 280, the conductive layer 240a, or the conductive layer 240b, the width of the opening 290 at the lowest position, the width of the opening 290 at the midpoint between these, or the average value of these three widths.

[0163] Although the present embodiment illustrates an example in which the openings 190, 290, and 390 are circular in plan view, the present invention is not limited thereto. In plan view, the openings 190, 290, and 390 can be, for example, a circle, an approximately circular shape such as an oval, a polygonal shape such as a triangle, a quadrangle (including a rectangle, a diamond, and a square), a pentagon, or a star-shaped polygon, or a polygonal shape with rounded corners. The polygon may be either a concave polygon (a polygon with at least one interior angle exceeding 180 degrees) or a convex polygon (a polygon with all interior angles equal to or less than 180 degrees). As shown in FIGS. 1B to 1D and 3A to 3D , the openings 190, 290, and 390 are preferably circular in plan view. By using a circular shape, the processing accuracy when forming the openings can be improved, allowing for the formation of openings of a fine size. In this specification and the like, a circle is not limited to a perfect circle.

[0164] As described above, Fig. 4A is an enlarged view of a region including the transistor 100 shown in Fig. 2B. Fig. 4A shows regions 130i, 130n1, and 130n2 as regions of the semiconductor layer 130. Note that in Fig. 4A, the hatching patterns of the regions 130n1 and 130n2 of the semiconductor layer 130 are different from the hatching pattern of, for example, the region 130i.

[0165] Region 130i is a region inside opening 190 that faces conductive layer 155 with insulating layer 135 sandwiched therebetween. Region 130i can be at least partially in contact with insulating layer 135. Specifically, the outer surface (conductive layer 155 side) of region 130i in the region located inside opening 190 can be in contact with insulating layer 135.

[0166] The region 130n1 is a region in contact with the conductive layer 120b and a region in its vicinity. The region 130n2 is a region in contact with the conductive layer 140b and a region in its vicinity. For example, the region 130n2 can include a region of the semiconductor layer 130 that overlaps with the conductive layer 140b.

[0167] The region 130i can be a channel formation region of the transistor 100. The region 130n1 can be one of the source region and the drain region of the transistor 100. The region 130n2 can be the other of the source region and the drain region of the transistor 100. The regions 130n1 and 130n2 are low-resistance regions having a higher carrier concentration than the region 130i.

[0168] The conductive layer 220 is provided so as to be in contact with the region 130n2. The upper surface of the insulating layer 183 is located higher than the upper surface of the semiconductor layer 130 in the region 130n2. The upper surface of the insulating layer 183 can be located higher than the upper surface of the semiconductor layer 130 in the region 130n2 by, for example, the thickness of the insulating layer 181. In other words, the difference between the height of the upper surface of the insulating layer 183 from the reference plane and the height of the upper surface of the semiconductor layer 130 in the region 130n2 from the reference plane can be set to, for example, the thickness of the insulating layer 181 or a value close to that. As described above, the reference plane can be, for example, the surface of the substrate or the upper surface of an interlayer film such as the insulating layer 110. Similarly, the upper surface of the insulating layer 183A is located higher than the upper surface of the semiconductor layer 130 in the region 130n2.

[0169] The upper surface of the insulating layer 183 is located above the upper surface of the region 130n2 of the semiconductor layer 130, thereby preventing a decrease in reliability of the semiconductor device due to the manufacturing process of the semiconductor device. Thus, a highly reliable semiconductor device can be provided.

[0170] 4B is an enlarged view of a region including the transistor 300 shown in FIG. 2B as described above. In FIG. 4B, regions 330i, 330n1, and 330n2 are shown as regions of the semiconductor layer 330. Note that in FIG. 4B, the hatching patterns of the regions 330n1 and 330n2 of the semiconductor layer 330 are different from the hatching pattern of, for example, the region 330i.

[0171] The region 330i is a region inside the opening 390 that faces the conductive layer 365a with the insulating layer 350 sandwiched therebetween. The region 330n1 is a region in contact with the conductive layer 320b and a region in its vicinity. The region 330n2 is a region in contact with the conductive layer 340b and a region in its vicinity. For example, the region 330n2 can include a region of the semiconductor layer 330 that overlaps with the conductive layer 340b.

[0172] The region 330i may be a channel formation region of the transistor 300. The region 330n1 may be one of the source region and the drain region of the transistor 300. The region 330n2 may be the other of the source region and the drain region of the transistor 300. The regions 330n1 and 330n2 are low-resistance regions having a higher carrier concentration than the region 330i.

[0173] 4B , a region 330dg is shown as a region of the semiconductor layer 330. The region 330dg faces the conductive layer 365 with the insulating layer 350 interposed therebetween and faces the conductive layer 355 with the insulating layer 335 interposed therebetween. The region 330dg can be a region included in the region 330i.

[0174] For the description of the channel formation region, the source region, and the drain region of the transistor 200, the above description of the channel formation region, the source region, and the drain region of the transistor 300 can be referred to by replacing the semiconductor layer 330, the opening 390, the insulating layer 350, the conductive layer 365a, the conductive layer 320b, and the conductive layer 340b with the semiconductor layer 230, the opening 290, the insulating layer 250, the conductive layer 320a, the conductive layer 220b, and the conductive layer 240b, respectively.

[0175] In planar transistors, the channel length is limited by the exposure limit of photolithography, making further miniaturization difficult. On the other hand, in one embodiment of the present invention, the channel length of the transistor 200 can be set by the thickness of the insulating layer 280. The channel length of the transistor 300 can be set by the thicknesses of the insulating layer 380a, the conductive layer 355, and the insulating layer 380b. Therefore, the channel lengths of the transistors 200 and 300 can be made very fine, equal to or less than the exposure limit of photolithography. Specifically, the channel lengths of the transistors 200 and 300 can be set to, for example, 0.1 nm to 60 nm, 0.1 nm to 50 nm, 1 nm to 40 nm, 1 nm to 30 nm, 5 nm to 20 nm, or 5 nm to 10 nm. The channel length of the transistor 100 can be set by the thickness of the conductive layer 155. Therefore, like the channel lengths of the transistors 200 and 300, the channel length of the transistor 100 can be made to be an extremely fine structure equal to or less than the exposure limit of photolithography.

[0176] As described above, the transistors 100, 200, and 300 included in the memory cell 10 can have a larger on-state current than, for example, a planar transistor. Therefore, a semiconductor device with high operating speed can be provided.

[0177] Furthermore, the transistors 100, 200, and 300 can each have a channel formation region and one or both of a source region and a drain region within the opening. As a result, the area occupied by the memory cell 10 can be reduced compared to when the transistors 100, 200, and 300 are planar transistors in which the channel formation region, source region, and drain region are separately provided on the XY plane. As a result, a semiconductor device that can be miniaturized or highly integrated can be realized.

[0178] <Constituent Materials of Semiconductor Device> Materials that can be used in the semiconductor device of this embodiment will be described below. Note that each layer constituting the semiconductor device of this embodiment may have a single-layer structure or a stacked-layer structure. 2A and 2B show an example in which the conductive layer 120a, the conductive layer 220a, and the conductive layer 320a have a single-layer structure. 4A and 4B show an example in which the conductive layer 120a, the conductive layer 220a, and the conductive layer 320a have a stacked-layer structure.

[0179] [Semiconductor Layer] As described above, the semiconductor layer 130, the semiconductor layer 230, and the semiconductor layer 330 each have a channel formation region. The semiconductor layer 130, the semiconductor layer 230, and the semiconductor layer 330 further have a source region and a drain region. The source region and the drain region are low-resistance regions with higher carrier concentrations than the channel formation region. The semiconductor layer 130, the semiconductor layer 230, and the semiconductor layer 330 may each have a stacked structure of two or more layers. Hereinafter, when the semiconductor layer 130, the semiconductor layer 230, and the semiconductor layer 330 are oxide semiconductor layers, materials that can be used for the semiconductor layer 130, the semiconductor layer 230, and the semiconductor layer 330 will be described.

[0180] The crystallinity of the semiconductor material used for the semiconductor layer 130, the semiconductor layer 230, and the semiconductor layer 330 is not particularly limited, and any of an amorphous semiconductor, a single crystal semiconductor, and a semiconductor having crystallinity other than single crystal (a microcrystalline semiconductor, a polycrystalline semiconductor, or a semiconductor having a crystalline region in part) may be used. The use of a single crystal semiconductor or a crystalline semiconductor is preferable because it can suppress deterioration of transistor characteristics.

[0181] The band gap of a metal oxide functioning as a semiconductor is preferably 2.0 eV or more, more preferably 2.5 eV or more. By using a metal oxide with a wide band gap, the off-state current of a transistor can be reduced. Because the off-state current of an OS transistor is low, the power consumption of a semiconductor device can be sufficiently reduced. Furthermore, because the frequency characteristics of an OS transistor are high, the semiconductor device can operate at high speed.

[0182] For an oxide semiconductor layer that can be used as a semiconductor layer of a transistor of one embodiment of the present invention, refer to the description in Embodiment 2. Detailed description thereof will be omitted here.

[0183] Note that the semiconductor device of this embodiment may also be applied to a transistor using another semiconductor material in the channel formation region. Examples of such another semiconductor material include semiconductors made of simple elements or compound semiconductors. Examples of semiconductors made of simple elements include silicon and germanium. Examples of compound semiconductors include gallium arsenide and silicon germanium. Other examples of compound semiconductors include organic semiconductors and nitride semiconductors. Note that the aforementioned oxide semiconductor is also a type of compound semiconductor. Note that these semiconductor materials may contain impurities as dopants.

[0184] Silicon that can be used as a semiconductor material for a transistor includes single crystal silicon, polycrystalline silicon, microcrystalline silicon, and amorphous silicon. An example of polycrystalline silicon is low temperature polysilicon (LTPS).

[0185] The semiconductor layer of the transistor may include a layered material that functions as a semiconductor. A layered material is a general term for a group of materials having a layered crystal structure. A layered crystal structure is a structure in which layers formed by covalent or ionic bonds are stacked via bonds weaker than covalent or ionic bonds, such as van der Waals bonds. A layered material has high electrical conductivity within a unit layer, that is, high two-dimensional electrical conductivity. By using a material that functions as a semiconductor and has high two-dimensional electrical conductivity in the channel formation region, a transistor with a large on-state current can be provided.

[0186] Examples of the layered material include graphene, silicene, and chalcogenides. Chalcogenides are compounds containing chalcogen (an element belonging to Group 16). Examples of chalcogenides include transition metal chalcogenides and Group 13 chalcogenides. Specific examples of transition metal chalcogenides that can be used as semiconductor layers of transistors include molybdenum sulfide (typically MoS ２ ), molybdenum selenide (typically MoSe ２ ), molybdenum telluride (typically MoTe ２ ), tungsten sulfide (typically WS ２ ), tungsten selenide (typically WSe ２ ), tungsten tellurium (typically WTe ２ ), hafnium sulfide (typically HfS ２ ), hafnium selenide (typically HfSe ２ ), zirconium sulfide (typically ZrS ２ ), and zirconium selenide (typically ZrSe ２ ) etc.

[0187] [Insulating Layer] It is preferable to use an inorganic insulating film for each of the insulating layers (insulating layer 110, insulating layer 135, insulating layer 180a, insulating layer 180b, insulating layer 181, insulating layer 181A, insulating layer 183, insulating layer 183A, insulating layer 250, insulating layer 280, insulating layer 335, insulating layer 350, insulating layer 380a, insulating layer 380b, etc.) included in the semiconductor device. Examples of inorganic insulating films include an oxide insulating film, a nitride insulating film, an oxynitride insulating film, and a nitride oxide insulating film. Examples of oxide insulating films include a silicon oxide film, an aluminum oxide film, a magnesium oxide film, a gallium oxide film, a germanium oxide film, an yttrium oxide film, a zirconium oxide film, a lanthanum oxide film, a neodymium oxide film, a hafnium oxide film, a tantalum oxide film, a cerium oxide film, a gallium zinc oxide film, and a hafnium aluminate film. Examples of nitride insulating films include a silicon nitride film and an aluminum nitride film. Examples of the oxynitride insulating film include a silicon oxynitride film, an aluminum oxynitride film, a gallium oxynitride film, an yttrium oxynitride film, and a hafnium oxynitride film. Examples of the nitride oxide insulating film include a silicon nitride oxide film and an aluminum nitride oxide film. An insulating layer included in a semiconductor device may be an organic insulating film.

[0188] For example, as transistors become more miniaturized and highly integrated, problems such as leakage current may occur due to thinner gate insulating layers. Using high-k materials for the gate insulating layer allows for lower voltages during transistor operation while maintaining the physical film thickness. It also allows for thinner equivalent oxide thickness (EOT) of the gate insulating layer. Meanwhile, using a material with a low dielectric constant for the insulating layer that functions as an interlayer film can reduce the parasitic capacitance that occurs between wiring. Therefore, it is advisable to select materials according to the function of the insulating layer. Materials with a low dielectric constant also have high dielectric strength.

[0189] Examples of materials with a high relative dielectric constant (high-k) include aluminum oxide, gallium oxide, hafnium oxide, tantalum oxide, zirconium oxide, hafnium zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxynitrides containing silicon and hafnium, and nitrides containing silicon and hafnium.

[0190] Examples of materials with a low relative dielectric constant include inorganic insulating materials such as silicon oxide, silicon oxynitride, and silicon nitride oxide, and resins such as polyester, polyolefin, polyamide (nylon, aramid, etc.), polyimide, polycarbonate, and acrylic resin. Other examples of inorganic insulating materials with a low relative dielectric constant include silicon oxide doped with fluorine, silicon oxide doped with carbon, and silicon oxide doped with carbon and nitrogen. Another example is silicon oxide having vacancies. These silicon oxides may contain nitrogen.

[0191] Furthermore, a material capable of exhibiting ferroelectricity may be used for the insulating layer of the semiconductor device. Examples of the material capable of exhibiting ferroelectricity include hafnium oxide, zirconium oxide, and HfZrO. Ｘ(X is a real number greater than 0), and other metal oxides. Ferroelectric materials include hafnium oxide to which element J1 (here, element J1 is one or more selected from zirconium, silicon, aluminum, gadolinium, yttrium, lanthanum, strontium, and the like) is added. The ratio of the number of hafnium atoms to the number of element J1 can be set as appropriate; for example, the ratio of the number of hafnium atoms to the number of element J1 can be set to 1:1 or close thereto. Ferroelectric materials include zirconium oxide to which element J2 (here, element J2 is one or more selected from hafnium, silicon, aluminum, gadolinium, yttrium, lanthanum, strontium, and the like) is added. The ratio of the number of zirconium atoms to the number of element J2 can be set as appropriate; for example, the ratio of the number of zirconium atoms to the number of element J2 can be set to 1:1 or close thereto. Furthermore, lead titanate (PbTiO Ｘ Piezoelectric ceramics having a perovskite structure, such as barium strontium titanate (BST), strontium titanate, lead zirconate titanate (PZT), strontium bismuth tantalate (SBT), bismuth ferrite (BFO), or barium titanate, may also be used.

[0192] Furthermore, examples of materials that may exhibit ferroelectricity include metal nitrides containing element M1, element M2, and nitrogen. Here, element M1 is one or more elements selected from aluminum, gallium, indium, etc. Furthermore, element M2 is one or more elements selected from boron, scandium, yttrium, lanthanum, cerium, neodymium, europium, titanium, zirconium, hafnium, vanadium, niobium, tantalum, chromium, etc. The ratio of the number of atoms of element M1 to the number of atoms of element M2 can be appropriately set. Furthermore, metal oxides containing element M1 and nitrogen may exhibit ferroelectricity even without containing element M2. Furthermore, examples of materials that may exhibit ferroelectricity include materials in which element M3 is added to the above metal nitrides. Furthermore, element M3 is one or more elements selected from magnesium, calcium, strontium, zinc, cadmium, etc. Here, the ratio of the number of atoms of the element M1, the number of atoms of the element M2, and the number of atoms of the element M3 can be set appropriately.

[0193] Furthermore, materials that can have ferroelectricity include SrTaO ２ N and BaTaO ２ Perovskite-type oxynitrides such as GaFeO and GaFeO with a κ-alumina structure ３ etc.

[0194] In the above description, metal oxides and metal nitrides are used as examples, but the present invention is not limited thereto. For example, metal oxynitrides in which nitrogen is added to the above metal oxides, or metal nitride oxides in which oxygen is added to the above metal nitrides, etc. may also be used.

[0195] Furthermore, as a material capable of exhibiting ferroelectricity, for example, a mixture or compound made of a plurality of materials selected from the materials listed above can be used. Alternatively, the insulating layer can have a laminated structure made of a plurality of materials selected from the materials listed above. However, since the crystal structure (characteristics) of the materials listed above can change not only depending on the film formation conditions but also on various processes, in this specification and the like, not only materials that exhibit ferroelectricity are referred to as ferroelectrics, but also as materials capable of exhibiting ferroelectricity.

[0196] Metal oxides containing either or both of hafnium and zirconium can have ferroelectricity even in thin films of a few nanometers. Furthermore, metal oxides containing either or both of hafnium and zirconium can have ferroelectricity even in very small areas. Therefore, by using metal oxides containing either or both of hafnium and zirconium, miniaturization of semiconductor devices can be achieved.

[0197] In this specification, a layer of a material that can have ferroelectricity may be referred to as a ferroelectric layer, a metal oxide film, or a metal nitride film. Also, in this specification, a device having such a ferroelectric layer, a metal oxide film, or a metal nitride film may be referred to as a ferroelectric device.

[0198] Ferroelectricity is believed to be exhibited by the displacement of oxygen or nitrogen in crystals contained in the ferroelectric layer due to an external electric field. Furthermore, it is believed that the exhibiting of ferroelectricity depends on the crystal structure of the crystals contained in the ferroelectric layer. Therefore, for an insulating layer to exhibit ferroelectricity, the insulating layer must contain crystals. In particular, an insulating layer containing crystals having an orthorhombic crystal structure is preferred because it exhibits ferroelectricity. The crystal structure of the crystals contained in the insulating layer may be one or more selected from cubic, tetragonal, orthorhombic, monoclinic, and hexagonal crystals. The insulating layer may also have an amorphous structure. In this case, the insulating layer may have a composite structure having an amorphous structure and a crystalline structure.

[0199] Furthermore, adding a Group 3 element (also referred to as a IIIa element) in the periodic table to an oxide containing one or both of hafnium and zirconium increases the oxygen vacancy concentration in the oxide, making it easier to form crystals with an orthorhombic crystal structure. This is preferable because it increases the proportion of crystals with an orthorhombic crystal structure and increases the remanent polarization. On the other hand, adding too much of the Group 3 element may reduce the crystallinity of the oxide and make it difficult to exhibit ferroelectricity. Therefore, the content of the Group 3 element in the oxide containing one or both of hafnium and zirconium is preferably 0.1 atomic% to 10 atomic%, more preferably 0.1 atomic% to 5 atomic%, and even more preferably 0.1 atomic% to 3 atomic%. Here, the content of the Group 3 element refers to the ratio of the number of atoms of the Group 3 element to the sum of the number of atoms of all metal elements contained in the layer. The Group 3 element is preferably one or more selected from scandium, lanthanum, and yttrium, and more preferably one or both of lanthanum and yttrium.

[0200] Furthermore, a transistor using a metal oxide can have stable electrical characteristics by being surrounded by an insulating layer that has a function of suppressing the permeation of impurities and oxygen. The insulating layer that has a function of suppressing the permeation of impurities and oxygen can be, for example, a single-layer or stacked insulating layer containing one or more elements selected from boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, and tantalum. Specifically, the insulating layer that has a function of suppressing the permeation of impurities and oxygen can be made of a metal oxide such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, or tantalum oxide, or a metal nitride such as aluminum nitride, silicon nitride oxide, or silicon nitride.

[0201] Specifically, examples of insulating layers that have the function of suppressing the permeation of impurities such as water and hydrogen and oxygen include metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide. Examples of insulating layers that have the function of suppressing the permeation of impurities such as water and hydrogen and oxygen include oxides containing aluminum and hafnium (hafnium aluminate). Examples of insulating layers that have the function of suppressing the permeation of impurities such as water and hydrogen and oxygen include metal nitrides such as aluminum nitride, aluminum titanium nitride, titanium nitride, silicon nitride oxide, and silicon nitride.

[0202] An insulating layer such as a gate insulating layer that is in contact with an oxide semiconductor layer or that is provided near the oxide semiconductor layer is preferably an insulating layer having a region containing oxygen that is released by heating (hereinafter, sometimes referred to as excess oxygen). For example, when an insulating layer having a region containing excess oxygen is in contact with an oxide semiconductor layer or is located near the oxide semiconductor layer, oxygen vacancies in the oxide semiconductor layer can be reduced. Examples of insulating layers that are likely to have a region containing excess oxygen include silicon oxide, silicon oxynitride, and silicon oxide having vacancies.

[0203] Since the insulating layer 110 functions as an interlayer film, it is preferable that the insulating layer 110 has a low dielectric constant. By using a material with a low dielectric constant for the interlayer film, the parasitic capacitance generated between wirings can be reduced. Silicon oxide and silicon oxynitride are both thermally stable, and therefore are suitable for the insulating layer 110.

[0204] The concentration of impurities such as water and hydrogen in the insulating layer 110 is preferably reduced. This can prevent impurities such as water and hydrogen from entering the channel formation region of the semiconductor layer 130.

[0205] Furthermore, a barrier insulating layer against hydrogen is preferably used as the insulating layer 110. When the insulating layer 110 provided on the outer side of the semiconductor layer 130 has a barrier property against hydrogen, diffusion of hydrogen into the semiconductor layer 130 can be suppressed.

[0206] Examples of materials for the barrier insulating layer against hydrogen include aluminum oxide, magnesium oxide, hafnium oxide, gallium oxide, silicon nitride, and silicon nitride oxide.

[0207] In this specification and the like, a barrier insulating layer refers to an insulating layer having barrier properties. The barrier properties refer to a property that makes it difficult for a corresponding substance to diffuse (also referred to as a property that makes it difficult for a corresponding substance to permeate, a property that the permeability of a corresponding substance is low, or a function that suppresses the diffusion of a corresponding substance). Note that hydrogen when described as a corresponding substance includes, for example, a hydrogen atom, a hydrogen molecule, a water molecule, and OH. − Furthermore, unless otherwise specified, impurities when described as corresponding substances refer to impurities in the channel formation region or semiconductor layer, and include, for example, hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, and nitrogen oxide molecules (N ２ O, NO, and NO ２ The term "oxygen" refers to at least one of an oxygen atom, an oxygen molecule, etc., when described as a corresponding substance.

[0208] For example, it is preferable to use a silicon nitride film as the insulating layer 110 .

[0209] Preferably, the insulating layers 180a, 180b, 280a, 280b, 380a, and 380b each have the aforementioned barrier insulating layer against hydrogen. The insulating layers 180a and 180b are provided to surround the semiconductor layer 130. The insulating layers 180a and 180b provided on the outside of the semiconductor layer 130 have barrier properties against hydrogen, thereby suppressing the diffusion of hydrogen into the semiconductor layer 130. Similarly, the insulating layers 280a and 280b have barrier properties against hydrogen, thereby suppressing the diffusion of hydrogen into the semiconductor layer 230. Furthermore, the insulating layers 380a and 380b have barrier properties against hydrogen, thereby suppressing the diffusion of hydrogen into the semiconductor layer 330. Each of the insulating layers 180a, 180b, 280a, 280b, 380a, and 380b preferably includes, for example, one or both of an aluminum oxide film and a silicon nitride film.

[0210] Silicon nitride also has a barrier property against oxygen. Therefore, by using silicon nitride for the insulating layer 180a, the insulating layer 180b, the insulating layer 280a, the insulating layer 280b, the insulating layer 380a, and the insulating layer 380b, oxygen is extracted from the semiconductor layer 130, the semiconductor layer 230, and the semiconductor layer 330, and it is possible to prevent excessive oxygen vacancies from being formed in the semiconductor layer 130, the semiconductor layer 230, and the semiconductor layer 330.

[0211] Furthermore, using silicon nitride for the insulating layer 180a, the insulating layer 180b, the insulating layer 280a, the insulating layer 280b, the insulating layer 380a, and the insulating layer 380b can prevent excess oxygen from being supplied to the semiconductor layer 130, the semiconductor layer 230, and the semiconductor layer 330. Therefore, excess oxygen can be prevented from being contained in the channel formation regions of the semiconductor layer 130, the semiconductor layer 230, and the semiconductor layer 330, and the reliability of the transistor 100, the transistor 200, and the transistor 300 can be improved.

[0212] Furthermore, it is preferable that the insulating layer 180a, the insulating layer 180b, the insulating layer 280a, the insulating layer 280b, the insulating layer 380a, and the insulating layer 380b each have the above-mentioned oxide insulating film, oxynitride insulating film, or insulating layer having a region containing excess oxygen.

[0213] For example, an insulating layer having a region containing excess oxygen can be formed by sputtering in an oxygen-containing atmosphere. Furthermore, by using a sputtering method that does not require the use of hydrogen-containing molecules in the deposition gas, the hydrogen concentrations in the insulating layers 180a, 180b, 280a, 280b, 380a, and 380b can be reduced. By depositing at least some of the layers constituting the insulating layers 180a, 180b, 280a, 280b, 380a, and 380b in this manner, oxygen can be supplied from the insulating layers 180a, 180b, 280a, 280b, 380a, and 380b to the channel formation regions of the semiconductor layers 130, 230, and 330, thereby reducing oxygen vacancies and VoH.

[0214] The concentrations of impurities such as water and hydrogen in the insulating layer 180a, the insulating layer 180b, the insulating layer 280a, the insulating layer 280b, the insulating layer 380a, and the insulating layer 380b are preferably reduced, thereby preventing impurities such as water and hydrogen from entering the channel formation regions of the semiconductor layer 130, the semiconductor layer 230, and the semiconductor layer 330.

[0215] For example, it is preferable to use a single-layer structure of a silicon nitride film, a silicon nitride oxide film, or an aluminum oxide film for the insulating layer 180a, the insulating layer 180b, the insulating layer 280a, the insulating layer 280b, the insulating layer 380a, and the insulating layer 380b, respectively. Alternatively, it is preferable to use a three-layer structure in which a silicon nitride film, a silicon oxide film, and a silicon nitride film are stacked in this order for the insulating layer 180a, the insulating layer 180b, the insulating layer 280a, the insulating layer 280b, the insulating layer 380a, and the insulating layer 380b, respectively. For example, it is preferable to use a three-layer structure in which an aluminum oxide film, a silicon oxide film, and an aluminum oxide film are stacked in this order for the insulating layer 180a, the insulating layer 180b, the insulating layer 280a, the insulating layer 280b, the insulating layer 380a, and the insulating layer 380b, respectively.

[0216] The insulating layer 250 and the insulating layer 350 preferably have a function of capturing and fixing hydrogen. This can reduce the hydrogen concentration in the semiconductor layer 230 and the semiconductor layer 330, particularly in the channel formation region of the transistor. Therefore, the V Ｏ By reducing H, the channel forming region can be made i-type or substantially i-type.

[0217] Examples of materials for insulating layers capable of capturing or fixing hydrogen include metal oxides such as oxides containing hafnium, oxides containing magnesium, oxides containing aluminum, and oxides containing aluminum and hafnium (hafnium aluminate). These metal oxides may further contain zirconium, such as oxides containing hafnium and zirconium. Metal oxides with amorphous structures have dangling bonds in some oxygen atoms, which enhance their ability to capture or fix hydrogen. Therefore, these metal oxides preferably have an amorphous structure. For example, an amorphous structure may be achieved by including silicon in these oxides. For example, it is preferable to use an oxide containing hafnium and silicon (hafnium silicate). Metal oxides may have crystalline regions and / or grain boundaries in some regions.

[0218] The ability to capture or fix a corresponding substance can also be said to have the property of making it difficult for the corresponding substance to diffuse. Therefore, the ability to capture or fix a corresponding substance can be rephrased as barrier properties.

[0219] When the gate insulating layer has a stacked structure, the layer in contact with the semiconductor layer 230 and the layer in contact with the semiconductor layer 330 preferably have a function of capturing and fixing hydrogen. This allows hydrogen contained in the semiconductor layer 230 and the semiconductor layer 330 to be more effectively captured or fixed. Therefore, the hydrogen concentrations in the semiconductor layer 230 and the semiconductor layer 330 can be reduced. For example, hafnium silicate or the like may be used as the layer of the insulating layer 250 in contact with the semiconductor layer 230 and the layer of the insulating layer 350 in contact with the semiconductor layer 330. In addition, the layers preferably have an amorphous structure.

[0220] By making the layer amorphous, it is possible to suppress the formation of crystal grain boundaries. By suppressing the formation of crystal grain boundaries, it is possible to improve the flatness of the layer. This makes it possible to make the film thickness distribution of the insulating layer 250 and the insulating layer 350 uniform and reduce portions with extremely thin film thicknesses, thereby improving the breakdown voltage of the insulating layer 250 and the insulating layer 350. It is also possible to make the film thickness distribution of the film provided on the insulating layer 250 and the film provided on the insulating layer 350 uniform.

[0221] Furthermore, by suppressing the formation of grain boundaries in the layers, leakage current due to defect levels at the grain boundaries can be reduced, allowing the insulating layer 250 and the insulating layer 350 to function as insulating films with low leakage current.

[0222] Furthermore, since hafnium oxide is a high dielectric constant (high-k) material, hafnium silicate can also be a high dielectric constant (high-k) material depending on the silicon content. Therefore, when hafnium oxide or hafnium silicate is used for the gate insulating layer, it is possible to reduce the gate potential applied during transistor operation while maintaining the physical film thickness of the gate insulating layer. Furthermore, it is possible to reduce the equivalent oxide thickness (EOT) of the gate insulating layer.

[0223] From the above, it is preferable to use an oxide containing one or both of aluminum and hafnium for the insulating layer 250 and the insulating layer 350, it is more preferable to use an oxide having an amorphous structure and containing one or both of aluminum and hafnium, and it is even more preferable to use aluminum oxide having an amorphous structure.

[0224] Furthermore, it is preferable to use the above-mentioned barrier insulating layer against hydrogen as the insulating layer 250 and the insulating layer 350. By using a barrier insulating layer against hydrogen as the insulating layer 250 and the insulating layer 350, it is possible to suppress diffusion of impurities contained in the conductive layer 320 and the conductive layer 365 into the semiconductor layer 230 and the semiconductor layer 330. For example, silicon nitride has a high barrier property against hydrogen and is therefore suitable for the insulating layer 250 and the insulating layer 350. Furthermore, the insulating layer 250 and the insulating layer 350 may include an insulating layer having a heat-stable structure, such as silicon oxide or silicon oxynitride.

[0225] With such a structure, a semiconductor device having good electrical characteristics, high reliability, little variation in the electrical characteristics of the transistors, and a large on-state current can be provided.

[0226] Furthermore, the insulating layer 250 and the insulating layer 350 may have an insulating layer with a thermally stable structure, such as silicon oxide or silicon oxynitride.

[0227] Furthermore, the insulating layer 250 and the insulating layer 350 may have an insulating layer having a heat-stable structure between a pair of insulating layers having the function of capturing and fixing hydrogen.

[0228] The insulating layer 250 and the insulating layer 350 preferably have a barrier insulating layer against oxygen. This can suppress oxidation of the conductive layer 240, the conductive layer 320, the conductive layer 340, the conductive layer 365, and the like. When the insulating layer 250 and the insulating layer 350 have a stacked structure, the layer in contact with the conductive layer 240 and the layer in contact with the conductive layer 340 are preferably barrier insulating layers against oxygen. In particular, among the layers constituting the insulating layer 250 and the insulating layer 350, the layer in contact with the conductive layer 240, the layer in contact with the conductive layer 320, the layer in contact with the conductive layer 340, and the layer in contact with the conductive layer 365 are preferably barrier insulating layers against oxygen.

[0229] By using a barrier insulating layer against hydrogen and oxygen for the layer of the insulating layer 250 and the layer of the insulating layer 350 that is in contact with the conductive layer 320 and the layer that is in contact with the conductive layer 365, it is possible to suppress oxidation of the conductive layer 320 and the conductive layer 365. Furthermore, it is possible to suppress the oxygen contained in the semiconductor layer 230 and the semiconductor layer 330 from diffusing into the conductive layer 320 and the conductive layer 365, and to suppress the formation of oxygen vacancies in the semiconductor layer 230 and the semiconductor layer 330.

[0230] Examples of the barrier insulating layer against oxygen include oxides containing one or both of aluminum and hafnium, magnesium oxide, gallium oxide, gallium zinc oxide, silicon nitride, and silicon nitride oxide. Examples of oxides containing one or both of aluminum and hafnium include aluminum oxide, hafnium oxide, oxides containing aluminum and hafnium (hafnium aluminate), and oxides containing hafnium and silicon (hafnium silicate).

[0231] The layer in the insulating layer 250 that is in contact with the conductive layer 240 is preferably less permeable to oxygen than at least the insulating layer 280 and the insulating layer 380a. The layer has oxygen barrier properties, which can prevent the side surfaces of the conductive layer 240 from being oxidized and an oxide film from being formed on the side surfaces. This can prevent a decrease in the on-state current or the field-effect mobility of the transistor 200. Similarly, the layer in the insulating layer 350 that is in contact with the conductive layer 340 is preferably less permeable to oxygen than at least the insulating layer 380b. This can prevent a decrease in the on-state current or the field-effect mobility of the transistor 300.

[0232] Each layer constituting the insulating layer 250 and each layer constituting the insulating layer 350 are preferably thin films. For example, by setting the thickness of each of the insulating layer 250 and the insulating layer 350 to 1 nm or more and 20 nm or less, preferably 3 nm or more and 10 nm or less, the subthreshold swing value (also referred to as S value), which is one of the transistor characteristics, can be reduced. Note that the S value refers to the amount of change in gate voltage when the drain current is changed by one order of magnitude with the drain voltage held constant in the subthreshold region.

[0233] The thickness of each layer constituting the insulating layer 250 and the insulating layer 350 is preferably 0.1 nm to 10 nm, more preferably 0.1 nm to 5 nm, more preferably 0.5 nm to 5 nm, more preferably 1 nm to less than 5 nm, and even more preferably 1 nm to 3 nm. Note that each layer constituting the insulating layer 250 and the insulating layer 350 preferably has a region with the above-described thickness in at least a portion thereof.

[0234] Furthermore, the insulating layers 250 and 350 preferably have a three-layer structure in which a first insulating layer having a material with a low dielectric constant, a second insulating layer having a function of capturing or fixing hydrogen, and a third insulating layer having barrier properties against hydrogen and oxygen are stacked in this order from the semiconductor layer 230 side and the semiconductor layer 330 side, respectively. Silicon oxide or silicon oxynitride is preferably used as the material with a low dielectric constant for the first insulating layer. The first insulating layer is a layer in contact with the semiconductor layer 230 or the semiconductor layer 330. Using an oxide for the first insulating layer can supply oxygen to the semiconductor layer 230 or the semiconductor layer 330. Furthermore, providing the third insulating layer can suppress diffusion of oxygen contained in the first insulating layer to the conductive layer 320 or the conductive layer 365, thereby suppressing oxidation of the conductive layer 320 or the conductive layer 365. Furthermore, a decrease in the amount of oxygen supplied from the first insulating layer to the semiconductor layer 230 or the semiconductor layer 330 can be suppressed.

[0235] The insulating layer 250 and the insulating layer 350 preferably have a four-layer structure in which a fourth insulating layer having a barrier property against oxygen, a first insulating layer made of a material with a low dielectric constant, a second insulating layer having a function of capturing or fixing hydrogen, and a third insulating layer having a barrier property against hydrogen and oxygen are stacked in this order from the semiconductor layer 230 side and the semiconductor layer 330 side, respectively. The first to third insulating layers can have a structure similar to that of the layers used in the three-layer structure described above. The fourth insulating layer is a layer in contact with the semiconductor layer 230 or the semiconductor layer 330. The fourth insulating layer has a barrier property against oxygen, which can prevent oxygen from being released from the semiconductor layer 230 or the semiconductor layer 330. For example, aluminum oxide may be used as the fourth insulating layer. Aluminum oxide has a function of capturing or fixing hydrogen, and is therefore suitable as the fourth insulating layer in contact with the semiconductor layer 230 or the semiconductor layer 330. Specifically, it is preferable to use a four-layer structure in which an aluminum oxide film, a silicon oxide film, a hafnium oxide film, and a silicon nitride film are stacked in this order from the semiconductor layer 230 side or the semiconductor layer 330 side.

[0236] Typically, the thicknesses of the fourth insulating layer, the first insulating layer, the second insulating layer, and the third insulating layer are 1 nm, 2 nm, 2 nm, and 1 nm, respectively. With such a structure, the transistor can have good electrical characteristics even when miniaturized or highly integrated.

[0237] Furthermore, it is preferable to use a three-layer structure in which a fourth insulating layer having a barrier property against oxygen, a first insulating layer having a material with a low relative dielectric constant, and a second insulating layer having a function of capturing or fixing hydrogen are stacked in this order from the semiconductor layer 230 side and the semiconductor layer 330 side, respectively, as the insulating layer 250 and the insulating layer 350. Specifically, it is preferable to use a three-layer structure in which an aluminum oxide film, a silicon oxide film, and a hafnium oxide film are stacked in this order from the semiconductor layer 230 side or the semiconductor layer 330 side.

[0238] Note that the insulating layer 110 may be an insulating layer having the above-described function of capturing or fixing hydrogen. This allows hydrogen in the semiconductor layer 130 to diffuse into the insulating layer 110 through the conductive layers 120a and 120b, and the hydrogen can be captured or fixed. This reduces the hydrogen concentration in the semiconductor layer 130. For example, the insulating layer 110 may have a two-layer structure including a silicon nitride film and a hafnium silicate film on the silicon nitride film.

[0239] The insulating layer 135 and the insulating layer 335 can also be referred to as a sidewall, a sidewall insulating layer, a sidewall protective layer, or the like.

[0240] The insulating layer 135 and the insulating layer 335 preferably include an insulating layer having a region containing oxygen that is released by heating, thereby enabling oxygen to be supplied from the insulating layer 135 and the insulating layer 335 to the semiconductor layer 130 and the semiconductor layer 330. For example, the insulating layer 135 and the insulating layer 335 are preferably made of silicon oxide or silicon oxynitride.

[0241] The insulating layer 135 and the insulating layer 335 preferably include a barrier insulating layer against hydrogen, which can suppress diffusion of hydrogen into the semiconductor layer 130 and the semiconductor layer 330, thereby improving the reliability of the transistor 100 and the transistor 300. For example, the insulating layer 135 and the insulating layer 335 are preferably made of aluminum oxide, hafnium oxide, silicon nitride, or silicon nitride oxide.

[0242] The insulating layer 135 and the insulating layer 335 may be made of the above-mentioned material that can have ferroelectricity.

[0243] For example, the insulating layer 135 and the insulating layer 335 can have a single-layer structure of a silicon oxide film, a single-layer structure of a silicon nitride film, a two-layer structure of a silicon oxide film and a silicon nitride film, a three-layer structure of a silicon oxide film, a silicon nitride film, and a silicon oxide film, or a three-layer structure of a silicon nitride film, a silicon oxide film, and a silicon nitride film. In the case of a two-layer structure of a silicon oxide film and a silicon nitride film, for example, it is preferable to provide a silicon oxide film on the semiconductor layer 230 side and the semiconductor layer 330 side, and a silicon nitride film on the conductive layer 155 side and the conductive layer 355 side. This makes it possible to efficiently supply oxygen to the semiconductor layer 130 and the semiconductor layer 330 and to suppress the diffusion of impurities such as hydrogen into the semiconductor layer 130 and the semiconductor layer 330. Alternatively, a silicon nitride film may be provided on the semiconductor layer 230 side and the semiconductor layer 330 side, and a silicon oxide film may be provided on the conductive layer 155 side and the conductive layer 355 side.

[0244] The insulating layer 181 preferably includes a barrier insulating layer against hydrogen, which can suppress diffusion of hydrogen into the semiconductor layer 130 and improve the reliability of the transistor 100. For example, the insulating layer 181 is preferably made of silicon nitride, silicon nitride oxide, aluminum oxide, or hafnium oxide.

[0245] The insulating layer 181 may include an insulating layer having a region containing oxygen that is desorbed by heating, which allows oxygen to be supplied from the insulating layer 181 to the semiconductor layer 130. For example, the insulating layer 181 may be made of silicon oxide or silicon oxynitride.

[0246] As will be described in detail later, in a manufacturing process of a semiconductor device according to one embodiment of the present invention, planarization treatment is performed on the insulating layer 183, with the insulating layer 181 as the end point. Therefore, using a material that reduces the thickness of the insulating layer 181 in the planarization treatment with the insulating layer 181 as the end point is preferable because the insulating layer 183 can be thinned and, for example, the semiconductor layer 130 can be prevented from being subjected to planarization treatment. Furthermore, in a manufacturing process of a semiconductor device according to one embodiment of the present invention, the insulating layer 181A is processed using the insulating layer 183 as a mask to form the insulating layer 181. Therefore, using a material that has a high etching selectivity with respect to the insulating layer 181 for the insulating layer 183 is preferable because processing of the insulating layer 183 during processing of the insulating layer 181A can be suppressed. For example, when silicon nitride is used for the insulating layer 181, silicon oxide is preferably used for the insulating layer 183. Note that the insulating layer 183 may be formed using, for example, silicon oxynitride, aluminum oxide, hafnium oxide, silicon nitride oxide, or silicon nitride.

[0247] The insulating layer 181A can be made of the same material as the insulating layer 181. The insulating layer 183A can be made of the same material as the insulating layer 183.

[0248] [Conductive Layer] For the conductive layers (conductive layer 120, conductive layer 140, conductive layer 155, conductive layer 220, conductive layer 240, conductive layer 320, conductive layer 340, conductive layer 355, conductive layer 365, etc.) included in the semiconductor device, it is preferable to use a metal element selected from aluminum, chromium, copper, silver, gold, platinum, zinc, tantalum, nickel, titanium, iron, cobalt, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum, etc., or an alloy containing any of the above metal elements as a component, or an alloy combining any of the above metal elements, etc. As the alloy containing any of the above metal elements as a component, a nitride of the alloy or an oxide of the alloy may be used. For example, it is preferable to use tantalum nitride, titanium nitride, tungsten, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, oxides containing lanthanum and nickel, etc. Furthermore, semiconductors with high electrical conductivity, typified by polycrystalline silicon containing impurity elements such as phosphorus, or silicides such as nickel silicide may also be used.

[0249] Nitrogen-containing conductive materials, such as nitrides containing tantalum, nitrides containing titanium, nitrides containing molybdenum, nitrides containing tungsten, nitrides containing ruthenium, nitrides containing tantalum and aluminum, or nitrides containing titanium and aluminum; oxygen-containing conductive materials, such as ruthenium oxide, oxides containing strontium and ruthenium, or oxides containing lanthanum and nickel; and materials containing metal elements, such as titanium, tantalum, or ruthenium, are preferred because they are conductive materials that are resistant to oxidation, have a function of suppressing oxygen diffusion, or maintain conductivity even after absorbing oxygen. Examples of oxygen-containing conductive materials include indium oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide (also referred to as ITO), indium tin oxide containing titanium oxide, indium tin oxide with added silicon (also referred to as ITSO), indium zinc oxide (also referred to as IZO (registered trademark)), and indium zinc oxide containing tungsten oxide. In this specification and the like, a conductive film formed using a conductive material containing oxygen may be referred to as an oxide conductive film.

[0250] Conductive materials containing tungsten, copper, or aluminum as a main component are preferred because they have high conductivity.

[0251] Furthermore, a plurality of conductive layers formed from the above materials may be stacked. For example, a stacked structure may be formed by combining the above-described material containing a metal element and a conductive material containing oxygen. A stacked structure may be formed by combining the above-described material containing a metal element and a conductive material containing nitrogen. A stacked structure may be formed by combining the above-described material containing a metal element, a conductive material containing oxygen, and a conductive material containing nitrogen.

[0252] When a metal oxide is used for the channel formation region of a transistor, the conductive layer that functions as a gate electrode preferably has a stacked structure that combines a material containing the metal element and a conductive material containing oxygen. In this case, the conductive material containing oxygen is preferably provided on the channel formation region side. By providing the conductive material containing oxygen on the channel formation region side, oxygen desorbed from the conductive material is easily supplied to the channel formation region.

[0253] The conductive layer 120 and the conductive layer 140 are conductive layers in contact with the semiconductor layer 130, and therefore, it is preferable to use a conductive material that is resistant to oxidation, a conductive material that maintains low electrical resistance even when oxidized, a metal oxide having conductivity (also referred to as an oxide conductor), or a conductive material that has a function of suppressing oxygen diffusion, for each of them. Examples of the conductive material include a conductive material containing nitrogen and a conductive material containing oxygen. This can suppress a decrease in the conductivity of the conductive layer 120 and the conductive layer 140.

[0254] By using a conductive material containing oxygen for the conductive layer 120 or the conductive layer 140, the conductive layer 120 or the conductive layer 140 can maintain its conductivity even if it absorbs oxygen. Furthermore, even when an insulating layer containing oxygen, such as hafnium oxide, is used as the insulating layer 110, the conductive layer 120 is preferably able to maintain its conductivity. For example, ITO, ITSO, IZO (registered trademark), or the like is preferably used for each of the conductive layer 120 and the conductive layer 140. Here, the conductive layer 220 and the conductive layer 320 can be made of a material that can be used for the conductive layer 120. Furthermore, the conductive layer 240 and the conductive layer 340 can be made of a material that can be used for the conductive layer 140.

[0255] 4A shows an example in which the conductive layer 120 has a three-layer structure including a conductive layer 120a1, a conductive layer 120a2 on the conductive layer 120a1, and a conductive layer 120b on the conductive layer 120a2. In this case, for example, it is preferable to use a conductive material that is resistant to oxidation or a conductive material that has a function of suppressing oxygen diffusion as the conductive layer 120a1, a highly conductive material as the conductive layer 120a2, and a conductive material containing oxygen (more preferably, an oxide conductor) as the conductive layer 120b. Specifically, for example, it is preferable to use titanium nitride as the conductive layer 120a1, tungsten as the conductive layer 120a2, and an oxide conductor (e.g., ITO, ITSO, or IZO (registered trademark)) as the conductive layer 120b. In this case, titanium nitride is in contact with the insulating layer 110, and the oxide conductor is in contact with the semiconductor layer 130. Furthermore, the oxide conductor is used in the layer closest to the channel formation region of the semiconductor layer 130. Compared to tungsten, an oxide conductor has lower contact resistance with the semiconductor layer 130, and therefore the current path between the source and drain can be shortened, thereby increasing the on-state current of the transistor. With such a structure, the conductive layer 120 can maintain conductivity even when in contact with the semiconductor layer 130. Furthermore, when an oxide insulating layer is used for the insulating layer 110, the insulating layer 110 can prevent the conductive layer 120 from being excessively oxidized. Furthermore, by using a metal material (here, tungsten) having higher conductivity than an oxide conductor and titanium nitride as the conductive layer 120a2, the conductivity of the conductive layer 120 can be increased.

[0256] 4A shows an example in which the conductive layer 220 has a three-layer structure including a conductive layer 220a1, a conductive layer 220a2 on the conductive layer 220a1, and a conductive layer 220b on the conductive layer 220a2. FIG. 4B shows an example in which the conductive layer 320 has a three-layer structure including a conductive layer 320a1, a conductive layer 320a2 on the conductive layer 320a1, and a conductive layer 320b on the conductive layer 320a2. The conductive layer 220a1 and the conductive layer 320a1 can be made of the same material as that used for the conductive layer 120a1. The conductive layer 220a2 and the conductive layer 320a2 can be made of the same material as that used for the conductive layer 120a2. The conductive layer 220b and the conductive layer 320b can be made of the same material as that used for the conductive layer 120b. The conductive layer 220 may have a single-layer structure. In this case, the conductive layer 220 can be made of the same material as can be used for the conductive layer 120b.

[0257] 4A shows an example in which the conductive layer 140 has a two-layer structure including a conductive layer 140a and a conductive layer 140b on the conductive layer 140a. In this case, for example, it is preferable to use a conductive material containing oxygen for the conductive layer 140b and a material having higher conductivity than the conductive layer 140b for the conductive layer 140a. Specifically, for example, it is preferable to use an oxide conductor (e.g., ITO, ITSO, or IZO (registered trademark)) for the conductive layer 140b and tungsten for the conductive layer 140a. Furthermore, ruthenium, titanium nitride, tantalum nitride, or the like may be used for the conductive layer 140a.

[0258] Of the conductive layer 140, the layer that is mainly in contact with the semiconductor layer 130 is the conductive layer 140b. By using an oxide conductor for the conductive layer 140b, the contact resistance with the semiconductor layer 130 can be reduced, which is preferable. Furthermore, by using a material having higher conductivity than an oxide conductor for the layer that constitutes the conductive layer 140, the conductivity of the conductive layer 140 can be increased, which is preferable.

[0259] Note that the conductive layer 140a may be made of a conductive material containing oxygen, and the conductive layer 140b may be made of a material having higher conductivity than the conductive layer 140a. In this case, an oxide conductor is used for the layer of the conductive layer 140 that is closest to the channel formation region of the semiconductor layer 130. Therefore, the current path between the source and the drain can be shortened, and the on-state current of the transistor can be increased.

[0260] The conductive layer 240a and the conductive layer 340a can each be formed using the same material as that used for the conductive layer 140a. The conductive layer 240b and the conductive layer 340b can each be formed using the same material as that used for the conductive layer 140b.

[0261] The conductive layer 155, the conductive layer 355, and the conductive layer 365 are preferably formed using a highly conductive material such as tungsten. Furthermore, the conductive layer 155, the conductive layer 355, and the conductive layer 365 are preferably formed using a conductive material that is not easily oxidized or a conductive material that has a function of suppressing oxygen diffusion. As described above, examples of the conductive material include a conductive material containing nitrogen (e.g., titanium nitride or tantalum nitride) and a conductive material containing oxygen (e.g., ruthenium oxide). This can suppress a decrease in the conductivity of the conductive layer 155, the conductive layer 355, and the conductive layer 365.

[0262] The conductive layer 365 is preferably made of a conductive material containing oxygen and a metal element contained in the metal oxide in which the channel is formed. Alternatively, the conductive material containing the above-mentioned metal element and nitrogen (e.g., titanium nitride, tantalum nitride, etc.) may be used. Alternatively, one or more of indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, and indium tin oxide to which silicon is added may be used. Alternatively, indium gallium zinc oxide containing nitrogen may be used. Using such a material may allow hydrogen contained in the metal oxide in which the channel is formed to be captured. Alternatively, hydrogen introduced from an outer insulating layer or the like may be captured.

[0263] 4B shows an example in which the conductive layer 365 has a two-layer structure including a conductive layer 365a and a conductive layer 365b on the conductive layer 365a. In this case, for example, it is preferable to use titanium nitride for the conductive layer 365a and tungsten for the conductive layer 365b. Alternatively, it is preferable to use tantalum nitride for the conductive layer 365a and copper for the conductive layer 365b. With such a structure, the conductivity of the conductive layer 365 can be increased.

[0264] The conductive layer 365 may also have a stacked structure of three or more layers, for example, a three-layer structure of tantalum nitride, titanium nitride on the tantalum nitride, and tungsten on the titanium nitride.

[0265] The conductive layer 365 preferably has high conductivity because it functions as a gate wiring. Tungsten is preferably used for the conductive layer 365. For example, a two-layer structure of titanium nitride and tungsten may be used.

[0266] The conductive layer 155 and the conductive layer 355 are preferably made of, for example, tungsten or tantalum nitride.

[0267] [Substrate] Substrates on which transistors are formed can include, for example, insulating substrates, semiconductor substrates, or conductive substrates. Examples of insulating substrates include glass substrates, quartz substrates, sapphire substrates, stabilized zirconia substrates (e.g., yttria-stabilized zirconia substrates), and resin substrates. Examples of semiconductor substrates include semiconductor substrates made of silicon or germanium, or compound semiconductor substrates made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, and gallium oxide. Examples of semiconductor substrates include those having an insulating region within the semiconductor substrate, such as an SOI (Silicon-On-Insulator) substrate. Examples of conductive substrates include graphite substrates, metal substrates, alloy substrates, and conductive resin substrates. Examples of substrates include substrates having a metal nitride, substrates having a metal oxide, and the like. Examples of substrates include a substrate having a conductor or semiconductor provided on an insulating substrate, a substrate having a conductor or insulator provided on a semiconductor substrate, and a substrate having a semiconductor or insulator provided on a conductive substrate. Alternatively, a substrate provided with elements may be used, such as a capacitor element, a resistor element, a switch element, a light-emitting element, and a memory element.

[0268] <Structure Example 2 of Semiconductor Device> The structure of a semiconductor device of another embodiment of the present invention will be described below. Specifically, another structure example of the memory cell 10 included in the semiconductor device of one embodiment of the present invention and the transistor included in the memory cell 10 will be described.

[0269] [Memory Cell 10A] FIG. 5A is a plan view showing a configuration example of a transistor 100A. FIG. 5B is a plan view showing a configuration example of a transistor 200A. FIG. 5C is a cross-sectional view taken along dashed dotted lines A1-A2 in FIGS. 5A and 5B. FIG. 5D is a cross-sectional view taken along dashed dotted lines B1-B2 in FIGS. 5A and 5B. FIGS. 5C and 5D show a configuration example of a memory cell 10A. Here, the transistor 100, the transistor 200, and the transistor 300 included in the memory cell 10A are referred to as the transistor 100A, the transistor 200A, and the transistor 300A, respectively. Note that FIG. 1D can be referred to for the configuration of the transistor 300A in a plan view.

[0270] In the memory cell 10A, the transistor 100A and the transistor 200A do not include the conductive layer 220. In this case, the semiconductor layer 230 is provided to cover the top surface of the insulating layer 183 and the side surface of the insulating layer 181 located outside the opening 190. The semiconductor layer 230 is provided to be in contact with a region of the semiconductor layer 130 that overlaps with the conductive layer 140. As described above, even if the transistor 100A and the transistor 200A do not include the conductive layer 220, the other of the source and drain of the transistor 100A can be electrically connected to one of the source and drain of the transistor 100B.

[0271] By employing a structure in which the conductive layer 220 is not provided in the memory cell, the number of manufacturing steps of the semiconductor device can be reduced compared to a structure in which the conductive layer 220 is provided in the memory cell. Therefore, the manufacturing cost of the semiconductor device can be reduced, and a low-cost semiconductor device can be provided. On the other hand, by employing a structure in which the conductive layer 220 is provided in the memory cell, the width of the opening 290 can be made smaller than a structure in which the conductive layer 220 is not provided in the memory cell.

[0272] 6A and 6B are cross-sectional views showing a configuration example of the memory cell 10B. 6A and 6B show an example in which the opening 290 shown in FIGS. 5C and 5D does not overlap with the insulating layer 183. Here, the transistor 100, the transistor 200, and the transistor 300 included in the memory cell 10B are referred to as the transistor 100B, the transistor 200B, and the transistor 300B, respectively.

[0273] In memory cell 10B, when opening 290 has a circular or rectangular shape in plan view, at least the center of opening 290 in plan view does not overlap insulating layer 183. Note that part of opening 290 may overlap insulating layer 183. Even in this case, the entire upper surface of insulating layer 183 does not overlap opening 290.

[0274] 6A and 6B show an example in which opening 390 overlaps with opening 290 but does not overlap with opening 190, but opening 390 may overlap with opening 190 or may not overlap with opening 290. For example, when opening 390 has a circular or rectangular shape in a plan view, the center of opening 390 in a plan view may overlap with opening 190 or with opening 290, or may not overlap with either opening 190 or opening 290. The center of opening 390 in a plan view may be located, for example, between opening 190 and opening 290 in a plan view. Furthermore, opening 290 and opening 390 may be located at positions facing each other with insulating layer 183 sandwiched therebetween in a plan view.

[0275] In the memory cell 10B, the contact area between the semiconductor layer 130 and the semiconductor layer 230 can be made larger than in the memory cell 10A. This reduces the contact resistance between the semiconductor layer 130 and the semiconductor layer 230. On the other hand, the occupied area of ​​the memory cell 10A can be made smaller than that of the memory cell 10B.

[0276] 7A is a circuit diagram showing a configuration example of the memory cell 10 C. Here, the transistor 100, the transistor 200, and the transistor 300 included in the memory cell 10 C are referred to as a transistor 100 C, a transistor 200 C, and a transistor 300 C, respectively.

[0277] In the memory cell 10C, the transistor 200C and the transistor 300C are dual-gate transistors. The first gate of the transistor 200C is electrically connected to one of the source and drain of the transistor 300C. The second gate of the transistor 200C is electrically connected to the wiring BGL1. The first gate of the transistor 300C is electrically connected to the wiring WWL. The second gate of the transistor 300C is electrically connected to the wiring BGL2. Hereinafter, the first gate of the transistor 200C will be simply referred to as the gate of the transistor 200C, and the second gate of the transistor 200C will be simply referred to as the backgate of the transistor 200C. Furthermore, the first gate of the transistor 300C will be simply referred to as the backgate of the transistor 300C, and the second gate of the transistor 300C will be simply referred to as the backgate of the transistor 300C.

[0278] The threshold voltage of the transistor 200C can be controlled by controlling the potential of the wiring BGL1 electrically connected to the back gate of the transistor 200C. For example, the on-state current of the transistor 200C can be increased by supplying a potential higher than the source potential or a positive potential to the wiring BGL1. This enables data stored in the memory cell 10C to be read at high speed. Note that the wiring BG1 may be supplied with the same potential as that of the gate of the transistor 200C, for example. In this case, the gate of the transistor 200C and the back gate of the transistor 200C can be electrically connected.

[0279] The threshold voltage of the transistor 300C can be controlled by controlling the potential of the wiring BGL2 electrically connected to the back gate of the transistor 300C. For example, by supplying a potential lower than the source potential or a potential lower than 0 V (preferably a negative potential) to the wiring BGL2, the threshold voltage of the transistor 300C can be shifted in the positive direction, resulting in a normally-off transistor. This allows the gate potential of the transistor 200C to be held for a long period of time. Therefore, data written to the memory cell 10C can be held for a long period of time.

[0280] 7B is a plan view showing a configuration example of a transistor 200C. FIG. 7C is a cross-sectional view taken along dashed dotted line A1-A2 in FIG. 7B. FIG. 7D is a cross-sectional view taken along dashed dotted line B1-B2 in FIG. 7B. FIGS. 7C and 7D show a configuration example of a memory cell 10C. Here, the configurations of the transistor 100 and the transistor 300 in plan view can be seen in FIGS. 1B and 1D, respectively.

[0281] The transistor 200C includes a conductive layer 255 that functions as a back gate electrode and an insulating layer 235 that functions as a back gate insulating layer. In the memory cell 10C, at least a part of the conductive layer 255 functions as the wiring BGL1 shown in FIG. 7A. At least a part of the conductive layer 355 functions as the wiring BGL2 shown in FIG. 7A.

[0282] The conductive layer 255 is located over the insulating layer 280a. The insulating layer 280b is located over the conductive layer 255 and the insulating layer 280a. The insulating layer 280b is provided to cover the top surface of the conductive layer 255, the side surfaces of the conductive layer 255, and the top surface of the insulating layer 280a. The conductive layer 255 has an opening 290.

[0283] 7C and 7D show an example in which the conductive layer 220b has a first recess and a second recess that is located outside the first recess and has a shallower depth. When forming the opening 290, the second recess is provided in the conductive layer 220b, and then, when processing the insulating layer 235, the first recess is provided in the conductive layer 220b. Therefore, in FIGS. 7C and 7D, the side surface of the first recess in the conductive layer 220b is aligned with the surface of the insulating layer 235 facing the semiconductor layer 230. Furthermore, the side surface of the second recess in the conductive layer 220b is aligned with, for example, the side surface of the insulating layer 280a facing the opening 290.

[0284] The insulating layer 235 is disposed so that at least a portion thereof is located inside the opening 290. The insulating layer 235 has at least a region located between the semiconductor layer 230 and the conductive layer 255. The insulating layer 235 contacts the side surface of the conductive layer 255 inside the opening 290.

[0285] 7C and 7D , the insulating layer 235 contacts the bottom and side surfaces of the recess (specifically, the second recess) of the conductive layer 220b, and also contacts the side surfaces of the insulating layer 280a, the conductive layer 255, the insulating layer 280b, the conductive layer 240a, and the conductive layer 240b inside the opening 290. The semiconductor layer 230 contacts the bottom and side surfaces of the recess (specifically, the first recess) of the conductive layer 220b, the insulating layer 235, and the top surface of the conductive layer 240b. The conductive layer 220b has a recess, which increases the area in which the semiconductor layer 230 contacts the conductive layer 220b. Therefore, the contact resistance between the semiconductor layer 230 and the conductive layer 220b can be reduced.

[0286] The insulating layer 235 is provided along at least a part of the sidewall of the opening 290. The semiconductor layer 230 has a region inside the opening 290 that faces the conductive layer 255 with the insulating layer 235 sandwiched therebetween. At least a part of this region of the semiconductor layer 230 is in contact with the insulating layer 235. The conductive layer 255 is provided to surround the semiconductor layer 230 with the insulating layer 235 sandwiched therebetween.

[0287] The conductive layer 255 is provided to face the conductive layer 320 functioning as the gate electrode of the transistor 200C, with the insulating layer 235, the semiconductor layer 230, and the insulating layer 250 sandwiched therebetween. Thus, in the memory cell 10C, the semiconductor layer 230 has a region that faces the conductive layer 320 with the insulating layer 250 sandwiched therebetween and also faces the conductive layer 255 with the insulating layer 235 sandwiched therebetween.

[0288] The conductive layer 255 is provided to surround at least a part of the channel formation region of the transistor 200C with the insulating layer 235 sandwiched therebetween. As described above, the conductive layer 255 functions as a backgate electrode of the transistor 200C. Therefore, the threshold voltage of the transistor 200C can be controlled by controlling the potential of the conductive layer 255. Supplying the conductive layer 255 with, for example, a potential higher than the source potential or a positive potential can increase the on-state current of the transistor 200C. This enables high-speed reading of data stored in the memory cell 10C. Note that the conductive layer 255 may be supplied with, for example, the same potential as that of the conductive layer 320. In this case, the conductive layer 255 and the conductive layer 320 can be electrically connected. For example, the conductive layer 255 and the conductive layer 320 can be electrically connected by providing an opening reaching the conductive layer 255 in the insulating layer 280b and the insulating layer 250, filling the opening with a conductive layer functioning as a plug, and providing the conductive layer 320 so as to be in contact with the conductive layer.

[0289] The conductive layer 255 can be formed using a material that can be used for the conductive layer 355. The insulating layer 235 can be formed using a material that can be used for the insulating layer 335. The insulating layer 235 preferably includes an insulating layer having a region containing oxygen that is desorbed by heating, for example. The insulating layer 235 preferably includes a barrier insulating layer against hydrogen, for example. Note that the insulating layer 235 can also be referred to as a sidewall, a sidewall insulating layer, a sidewall protective layer, or the like, similar to the insulating layer 335.

[0290] 7B to 7D show an example in which the conductive layer 255 extends in a direction parallel to the conductive layer 355, but one embodiment of the present invention is not limited thereto, and the conductive layer 255 may extend in a direction different from that of the conductive layer 355. For example, the conductive layer 355 may extend in the X direction, and the conductive layer 255 may extend in the Y direction.

[0291] [Memory Cell 10D] Figures 8A and 8B are cross-sectional views showing an example configuration of memory cell 10D. In memory cell 10D, insulating layer 180a shown in Figures 2A and 2B has a three-layer stacked structure of insulating layer 180a1, insulating layer 180a2 on insulating layer 180a1, and insulating layer 180a3 on insulating layer 180a2. In addition, insulating layer 180b has a three-layer stacked structure of insulating layer 180b1, insulating layer 180b2 on insulating layer 180b1, and insulating layer 180b3 on insulating layer 180b2. In addition, insulating layer 280 has a three-layer stacked structure of insulating layer 280_1, insulating layer 280_2 on insulating layer 280_1, and insulating layer 280_3 on insulating layer 280_2. Insulating layer 380a has a three-layer laminated structure of insulating layer 380a1, insulating layer 380a2 on insulating layer 380a1, and insulating layer 380a3 on insulating layer 380a2. Insulating layer 380b has a three-layer laminated structure of insulating layer 380b1, insulating layer 380b2 on insulating layer 380b1, and insulating layer 380b3 on insulating layer 380b2.

[0292] The transistor 100, the transistor 200, and the transistor 300 included in the memory cell 10D are referred to as the transistor 100D, the transistor 200D, and the transistor 300D, respectively. Planar structures of the transistor 100D, the transistor 200D, and the transistor 300D can be seen in FIGS. 1B, 1C, and 1D, respectively.

[0293] The insulating layer 180a2 and the insulating layer 180b2 are closer to the channel formation region of the semiconductor layer 130 than the insulating layer 180a1 and the insulating layer 180b3. By using an insulating layer containing oxygen for the insulating layer 180a2 and the insulating layer 180b2, oxygen can be supplied to the semiconductor layer 130.

[0294] The insulating layer 180a2 preferably has a region with a higher oxygen content than at least one of the insulating layer 180a1 and the insulating layer 180a3. The insulating layer 180b2 preferably has a region with a higher oxygen content than at least one of the insulating layer 180b1 and the insulating layer 180b3. Increasing the oxygen content of the insulating layer 180a2 and the insulating layer 180b2 makes it easier to form an i-type region in the semiconductor layer 130.

[0295] It is more preferable to use a film that releases oxygen when heated for the insulating layer 180a2 and the insulating layer 180b2. The insulating layer 180a2 and the insulating layer 180b2 release oxygen due to heat applied during the manufacturing process of the semiconductor device, and oxygen can be supplied to the semiconductor layer 130. By supplying oxygen from the insulating layer 180a2 and the insulating layer 180b2 to the semiconductor layer 130, particularly to the channel formation region of the semiconductor layer 130, oxygen vacancies and V in the semiconductor layer 130 can be reduced. Ｏ H can be reduced, and a highly reliable transistor can be obtained that exhibits favorable electrical characteristics.

[0296] To improve the electrical characteristics and reliability of an OS transistor, it is important to sufficiently reduce the hydrogen concentration in the oxide semiconductor and then optimize the amount of oxygen supplied to the oxide semiconductor.

[0297] In particular, when the channel length of a transistor is short, oxygen vacancies in the channel formation region and V Ｏ The influence of H on the electrical characteristics and reliability is particularly large. Therefore, by sufficiently reducing the hydrogen concentration in the semiconductor layer 130 and then optimizing the amount of oxygen supplied to the semiconductor layer 130, a transistor with a short channel length that has good electrical characteristics and high reliability can be realized.

[0298] The insulating layer 180a2 and the insulating layer 180b2 are preferably formed by a deposition method such as a sputtering method or a plasma-enhanced CVD (PECVD) method. In particular, when a sputtering method is used, hydrogen is not used as a deposition gas, and therefore a film with an extremely low hydrogen content can be obtained. Therefore, the supply of hydrogen to the semiconductor layer 130 can be suppressed, and the electrical characteristics of the transistor can be stabilized.

[0299] To increase the amount of oxygen supplied to the semiconductor layer 130, for example, heat treatment in an oxygen-containing atmosphere or plasma treatment in an oxygen-containing atmosphere may be performed after the insulating layer 180a2 or the insulating layer 180b2 is formed. Alternatively, oxygen may be supplied by forming an oxide film on the top surface of the insulating layer 180a2 or the insulating layer 180b2 by a sputtering method in an oxygen atmosphere. The oxide film may then be removed. By performing such treatment, oxygen can be supplied to the insulating layer 180a2 or the insulating layer 180b2, thereby increasing the amount of oxygen supplied to the semiconductor layer 130.

[0300] An insulating layer suitable for the insulating layer 180a2 and the insulating layer 180b2 is preferably used as the insulating layer 135. This allows oxygen to be supplied to the semiconductor layer 130 more efficiently.

[0301] Furthermore, it is preferable to use a material with a low dielectric constant for the insulating layer 180a2 and the insulating layer 180b2, which can reduce parasitic capacitance between wirings. For example, silicon oxide or silicon oxynitride can be used for the insulating layer 180a2 and the insulating layer 180b2.

[0302] It is preferable to use a barrier insulating layer against oxygen for each of the insulating layers 180a1, 180a3, 180b1, and 180b3, which can suppress oxidation of the conductive layers 120, 140, and 155 and prevent the conductive layers from becoming high in resistance.

[0303] Furthermore, the insulating layer 180a1, the insulating layer 180a3, the insulating layer 180b1, and the insulating layer 180b3 may each be a barrier insulating layer against hydrogen. Such a configuration is preferable because it can suppress the diffusion of impurities such as hydrogen into the semiconductor layer 130.

[0304] It is preferable to use a silicon nitride film or an aluminum oxide film as the insulating layer 180a1, the insulating layer 180a3, the insulating layer 180b1, and the insulating layer 180b3 that satisfy the above conditions. It is also preferable to use a silicon oxide film as the insulating layer 180a2 and the insulating layer 180b2.

[0305] The insulating layers 280_1, 280_2, and 280_3 have the same structure as the insulating layers 180a1, 180a2, and 180a3, respectively, and can be deposited by the same method. The insulating layers 280_1, 280_2, and 280_3 have the same structure as the insulating layers 180b1, 180b2, and 180b3, respectively, and can be deposited by the same method. The insulating layers 380a1, 380a2, and 380a3 have the same structure as the insulating layers 180a1, 180a2, and 180a3, respectively, and can be deposited by the same method. The insulating layer 380b1, the insulating layer 380b2, and the insulating layer 380b3 have the same structure as the insulating layer 180b1, the insulating layer 180b2, and the insulating layer 180b3, respectively, and can be formed by the same method.

[0306] 9A and 9B are cross-sectional views showing a configuration example of a memory cell 10E. 9A and 9B show an example in which an insulating layer 235 is disposed inside the opening 290 shown in FIGS. 8A and 8B, respectively. Here, the transistors 100, 200, and 300 included in the memory cell 10E are referred to as transistors 100E, 200E, and 300E, respectively.

[0307] The insulating layer 235 has a region located between the semiconductor layer 230 and the insulating layer 280. The insulating layer 235 is in contact with the semiconductor layer 230 inside the opening 290. Specifically, the insulating layer 235 is in contact with at least a part of a channel formation region of the semiconductor layer 230. Note that although the transistor 200E shown in FIGS. 9A and 9B does not include the conductive layer 255, the transistor 200E may include the conductive layer 255.

[0308] By providing the insulating layer 235 between the insulating layer 280_1, the insulating layer 280_2, and the insulating layer 280_3 and the semiconductor layer 230, for example, the entire outer surface (opposite the conductive layer 320) of the channel formation region of the semiconductor layer 230 can be in contact with the same insulating layer. This allows the characteristics of the channel formation region of the semiconductor layer 230 to be uniform regardless of, for example, height, specifically, height from the reference plane. For example, the insulating layer 235 can supply oxygen uniformly to the entire channel formation region of the semiconductor layer 230 by forming a region containing oxygen desorbed by heat. Furthermore, if the insulating layer 235 has a barrier insulating layer against hydrogen, diffusion of hydrogen to the entire channel formation region of the semiconductor layer 230 can be suppressed. As described above, a highly reliable semiconductor device can be provided.

[0309] 8A to 9B show an example in which the insulating layer 180a, the insulating layer 180b, the insulating layer 280, the insulating layer 380a, and the insulating layer 380b each have a three-layer stacked structure, but the insulating layer 180a, the insulating layer 180b, the insulating layer 280, the insulating layer 380a, and the insulating layer 380b may each have a two-layer stacked structure or a four- or more-layer stacked structure. For example, the insulating layer 180a, the insulating layer 180b, the insulating layer 380a, and the insulating layer 380b may each have a two-layer stacked structure, and the insulating layer 280 may have a three-layer stacked structure. In this case, for example, the insulating layer 180a3, the insulating layer 180b1, the insulating layer 380a3, and the insulating layer 380b1 may not be provided.

[0310] [Memory Cell 10F] Figures 10A and 10B are cross-sectional views showing a configuration example of a memory cell 10F. In the memory cell 10F, only one recess is provided in the conductive layer 120b and the conductive layer 320b shown in Figures 2A and 2B. Here, the transistor 100, the transistor 200, and the transistor 300 included in the memory cell 10F are referred to as transistor 100F, transistor 200F, and transistor 300F, respectively. Note that Figures 1B, 1C, and 1D can be referred to for the configurations of the transistor 100F, the transistor 200F, and the transistor 300F in a plan view, respectively.

[0311] A recess may be formed in the conductive layer 120b in one or both of the steps of forming the opening 190 and forming the insulating layer 135. For example, in the transistor 100 shown in FIGS. 2A and 2B, a recess is formed in the conductive layer 120b in both steps. On the other hand, in the transistor 100F, a recess is not formed in the conductive layer 120b in the step of forming the opening 190, but is formed in the step of forming the insulating layer 135. Furthermore, a recess may be formed in the conductive layer 320b in one or both of the steps of forming the opening 390 and forming the insulating layer 335. For example, in the transistor 300 shown in FIGS. 2A and 2B, a recess is formed in the conductive layer 320b in both steps. On the other hand, in the transistor 300F, a recess is not formed in the conductive layer 320b in the step of forming the opening 390, but is formed in the step of forming the insulating layer 335.

[0312] In the transistor 100F, the insulating layer 135 is in contact with the side surfaces of the insulating layer 180a, the conductive layer 155, the insulating layer 180b, the conductive layer 140a, the conductive layer 140b, and the top surface of the conductive layer 120b inside the opening 190. The semiconductor layer 130 is in contact with the bottom and side surfaces of the recess of the conductive layer 120b. In the transistor 300F, the insulating layer 335 is in contact with the side surfaces of the insulating layer 380a, the conductive layer 355, the insulating layer 380b, the conductive layer 340a, the conductive layer 340b, and the top surface of the conductive layer 320b inside the opening 390. The semiconductor layer 330 is in contact with the bottom and side surfaces of the recess of the conductive layer 320b.

[0313] When a recess is formed in the conductive layer 320b in at least one of the steps of forming the opening 390 and forming the insulating layer 335, the height of the bottom surface of the conductive layer 365a inside the opening 390 can be lowered. This makes it easier for a gate electric field to be applied to the channel formation region of the semiconductor layer 330. Therefore, the transistor 300F can have favorable electrical characteristics.

[0314] When a recess is formed in the conductive layer 120b in the step of forming the insulating layer 135, the area in which the semiconductor layer 130 contacts the conductive layer 120b can be increased, as described above. Therefore, the contact resistance between the semiconductor layer 130 and the conductive layer 120b can be reduced. Similarly, when a recess is formed in the conductive layer 320b in the step of forming the insulating layer 335, the area in which the semiconductor layer 330 contacts the conductive layer 320b can be increased, as described above. Therefore, the contact resistance between the semiconductor layer 330 and the conductive layer 320b can be reduced.

[0315] [Memory Cell 10G] Figures 11A and 11B are cross-sectional views showing a configuration example of a memory cell 10G. In the memory cell 10G, the insulating layer 135 shown in Figures 2A and 2B does not cover the side surfaces of the conductive layer 140b, and the insulating layer 335 does not cover the side surfaces of the conductive layer 340b. Here, the transistors 100, 200, and 300 included in the memory cell 10G are referred to as transistors 100G, 200G, and 300G, respectively. Note that Figures 1B, 1C, and 1D can be referred to for the planar structures of the transistors 100G, 200G, and 300G, respectively.

[0316] 11A and 11B , the insulating layer 135 contacts the bottom and side surfaces of the recess of the conductive layer 120, and also contacts the side surfaces of the insulating layer 180a, the conductive layer 155, and the insulating layer 180b inside the opening 190. The insulating layer 135 contacts the side surfaces of the conductive layer 140a but not the side surfaces of the conductive layer 140b. While FIGS. 11A and 11B show an example in which the insulating layer 135 contacts the entire side surface of the conductive layer 140a facing the opening 190, a portion of the side surface of the conductive layer 140a facing the opening 190 may not be in contact with the insulating layer 135. While FIGS. 11A and 11B show an example in which the insulating layer 335 contacts the entire side surface of the conductive layer 340a facing the opening 390, a portion of the side surface of the conductive layer 340a facing the opening 390 may not be in contact with the insulating layer 335.

[0317] The insulating layer 135 functions as a gate insulating layer of the transistor 100G. Therefore, the insulating layer 135 covers at least the entire side surface of the conductive layer 155 on the opening 190 side, electrically insulating the conductive layer 155 from the semiconductor layer 130. Inside the opening 190, the insulating layer 135 may be in contact with one or more of the side surfaces of the insulating layer 180a, the side surfaces of the insulating layer 180b, the side surfaces of the conductive layer 140a, and the side surfaces of the conductive layer 140b, or may cover part or all of each of the side surfaces. Similarly, inside the opening 390, the insulating layer 335 may be in contact with one or more of the side surfaces of the insulating layer 380a, the side surfaces of the insulating layer 380b, the side surfaces of the conductive layer 340a, and the side surfaces of the conductive layer 340b, or may cover part or all of each of the side surfaces.

[0318] When at least a portion of the side surface of the conductive layer 140b is not covered with the insulating layer 135, that portion can be in contact with the semiconductor layer 130. This increases the contact area between the semiconductor layer 130 and the conductive layer 140. This reduces the contact resistance between the semiconductor layer 130 and the conductive layer 140, which is preferable. Similarly, when the insulating layer 135 does not cover the side surface of the conductive layer 140b and does not cover at least a portion of the side surface of the conductive layer 140a, that portion is in contact with the semiconductor layer 130. This increases the contact area between the semiconductor layer 130 and the conductive layer 140. This reduces the contact resistance between the semiconductor layer 130 and the conductive layer 140, which is preferable.

[0319] Similarly, when at least a portion of the side surface of the conductive layer 340b is not covered with the insulating layer 335, or when the insulating layer 335 does not cover the side surface of the conductive layer 340b and does not cover at least a portion of the side surface of the conductive layer 340a, it is possible to increase the contact area between the semiconductor layer 330 and the conductive layer 340. This is preferable because it allows the contact resistance between the semiconductor layer 330 and the conductive layer 340 to be reduced.

[0320] The configuration of the insulating layer 335 shown in FIGS. 10A to 11B can also be applied to the insulating layer 235 shown in, for example, FIGS. 7C, 7D, 9A, and 9B.

[0321] 12A and 12B are cross-sectional views showing an example configuration of a memory cell 10H. In the memory cell 10H, an insulating layer 383 and an insulating layer 385 on the insulating layer 383 are provided between the insulating layer 350 and the conductive layer 365a shown in FIGS. 2A and 2B. Note that the width D2 of the opening 390 is shown in FIGS. 12A and 12B.

[0322] Here, the transistor 100, the transistor 200, and the transistor 300 included in the memory cell 10H are referred to as the transistor 100H, the transistor 200H, and the transistor 300H, respectively. Note that the planar structures of the transistor 100H, the transistor 200H, and the transistor 300H can be seen in FIGS. 1B, 1C, and 1D, respectively.

[0323] The insulating layer 383 and the insulating layer 385 function as interlayer films. The insulating layer 383 has an opening 370 that reaches the insulating layer 350 and overlaps with the opening 390. The conductive layer 365a is disposed so that at least a portion thereof is located inside the opening 370. Furthermore, the conductive layer 365b may also be disposed so that at least a portion thereof is located inside the opening 370. The conductive layer 365a is in contact with the insulating layer 350 inside the opening 370.

[0324] The conductive layer 365 a is provided to fill at least a part of the opening 390 and the opening 370 .

[0325] In the transistor of one embodiment of the present invention, at least one layer constituting the conductive layer 365 is provided inside the opening 390 and inside the opening 370. When the conductive layer 365 has a stacked-layer structure, it becomes more difficult to arrange all of the layers constituting the conductive layer 365 in the opening 390 and the opening 370 as the diameters of the opening 390 and the opening 370 become smaller with miniaturization of the transistor. In FIGS. 12A and 12B , an example is shown in which the conductive layer 365 has a two-layer structure, in which only the conductive layer 365a is provided inside the opening 390, and the conductive layers 365a and 365b are provided inside the opening 370. Note that depending on the diameter of the opening 390, the thickness of the conductive layer 365a, and the like, both the conductive layer 365a and the conductive layer 365b may be located inside the opening 390. Furthermore, depending on the diameter of the opening 370, the thickness of the conductive layer 365a, the thickness of the conductive layer 365b, and the like, only the conductive layer 365a may be located inside the opening 370.

[0326] The portions of the conductive layers 365a and 365b that do not overlap with the opening 390 are mainly located on the insulating layer 385. Therefore, the conductive layer 365 mainly overlaps with the conductive layer 340 via the insulating layers 383 and 385. This increases the physical distance between the conductive layers 365 and 340, and reduces the parasitic capacitance generated between the conductive layers 365 and 340. Note that the conductive layers 340 and 365 may have overlapping portions without the insulating layer 385 interposed therebetween.

[0327] 12A and 12B show an example in which the width of the opening 370 is narrower than the width D2 of the opening 390. The narrower the width of the opening 370, the narrower the region where the conductive layer 340 and the conductive layer 365 overlap without the insulating layer 385 therebetween can be made, and the parasitic capacitance generated between the conductive layer 340 and the conductive layer 365 can be reduced, which is preferable. For example, the width of the opening 370 is preferably the same as or smaller than the width of the opening 390.

[0328] Note that the width of the opening 370 may be larger than the width of the opening 390. Here, the magnitude relationship between the two widths in the semiconductor device of one embodiment of the present invention can be confirmed by a cross section parallel to the Z direction. For example, the width of the opening 370 is preferably smaller than the width of the short side of the conductive layer 365 (the maximum width of the conductive layers 365a and 365b in FIG. 12B ). Furthermore, for example, the maximum width of the conductive layer 365 is preferably equal to or smaller than the width of the short side of the conductive layer 355 (the maximum width of the conductive layer 355 in the Y direction in FIG. 12B ). This allows the area of ​​the overlapping portion between the conductive layer 340 and the conductive layer 365 without the insulating layer 385 interposed therebetween to be sufficiently smaller than the area of ​​the overlapping portion between the conductive layer 340 and the conductive layer 365 interposed therebetween, thereby reducing the parasitic capacitance generated between the conductive layer 340 and the conductive layer 365.

[0329] That is, the transistor 300H has a structure in which the parasitic capacitance generated between the other of the source electrode and the drain electrode and the gate wiring is reduced, thereby making it possible to provide a semiconductor device with high operating speed.

[0330] The shape of the opening 370 in a plan view can be the same as the shape in a plan view that can be applied to the opening 390. The shape of the opening 370 in a plan view can be, for example, a circle.

[0331] The width of the opening 370 may vary in the depth direction. In particular, the width of the opening 370 used here is the maximum width of the opening 370 provided in the insulating layer 383 in a cross-sectional view.

[0332] A barrier insulating layer against hydrogen is preferably used for the insulating layer 383. This can suppress diffusion of hydrogen from above the insulating layer 383 to the semiconductor layer 330. A silicon nitride film and a silicon nitride oxide film each have characteristics of releasing little impurities (for example, water and hydrogen) from themselves and being less permeable to oxygen and hydrogen, and therefore can be suitably used for the insulating layer 383.

[0333] It is particularly preferable to use silicon nitride formed by a sputtering method as the insulating layer 383. The sputtering method does not require the use of molecules containing hydrogen in the deposition gas, and therefore can reduce the hydrogen concentration in the insulating layer 383. Furthermore, by forming the insulating layer 383 by a sputtering method, silicon nitride with high density can be formed.

[0334] Alternatively, an insulating layer having a function of capturing or fixing hydrogen may be used as the insulating layer 383. With such a structure, hydrogen can be prevented from diffusing from above the insulating layer 383 to the semiconductor layer 330, and hydrogen contained in the semiconductor layer 330 can be captured or fixed. Therefore, the hydrogen concentration in the semiconductor layer 330 can be reduced. The insulating layer 383 can be formed using aluminum oxide, hafnium oxide, hafnium silicate, or the like.

[0335] Alternatively, the insulating layer 383 may have a stacked structure of an insulating layer having a function of capturing or fixing hydrogen and a barrier insulating layer against hydrogen. For example, the insulating layer 383 may be a stacked film of aluminum oxide and silicon nitride over the aluminum oxide.

[0336] The insulating layer 385 functions as an interlayer film, and therefore is preferably made of the above-mentioned material having a low relative dielectric constant. For example, the insulating layer 385 preferably includes a silicon oxide film.

[0337] 13A and 13B are cross-sectional views showing a configuration example of the memory cell 10I. In the memory cell 10I, the conductive layer 365a shown in FIGS. 12A and 12B is not provided, and a conductive layer 360 is provided over the insulating layer 350. Here, the transistors 100, 200, and 300 included in the memory cell 10I are referred to as the transistor 100I, the transistor 200I, and the transistor 300I, respectively. Note that FIGS. 1B, 1C, and 1D can be referred to for the structures of the transistor 100I, the transistor 200I, and the transistor 300I in a plan view, respectively.

[0338] The conductive layer 360 functions as a gate electrode (first gate electrode) of the transistor 300I. The conductive layer 365 functions as a gate wiring as described above. The conductive layer 360 can be formed using, for example, a material that can be used for the conductive layer 365a. The conductive layer 365 included in the memory cell 10I can be formed using, for example, a material that can be used for the conductive layer 365b.

[0339] The conductive layer 360 is included in the components of the transistor 3001. The conductive layer 365 may not be included in the components of the transistor 3001. Note that the conductive layer 365 may be included in the components of the transistor 3001.

[0340] 13A and 13B , an opening 370 that reaches the semiconductor layer 330 is provided in the insulating layer 383 at a position overlapping with the opening 390. At least some of the components of the transistor 300I are disposed inside the opening 370. Specifically, the insulating layer 350 and the conductive layer 360 are disposed such that at least a portion of each is located inside the opening 370. The insulating layer 350 contacts the semiconductor layer 330 and the insulating layer 383 inside the opening 370.

[0341] The portion of insulating layer 350 that is disposed inside opening 370 is provided to reflect the shape of opening 370. Specifically, insulating layer 350 is provided so as to cover the sidewall of opening 370 (the side surface of insulating layer 383). Then, conductive layer 360 is provided so as to fill at least a portion of the recess in insulating layer 350 that reflects the shape of opening 370.

[0342] In the transistor 300I, the conductive layer 360 does not overlap with the top surface of the conductive layer 340, which makes it possible to reduce the parasitic capacitance generated between the conductive layer 340 and the conductive layer 360. As shown in Figures 13A and 13B, in a cross-sectional view, the maximum width of the conductive layer 360 is smaller than the width D2 of the opening 390. When the maximum width of the conductive layer 360 is smaller than the width D2 of the opening 390, the parasitic capacitance generated between the conductive layer 360 and the conductive layer 340 can be reduced, which is preferable.

[0343] 13A and 13B show an example in which the width of opening 370 is the same as the width of opening 390 (same as width D2). It is more preferable that the width of opening 370 is the same as or smaller than the width of opening 390. This is preferable because conductive layer 360 does not overlap the upper surface of conductive layer 340 and the parasitic capacitance generated between conductive layer 360 and conductive layer 340 can be reduced.

[0344] Note that, although this embodiment illustrates an example in which the conductive layer 360 does not overlap with the upper surface of the conductive layer 340, the conductive layer 360 may have a portion that overlaps with the upper surface of the conductive layer 340. The smaller the overlapping portion, the smaller the parasitic capacitance that occurs between the conductive layer 360 and the conductive layer 340, which is preferable. For example, the width of the opening 370 is preferably smaller than the width of the short side of the conductive layer 365 (the maximum width of the conductive layer 365 in FIG. 13B ). Furthermore, for example, the maximum width of the conductive layer 365 is preferably equal to or smaller than the width of the short side of the conductive layer 355 (the maximum width of the conductive layer 355 in the Y direction in FIG. 13B ).

[0345] It is preferable that the height of the top surface of the conductive layer 360 and the height of the top surface of the insulating layer 385 are the same or approximately the same. The conductive layer 365 is provided over the insulating layer 385, the insulating layer 383, and the conductive layer 360, and is in contact with the top surface of the conductive layer 360. It can also be said that the conductive layer 360 and the conductive layer 365 are electrically connected to each other. The insulating layer 383 and the insulating layer 385 are located between the conductive layer 365 and the conductive layer 340. This allows the physical distance between the conductive layer 365 and the conductive layer 340 to be increased, and the parasitic capacitance generated between the conductive layer 365 and the conductive layer 340 to be reduced.

[0346] That is, the transistor 300I has a structure in which the parasitic capacitance between the gate electrode and the other of the source electrode and the drain electrode and the parasitic capacitance between the gate wiring and the other of the source electrode and the drain electrode are reduced, thereby providing a semiconductor device with high operating speed.

[0347] [Memory Cell 10J] Figures 14A and 14B are cross-sectional views showing a configuration example of the memory cell 10J. In the memory cell 10J, the conductive layer 365 shown in Figures 2A and 2B has a single-layer structure. Here, the transistors 100, 200, and 300 included in the memory cell 10J are referred to as the transistor 100J, the transistor 200J, and the transistor 300J, respectively. Note that Figures 1B, 1C, and 1D can be referred to for the planar structures of the transistor 100J, the transistor 200J, and the transistor 300J, respectively.

[0348] Like the conductive layer 365 of the transistor 300J, a conductive layer functioning as a gate electrode may have a single-layer structure. The conductive layer 365 is preferably provided to fill the opening 390.

[0349] [Memory Cell 10K] Figures 15A and 15B are cross-sectional views showing a configuration example of the memory cell 10K. In the memory cell 10K, both the conductive layer 365a and the conductive layer 365b are located inside the opening 390 shown in Figures 2A and 2B. Here, the transistors 100, 200, and 300 included in the memory cell 10K are referred to as the transistor 100K, the transistor 200K, and the transistor 300K, respectively. Note that Figures 1B, 1C, and 1D can be referred to for the configurations of the transistors 100K, 200K, and 300K in plan view, respectively.

[0350] In the transistor 300K, the conductive layer 365b is located inside the opening 390. As described above, depending on the diameter of the opening 390 and the thickness of the conductive layer 365a, not only the conductive layer 365a but also the conductive layer 365b may be provided inside the opening 290.

[0351] The above-described structures of the memory cells 10A to 10K can be combined as appropriate. For example, the insulating layer 235 and the conductive layer 255 may be provided in the memory cell 10A, the memory cell 10B, and the memory cells 10F to 10K. The insulating layers 180a, 180b, 280, 380a, and 380b of the memory cells 10A, 10B, and the memory cells 10F to 10K may each have a stacked structure similar to the memory cells 10D and 10E. Furthermore, the structures of the gate electrode and the gate insulating layer of the transistor 300 shown in FIGS. 12A to 15B may be applied to the transistors 300A to 300G.

[0352] [Transistor 100L and Transistor 100M] Other configuration examples of the transistor 100 will be described below. Note that the configuration of the transistor 100L described below can also be applied to the transistor 200 and the transistor 300. Similarly, the configuration of the transistor 100M described below can also be applied to the transistor 200 and the transistor 300.

[0353] 16A is a cross-sectional view illustrating a configuration example of a semiconductor device including a transistor 100L, in which the insulating layer 135 illustrated in FIG. 4A has a two-layer structure. Here, the insulating layer 135 may have a stacked structure of three or more layers. Although not illustrated in FIG. 16A , the insulating layer 235 and the insulating layer 335 can also have a stacked structure of two or more layers, similar to the insulating layer 135. Furthermore, for example, the insulating layer 135 and the insulating layer 335 included in the memory cells 10A to 10K and the insulating layer 235 included in the memory cells 10C and 10E can also have a stacked structure of two or more layers.

[0354] The insulating layer 135 included in the transistor 100L includes an insulating layer 135a and an insulating layer 135b over the insulating layer 135a. One of the insulating layer 135a and the insulating layer 135b preferably includes an insulating layer having a region containing oxygen that is desorbed by heating. The other of the insulating layer 135a and the insulating layer 135b preferably includes a barrier insulating layer against hydrogen.

[0355] This allows oxygen to be supplied from the insulating layer 135a or the insulating layer 135b to the semiconductor layer 130 and prevents hydrogen from diffusing into the semiconductor layer 130. Thus, the transistor 100L can be a highly reliable transistor.

[0356] For example, it is preferable to use a silicon nitride film for the insulating layer 135a and a silicon oxide film for the insulating layer 135b, or to use a silicon oxide film for the insulating layer 135a and a silicon nitride film for the insulating layer 135b.

[0357] In the transistor 100L, the insulating layer 135a is provided in contact with the bottom and side surfaces of the recess of the conductive layer 120b, and the insulating layer 135b is provided on the insulating layer 135a. For example, an insulating film to be the insulating layer 135a and an insulating film to be the insulating layer 135b are stacked, and then the two insulating films are processed to form the insulating layer 135a and the insulating layer 135b having the structure shown in FIG.

[0358] 16B is a cross-sectional view illustrating a configuration example of a semiconductor device including a transistor 100M, illustrating an example in which the sidewalls of the opening 190 illustrated in FIG. 4A are tapered. Note that, although not illustrated in FIG. 16B , the sidewalls of the opening 290 and the opening 390 may also be tapered, similar to the sidewall of the opening 190. Furthermore, for example, the sidewalls of the openings 190, 290, and 390 included in memory cells 10A to 10K may also be tapered.

[0359] By tapering the sidewalls of the opening 190, the coverage of the insulating layer 135, the semiconductor layer 130, the insulating layer 181, etc. can be improved, and defects such as voids can be reduced. When the sidewalls of the opening 190 are tapered, for example, the taper angle θ180 of the side surface of the insulating layer 180a inside the opening 190 is preferably 45 degrees or more and less than 90 degrees. Specifically, a taper angle θ180 of 80 degrees or more and less than 90 degrees is preferable because it allows for miniaturization or high integration of the semiconductor device. Furthermore, a taper angle θ180 of 45 degrees or more, or 50 degrees or more and less than 80 degrees, 75 degrees or less, 70 degrees or less, 65 degrees or less, or 60 degrees or less is preferable because it improves the coverage of the film formed inside the opening 190.

[0360] Alternatively, for example, the sidewall of the opening 190 may have an inverse tapered shape. In other words, the taper angle θ180 of the side surface of the insulating layer 180a inside the opening 190 may be greater than 90 degrees.

[0361] <Example of Manufacturing Method of Semiconductor Device> Next, a manufacturing method of a semiconductor device according to one embodiment of the present invention will be described. Note that with regard to materials and forming methods of elements, descriptions of parts similar to those described above may be omitted.

[0362] Thin films (insulating films, semiconductor films, conductive films, etc.) constituting a semiconductor device can be formed using a sputtering method, a chemical vapor deposition (CVD) method, a vacuum deposition method, a molecular beam epitaxy (MBE) method, a pulsed laser deposition (PLD) method, an atomic layer deposition (ALD) method, or the like.

[0363] Sputtering methods include RF sputtering, which uses a high-frequency power supply as the sputtering power source, DC sputtering, which uses a direct current power supply, and pulsed DC sputtering, which changes the voltage applied to the electrode in a pulsed manner. RF sputtering is mainly used to form insulating films, while DC sputtering is mainly used to form metal conductive films. Pulsed DC sputtering is mainly used to form films of compounds such as oxides, nitrides, or carbides using reactive sputtering.

[0364] CVD methods can be further classified into plasma-enhanced CVD (PECVD) methods that utilize plasma, thermal CVD (TCVD) methods that utilize heat, and photo-CVD (photo-CVD) methods that utilize light. CVD methods can also be further classified into metal CVD (MCVD) methods and metal organic CVD (MOCVD) methods depending on the source gas used.

[0365] The plasma CVD method can produce high-quality films at relatively low temperatures. Furthermore, the thermal CVD method is a film formation method that can reduce plasma damage to the workpiece because it does not use plasma. For example, wiring, electrodes, and elements (transistors, capacitors, etc.) included in a semiconductor device may become charged up by receiving electric charge from the plasma. In this case, the accumulated electric charge may destroy the wiring, electrodes, or elements included in the semiconductor device. On the other hand, the thermal CVD method, which does not use plasma, does not cause such plasma damage, and therefore can increase the yield of semiconductor devices. Furthermore, the thermal CVD method does not cause plasma damage during film formation, so films with fewer defects can be obtained.

[0366] As the ALD method, a thermal ALD method in which a reaction between a precursor and a reactant is carried out using only thermal energy, a PEALD method in which a plasma-excited reactant is used, or the like can be used.

[0367] The ALD method allows atoms to be deposited layer by layer, and therefore has the advantages of enabling ultrathin film formation, film formation on high-aspect-ratio structures or surfaces with large steps, film formation with fewer defects such as pinholes, film formation with excellent coverage, and film formation at low temperatures. Furthermore, the PEALD method may be preferable because it utilizes plasma, enabling film formation at lower temperatures. Note that some precursors used in the ALD method contain elements such as carbon or chlorine. Therefore, films formed by the ALD method may contain higher amounts of elements such as carbon or chlorine than films formed by other film formation methods. The amounts of these elements can be quantified using XPS or SIMS. The metal oxide film formation method of one embodiment of the present invention uses the ALD method, but employs one or both of a high substrate temperature during film formation and an impurity removal treatment. Therefore, the amount of carbon and chlorine contained in the film may be lower than when the ALD method is used without these.

[0368] Unlike film formation methods in which particles emitted from a target are deposited, the ALD method is a film formation method in which a film is formed by a reaction on the surface of a workpiece. Therefore, it is a film formation method that is less affected by the shape of the workpiece and has good step coverage. In particular, the ALD method has excellent step coverage and excellent thickness uniformity, making it suitable for coating the surface of an opening with a high aspect ratio, for example.

[0369] The CVD and ALD methods differ from sputtering methods in that particles emitted from a target or the like are deposited. Therefore, they are film formation methods that are less affected by the shape of the workpiece and have good step coverage. In particular, the ALD method has excellent step coverage and excellent thickness uniformity, making it suitable for coating the surface of an opening with a high aspect ratio, for example. However, because the ALD method has a relatively slow film formation rate, it may be preferable to use it in combination with other film formation methods, such as the CVD method, which has a faster film formation rate.

[0370] Furthermore, the CVD method allows deposition of a film of any composition by adjusting the flow rate ratio of the source gases. For example, the CVD method allows deposition of a film with a continuously changing composition by changing the flow rate ratio of the source gases during deposition. When deposition is performed while changing the flow rate ratio of the source gases, the time required for deposition can be shortened compared to deposition using multiple deposition chambers because no time is required for transport or pressure adjustment. Therefore, the productivity of semiconductor devices can be improved in some cases.

[0371] In addition, in the ALD method, a film of any composition can be formed by simultaneously introducing multiple different precursors, or by controlling the number of cycles of each precursor when multiple different precursors are introduced.

[0372] Furthermore, thin films (insulating films, semiconductor films, conductive films, etc.) constituting the semiconductor device can be formed by a wet film formation method such as spin coating, dip coating, spray coating, inkjet printing, dispensing, screen printing, offset printing, doctor knife method, slit coating, roll coating, curtain coating, or knife coating.

[0373] Furthermore, when processing a thin film that constitutes a semiconductor device, for example, a photolithography method can be used. Alternatively, the thin film may be processed by a nanoimprint method, a sandblasting method, a lift-off method, or the like. Furthermore, a thin film having a desired shape may be directly formed by a film formation method using a shielding mask such as a metal mask.

[0374] There are two typical photolithography methods: one is to form a resist mask on the thin film to be processed, process the thin film by etching, and then remove the resist mask; the other is to form a photosensitive thin film, and then process the thin film into the desired shape by exposure and development.

[0375] In photolithography, the light used for exposure may be, for example, i-line (wavelength 365 nm), g-line (wavelength 436 nm), h-line (wavelength 405 nm), or a mixture of these. Other light sources that can be used include ultraviolet light, KrF laser light, ArF laser light, etc. Exposure may also be performed by immersion exposure technology. Extreme ultraviolet (EUV) light or X-rays may also be used as the light used for exposure. An electron beam may also be used instead of the light used for exposure. Extreme ultraviolet light, X-rays, or an electron beam are preferred because they enable extremely fine processing. When exposure is performed by scanning a beam such as an electron beam, a photomask is not required.

[0376] The thin film can be etched by dry etching, wet etching, sandblasting, or the like.

[0377] [Example of Manufacturing Method of Memory Cell 10] An example of a manufacturing method of a semiconductor device having the memory cell 10 shown in Figures 2A and 2B will be described with reference to Figures 17A to 24. Figures 17A to 24 show a cross-sectional view taken along dashed line A1-A2 in Figure 2A and a cross-sectional view taken along dashed line B1-B2 in Figure 2B side by side.

[0378] 17A, an insulating layer 110 is formed on a substrate (not shown), a conductive layer 120a is formed on the insulating layer 110, and a conductive layer 120b is formed on the conductive layer 120a. Furthermore, an insulating layer 180a is formed on the conductive layer 120b and the insulating layer 110, and a conductive layer 155 is formed on the insulating layer 180a.

[0379] Note that after the insulating layer 180a is formed, planarization treatment is preferably performed to planarize the top surface of the insulating layer 180a. CMP treatment is suitable as the planarization treatment. Alternatively, planarization treatment using etching (also referred to as etch-back treatment) may be performed. By performing the planarization treatment on the insulating layer 180a, the surface on which the conductive layer 155 is to be formed can be flattened, and discontinuity of the conductive layer 155 can be suppressed. Note that the planarization treatment is not necessarily performed, and in that case, manufacturing costs can be reduced.

[0380] Subsequently, as shown in FIG. 17B, an insulating layer 180b is formed on the conductive layer 155 and the insulating layer 180a, a conductive layer 140a is formed on the insulating layer 180b, and a conductive layer 140b is formed on the conductive layer 140a.

[0381] 17C , openings 190 reaching the conductive layer 120 are formed in the conductive layer 140b, the conductive layer 140a, the insulating layer 180b, the conductive layer 155, and the insulating layer 180a. At this time, it is preferable that a recess be provided in the conductive layer 120b at a position overlapping with the opening 190. It is preferable that the formation of the openings 190 exposes the bottom and side surfaces of the recesses in the conductive layer 120b.

[0382] To facilitate microfabrication and reduce the size of the transistors, highly anisotropic etching is preferably used to process a portion of the conductive layer 120b, a portion of the conductive layer 140a, a portion of the conductive layer 140b, a portion of the conductive layer 155, a portion of the insulating layer 180a, and a portion of the insulating layer 180b when forming the opening 190. Dry etching is particularly suitable for microfabrication and is therefore preferable. The opening 190 may be formed under different processing conditions depending on the layer. Note that the slopes of the side surfaces of the conductive layer 120b, the conductive layer 140a, the conductive layer 140b, the conductive layer 155, the insulating layer 180a, and the insulating layer 180b within the opening 190 may differ depending on the materials and processing conditions of the conductive layer 120b, the conductive layer 140a, the conductive layer 140b, the conductive layer 155, the insulating layer 180a, and the insulating layer 180b.

[0383] Furthermore, for example, by the process of forming the opening 190, a region containing a halogen element may be provided on at least one of the bottom and side surfaces of the recess in the conductive layer 120b, the side surfaces of the insulating layer 180a, the side surfaces of the insulating layer 180b, the side surfaces of the conductive layer 155, the side surfaces of the conductive layer 140a, and the top and side surfaces of the conductive layer 140b. Examples of such a region include a region containing fluorine, a region containing chlorine, or a region containing fluorine and chlorine. For example, a halogen element derived from the etching gas used in the dry etching may remain in such a region.

[0384] Subsequently, heat treatment may be performed at a temperature of, for example, 250° C. to 650° C., preferably 300° C. to 500° C., and more preferably 320° C. to 450° C.

[0385] The heat treatment is performed in an atmosphere of nitrogen gas or an inert gas, or an atmosphere containing an oxidizing gas at 10 ppm or more, 1% or more, or 10% or more. For example, when the heat treatment is performed in a mixed atmosphere of nitrogen gas and oxygen gas, the oxygen gas concentration is preferably about 20%. The heat treatment may be performed under reduced pressure. Alternatively, after the heat treatment in the nitrogen gas or inert gas atmosphere, the heat treatment may be performed in an atmosphere containing an oxidizing gas at 10 ppm or more, 1% or more, or 10% or more to compensate for the desorbed oxygen. By performing the above-described heat treatment, impurities such as water contained in the insulating layers 180a and 180b can be reduced before the formation of the semiconductor layer 130.

[0386] The gas used in the heat treatment is preferably highly purified. For example, the amount of moisture contained in the gas used in the heat treatment is preferably 1 ppb or less, more preferably 0.1 ppb or less, and even more preferably 0.05 ppb or less. By performing the heat treatment using a highly purified gas, moisture and the like can be prevented from being introduced into the insulating layers 180a and 180b as much as possible.

[0387] 17D , insulating layer 135 is formed to cover opening 190 and to have a region located on conductive layer 140b. Insulating layer 135 is provided in contact with the bottom and side surfaces of the recess in conductive layer 120b, the side surfaces of insulating layer 180a, the side surfaces of conductive layer 155, the side surfaces of insulating layer 180b, the side surfaces of conductive layer 140a, and the top and side surfaces of conductive layer 140b.

[0388] The insulating layer 135 is preferably formed by a CVD method or an ALD method, and more preferably by an ALD method, since it is a layer provided inside the opening 190. This allows the insulating layer 135 to be provided with good coverage.

[0389] 18A , the insulating layer 135 is processed to expose the top surface of the conductive layer 140 and to expose the conductive layer 120 in the opening 190. In the opening 190, it is preferable that the bottom surface of the recess of the conductive layer 120b is exposed.

[0390] The insulating layer 135 can be processed without using photolithography. The insulating layer 135 is processed by, for example, anisotropic etching of the entire surface without forming a resist mask. For example, the insulating layer 135 is processed by anisotropic etching until the top surface of the conductive layer 140b is exposed. As a result, the region of the insulating layer 135 located on the top surface of the conductive layer 140 and the region located on the bottom surface of the opening 190 can be removed, and the insulating layer 135 can be left only on the inner side surface of the opening 190. The insulating layer 135 is preferably processed by highly anisotropic etching using a dry etching method.

[0391] Here, by forming the insulating layer 135 after forming the conductive layer 140, it is possible to suppress the continuation of anisotropic etching of the insulating layer 135 even after the region of the insulating layer 135 located outside the opening 190 is removed, compared to when the insulating layer 135 is formed without forming the conductive layer 140. Therefore, for example, it is possible to prevent the side surface of the conductive layer 155 on the opening 190 side from being exposed. Therefore, it is possible to prevent the conductive layer 155 from contacting the semiconductor layer 130 to be formed later. As described above, a method for manufacturing a semiconductor device with a high yield can be realized.

[0392] As shown in FIG. 18A, when processing the insulating layer 135, a portion of the conductive layer 120b may be removed to provide a recess in the conductive layer 120b.

[0393] 18B , a semiconductor layer 130 is formed to cover the opening 190 and to be in contact with the upper surface of the conductive layer 140 and the conductive layer 120. The semiconductor layer 130 is formed to cover the insulating layer 135 inside the opening 190. The semiconductor layer 130 can be formed to be in contact with the bottom and side surfaces of the recess of the conductive layer 120b, the insulating layer 135, and the upper surface of the conductive layer 140b.

[0394] The semiconductor layer 130 can be formed by, for example, sputtering, ALD, CVD, vacuum deposition, MBE, or PLD.

[0395] The semiconductor layer 130 is preferably formed as a film with as uniform a thickness as possible along the bottom and side surfaces of the recesses in the conductive layer 120b, the insulating layer 135, and the top surface of the conductive layer 140b. By forming the semiconductor layer 130 using the ALD method, a thin film can be formed with good controllability. Therefore, it is preferable to form the semiconductor layer 130 using the ALD method.

[0396] Furthermore, when the semiconductor layer 130 has high crystallinity, diffusion of impurities in the semiconductor layer 130 is suppressed, so that the electrical characteristics of the transistor are less likely to fluctuate and reliability can be improved. Forming the semiconductor layer 130 by a sputtering method is preferable because it is easier to form a layer with high crystallinity than when an ALD method is used.

[0397] When the semiconductor layer 130 is formed by sputtering, oxygen or a mixed gas of oxygen and a noble gas is used as the sputtering gas. By increasing the proportion of oxygen contained in the sputtering gas, the amount of excess oxygen in the oxide film to be formed can be increased. When the oxide film is formed by sputtering, for example, an In-M-Zn oxide target can be used.

[0398] When the semiconductor layer 130 is formed by a sputtering method, an oxygen-excess oxide semiconductor is formed when the percentage of oxygen contained in the sputtering gas is set to more than 30% and less than or equal to 100%, preferably 70% to 100%. A transistor using an oxygen-excess oxide semiconductor for a channel formation region can have relatively high reliability. However, one embodiment of the present invention is not limited thereto. An oxygen-deficient oxide semiconductor is formed when the percentage of oxygen contained in the sputtering gas is set to 1% to 30%, preferably 5% to 20%. A transistor using an oxygen-deficient oxide semiconductor for a channel formation region can have relatively high field-effect mobility. Furthermore, the crystallinity of the semiconductor layer 130 can be improved by performing film formation while heating the substrate.

[0399] For a manufacturing method of a semiconductor layer, the description in Embodiment Mode 2 can be referred to.

[0400] Next, heat treatment is preferably performed. The heat treatment is preferably performed within a temperature range in which the semiconductor layer 130 does not become polycrystallized. The temperature of the heat treatment is preferably 100° C. or higher and 650° C. or lower, more preferably 250° C. or higher and 600° C. or lower, and further preferably 350° C. or higher and 550° C. or lower. The above description can be referred to for details of the heat treatment.

[0401] In addition, it is preferable that the gas used in the heat treatment be highly purified. By performing the heat treatment using a highly purified gas, for example, moisture can be prevented from being taken into the semiconductor layer 130 as much as possible.

[0402] In this embodiment, the heat treatment is performed at a temperature of 450° C. for one hour with a flow rate ratio of nitrogen gas to oxygen gas of 4:1. This heat treatment using oxygen gas can reduce impurities such as carbon, water, and hydrogen in the semiconductor layer 130. Reducing the impurities in the film in this manner can improve the crystallinity of the semiconductor layer 130, resulting in a denser and more compact structure. This increases the crystalline region in the semiconductor layer 130, reducing in-plane variations in the crystalline region in the semiconductor layer 130. Therefore, in-plane variations in the electrical characteristics of the transistor can be reduced.

[0403] When at least one of the insulating layer 180a, the insulating layer 180b, and the insulating layer 135 contains oxygen, oxygen is preferably supplied by heat treatment from the insulating layer containing oxygen to the channel formation region of the semiconductor layer 130. This can reduce oxygen vacancies and VoH.

[0404] In this manner, oxygen (also referred to as excess oxygen) released by heating from an insulating layer in contact with the semiconductor layer 130 or an insulating layer located near the semiconductor layer 130 may be supplied to the semiconductor layer 130. The excess oxygen has a function of trapping electrons, which makes it easier for negative charges to be formed. Therefore, the threshold voltage of the transistor is shifted in the positive direction, making it possible to realize a normally-off transistor.

[0405] 18C , the semiconductor layer 130, the conductive layer 140a, and the conductive layer 140b are processed to remove portions of the semiconductor layer 130, the conductive layer 140a, and the conductive layer 140b. This exposes a portion of the top surface of the insulating layer 180b. The semiconductor layer 130, the conductive layer 140a, and the conductive layer 140b can be processed using the same mask. This is preferable because it reduces the number of masks required to manufacture a semiconductor device.

[0406] 19A, an insulating layer 181A is formed so as to cover the semiconductor layer 130. Specifically, the insulating layer 181A is formed so as to cover the semiconductor layer 130, the side surfaces of the conductive layer 140b, the side surfaces of the conductive layer 140a, and the upper surface of the insulating layer 180b.

[0407] The insulating layer 181A is formed along the opening 190, which has a large aspect ratio. Specifically, the insulating layer 181A is formed along a recess in the semiconductor layer 130 formed at a position overlapping the opening 190. For the above reasons, it is preferable to use a film formation method with good coverage for forming the insulating layer 181A. The insulating layer 181A is preferably formed using, for example, a CVD method or an ALD method, and is more preferably formed using an ALD method. The insulating layer 181A can be formed to have a recess at a position overlapping the opening 190.

[0408] 19A , an insulating layer 183A is formed on the insulating layer 181A so as to have a region located inside the opening 190. The insulating layer 183A can be formed using, for example, a CVD method, an ALD method, a sputtering method, a vacuum deposition method, an MBE method, or a PLD method.

[0409] 19B, a planarization process is performed on the insulating layer 183A until at least a portion of the upper surface of the insulating layer 181A is exposed. In other words, a planarization process is performed on the insulating layer 183A, with the insulating layer 181A as the end point. This forms the insulating layer 183 having a region located inside the opening 190. Specifically, the insulating layer 183 is formed having a region located inside the recess of the insulating layer 181A. For example, the insulating layer 183 can be formed so as to fill the recess of the insulating layer 181A. Note that CMP is a suitable planarization process.

[0410] Even after the planarization treatment is performed on the insulating layer 183A, a portion of the insulating layer 183A remains. For example, the insulating layer 183A remains in a region that does not overlap with either the opening 190 or the conductive layer 140. As shown in FIGS. 3A and 3B , the insulating layer 183A remains so as to surround the semiconductor layer 130 and the conductive layer 140. Specifically, the insulating layer 183A remains so as to surround, in a planar view, the side surface of the semiconductor layer 130 located outside the opening 190 and the side surface of the conductive layer 140 opposite to the side surface on the opening 190 side.

[0411] 3A and 3B , openings 191 overlapping with the semiconductor layer 130 are formed by the planarization treatment on the insulating layer 183A, and island-shaped insulating layers 183 are formed inside the openings 191. In other words, openings 191 overlapping with the conductive layer 140 and the openings 190 are formed by the planarization treatment on the insulating layer 183A, and island-shaped insulating layers 183 are formed inside the openings 191.

[0412] Next, as shown in FIG. 19C , the insulating layer 181A is processed to remove a portion of the insulating layer 181A. This forms the insulating layer 181 having a region located inside the opening 190. Furthermore, at least a portion of the top surface of the semiconductor layer 130 is exposed. The insulating layer 181A can be processed using, for example, the insulating layer 183 and the insulating layer 183A as masks. In this case, at least a portion of the region of the insulating layer 181A that does not overlap with the insulating layer 183 can be removed. Specifically, the region of the insulating layer 181A that does not overlap with either the insulating layer 183A or the insulating layer 183 can be removed. As a result, the insulating layer 181 is formed to overlap with the insulating layer 183, and the region of the semiconductor layer 130 that overlaps with the conductive layer 140 can be exposed.

[0413] Even after the insulating layer 181A is processed to form the insulating layer 181, a portion of the insulating layer 181A remains. Specifically, the insulating layer 181A remains in a region overlapping with the insulating layer 183A. By processing the insulating layer 181A, an opening 191 overlapping with the semiconductor layer 130 is formed in the insulating layer 181A, as shown in FIGS. 3A and 3B , and an island-shaped insulating layer 181 is formed inside the opening 191. In other words, by processing the insulating layer 181A, an opening 191 overlapping with the conductive layer 140 and the opening 190 is formed, and an island-shaped insulating layer 181 is formed inside the opening 191.

[0414] 19A to 19C , the insulating layer 183 can be formed by performing a planarization treatment on the insulating layer 183A, with the insulating layer 181A as the end point. In this case, as shown in Fig. 19C , the upper surfaces of the insulating layer 183 and the insulating layer 183A can be positioned higher than the upper surface of the region of the semiconductor layer 130 that overlaps with the conductive layer 140. For example, the upper surfaces of the insulating layer 183 and the insulating layer 183A can be positioned higher than the upper surface of the region of the semiconductor layer 130 that overlaps with the conductive layer 140 by, for example, the thickness of the insulating layer 181 and the insulating layer 181A, respectively.

[0415] Here, if the insulating layer 183A is formed without forming the insulating layer 181A and then planarized until at least a portion of the top surface of the semiconductor layer 130 is exposed, the planarization process may be performed not only on the insulating layer 183A but also on the semiconductor layer 130. This may result in removal of a region of the semiconductor layer 130 that is in contact with the conductive layer 140. Furthermore, it may become difficult to control the thickness of the region of the semiconductor layer 130 that overlaps with the conductive layer 140. As a result, the reliability of the semiconductor device may be reduced. Therefore, by forming the insulating layer 183A after forming the insulating layer 181A and then performing planarization on the insulating layer 183A until at least a portion of the top surface of the insulating layer 181A is exposed, the planarization process may be prevented from being performed on the semiconductor layer 130. Therefore, a method for manufacturing a semiconductor device with a high yield can be realized.

[0416] As shown in FIGS. 19A to 19C , the insulating layers 181 and 183 can be formed without using photolithography. That is, the insulating layer 183 can be formed by planarization treatment, and then the insulating layer 181 can be formed by processing using the insulating layer 183 as a mask. This reduces the number of manufacturing steps for the semiconductor device compared to, for example, forming the insulating layers 181 and 183 using photolithography. This reduces the manufacturing cost of the semiconductor device, allowing a low-cost semiconductor device to be provided. Note that the insulating layers 181 and 183 may also be formed using photolithography. In this case, the insulating layers 181A and 183A can be processed so that they do not remain outside the conductive layer 140 (the side opposite the opening 190), for example.

[0417] As described above, in the manufacturing process of the semiconductor device of one embodiment of the present invention, the insulating layer 183A is subjected to planarization treatment with the insulating layer 181A as the end point. Therefore, using a material for the insulating layer 183A that reduces the thickness loss of the insulating layer 181A in the planarization treatment with the insulating layer 181A as the end point is preferable because the thickness of the insulating layer 181A during deposition can be reduced and, for example, planarization treatment can be prevented from being performed on the semiconductor layer 130. Furthermore, in the manufacturing process of the semiconductor device of one embodiment of the present invention, the insulating layer 181A is processed using the insulating layers 183 and 183A as masks. Therefore, using a material with a high etching selectivity to the insulating layer 181A for the insulating layer 183A is preferable because processing of the insulating layer 183 and 183A can be prevented when the insulating layer 181A is processed. For example, when silicon nitride is used for the insulating layer 181A, silicon oxide is preferably used for the insulating layer 183A. For example, the insulating layer 181A before processing can be referred to as a first insulating film, and the insulating layer 183A before planarization can be referred to as a second insulating film.

[0418] 20A, a conductive layer 220a is formed on the insulating layer 183, the insulating layer 183A, and the semiconductor layer 130, and a conductive layer 220b is formed on the conductive layer 220a. Next, as shown in FIG. 20B, the conductive layer 220a and the conductive layer 220b are processed. For example, portions of the conductive layer 220a and the conductive layer 220b are removed so that portions of the top surface of the semiconductor layer 130 and the top surface of the insulating layer 183A are exposed. Thus, the conductive layer 220 is formed. The conductive layer 220 can be formed so as to be in contact with the top surface of the insulating layer 183, the side surface of the insulating layer 181, and the top surface of the semiconductor layer 130.

[0419] Through the above steps, the transistor 100 including the conductive layer 120, the conductive layer 140, the conductive layer 155, the conductive layer 220, the semiconductor layer 130, and the insulating layer 135 can be formed.

[0420] Subsequently, as shown in FIG. 21A, an insulating layer 280 is formed on the conductive layer 220, the semiconductor layer 130, and the insulating layer 183A, a conductive layer 240a is formed on the insulating layer 280, and a conductive layer 240b is formed on the conductive layer 240a.

[0421] 21A , an opening 290 reaching the conductive layer 220 is formed in the conductive layer 240b, the conductive layer 240a, and the insulating layer 280. At this time, a recess is preferably provided in the conductive layer 220b at a position overlapping the opening 290. By forming the opening 290, the bottom and side surfaces of the recess in the conductive layer 220b are preferably exposed.

[0422] The opening 290 can be formed in the same manner as the opening 190. For example, the processing of the conductive layer 240b and the processing of the conductive layer 240a can be performed under the same conditions as the processing of the conductive layer 140b and the processing of the conductive layer 140a, respectively. Furthermore, the processing of the insulating layer 280 can be performed under the same conditions as the processing of the insulating layer 180a or the processing of the insulating layer 180b, for example.

[0423] 21B , a semiconductor layer 230 is formed to cover the opening 290 and to be in contact with the conductive layer 220 and the conductive layer 240. The semiconductor layer 230 can be formed to be in contact with the bottom and side surfaces of the recess of the conductive layer 220, the side surfaces of the insulating layer 280 and the conductive layer 240 facing the opening 290, and the upper surface of the conductive layer 240. Specifically, the semiconductor layer 230 can be formed to be in contact with the bottom and side surfaces of the recess of the conductive layer 220b, the side surfaces of the insulating layer 280, the conductive layer 240a, and the conductive layer 240b facing the opening 290, and the upper surface of the conductive layer 240b. The semiconductor layer 230 can be formed by a method similar to that for the semiconductor layer 130.

[0424] 21B , the semiconductor layer 230, the conductive layer 240a, and the conductive layer 240b are processed to remove portions of the semiconductor layer 230, the conductive layer 240a, and the conductive layer 240b. This exposes a portion of the top surface of the insulating layer 280. In the step shown in FIG. 21B , the semiconductor layer 230, the conductive layer 240a, and the conductive layer 240b can be processed using the same mask. This is preferable because it reduces the number of masks required to manufacture a semiconductor device.

[0425] 22, an insulating layer 250 is formed so as to cover the semiconductor layer 230. Specifically, the insulating layer 250 is formed so as to cover the semiconductor layer 230, the side surfaces of the conductive layer 240b, the side surfaces of the conductive layer 240a, and the top surface of the insulating layer 280b.

[0426] The insulating layer 250 is formed along the opening 290, which has a large aspect ratio. Specifically, the insulating layer 250 is formed along a recess in the semiconductor layer 230 formed at a position overlapping the opening 290. For the above reasons, it is preferable to use a film formation method with good coverage for forming the insulating layer 250. The insulating layer 250 is preferably formed using, for example, a CVD method or an ALD method, and is more preferably formed using an ALD method. The insulating layer 250 can be formed so as to have a recess at a position overlapping the opening 290.

[0427] 22 , a conductive layer 320a is formed on the insulating layer 250 so as to have a region located inside the opening 290. Furthermore, a conductive layer 320b is formed on the conductive layer 320a. The conductive layer 320a is preferably formed so as to fill the opening 290. Specifically, the conductive layer 320a is preferably formed so as to fill the recessed portion of the insulating layer 250. Note that depending on the diameter of the opening 290 and the thickness of the conductive layer 320a, the conductive layer 320b may also be formed inside the opening 290.

[0428] The conductive layer 320a is formed inside the opening 290 having a large aspect ratio. Therefore, it is preferable to use a film formation method with good coverage for forming the conductive layer 320a, and it is more preferable to use a CVD method, an ALD method, or the like.

[0429] Through the above steps, the transistor 200 including the conductive layer 220, the conductive layer 240, the conductive layer 320, the semiconductor layer 230, and the insulating layer 250 can be formed.

[0430] 23, an insulating layer 380a is formed over the conductive layer 320 and the insulating layer 250, and a conductive layer 355 is formed over the insulating layer 380a. Note that after the insulating layer 380a is formed, planarization treatment is preferably performed to planarize the top surface of the insulating layer 380a. CMP treatment is suitable as the planarization treatment. Alternatively, etch-back treatment may be performed. By performing the planarization treatment on the insulating layer 380a, the surface on which the conductive layer 355 is to be formed can be planarized, and discontinuity of the conductive layer 355 can be suppressed. Note that the planarization treatment is not necessarily performed, in which case the manufacturing cost can be reduced.

[0431] Subsequently, as shown in FIG. 23, an insulating layer 380b is formed on the conductive layer 355 and the insulating layer 380a, a conductive layer 340a is formed on the insulating layer 380b, and a conductive layer 340b is formed on the conductive layer 340a.

[0432] 23 , an opening 390 reaching the conductive layer 320 is formed in the conductive layer 340b, the conductive layer 340a, the insulating layer 380b, the conductive layer 355, and the insulating layer 380a. At this time, a recess is preferably provided in the conductive layer 320b at a position overlapping with the opening 390. By forming the opening 390, the bottom and side surfaces of the recess in the conductive layer 320b are preferably exposed.

[0433] The opening 390 can be formed by the same method as the opening 190. For example, the processing of the conductive layer 340b, the processing of the conductive layer 340a, the processing of the insulating layer 380b, the processing of the conductive layer 355, and the processing of the insulating layer 380a can be performed under the same conditions as the processing of the conductive layer 140b, the processing of the conductive layer 140a, the processing of the insulating layer 180b, the processing of the conductive layer 155, and the processing of the insulating layer 180a, respectively.

[0434] Subsequently, an insulating layer 335 is formed to cover the opening 390 and to have a region located on the conductive layer 340b. The insulating layer 335 is provided in contact with the bottom and side surfaces of the recess of the conductive layer 320b, the side surfaces of the insulating layer 380a, the side surfaces of the conductive layer 355, the side surfaces of the insulating layer 380b, the side surfaces of the conductive layer 340a, and the top and side surfaces of the conductive layer 340b. Like the insulating layer 135, the insulating layer 335 is preferably formed by a CVD method or an ALD method, and more preferably by an ALD method.

[0435] Subsequently, the insulating layer 335 is processed to expose the top surface of the conductive layer 340 and to expose the conductive layer 320 in the opening 390. It is preferable that the bottom surface of the recess of the conductive layer 320b is exposed in the opening 390. The insulating layer 335 can be processed in the same manner as the insulating layer 135.

[0436] 23 , a semiconductor layer 330 is formed to cover the opening 390 and to be in contact with the upper surface of the conductive layer 340 and the conductive layer 320. The semiconductor layer 330 is formed to cover the insulating layer 335 inside the opening 390. The semiconductor layer 330 can be formed to be in contact with the bottom and side surfaces of the recess in the conductive layer 320b, the insulating layer 335, and the upper surface of the conductive layer 340b. The semiconductor layer 330 can be formed by a method similar to that for the semiconductor layer 130.

[0437] Next, the semiconductor layer 330, the conductive layer 340a, and the conductive layer 340b are processed to remove parts of the semiconductor layer 330, the conductive layer 340a, and the conductive layer 340b. This exposes part of the top surface of the insulating layer 380b. The semiconductor layer 330, the conductive layer 340a, and the conductive layer 340b can be processed using the same mask as the semiconductor layer 130, the conductive layer 140a, and the conductive layer 140b. This is preferable because it reduces the number of masks required to manufacture a semiconductor device.

[0438] 24 , an insulating layer 350 is formed to cover the semiconductor layer 330. Specifically, the insulating layer 350 is formed to cover the semiconductor layer 330, the side surfaces of the conductive layer 340 b, the side surfaces of the conductive layer 340 a, and the top surface of the insulating layer 380 b. The insulating layer 350 can be formed by a method similar to that for the insulating layer 250.

[0439] 24, a conductive layer 365a is formed on the insulating layer 350 so as to have a region located inside the opening 390. Furthermore, a conductive layer 365b is formed on the conductive layer 365a. The conductive layer 365a is preferably formed so as to fill the opening 390. Specifically, the conductive layer 365a is preferably formed so as to fill the recessed portion of the insulating layer 350. Note that depending on the diameter of the opening 390 and the thickness of the conductive layer 365a, the conductive layer 365b may also be formed inside the opening 390. The conductive layer 365 can be formed by a method similar to that for the conductive layer 320.

[0440] Through the above steps, the transistor 300 including the conductive layer 320, the conductive layer 340, the conductive layer 355, the conductive layer 365, the semiconductor layer 330, the insulating layer 335, and the insulating layer 350 can be formed. In addition, the memory cell 10 including the transistor 100, the transistor 200, and the transistor 300 can be manufactured. Furthermore, a semiconductor device including the memory cell 10 can be manufactured.

[0441] When manufacturing the memory cell 10H, the steps up to the formation of the insulating layer 350 are performed by the same manufacturing method as described above. Next, a sacrificial layer is formed so as to have a region located inside the opening 390. Next, an insulating layer 383 is formed so as to cover the insulating layer 350 and the sacrificial layer, and an insulating layer 385 is formed on the insulating layer 383. Next, a planarization treatment is performed on the insulating layer 385, the insulating layer 383, and the sacrificial layer. This exposes the top surface of the sacrificial layer, and the top surfaces of the sacrificial layer, the insulating layer 383, and the insulating layer 385 are planarized. Next, the sacrificial layer is removed. This forms an opening 370 in the insulating layer 383. Then, a conductive layer 365 is formed so as to have a region located inside the opening 390 and the opening 370. In this manner, the memory cell 10H can be manufactured.

[0442] When manufacturing the memory cell 10I, the steps up to the formation of the semiconductor layer 330 are performed by the same manufacturing method as described above. Next, a sacrificial layer is formed so as to have a region located inside the opening 390. Next, an insulating layer 383 is formed so as to cover the insulating layer 380b, the conductive layer 240, the semiconductor layer 330, and the sacrificial layer, and an insulating layer 385 is formed on the insulating layer 383. Next, a planarization treatment is performed on the insulating layer 385, the insulating layer 383, and the sacrificial layer. This exposes the top surface of the sacrificial layer, and the top surfaces of the sacrificial layer, the insulating layer 383, and the insulating layer 385 are planarized. Next, the sacrificial layer is removed. This forms an opening 370 in the insulating layer 383.

[0443] Next, an insulating layer 350 is formed to cover the openings 370 and 390, and a conductive layer 360 is formed over the insulating layer 350. Next, planarization treatment is performed on the conductive layer 360 and the insulating layer 350. As a result, the top surfaces of the insulating layer 383 and the insulating layer 385 are exposed, and the top surfaces of the conductive layer 360, the insulating layer 350, the insulating layer 383, and the insulating layer 385 are planarized. Then, a conductive layer 365 is formed over the insulating layer 383, the insulating layer 385, and the conductive layer 360. In this manner, the memory cell 10I can be manufactured.

[0444] This embodiment mode can be combined with other embodiment modes as appropriate. In addition, in this specification, when a plurality of configuration examples are shown in one embodiment mode, the configuration examples can be combined as appropriate.

[0445] Embodiment 2 In this embodiment, an oxide semiconductor layer that can be used as a semiconductor layer of a transistor will be described.

[0446] [Oxide Semiconductor Layer] The oxide semiconductor layer of one embodiment of the present invention preferably includes a crystalline metal oxide. Examples of the structure of a crystalline metal oxide include a c-axis aligned crystal (CAAC) structure, a polycrystalline (poly-crystal) structure, and a nanocrystalline (nc) structure. By using a crystalline metal oxide for the oxide semiconductor layer, the density of defect states in the oxide semiconductor layer can be reduced. Therefore, the reliability of a transistor including the oxide semiconductor layer of one embodiment of the present invention can be improved, and the reliability of a semiconductor device including the transistor can be improved.

[0447] The oxide semiconductor layer of one embodiment of the present invention preferably includes a metal oxide having a CAAC structure. The CAAC structure is a crystal structure in which a plurality of microcrystals (typically, a plurality of microcrystals having a hexagonal crystal structure) have c-axis orientation and are connected without being oriented in the a-b plane. Furthermore, when a cross section of an oxide semiconductor layer having a CAAC structure is observed using a high-resolution transmission electron microscope (TEM) image, it can be confirmed that metal atoms are arranged in a layered manner in the crystal parts. Therefore, the oxide semiconductor layer having a CAAC structure can also be said to have a structure having layered crystal parts.

[0448] The crystallinity of the oxide semiconductor layer can be analyzed by, for example, X-ray diffraction (XRD), TEM, or electron diffraction (ED). Alternatively, a combination of these methods may be used for analysis.

[0449] Note that the crystallinity of the semiconductor material included in the oxide semiconductor layer is not particularly limited. For example, the oxide semiconductor layer may include one or more of an amorphous semiconductor (a semiconductor having an amorphous structure), a single-crystal semiconductor (a semiconductor having a single-crystal structure), or a semiconductor having crystallinity other than single crystal (a microcrystalline semiconductor, a polycrystalline semiconductor, or a semiconductor having a crystalline region in part). When the oxide semiconductor layer has crystallinity, deterioration of transistor characteristics can be suppressed in some cases.

[0450] Examples of metal oxides contained in the oxide semiconductor layer of one embodiment of the present invention include indium oxide, gallium oxide, and zinc oxide. The metal oxide according to one embodiment of the present invention preferably contains at least indium (In) or zinc (Zn). The metal oxide preferably contains two or three elements selected from indium, an element M, and zinc. The element M is a metal element or a metalloid element having a high bond energy with oxygen, e.g., a metal element or a metalloid element having a bond energy with oxygen higher than that of indium. Specific examples of the element M include aluminum, gallium, tin, yttrium, titanium, vanadium, chromium, manganese, iron, cobalt, nickel, zirconium, molybdenum, hafnium, tantalum, tungsten, lanthanum, cerium, neodymium, magnesium, calcium, strontium, barium, boron, silicon, germanium, and antimony. The element M contained in the metal oxide is preferably one or more of the above elements, more preferably one or more selected from aluminum, gallium, tin, and yttrium, and even more preferably gallium. When the element M contained in the metal oxide is gallium, the metal oxide according to one embodiment of the present invention preferably contains one or more selected from indium, gallium, and zinc. Note that in this specification and the like, metal elements and metalloid elements may be collectively referred to as "metal elements," and the "metal elements" described in this specification and the like may also include metalloid elements.

[0451] Examples of metal oxides according to one embodiment of the present invention include indium zinc oxide (In—Zn oxide), indium tin oxide (In—Sn oxide), indium titanium oxide (In—Ti oxide), indium gallium oxide (In—Ga oxide), indium gallium aluminum oxide (In—Ga—Al oxide), indium gallium tin oxide (In—Ga—Sn oxide, also referred to as IGTO), gallium zinc oxide (Ga—Zn oxide, also referred to as GZO), aluminum zinc oxide (Al—Zn oxide, also referred to as AZO), and indium gallium tin oxide (In—Ga—Sn oxide, also referred to as IGTO). Examples of usable oxides include indium aluminum zinc oxide (In-Al-Zn oxide, also referred to as IAZO), indium tin zinc oxide (In-Sn-Zn oxide), indium titanium zinc oxide (In-Ti-Zn oxide), indium gallium zinc oxide (In-Ga-Zn oxide, also referred to as IGZO), indium gallium tin zinc oxide (In-Ga-Sn-Zn oxide, also referred to as IGZTO), and indium gallium aluminum zinc oxide (In-Ga-Al-Zn oxide, also referred to as IGAZO or IAGZO). Alternatively, examples of usable oxides include indium tin oxide containing silicon (also referred to as ITSO), gallium tin oxide (Ga-Sn oxide), and aluminum tin oxide (Al-Sn oxide).

[0452] By increasing the ratio of the number of indium atoms to the total number of atoms of all metal elements contained in the metal oxide, the transistor can have a large on-state current and high frequency characteristics.

[0453] Note that the metal oxide may contain one or more metal elements having a higher period number in the periodic table instead of indium. Alternatively, the metal oxide may contain one or more metal elements having a higher period number in the periodic table in addition to indium. The greater the overlap of the orbitals of metal elements, the greater the carrier conduction in the metal oxide tends to be. Therefore, by including a metal element having a higher period number in the periodic table, the field-effect mobility of a transistor may be improved. Examples of metal elements having a higher period number in the periodic table include metal elements belonging to the fifth period and the sixth period. Specific examples of such metal elements include yttrium, zirconium, silver, cadmium, tin, antimony, barium, lead, bismuth, lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium. Lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium are called light rare earth elements.

[0454] The metal oxide may contain one or more nonmetallic elements, which may increase the field-effect mobility of the transistor. Examples of nonmetallic elements include carbon, nitrogen, phosphorus, sulfur, selenium, fluorine, chlorine, bromine, and hydrogen.

[0455] Furthermore, by increasing the ratio of the number of zinc atoms to the sum of the numbers of atoms of all metal elements contained in the metal oxide, the metal oxide can be made highly crystalline, and the diffusion of impurities in the metal oxide can be suppressed, thereby suppressing fluctuations in the electrical characteristics of the transistor and improving its reliability.

[0456] Furthermore, by increasing the ratio of the number of atoms of element M to the sum of the numbers of atoms of all metal elements contained in the metal oxide, the formation of oxygen vacancies in the metal oxide can be suppressed. Therefore, carrier generation due to oxygen vacancies can be suppressed, and a transistor with a small off-state current can be obtained. Furthermore, fluctuations in the electrical characteristics of the transistor can be suppressed, thereby improving reliability.

[0457] In the present embodiment, an In—Ga—Zn oxide may be used as an example of the metal oxide.

[0458] The oxide semiconductor layer of one embodiment of the present invention can be manufactured by forming a metal oxide by two different deposition methods. For example, the oxide semiconductor layer of one embodiment of the present invention can be manufactured by forming a metal oxide by a first deposition method and a second deposition method. Note that an oxide semiconductor layer formed by two different deposition methods may be referred to as a hybrid OS.

[0459] The oxide semiconductor layer of one embodiment of the present invention has crystallinity and preferably has a CAAC structure.

[0460] In the formation of an oxide semiconductor layer according to one embodiment of the present invention, a crystalline metal oxide is deposited by the first deposition method. The deposited metal oxide preferably has a CAAC structure. For example, a metal oxide deposited by a sputtering method is likely to have crystallinity.

[0461] When a metal oxide is formed using the first film-forming method, a mixed layer may be formed at the interface between the metal oxide and a layer on which the metal oxide is to be formed. For example, when a sputtering method is used as the first film-forming method, the mixed layer may be formed by particles (also called sputtering particles) emitted from a target or the like, or by energy imparted to the substrate by the sputtering particles. There is a concern that the mixed layer may inhibit the crystallization of the metal oxide.

[0462] For example, when an insulating layer having silicon, such as silicon oxide, is used as a surface to be formed, silicon may be mixed into the metal oxide when a metal oxide is formed on the silicon oxide using the first film formation method, and there is a concern that the mixing of impurities such as silicon into the metal oxide may inhibit the crystallization of the metal oxide.

[0463] Therefore, in one embodiment of the present invention, before forming a metal oxide by the first film formation method, a metal oxide is formed by the second film formation method. That is, after forming a metal oxide as a first layer by the second film formation method, a metal oxide is formed as a second layer on the first layer by the first film formation method. In this case, it is preferable to use a film formation method that causes less damage to the formation surface than the first film formation method as the second film formation method. By using a film formation method that causes less damage to the formation surface as the second film formation method, formation of a mixed layer at the interface between the oxide semiconductor layer and a layer on which the oxide semiconductor layer is to be formed can be suppressed. Furthermore, since the incorporation of impurities such as silicon into the second layer can be suppressed, the crystallinity of the second layer can be potentially improved. For example, atomic layer deposition (ALD) and chemical vapor deposition (CVD) are suitable as the second film formation method because they can suppress damage to the surface to be formed compared to sputtering.

[0464] In addition, for example, a metal oxide having a microcrystalline structure or an amorphous structure with lower crystallinity than a CAAC structure may be formed as the first layer. By forming a second layer with high crystallinity on the first layer with low crystallinity, or by forming the second layer and then performing heat treatment, the crystallinity of the first layer may be increased using the second layer as a nucleus. This may increase the crystallinity of the entire oxide semiconductor layer, including the vicinity of the interface with the surface on which it is formed.

[0465] In the oxide semiconductor layer of one embodiment of the present invention, it is preferable that a metal oxide be first formed over a surface to be formed by the second film formation method, and then a metal oxide be formed above the metal oxide by the first film formation method.

[0466] The first film formation method includes, for example, a sputtering method and a PLD method.

[0467] Examples of the second film formation method include an ALD method, a plasma enhanced CVD (PECVD) method, a thermal CVD method, a photo-assisted CVD method, a metal organic CVD (MOCVD) method, and a molecular beam epitaxy (MBE) method. The MBE method is a film formation method that grows a thin film having a crystalline structure that reflects the crystalline system of the substrate, and can be said to be one of the film formation methods that causes little damage to the surface on which the film is formed. Furthermore, a wet method can be used as the second film formation method. The wet method is one of the film formation methods that causes little damage to the surface on which the film is formed. An example of the wet method is a spray coating method.

[0468] For example, the oxide semiconductor layer of one embodiment of the present invention can be manufactured by forming a metal oxide as a first layer by the second deposition method and then forming a metal oxide as a second layer by the first deposition method. Specifically, an ALD method can be used as the second deposition method, and a sputtering method can be used as the first deposition method. The metal oxide formed by the first deposition method preferably has a CAAC structure.

[0469] Furthermore, a third layer can be further formed on the second layer. Because the second layer has high crystallinity, the third layer can grow crystals using the crystals of the second layer as nuclei or seeds. Therefore, even if a film formation method that easily imparts crystallinity is not used as a film formation method for the third layer, the third layer can be crystallized. Here, for example, by forming the third layer using a film formation method that has higher coverage than the second layer, the oxide semiconductor layer can have both high crystallinity and high coverage throughout the layer.

[0470] Furthermore, the second layer has excellent crystallinity because the influence of the surface on which it is formed is reduced by providing the first layer, and therefore the third layer, which is crystallized using the second layer as a nucleus or seed, is also expected to have excellent crystallinity.

[0471] The third layer is an uppermost layer of the oxide semiconductor layer, and is in contact with, for example, a gate insulating film when the oxide semiconductor layer is used as a semiconductor layer of a transistor. By increasing the crystallinity of the layer in contact with the gate insulating film, carrier mobility can be increased when the transistor is in an on state.

[0472] For example, the oxide semiconductor layer of one embodiment of the present invention can be manufactured by forming a metal oxide as a first layer by the second deposition method, forming a metal oxide as a second layer by the first deposition method, and forming a metal oxide as a third layer by the second deposition method. Specifically, an ALD method can be used as the second deposition method, and a sputtering method can be used as the first deposition method. Furthermore, the metal oxide formed by the first deposition method preferably has a CAAC structure. The ALD method has better coverage than the sputtering method. By using the ALD method for the first and third layers, the coverage of the oxide semiconductor layer can be improved. Therefore, the oxide semiconductor layer can be well covered over steps or openings with a high aspect ratio.

[0473] [Method for Forming Oxide Semiconductor Layer] Described below is an example of a method for forming the oxide semiconductor layer 430. Here, the oxide semiconductor layer 430 can be applied to, for example, the semiconductor layer 130, the semiconductor layer 230, and the semiconductor layer 330 described in the above embodiments.

[0474] The oxide semiconductor layer 430 can be manufactured, for example, by forming an oxide semiconductor 430a over a layer 429 that is a surface to be formed by an ALD method, forming an oxide semiconductor 430b over the oxide semiconductor 430a by a sputtering method, and forming an oxide semiconductor 430c over the oxide semiconductor 430b by an ALD method. After the oxide semiconductor layer 430 is formed, heat treatment is preferably performed. The heat treatment can improve the crystallinity of the oxide semiconductor layer 430. The heat treatment here is not limited to heat treatment. For example, it may be heat applied during the manufacturing process. The layer 429 is an insulating film, such as a silicon oxide film, a silicon oxynitride film, a silicon nitride film, a silicon nitride oxide film, an aluminum oxide film, or a hafnium oxide film. Here, the layer 429 corresponds to one or more of the conductive layer 120, the insulating layer 135, the conductive layer 140, the conductive layer 220, the conductive layer 240, the conductive layer 320, the insulating layer 335, the conductive layer 340, and the like shown in the above embodiment.

[0475] The layer 429 does not necessarily have crystallinity. When the layer 429 has crystallinity, the layer 429 may have a crystal structure with low lattice matching with a metal oxide included in the oxide semiconductor layer 430.

[0476] An example of a method for manufacturing the oxide semiconductor layer 430 will be described with reference to FIGS. 25A to 26D.

[0477] First, an oxide semiconductor 430a is formed on the layer 429 (FIG. 25A). Then, an oxide semiconductor 430b is formed on the oxide semiconductor 430a (FIG. 25B).

[0478] The oxide semiconductor 430b is preferably formed by a sputtering method and has a composition suitable for forming a CAAC structure.

[0479] The oxide semiconductor 430a is preferably formed by a deposition method that causes less damage to a surface on which the oxide semiconductor 430a is formed than the oxide semiconductor 430b. Here, the oxide semiconductor 430a is formed by an ALD method.

[0480] When a metal oxide film is formed by sputtering, damage to the surface on which the metal oxide film is formed may cause alloying between components contained in the metal oxide film and components contained in the layer on which the metal oxide film is formed. When alloying occurs, it is difficult to improve the crystallinity of the alloyed region even when heat treatment, which will be described later, is performed. Furthermore, there is a concern that using an oxide semiconductor layer having an alloyed region in a transistor may adversely affect the initial characteristics or reliability of the transistor. Therefore, it is preferable to suppress alloying between components contained in the metal oxide film and components contained in the layer on which the metal oxide film is formed.

[0481] In a method for forming an oxide semiconductor layer according to one embodiment of the present invention, the oxide semiconductor 430a is formed over the layer 429, and then the oxide semiconductor 430b is formed by a sputtering method. The oxide semiconductor 430a is preferably formed by a deposition method that causes little damage to a surface on which the oxide semiconductor 430a is to be formed. By forming the oxide semiconductor 430a between the oxide semiconductor 430b and the layer 429 by a deposition method that causes little damage to the surface on which the oxide semiconductor 430a is to be formed, alloying of components contained in the oxide semiconductor layer 430 and components contained in the layer 429 can be suppressed, and the crystallinity of the oxide semiconductor layer 430 can be further improved.

[0482] With this structure, the thickness of the alloyed region can be reduced, or can be reduced to such a degree that the alloyed region is not observable. For example, the thickness of the alloyed region can be set to 0 nm or more and 3 nm or less, preferably 0 nm or more and 2 nm or less, more preferably 0 nm or more and 1 nm or less, and further preferably 0 nm or more and less than 0.3 nm. Note that FIGS. 25A and 25B show an example in which no alloyed region is formed between the layer 429 and the oxide semiconductor 430a.

[0483] The thickness of the alloyed region may be calculated by performing a line analysis of the composition of the alloyed region and its surroundings using SIMS or energy dispersive X-ray spectroscopy (EDX).

[0484] For example, EDX line analysis is performed on the region and its periphery, with the direction perpendicular to the surface of the oxide semiconductor 430a being the depth direction. Next, in the profile of the quantitative values ​​of each element in the depth direction obtained by this analysis, the depth at which the quantitative value of a metal (e.g., In if the oxide semiconductor 430a contains In) that is the main component of the oxide semiconductor 430a but is not the main component of the layer that will become the surface (here, layer 429) becomes half-maximum is defined as the depth (position) of the interface between the region and the oxide semiconductor 430a. Furthermore, the depth at which the quantitative value of an element (e.g., Si) that is the main component of the layer that will become the surface but is not the main component of the oxide semiconductor 430a becomes half-maximum is defined as the depth (position) of the interface between the region and the layer that will become the surface. From the above, the thickness of the alloyed region can be calculated.

[0485] In the oxide semiconductor layer of one embodiment of the present invention, when the thickness of the alloyed region is observed by EDX analysis, the thickness is, for example, 0 nm to 3 nm, preferably 0 nm to 2 nm, more preferably 0 nm to 1 nm, and still more preferably 0 nm to less than 0.3 nm.

[0486] For example, when a silicon oxide layer is used as the layer 429 and the oxide semiconductor layer 430 formed over the layer 429 is subjected to SIMS analysis, the depth at which the silicon concentration is 50% of the maximum concentration of the layer 429 is defined as the interface, and the silicon concentration is 1.0×10 ２１ atoms / cm ３ , preferably 5.0 × 10 ２０ atoms / cm ３ , more preferably 1.0 × 10 ２０ atoms / cm ３ The distance between the depth at which the thickness decreases to 3 nm and the interface is defined as thickness t_s2. The thickness t_s2 is preferably 3 nm or less, and more preferably 2 nm or less.

[0487] By reducing the thickness of the alloyed region, the thickness t_s2 can be set to a value within the above range.

[0488] Note that by reducing the alloyed region, it is possible to form a CAAC structure near the formation surface. Here, the vicinity of the formation surface refers to, for example, a region of the oxide semiconductor layer 430 that is approximately perpendicular to the formation surface and is located between more than 0 nm and 3 nm, preferably between more than 0 nm and 2 nm, more preferably between 1 nm and 2 nm.

[0489] Note that the CAAC structure near the formation surface can be confirmed in some cases by observation using a TEM. For example, in cross-sectional observation of the oxide semiconductor layer 430 using a high-resolution TEM, bright spots arranged in layers in a direction parallel to the formation surface are confirmed near the formation surface.

[0490] When the oxide semiconductor 430a is formed by an ALD method, an oxide semiconductor layer having a microcrystalline structure or an amorphous structure with lower crystallinity than that of a CAAC structure may be formed. That is, at the manufacturing stage shown in FIG. 25A , the oxide semiconductor 430a may have a region with lower crystallinity than the oxide semiconductor 430b.

[0491] After the oxide semiconductor 430a is formed by an ALD method, an In-M-Zn oxide is formed as the oxide semiconductor 430b over the oxide semiconductor 430a by a sputtering method.

[0492] Here, when the oxide semiconductor 430b is formed by sputtering, the mixed layer 431 is formed on or near the surface of the oxide semiconductor 430a. Furthermore, sputtering particles or energy imparted to the substrate by the sputtering particles or the like during the formation of the oxide semiconductor 430b may form minute crystalline regions in the mixed layer 431. In a subsequent heat treatment step, the mixed layer 431 or the minute crystalline regions formed in the mixed layer 431 may act as nuclei, causing at least a part of the oxide semiconductor 430a to crystallize.

[0493] An In-Mn-Zn oxide can be used as a target for sputtering. When forming a metal oxide by sputtering, oxygen or a mixed gas of oxygen and a noble gas can be used as a sputtering gas. In addition, by increasing the proportion of oxygen contained in the sputtering gas, the amount of excess oxygen in the oxide film to be formed can be increased.

[0494] Furthermore, the higher the ratio of the flow rate of oxygen gas to the total film-forming gas used during deposition (hereinafter also referred to as oxygen flow rate ratio), the more crystalline the metal oxide that can be formed.

[0495] When a metal oxide is formed by a sputtering method, an oxygen-excess metal oxide may be formed when the percentage of oxygen contained in the sputtering gas is set to more than 30% and less than or equal to 100%, preferably 70% to 100%. A transistor using an oxygen-excess oxide semiconductor layer for a channel formation region can have relatively high reliability. However, one embodiment of the present invention is not limited thereto. An oxygen-deficient metal oxide is formed when the percentage of oxygen contained in the sputtering gas is set to 1% to 30%, preferably 5% to 20%. A transistor using an oxygen-deficient metal oxide for a channel formation region can have relatively high field-effect mobility.

[0496] In the formation of the oxide semiconductor 430b by a sputtering method, it is preferable to heat the substrate. In the formation of the metal oxide, a metal oxide with high crystallinity can be formed by increasing the substrate temperature (stage temperature) during the formation of the metal oxide. In the formation of the oxide semiconductor 430b by a sputtering method, the substrate heating temperature is preferably from 100° C. to 400° C., more preferably from 200° C. to 300° C., for example.

[0497] Through the above steps, as illustrated in FIG. 25B, an oxide semiconductor 430a and an oxide semiconductor 430b can be formed over the layer 429.

[0498] Next, the oxide semiconductor 430c is formed over the oxide semiconductor 430b (FIG. 25C). Here, the oxide semiconductor 430c is formed by an ALD method. For the formation of the oxide semiconductor 430c by an ALD method, the method for forming the oxide semiconductor 430a can be referred to.

[0499] When the oxide semiconductor 430c is formed on the oxide semiconductor 430b having the CAAC structure by an ALD method, the oxide semiconductor 430c may grow epitaxially using the oxide semiconductor 430b as a nucleus. Therefore, the oxide semiconductor 430c may have a region having the CAAC structure when the oxide semiconductor 430c is formed. In addition, the region having the CAAC structure is preferably formed over the entire oxide semiconductor 430c.

[0500] Next, a heat treatment step may be carried out.

[0501] The heat treatment can be performed at a temperature of, for example, 100° C. to 800° C., preferably 250° C. to 650° C., and more preferably 350° C. to 550° C. Typically, the heat treatment can be performed at 400° C.±25° C. (375° C. to 425° C.). The treatment time can be 10 hours or less, or 1 minute to 5 hours, or 1 minute to 2 hours. When an RTA apparatus is used, the treatment time can be, for example, 1 second to 5 minutes. It is expected that the heat treatment can repair atomic-level gaps in the crystal portions of the CAAC structure of the oxide semiconductor 430b with the oxide semiconductor 430c (in other words, crystal molecules formed by the ALD method).

[0502] The heating device used for the heat treatment is not particularly limited, and may be a device that heats the workpiece by heat conduction or heat radiation from a heating element such as a resistance heating element. For example, an electric furnace or an RTA (Rapid Thermal Ann...

Claims

a first semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, a first insulating layer, a second insulating layer, a third insulating layer, a fourth insulating layer, and a fifth insulating layer; the first insulating layer overlies the first conductive layer; the second conductive layer is located on the first insulating layer; the second insulating layer is located on the second conductive layer and on the first insulating layer; the third conductive layer is located on the second insulating layer; the first insulating layer, the second conductive layer, the second insulating layer, and the third conductive layer have a first opening reaching the first conductive layer; the third insulating layer contacts a side surface of the second conductive layer inside the first opening, the first semiconductor layer is in contact with the first conductive layer; the first semiconductor layer is in contact with an upper surface of the third conductive layer; the first semiconductor layer has a first region facing the second conductive layer with the third insulating layer interposed therebetween within the first opening; the first region is at least partially in contact with the third insulating layer; the fourth insulating layer is located inside the first opening and on the inner side of the first semiconductor layer; the fifth insulating layer is provided so as to fill the first opening on the inner side of the fourth insulating layer and is planarized; the first semiconductor layer has a second region overlapping the third conductive layer; A semiconductor device, wherein an upper surface of the fifth insulating layer is located above an upper surface of the first semiconductor layer in the second region. 　 In claim 1, A sixth insulating layer and a seventh insulating layer, the sixth insulating layer covers a side surface of the third conductive layer opposite to a side surface of the third conductive layer on the first opening side; The seventh insulating layer is located on the sixth insulating layer. 　 In claim 1, a second semiconductor layer, a fourth conductive layer, a fifth conductive layer, a sixth conductive layer, a sixth insulating layer, and a seventh insulating layer; the fourth conductive layer is located on the fifth insulating layer; the fourth conductive layer is in contact with the second region; the sixth insulating layer is located on the fourth conductive layer; the fifth conductive layer is located on the sixth insulating layer; the sixth insulating layer and the fifth conductive layer have a second opening reaching the fourth conductive layer; the second semiconductor layer has a region in contact with the fourth conductive layer and the fifth conductive layer and located inside the second opening, the seventh insulating layer is located on the second semiconductor layer and is located inside the second opening portion relative to the second semiconductor layer; The sixth conductive layer is located on the seventh insulating layer and is located inside the second opening relative to the seventh insulating layer. 　 In claim 3, a third semiconductor layer, a seventh conductive layer, an eighth conductive layer, an eighth insulating layer, and a ninth insulating layer; the eighth insulating layer overlies the sixth conductive layer; the seventh conductive layer is located on the eighth insulating layer; the eighth insulating layer and the seventh conductive layer have a third opening reaching the sixth conductive layer; the third semiconductor layer has a region that is in contact with the sixth conductive layer and the seventh conductive layer and is located inside the third opening, the ninth insulating layer is located on the third semiconductor layer and is located inside the third opening relative to the third semiconductor layer; The eighth conductive layer is located on the ninth insulating layer and is located inside the third opening relative to the ninth insulating layer. 　 In claim 4, a ninth conductive layer and a tenth insulating layer; the eighth insulating layer includes an eleventh insulating layer and a twelfth insulating layer on the eleventh insulating layer; the ninth conductive layer is located on the eleventh insulating layer; the twelfth insulating layer is located on the ninth conductive layer and on the eleventh insulating layer; the eleventh insulating layer, the ninth conductive layer, and the twelfth insulating layer have the third opening; the tenth insulating layer contacts a side surface of the ninth conductive layer inside the third opening, the third semiconductor layer is in contact with the tenth insulating layer inside the third opening, The third semiconductor layer faces the eighth conductive layer across the ninth insulating layer, and has a third region facing the ninth conductive layer across the tenth insulating layer. 　 In any one of claims 1 to 5, The first semiconductor layer is made of a metal oxide, The metal oxide has two or three elements selected from indium, an element M, and zinc, The element M is one or more elements selected from aluminum, gallium, tin, yttrium, titanium, vanadium, chromium, manganese, iron, cobalt, nickel, zirconium, molybdenum, hafnium, tantalum, tungsten, lanthanum, cerium, neodymium, magnesium, calcium, strontium, barium, boron, silicon, germanium, and antimony. 　 In any one of claims 3 to 5, The first semiconductor layer and the second semiconductor layer each include a metal oxide; The metal oxide has two or three elements selected from indium, an element M, and zinc, The element M is one or more elements selected from aluminum, gallium, tin, yttrium, titanium, vanadium, chromium, manganese, iron, cobalt, nickel, zirconium, molybdenum, hafnium, tantalum, tungsten, lanthanum, cerium, neodymium, magnesium, calcium, strontium, barium, boron, silicon, germanium, and antimony. 　 In claim 4 or 5, a metal oxide is used for each of the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer; The metal oxide has two or three elements selected from indium, an element M, and zinc, The element M is one or more elements selected from aluminum, gallium, tin, yttrium, titanium, vanadium, chromium, manganese, iron, cobalt, nickel, zirconium, molybdenum, hafnium, tantalum, tungsten, lanthanum, cerium, neodymium, magnesium, calcium, strontium, barium, boron, silicon, germanium, and antimony. 　 forming a first conductive layer; forming a first insulating layer on the first conductive layer; forming a second conductive layer on the first insulating layer; forming a second insulating layer on the second conductive layer and on the first insulating layer; forming a third conductive layer on the second insulating layer; forming a first opening portion through the third conductive layer, the second insulating layer, the second conductive layer, and the first insulating layer, the first opening portion reaching the first conductive layer; forming a third insulating layer to cover the first opening; the third insulating layer is processed by anisotropic etching to expose an upper surface of the third conductive layer and the first conductive layer; forming a first semiconductor layer so as to cover the third insulating layer and to be in contact with an upper surface of the third conductive layer and the first conductive layer; forming a fourth insulating layer so as to cover the first semiconductor layer; forming a fifth insulating layer on the fourth insulating layer to have a region located within the first opening; performing a planarization process on the fifth insulating layer until at least a portion of an upper surface of the fourth insulating layer is exposed, thereby forming a sixth insulating layer having a region located inside the first opening; removing a portion of the fourth insulating layer to form a seventh insulating layer having a region located inside the first opening and exposing at least a portion of an upper surface of the first semiconductor layer; forming a fourth conductive layer in contact with an upper surface of the sixth insulating layer and an upper surface of the first semiconductor layer; forming an eighth insulating layer on the fourth conductive layer; forming a fifth conductive layer on the eighth insulating layer; forming a second opening portion in the fifth conductive layer and the eighth insulating layer, the second opening portion reaching the fourth conductive layer; forming a second semiconductor layer so as to cover the second opening and to be in contact with the fourth conductive layer and the fifth conductive layer; forming a ninth insulating layer so as to cover the second semiconductor layer; A method for manufacturing a semiconductor device, comprising forming a sixth conductive layer over the ninth insulating layer so as to have a region located inside the second opening. 　 In claim 9, forming a tenth insulating layer on the sixth conductive layer; forming a seventh conductive layer on the tenth insulating layer; forming a third opening portion in the seventh conductive layer and the tenth insulating layer, the third opening portion reaching the sixth conductive layer; forming a third semiconductor layer so as to cover the third opening and to be in contact with the sixth conductive layer and the seventh conductive layer; forming an eleventh insulating layer so as to cover the third semiconductor layer; A method for manufacturing a semiconductor device, comprising the steps of: forming an eighth conductive layer over the eleventh insulating layer so as to have a region located inside the third opening. 　 In claim 9, forming a tenth insulating layer on the sixth conductive layer; forming a seventh conductive layer on the tenth insulating layer; forming an eleventh insulating layer on the seventh conductive layer and on the tenth insulating layer; forming an eighth conductive layer on the eleventh insulating layer; forming a third opening portion through the eighth conductive layer, the eleventh insulating layer, the seventh conductive layer, and the tenth insulating layer, the third opening portion reaching the sixth conductive layer; forming a twelfth insulating layer so as to cover the third opening; the twelfth insulating layer is processed by anisotropic etching to expose an upper surface of the eighth conductive layer and the sixth conductive layer; forming a third semiconductor layer so as to cover the twelfth insulating layer and to be in contact with an upper surface of the eighth conductive layer and the sixth conductive layer; forming a thirteenth insulating layer so as to cover the third semiconductor layer; A method for manufacturing a semiconductor device, comprising the steps of: forming a ninth conductive layer over the thirteenth insulating layer so as to have a region located inside the third opening. 　 In any one of claims 9 to 11, A method for manufacturing a semiconductor device, comprising: performing a planarization treatment on the fifth insulating layer; and then processing the fourth insulating layer to remove at least a portion of a region of the fourth insulating layer that does not overlap with the sixth insulating layer. 　 In any one of claims 9 to 11, performing a planarization process on the fifth insulating layer to form a fourth opening in the fifth insulating layer so as to overlap with the first semiconductor layer; A method for manufacturing a semiconductor device, comprising the steps of: processing the fourth insulating layer to remove a region of the fourth insulating layer that does not overlap with any of the fifth insulating layer and the sixth insulating layer.

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