Delay device, memory control system, delay method, and program

Abstract

In this delay device (100-i), an operation time calculation unit (106-i) calculates the operation time it takes for another memory, which is connected to another delay device, to complete an operation of the other memory, on the basis of the latency of the operation of the other memory and the execution time of that operation, as calculated on the basis of a signal that is input by a first input unit (102-i) and that indicates the operation of the other memory. On the basis of a delay amount calculated by the other delay device and the operation time of the other memory, as indicated by a signal input by a second input unit (103-i), a delay amount calculation unit (107-i) calculates the delay amount of the timing at which to output a signal input by a first input / output unit (101-i) in order for the memory connected to the delay device (100-i) to start the operation indicated by the signal input by the first input / output unit (101-i) at the timing at which the operation of the other memory is completed. An adjustment unit (108-i) adjusts the timing at which the signal input by the first input / output unit (101-i) is output from a second input / output unit (104-i), on the basis of the delay amount.

Description

Delay device, memory control system, delay method and program

[0001] The present disclosure relates to a delay device, a memory control system, a delay method, and a program.

[0002] In recent years, industrial equipment such as programmable logic controllers (PLCs) has been required to perform highly accurate and large-scale control. To achieve such control, it is essential to increase the speed of the industrial equipment's computational performance. To achieve this, techniques for improving the throughput between a central processing unit (CPU) and memory are known. For example, Patent Document 1 discloses a technique for arranging a data collision avoidance circuit within a memory control device to avoid data collisions between multiple main memories, such as double data rate (DDR)-synchronous dynamic random access memory (SDRAM).

[0003] JP 2009-093227 A

[0004] In the above technology, a circuit for avoiding data collisions is built into the memory control device, so it must be installed inside the memory control device during the manufacturing stage, and therefore the above technology cannot be applied to memory control devices manufactured in accordance with existing memory standards. On the other hand, a highly versatile method that can be applied to existing memory control devices is required.

[0005] The present disclosure has been made in consideration of the above circumstances, and aims to provide a delay device, memory control system, delay method, and program that can improve the throughput between a CPU and memory by being attached externally to a memory control device.

[0006] In order to achieve the above object, the delay device according to the present disclosure is a delay device in a memory control system comprising: a plurality of memories whose operations are defined based on the state of signals at terminals; a plurality of memory control devices that control the operations of the memories; and a plurality of delay devices that relay signals between the memories and the memory control devices, wherein the memory control devices are connected to one or more CPUs via one system bus, and each of the delay devices comprises a first input / output means that inputs / outputs a signal to / from the memory control device; a first input means that inputs a signal indicating the operation of another memory connected to the other delay device; a second input means that inputs / outputs a signal to / from the memory; and a delay device that relays a signal between the other memory and the memory control device based on the latency of the operation of the other memory and the execution time of the operation, which are calculated based on the signal input by the first input means. a delay amount calculation means for calculating a delay amount for outputting the signal input by the first input / output means, based on the delay amount indicated by the signal input by the second input means and the operation time of the other memory calculated by the operation time calculation means, so that the memory starts the operation indicated by the signal input by the first input / output means from the memory control device at the timing when the operation of the other memory is completed; an adjustment means for adjusting the timing at which the signal input by the first input / output means is output from the second input / output means, based on the delay amount calculated by the delay amount calculation means; and an output means for outputting the delay amount calculated by the delay amount calculation means to the other delay device, and the second input / output means outputs the signal input by the first input / output means, the timing of which has been adjusted by the adjustment means, to the memory.

[0007] According to the present disclosure, it is possible to provide a delay device, a memory control system, a delay method, and a program that can improve the throughput between a CPU and a memory by being attached externally to a memory control device.

[0008] FIG. 1 is a block diagram showing the configuration of a memory control system including N delay devices according to a first embodiment; FIG. 2 is a block diagram showing the configuration of a memory control system including two delay devices according to a first embodiment; FIG. 3 is a diagram showing the functional configuration of a delay device according to a first embodiment; FIG. 4 is a diagram showing an example of a timing chart of a signal input from a memory control device according to a first embodiment to a delay device; FIG. 5 is a diagram showing an example of a timing chart of a signal output from a delay device according to a first embodiment to a memory;

[0009] 1, a memory control system 1 according to the first embodiment includes a plurality of delay devices 100-i (i is a natural number equal to or less than N, and N is a natural number equal to or greater than 2), a plurality of memory control devices 200-i, and a plurality of memories 300-i. The memory control devices 200-i of the memory control system 1 are connected to CPUs j (j is a natural number equal to or less than M, and M is a natural number equal to or greater than 1) via one system bus 10. The delay devices 100-i are connected to the memory control devices 200-i via first buses 11-i, and are connected to the memories 300-i via second buses 12-i.

[0010] In the memory control system 1, one memory 300-i is provided with one delay device 100-i, one memory control device 200-i, one first bus 11-i, and one second bus 12-i, and one memory 300-i, one delay device 100-i, one memory control device 200-i, one first bus 11-i, and one second bus 12-i constitute one memory control system. In the memory control system 1, there is no restriction on the number of the memory control systems.

[0011] The delay device 100-i is a device that relays signals between the memory control device 200-i and the memory 300-i. As will be described later, the delay device 100-i calculates a delay amount, delays a signal input from the memory control device 200-i by the calculated delay amount, and outputs the signal to the memory 300-i, thereby preventing collisions of signals output from the memories 300-1, ..., 300-N.

[0012] The memory control device 200-i is a device that controls the operation of the memory 300-i. The memory control device 200-i, for example, outputs an operation clock signal and transmits and receives read and write data. The memory control device 200-i is also connected to one or more CPUs 400-j via a single system bus 10, and transmits and receives data exchanged between the CPUs 400-j and the memory 300-i via the system bus 10.

[0013] The memory 300-i is a memory whose operation is defined based on the state of a signal at a terminal, and whose latency until the operation is executed is specified. For example, the memory 300-i is a memory that falls into the category of DDR-SDRAM. In this embodiment, the memory 300-i is a DDR4-SDRAM. In the memory control system 1, the frequencies of the operating clock signals of the memories 300-i must be the same, but phase differences between the operating clock signals are allowed.

[0014] For example, DDR4-SDRAM terminals include CKE, CS, ACT, RAS, CAS, WE, AP, AD, BG, and BA. In DDR4-SDRAM, commands such as mode register set, read, and write are defined depending on the state of these terminals, and the operations are defined by the commands. Furthermore, in DDR4-SDRAM, due to its specifications, latency occurs between the reception of a command to execute an operation such as read or write and the actual operation. The latency value is uniquely determined by the value specified in the mode register set command. This latency is one of the factors that causes a decrease in transmission efficiency between the CPU and main memory.

[0015] 2 shows a case where the memory control system 1 includes two memory control systems and is connected to one CPU 400-1, that is, where N is 2 and M is 1. Below, the function of the delay device 100-i will be explained using the configuration of FIG. 2 as an example.

[0016] 3 shows the functional configuration of the delay device 100-i. Functionally, the delay device 100-i includes a first input / output unit 101-i, a first input unit 102-i, a second input unit 103-i, a second input / output unit 104-i, an output unit 105-i, an operation time calculation unit 106-i, a delay amount calculation unit 107-i, and an adjustment unit 108-i. The first input / output unit 101-i, the first input unit 102-i, the second input unit 103-i, the second input / output unit 104-i, and the output unit 105-i function as interfaces with external circuits including the memory control device 200-i and the memory 300-i. The operation time calculation unit 106-i, the delay amount calculation unit 107-i, and the adjustment unit 108-i are functions realized by the internal circuitry of the delay device 100-i.

[0017] First, the first input / output unit 101-i, the first input unit 102-i, the second input unit 103-i, the second input / output unit 104-i, and the output unit 105-i, which function as interfaces with external circuits, will be described.

[0018] The first input / output unit 101-i inputs and outputs signals to and from the memory control device 200-i. The first input / output unit 101-i is an example of a first input / output means.

[0019] 2, the first input / output unit 101-1 of the delay device 100-1 inputs / outputs signals to / from the memory control device 200-1 via the first bus 11-1, and the first input / output unit 101-2 of the delay device 100-2 inputs / outputs signals to / from the memory control device 200-2 via the first bus 11-2.

[0020] The first input unit 102-i inputs and outputs signals indicating the operation of other memories connected to other delay devices. Specifically, the first input unit 102-i inputs a signal indicating the operation of memory 300-(i-1) (when i is 2 or greater and N or less) or memory 300-N (when i is 1). Here, when i is 2 or greater and N or less, the first input unit 102-i inputs a signal indicating the operation of memory 300-(i-1) from the second bus 12-(i-1) connecting the second input / output unit 104-(i-1) of the delay device 100-(i-1) and the memory 300-(i-1); when i is 1, the first input unit 102-i inputs a signal indicating the operation of memory 300-N from the second bus 12-N connecting the second input / output unit 104-N of the delay device 100-N and the memory 300-N. The first input unit 102-i is an example of a first input means.

[0021] 2, the first input unit 102-2 of the delay device 100-2 inputs a signal indicating the operation of the memory 300-1 from the second bus 12-1 connecting the second input / output unit 104-1 of the delay device 100-1 and the memory 300-1. Also, the first input unit 102-1 of the delay device 100-1 inputs a signal indicating the operation of the memory 300-2 from the second bus 12-2 connecting the second input / output unit 104-2 of the delay device 100-2 and the memory 300-2.

[0022] In addition, when i is greater than or equal to 2 and less than or equal to N, the first input unit 102-i may input a signal indicating the operation of the memory 300-(i-1) from the first bus 11-(i-1) connecting the memory control device 200-(i-1) and the first input / output unit 101-(i-1) of the delay device 100-(i-1), or when i is 1, may input a signal indicating the operation of the memory 300-N from the first bus 11-N connecting the memory control device 200-N and the first input / output unit 101-N of the delay device 100-N.

[0023] For example, the first input unit 102-2 of the delay device 100-2 inputs a signal indicating the operation of the memory 300-1 from the first bus 11-1 connecting the memory control device 200-1 and the first input / output unit 101-1 of the delay device 100-1. Also, the first input unit 102-1 of the delay device 100-1 inputs a signal indicating the operation of the memory 300-2 from the first bus 11-2 connecting the memory control device 200-2 and the first input / output unit 101-2 of the delay device 100-2.

[0024] The second input unit 103-i inputs a signal indicating the delay amount calculated by another delay device. Specifically, the second input unit 103-i inputs a signal indicating the delay amount calculated by the delay device 100-(i-1) (when i is 2 or more and N or less) or the delay device 100-N (when i is 1). The second input unit 103-i is an example of a second input means.

[0025] 2, the signal indicating the delay amount calculated by delay device 100-1 is output from output unit 105-1, and the second input unit 103-2 of delay device 100-2 receives the signal indicating the output delay amount. Also, the signal indicating the delay amount calculated by delay device 100-2 is output from output unit 105-2, and the second input unit 103-1 of delay device 100-1 receives the signal indicating the output delay amount.

[0026] The second input / output unit 104-i inputs and outputs signals to and from the memory 300-i. The second input / output unit 104-i is an example of a second input / output means.

[0027] 2, the second input / output unit 104-1 of the delay device 100-1 inputs / outputs signals to / from the memory 300-1 via the second bus 12-1, and the second input / output unit 104-2 of the delay device 100-2 inputs / outputs signals to / from the memory 300-2 via the second bus 12-2.

[0028] The output unit 105-i outputs the delay amount calculated by the delay amount calculation unit 107-i to another delay device. Specifically, the output unit 105-i outputs the delay amount calculated by the delay amount calculation unit 107-i to the delay device 100-(i+1) (when i is 1 or more and N-1 or less) or the delay device 100-1 (when i is N). The output unit 105-i is an example of an output means.

[0029] For example, output section 105-1 of delay device 100-1 outputs the delay amount calculated by delay amount calculation section 107-1 to delay device 100-2, and output section 105-2 of delay device 100-2 outputs the delay amount calculated by delay amount calculation section 107-2 to delay device 100-1.

[0030] Next, the operation time calculation unit 106-i, the delay amount calculation unit 107-i, and the adjustment unit 108-i will be described.

[0031] Below, the function of each unit will be explained using an example in which CPU 400-j issues k memory access instructions (k is a natural number equal to or greater than 2) to memory 300-i. CPU 400-j accesses memory 300-i one by one in the execution order of the k memory access instructions. There are no restrictions on the timing at which CPU 400-j issues memory access instruction k. For example, the interval from the issuance of memory access instruction k to the issuance of memory access instruction k+1 does not need to be the same as the interval from the issuance of memory access instruction k+1 to the issuance of memory access instruction k+2.

[0032] The memory control device 200-i receives k memory access instructions issued by the CPU 400-j, and outputs a signal for controlling the operation of the memory 300-i and an operation clock signal to the delay device 100-i to access the memory 300-i required to execute the k memory access instructions.

[0033] For example, suppose three read commands are issued from CPU 400-1 to memories 300-1 and 300-2 of memory control system 1 in FIG. 2. The column address values ​​in each read command are arbitrarily different values, "CA0", "CA1", and "CA2". The row address values ​​in each read command are arbitrarily different values, "RA0", "RA1", and "RA2". The bank address values ​​in each read command are arbitrarily different values, "BA0", "BA1", and "BA2". The bank group values ​​in each read command are arbitrarily different values, "BG0", "BG1", and "BG2". It is assumed that there is no interval between the read commands from CPU 400-1 to memories 300-1 and 300-2. The interval from the ACT command to the issuance of a read command is 11 clocks. The memories 300-1 and 300-2 execute a read burst operation in accordance with the read command issued by the CPU 400-1.

[0034] The operation time calculation unit 106-i calculates the operation time required for the completion of the operation of the other memory based on the latency of the operation of the other memory and the execution time of the operation, which are calculated based on the signal input by the first input unit 102-i. Specifically, the operation time calculation unit 106-i calculates the sum of the operation latency and execution time of the operation of memory 300-(i-1) (when i is 2 or more and N or less) or memory 300-N (when i is 1) based on the signal input by the first input unit 102-i, thereby calculating the operation time required for the completion of the operation of memory 300-(i-1) (when i is 2 or more and N or less) or memory 300-N (when i is 1). The operation time calculation unit 106-i is an example of operation time calculation means.

[0035] The latency of an operation is the time required to execute an operation indicated by a signal. The execution time of an operation is the time required to execute an operation indicated by a signal. The operation time is the time required from receiving a signal indicating an operation, i.e., a command, to completing execution of the operation, and is calculated as the sum of the latency of the operation and the execution time of the operation.

[0036] First, before a memory access instruction is issued, the operation time calculation unit 106-i obtains values ​​required to calculate the latency and execution time of the operation.

[0037] For example, before three read commands are issued from the CPU 400-1, the operation time calculation unit 106-2 of the delay device 100-2 analyzes the signals input to the memory 300-1 when the mode register set command is executed to transition to MR0 mode and MR1 mode, thereby obtaining the values ​​of CAS (Column Address Strobe) latency and additive latency required to calculate the latency of the read burst operation and the value of the burst length required to calculate the execution time of the read burst operation. The latency of the read burst operation is calculated as the sum of the CAS latency and the additive latency. The execution time of the read burst operation is the issuance time of the read burst data and is calculated by dividing the burst length by 2.

[0038] Specifically, the operation time calculation unit 106-2 determines whether the memory 300-1 is operating in the MR0 mode based on the states of the signals at the terminals CKH, CS, ACT, RAS, CAS, WE, BG[1:0], and BA[1:0] among the signals input by the first input unit 102-2. For example, if CKH=H, CS=L, ACT=H, RAS=L, CAS=L, WE=L, BG[1:0]=0, and BA[1:0]=0, the operation time calculation unit 106-2 determines that the memory 300-1 is operating in the MR0 mode. Then, from the signal states of the terminals AD

[12] , AD[6:4], and AD[2] among the signals input by the first input unit 102-2, the operation time calculation unit 106-2 obtains the value of the CAS latency from the signal state of the terminal AD[1:0], and obtains the value of the burst length from the signal state of the terminal AD[1:0]. For example, the operation time calculation unit 106-2 obtains 11 clocks for the CAS latency of memory 300-1 and 8 for the burst length.

[0039] Furthermore, the operation time calculation unit 106-2 determines whether the memory 300-1 is operating in MR1 mode based on the state of the signals at the CKH, CS, ACT, RAS, CAS, WE, BG[1:0], and BA[1:0] terminals among the signals input by the first input unit 102-2. If the operation time calculation unit 106-2 determines that the memory 300-1 is operating in MR1 mode, it obtains the value of additive latency based on the state of the signal at the AD[4:3] terminal among the signals input by the first input unit 102-2. For example, the operation time calculation unit 106-2 obtains 10 clocks for additive latency.

[0040] Then, when the operation time calculation unit 106-2 determines that the operation of memory 300-1 is an operation based on a read command, it calculates the latency of the read burst operation to be 21 clocks by adding the CAS latency value and the additive latency value, and calculates the execution time of the read burst operation to be 4 clocks by dividing the burst length by 2. Then, the operation time calculation unit 106-2 calculates the operation time required to complete the read burst operation of memory 300-1 to be 25 clocks.

[0041] Furthermore, the operation time calculation unit 106-i calculates the operation latency of the memory 300-i based on the signal input by the first input / output unit 101-i.

[0042] For example, the operation time calculation unit 106-2 calculates the latency of the read burst operation for memory 300-2 by analyzing the signal input by the first input / output unit 101-2 in the same manner as for memory 300-1. For example, the operation time calculation unit 106-2 obtains the CAS latency of memory 300-2 as 11 clocks in MR0 mode and the additive latency as 10 clocks in MR1 mode. Then, the operation time calculation unit 106-2 calculates the latency of the read burst operation of memory 300-2 as 21 clocks.

[0043] Next, after a memory access instruction is issued, delay amount calculation unit 107-i of delay device 100-i calculates the amount of delay for the signal of memory access instruction k. However, for memory access instruction k, if the remainder when dividing memory access instruction number k by the number of memories that execute the memory access instruction is 1, delay amount calculation unit 107-i omits the process of calculating the amount of delay and sets the amount of delay to 0. This is because memory access instruction k, for which the remainder when dividing number k by the number of memories that execute the memory access instruction is 1, is executed by memory 300-i after execution of the previous memory access instruction has finished, and therefore there is no need to delay memory access instruction k.

[0044] 4 shows a timing chart of signals input from memory control devices 200-1 and 200-2 to delay devices 100-1 and 100-2 when the above three read commands are output from CPU 400-1. The upper part of FIG. 4 is a timing chart of signals input from memory control device 200-1 to delay device 100-1, and the lower part of FIG. 4 is a timing chart of signals input from memory control device 200-2 to delay device 100-2. In FIG. 4, "CLK", "CMD", "BG", "BA", "AD", and "DQ" respectively represent an operating clock signal, a command, a bank group address, a bank address, an address indicating a column address or a row address, and data. Also, in FIG. 4, "ACT" and "R" represent an ACT command and a read command.

[0045] CPU 400-1 accesses memories 300-1 and 300-2 one by one in the order of execution of the three read commands, so as shown in the upper part of Figure 4, read command number 1 and read command number 3 are input from memory control device 200-1 to delay device 100-1, and as shown in the lower part of Figure 4, read command number 2 is input from memory control device 200-2 to delay device 100-2.

[0046] The delay amount calculation unit 107-1 of delay device 100-1 sets the delay amount for the read command numbered 1 to 0 because the remainder when number "1" is divided by the number of memories "2" is 1. Similarly, the delay amount calculation unit 107-1 of delay device 100-1 sets the delay amount for the read command numbered 3 to 0 because the remainder when number "3" is divided by the number of memories "2" is 1. Below, the function of the delay amount calculation unit 107-i will be explained using an example where delay amount calculation unit 107-2 of delay device 100-2 calculates the delay amount for the read command numbered 2.

[0047] The delay amount calculation unit 107-i calculates the delay amount of the timing at which the memory 300-i outputs the signal input by the first input / output unit 101-i so that the memory 300-i starts the operation indicated by the signal input by the first input / output unit 101-i from the memory control device 200-i at the timing at which the operation of the other memory is completed, based on the delay amount indicated by the signal input by the second input unit 103-i and the operation time of the other memory calculated by the operation time calculation unit 106-i. Specifically, the delay amount calculation unit 107-i calculates the delay amount of the timing at which the memory 300-i outputs the signal input to the first input / output unit 101-i so that the memory 300-i starts the operation indicated by the signal input by the first input / output unit 101-i from the memory control device 200-i at the timing at which the operation of the memory 300-(i-1) (when i is 2 or more and N or less) or the memory 300-N (when i is 1) is completed, based on the delay amount indicated by the signal input by the second input unit 103-i and the operation time of the memory 300-(i-1) (when i is 2 or more and N or less) or the memory 300-N (when i is 1) calculated by the operation time calculation unit 106-i. The delay amount calculation unit 107-i is an example of a delay amount calculation means.

[0048] More specifically, the delay amount calculation unit 107-i subtracts the operational latency of memory 300-i from the operating time of memory 300-(i-1) (when i is 2 or greater and N or less) or memory 300-N (when i is 1), and adds the delay amount indicated by the signal input by second input unit 103-i to the value obtained by the subtraction, thereby calculating the delay amount in the timing of outputting the signal input by first input / output unit 101-i. This delay amount is expressed by the following equation (1). t1 is the operating time of memory 300-(i-1) (when i is 2 or greater and N or less) or memory 300-N (when i is 1). t2 is the operational latency of memory 300-i. t3 is the delay amount indicated by the signal input by the second input unit 103-i, and is the delay amount calculated by delay device 100-(i-1) (when i is 2 or greater and N or less) or delay device 100-N (when i is 1).

[0049] (Equation 1) Delay amount = t1 - t2 + t3

[0050] For example, during a read burst operation of memory 300-2 in response to a read command of number 2, the operation time (t1) of memory 300-1 in response to a read command of number 1 is 25 clocks, the operation latency (t2) of memory 300-2 is 21 clocks, and the delay amount (t3) of delay device 100-1 is 0 clocks. Therefore, delay amount calculation unit 107-2 of delay device 100-2 calculates the delay amount to be 4 clocks. Then, output unit 105-2 of delay device 100-2 outputs the delay amount of 4 clocks calculated by delay amount calculation unit 107-2 to delay device 100-1.

[0051] The adjustment unit 108-i adjusts the timing at which the signal input by the first input / output unit 101-i is output from the second input / output unit 104-i based on the delay amount calculated by the delay amount calculation unit 107-i. Note that the adjustment unit 108-i is an example of an adjustment means.

[0052] For example, the adjustment unit 108-2 delays the timing at which the signal input by the first input / output unit 101-2, i.e., the signal input from the memory control device 200-2, is output from the second input / output unit 104-2 based on the delay amount calculated by the delay amount calculation unit 107-2. Therefore, the adjustment unit 108-2 delays the timing at which the read command numbered 2 is output from the second input / output unit 104-2 by the delay amount of "4 clocks" calculated by the delay amount calculation unit 107-2. Note that if the delay amount calculation unit 107-1 sets the delay amount to 0, the adjustment unit 108-1 does not delay the timing at which the signal input by the first input / output unit 101-1, i.e., the signal input from the memory control device 200-1, is output from the second input / output unit 104-1. Therefore, the adjustment unit 108-1 does not delay the timing at which the read commands numbered 1 and 3 are output from the second input / output unit 104-1.

[0053] The second input / output unit 104-i outputs the signal input by the first input / output unit 101-i, the timing of which has been adjusted by the adjustment unit 108-i, to the memory 300-i.

[0054] 5 shows timing charts of signals output from delay devices 100-1 and 100-2 to memories 300-1 and 300-2. The upper part of Fig. 5 is a timing chart of signals output from second input / output unit 104-1 of delay device 100-1 to memory 300-1, and the lower part of Fig. 5 is a timing chart of signals output from second input / output unit 104-2 of delay device 100-2 to memory 300-2.

[0055] As shown in the lower part of FIG. 5, the read command numbered 2 output from the second input / output unit 104-2 of the delay device 100-2 to the memory 300-2 is delayed by four clocks after the interval and then output.

[0056] The memory 300-i completes its operation in accordance with the procedure defined by the memory standard in response to the signal from the delay device 100-i. The signal output from the memory 300-i after completion of the operation is input to the second input / output unit 104-i of the delay device 100-i, and then input to the first input / output unit 101-i without passing through the operation time calculation unit 106-i, delay amount calculation unit 107-i, and adjustment unit 108-i of the delay device 100-i. The signal output from the first input / output unit 101-i is then input to the CPU 400-j via the first bus 11-i, the memory control device 200-i, and the system bus 10.

[0057] For example, memory 300-1 outputs read burst data after the latency of the read burst operation, i.e., 21 clocks, has elapsed in accordance with the read command numbered 1 from delay device 100-1. Also, memory 300-2 outputs read burst data after the sum of the delay amount and the latency of the read burst operation, i.e., 25 clocks, has elapsed in accordance with the read command numbered 2 from delay device 100-2. The read burst data output from memory 300-2 passes through system bus 10 with a delay amount greater than the read burst data output from memory 300-1, thereby preventing collisions of read burst data.

[0058] Next, the delay processing according to this embodiment will be explained using Fig. 6. The delay processing in Fig. 6 is executed, for example, when the memory control system 1 and CPU 400-j are powered on, and is executed for all commands from CPU 400-j. In the following example, it is assumed that multiple memory access commands are issued from CPU 400-j.

[0059] The operation time calculation unit 106-i analyzes the signal input by the first input unit 102-i to determine whether the operation of the memory 300-(i-1) is in MR0 mode, or analyzes the signal input by the first input / output unit 101-i to determine whether the operation of the memory 300-i is in MR0 mode (step S101). If the operation time calculation unit 106-i determines that the operation of the memory 300-(i-1) or the memory 300-i is in MR0 mode (step S101; YES), it acquires the CAS latency (step S102) and further acquires the burst length (step S103). Then, the process returns to step S101.

[0060] For example, the operation time calculation unit 106-2 determines whether the memory 300-1 is operating in the MR0 mode from the states of the signals at the CKH, CS, ACT, RAS, CAS, WE, BG[1:0], and BA[1:0] terminals among the signals input by the first input unit 102-2. If the operation time calculation unit 106-2 determines that the memory 300-1 is operating in the MR0 mode, it obtains the value of the CAS latency from the states of the signals at the AD

[12] , AD[6:4], and AD[2] terminals among the signals input by the first input unit 102-2, and obtains the value of the burst length from the state of the signal at the AD[1:0] terminal. Furthermore, the operation time calculation unit 106-2 analyzes the signal input by the first input / output unit 101-2 in the same manner as in the case of the memory 300-1, thereby acquiring the CAS latency value and the burst length value for the memory 300-2. Note that the process of step S103 can be omitted for the memory 300-i.

[0061] When the operation time calculation unit 106-i determines that the operation of the memory 300-(i-1) or the memory 300-i is not in the MR0 mode (step S101; NO), it determines whether the operation of the memory 300-(i-1) or the memory 300-i is in the MR1 mode (step S104). When the operation time calculation unit 106-i determines that the operation of the memory 300-(i-1) or the memory 300-i is in the MR1 mode (step S104; YES), it acquires the additive latency (step S105) and returns to step S101.

[0062] For example, the operation time calculation unit 106-2 determines whether the memory 300-1 is operating in MR1 mode based on the signal states of the CKH, CS, ACT, RAS, CAS, WE, BG[1:0], and BA[1:0] terminals among the signals input by the first input unit 102-2. If the operation time calculation unit 106-2 determines that the memory 300-1 is operating in MR1 mode, it acquires the value of additive latency based on the signal state of the AD[4:3] terminal among the signals input by the first input unit 102-2. Furthermore, the operation time calculation unit 106-2 acquires the value of additive latency by analyzing the signal input by the first input / output unit 101-2 in the same manner as in the case of the memory 300-1.

[0063] If the operation time calculation unit 106-i determines that the operation of the memory 300-(i-1) is not in the MR1 mode (step S104; NO), it determines whether the operation of the memory 300-(i-1) is an operation based on a memory access command (step S106). If the operation time calculation unit 106-i determines that the operation of the memory 300-(i-1) is an operation based on a memory access command (step S106; YES), it calculates the operation time of the memory 300-(i-1) and calculates the latency of the operation of the memory 300-i (step S107). Next, the delay amount calculation unit 107-i calculates the delay amount in the timing of outputting the signal input to the first input / output unit 101-i (step S108). Then, the adjustment unit 108-i adjusts the timing at which the signal input by the first input / output unit 101-i is output from the second input / output unit 104-i based on the calculated delay amount (step S109), and the second input / output unit 104-i outputs the signal input to the first input / output unit 101-i, the timing of which has been adjusted by the adjustment unit 108-i, to the memory 300-i (step S110).On the other hand, if the operation time calculation unit 106-i determines that the operation of the memory 300-(i-1) is not an operation due to a memory access command (step S106; NO), the process returns to step S101.

[0064] For example, when the operation time calculation unit 106-2 determines that the operation of memory 300-1 is an operation based on the read command numbered 1, it calculates the operation time of the read burst operation of memory 300-1 based on the read command numbered 1 to be 25 clocks. Furthermore, the operation time calculation unit 106-2 calculates the latency of the read burst operation for memory 300-2 to be 21 clocks. Then, the delay amount calculation unit 107-2 of the delay device 100-2 calculates the delay amount to be 4 clocks based on Equation 1. The adjustment unit 108-2 delays the timing at which the signal input from the memory control device 200-2 is output from the second input / output unit 104-2 by the delay amount of 4 clocks calculated by the delay amount calculation unit 107-2, and the second input / output unit 104-2 outputs the read command delayed by 4 clocks to memory 300-2.

[0065] According to this embodiment, a delay device external to the memory control device can delay the timing of inputting a memory access command to a subsequent memory so as to conceal the operation latency occurring in the previous memory. Therefore, in a configuration in which one system bus is shared by multiple memories, conflicts on the system bus can be prevented. This enables continuous access to the memory, improving the throughput between the CPU and the memory.

[0066] Furthermore, according to this embodiment, the delay device that delays the signal input to the memory is not provided inside the memory control device but is externally attached, so it can be applied to existing memory control devices, providing high versatility.

[0067] Furthermore, according to this embodiment, the delay device can be applied to a system having multiple memories, making it possible to simultaneously increase memory capacity and improve throughput between the CPU and memory.

[0068] Furthermore, according to this embodiment, it is possible to have multiple CPUs, so that the interval between issuing multiple memory access instructions from the CPU can be reduced, thereby improving the throughput between the CPU and memory.

[0069] Second Embodiment A memory control system 1 according to a second embodiment is a system including the delay device 100-i shown in FIG.

[0070] The delay device 100-i functionally includes a first input / output unit 101-i, a first input unit 102-i, a second input unit 103-i, a second input / output unit 104-i, an output unit 105-i, an operation time calculation unit 106-i, a delay amount calculation unit 107-i, an adjustment unit 108-i, and a phase difference calculation unit 109-i. Below, functions different from the functions of the delay device 100-i of the first embodiment will be described.

[0071] The phase difference calculation unit 109-i calculates the phase difference between the operation clock signal of the signal input by the first input / output unit 101-i and the operation clock signal of the signal input by the first input unit 102-i. The phase difference calculation unit 109-i is an example of a phase difference calculation means.

[0072] Note that, since the phase of the operation clock signal input to memory 300-i (i is a natural number between 2 and N) is adjusted based on the operation clock signal input to memory 300-1, phase difference calculation unit 109-1 of delay device 100-1 does not perform processing to calculate a phase difference. Alternatively, delay device 100-1 does not need to include phase difference calculation unit 109-1.

[0073] For example, if the operational clock signal input to memory 300-2 is 90 degrees behind the phase of the operational clock signal input to memory 300-1, the phase difference calculation unit 109-2 calculates the phase difference to be −90 degrees, or −0.25 clocks.

[0074] The delay amount calculation unit 107-i subtracts the operation latency of the memory 300-i from the operation time of the memory 300-(i-1) (when i is 2 or more and N or less) or the memory 300-N (when i is 1), and adds the delay amount indicated by the signal input by the second input unit 103-i and the phase difference calculated by the delay amount calculation unit 107-i to the value obtained by the subtraction, thereby calculating the delay amount of the timing at which the signal input by the first input / output unit 101-i is output. The delay amount is expressed by the following equation (2). t1, t2, and t3 are the same as in the first embodiment. t4 is the phase difference between the operation clock signal of the signal input by the first input / output unit 101-i and the operation clock signal of the signal input by the first input unit 102-i.

[0075] (Equation 2) Delay amount = t1 - t2 + t3 + t4

[0076] For example, during a read burst operation of memory 300-2 in response to a read command numbered 2, the operation time (t1) of memory 300-1 in response to a read command numbered 1 is 25 clocks, the operation latency (t2) of memory 300-2 is 21 clocks, the delay amount (t3) of delay device 100-1 is 0 clocks, and the phase difference between the operation clock signal of the signal input by first input / output unit 101-2 and the operation clock signal of the signal input by first input unit 102-2 is -0.25. Therefore, delay amount calculation unit 107-2 of delay device 100-2 calculates the delay amount to 3.75 clocks. Then, output unit 105-2 of delay device 100-2 outputs the delay amount of 3.75 clocks calculated by delay amount calculation unit 107-2 to delay device 100-1.

[0077] Next, the delay processing according to this embodiment will be described. In the delay processing according to this embodiment, the phase difference calculation unit 109-i performs the following process to calculate the phase difference after step S107 and before step S108 in the flowchart of the delay processing in FIG.

[0078] The phase difference calculation unit 109-i calculates the phase difference between the operation clock signal of the signal input by the first input / output unit 101-i and the operation clock signal of the signal input by the first input unit 102-i.

[0079] For example, if the operation time calculation unit 106-2 calculates the operation time of memory 300-1 as 25 clocks and the operation latency of memory 300-2 as 21 clocks, then the phase difference calculation unit 109-2 calculates the phase difference as -0.25 clocks. Then, the delay amount calculation unit 107-2 of delay device 100-2 calculates the delay amount as 3.75 clocks based on Equation 2.

[0080] According to this embodiment, signals from the memory control device are output to the multiple memories in consideration of the phase difference between the operation clock signals output from the multiple memory control devices, so that the execution timing of the operations by the multiple memories does not overlap, thereby preventing collisions of data output from the multiple memories.

[0081] (Modifications) Although the embodiments of the present disclosure have been described above, various modifications and applications are possible when implementing the present disclosure.

[0082] In the above embodiment, the memory control system 1 is described as having the same number of delay devices 100-i as the number of memory control devices 200-i and memories 300-i. However, this is not limited to this, and a configuration in which one delay device is provided for multiple memory control devices 200-i and memories 300-i may also be used. In this case, the delay device 100 includes the first input / output units 101-i, first input units 102-i, second input units 103-i, second input / output units 104-i, output units 105-i, operation time calculation units 106-i, delay amount calculation units 107-i, and adjustment units 108-i of at least two or more of the N delay devices 100-i shown in FIG. 1. Furthermore, the delay device 100 may include the phase difference calculation units 109-i of at least two or more delay devices 100-i.

[0083] For example, the memory control system 1 may be configured such that one delay device 100 is provided for multiple memories 300-i, as shown in FIG. 8. As shown in FIG. 9, the delay device 100 includes N first input / output units 101-i, N first input units 102-i, N second input units 103-i, N second input / output units 104-i, and N output units 105-i. The delay device 100 also includes N function units 120-i, each of which includes an operation time calculation unit 106-i, a delay amount calculation unit 107-i, and an adjustment unit 108-i. In other words, the delay device 100 includes functions equivalent to the N delay devices 100-i. The delay device 100 is equipped with a third input / output unit 110-i that inputs and outputs signals to and from the memory control device 200-i via the first bus 11-i, and a fourth input / output unit 111-i that inputs and outputs signals to and from the memory 300-i via the second bus 12-i.

[0084] In the delay device 100 of Fig. 9, the third input / output unit 110-i inputs and outputs signals to the first input / output unit 101-i, and the fourth input / output unit 111-i inputs and outputs signals to the second input / output unit 104-i. Also, in the delay device 100 of Fig. 9, the first input unit 102-1 inputs a signal output from the second input / output unit 104-N or a signal output from the first input / output unit 101-N. Also, in the delay device 100 of Fig. 9, the second input unit 103-1 inputs a signal output from the output unit 105-N.

[0085] In this way, by realizing the functions of a plurality of delay devices 100-i in one delay device, it is possible to reduce the mounting area and mounting cost of the delay device.

[0086] In addition, by applying an operating program that specifies the operation of delay device 100-i or delay device 100 according to the above embodiment to an existing personal computer or information terminal device, it is also possible to cause the personal computer or information terminal device to function as delay device 100-i or delay device 100 according to the embodiment.

[0087] Furthermore, the method of distribution of such a program is arbitrary; for example, it may be stored on a computer-readable recording medium such as a CD-ROM (Compact Disk Read-Only Memory), a DVD (Digital Versatile Disk), or a memory card and distributed, or it may be distributed via a communication network such as the Internet.

[0088] The present disclosure allows various embodiments and modifications without departing from the broad spirit and scope of the present disclosure. Furthermore, the above-described embodiments are intended to explain the present disclosure and do not limit the scope of the present disclosure. That is, the scope of the present disclosure is defined by the claims, not the embodiments. Various modifications made within the scope of the claims and the meaning of equivalent disclosures are considered to be within the scope of the present disclosure.

[0089] According to the present disclosure, it is possible to provide a delay device, a memory control system, a delay method, and a program that can improve the throughput between a CPU and a memory by being attached externally to a memory control device.

[0090] 1 Memory control system, 10 System bus, 11-1, 11-2, 11-i, 11-N First bus, 12-1, 12-2, 12-i, 12-N Second bus, 100, 100-1, 100-2, 100-i, 100-N Delay device, 101-1, 101-2, 101-i, 101-N First input / output unit, 102-1, 102-2, 102-i, 102-N First input unit, 103-1, 103-2, 103-i, 103-N Second input unit, 104-1, 104-2, 104-i, 104-N Second input / output unit, 105-1, 105-2, 105-i, 105-N Output unit, 106-1, 106-2, 106-i Operation time calculation unit, 107-1, 107-2, 107-i delay amount calculation unit, 108-1, 108-2, 108-i adjustment unit, 109-1, 109-2, 109-i phase difference calculation unit, 110-1, 110-i, 110-N third input / output unit, 111-1, 111-i, 111-N fourth input / output unit, 120-1, 120-i, 120-N function unit, 200-1, 200-2, 200-i, 200-N memory control device, 300-1, 300-2, 300-i, 300-N memory, 400-1, 400-j, 400-M CPU.

Claims

1. A delay device in a memory control system comprising: a plurality of memories whose operation is defined based on the state of a signal at a terminal; a plurality of memory control devices which control the operation of the memories; and a plurality of delay devices which relay signals between the memories and the memory control devices, wherein the memory control devices are connected to one or more CPUs via a single system bus, wherein each of the delay devices has: a first input / output means for inputting / outputting a signal to / from the memory control devices; a first input means for inputting a signal indicating an operation of another memory connected to the other delay devices; a second input means for inputting a signal indicating a delay amount calculated by the other delay devices; a second input / output means for inputting / outputting a signal to / from the memory; and an operation time calculation means for calculating the operation time required for the operation of the other memories to be completed based on the latency of the operation of the other memories calculated based on the signal input by the first input means and the execution time of the operation. a delay amount calculation means for calculating a delay amount of timing for outputting the signal input by the first input / output means, based on the delay amount indicated by the signal input by the second input means and the operation time of the other memory calculated by the operation time calculation means, so that the memory starts the operation indicated by the signal input by the first input / output means from the memory control device at a timing when the operation of the other memory is completed; an adjustment means for adjusting the timing at which the signal input by the first input / output means is output from the second input / output means, based on the delay amount calculated by the delay amount calculation means; and an output means for outputting the delay amount calculated by the delay amount calculation means to the other delay device, wherein the second input / output means outputs the signal input by the first input / output means, the timing of which has been adjusted by the adjustment means, to the memory.

2. The memory control system comprises N memories i (i is a natural number equal to or less than N) (N is a natural number equal to or greater than 2), a memory control device i that controls the operation of the memory i, and a delay device i that relays signals between the memory i and the memory control device i, the memory control device i being connected to one or more CPUs via one system bus, and in the delay device i, the first input / output means inputs / outputs a signal to / from the memory control device i, the first input means inputs a signal indicating the operation of memory i-1 (when i is equal to or greater than 2 and equal to or less than N) or memory N (when i is 1), the second input means inputs a signal indicating the amount of delay calculated by delay device i-1 (when i is equal to or greater than 2 and equal to or less than N) or delay device N (when i is 1), and the second input / output means inputs / outputs a signal to / from the memory i, the operation time calculation means calculates the operation time required for the memory i-1 (when i is 2 or more and N or less) or memory N (when i is 1) to complete the operation by calculating the sum of the latency of the operation of the memory i-1 (when i is 2 or more and N or less) or memory N (when i is 1) and the execution time of the operation based on the signal input by the first input means, the delay amount calculation means calculates the delay amount of the timing at which the memory i outputs the signal input by the first input / output means to start the operation indicated by the signal input by the first input / output means from the memory i at the timing at which the operation of the memory i-1 (when i is 2 or more and N or less) or memory N (when i is 1) is completed based on the delay amount indicated by the signal input by the second input means and the operation time of the memory i-1 (when i is 2 or more and N or less) or memory N (when i is 1) calculated by the operation time calculation means, The delay device of claim 1, wherein the output means outputs the delay amount calculated by the delay amount calculation means to delay device i+1 (when i is 1 or more and N-1 or less) or delay device 1 (when i is N), and the second input / output means outputs the signal input by the first input / output means, the timing of which has been adjusted by the adjustment means, to the memory i.

3. The delay device according to claim 2, wherein the first input means of the delay device i inputs a signal indicating the operation of the memory i-1 from a bus connecting the second input / output means of the delay device i-1 and the memory i-1 when i is 2 or more and N or less, or inputs a signal indicating the operation of the memory N from a bus connecting the second input / output means of the delay device N and the memory N when i is 1.

4. The delay device described in claim 2, wherein the first input means of the delay device i inputs a signal indicating the operation of the memory i-1 from a bus connecting the memory control device i-1 and the first input / output means of the delay device i-1 when i is 2 or more and N or less, or inputs a signal indicating the operation of the memory N from a bus connecting the memory control device N and the first input / output means of the delay device N when i is 1.

5. A delay device according to any one of claims 2 to 4, wherein in the delay device i, the operation time calculation means calculates the latency of the operation of the memory i based on the signal input by the first input / output means, and the delay amount calculation means calculates the delay amount of the timing of outputting the signal input by the first input / output means by subtracting the latency of the operation of the memory i from the operation time of the memory i-1 (when i is 2 or more and is 0 or less) or memory N (when i is 1) and adding the delay amount indicated by the signal input by the second input means to the value obtained by the subtraction.

6. The delay device according to claim 5, wherein the delay device i comprises a phase difference calculation means for calculating a phase difference between an operation clock signal of a signal input by the first input / output means and an operation clock signal of a signal input by the first input means, and in the delay device i, the delay amount calculation means calculates the delay amount of the timing of outputting the signal input by the first input / output means by subtracting the latency of the operation of the memory i from the operation time of the memory i-1 (when i is 2 or more and N or less) or the memory N (when i is 1) and adding the delay amount indicated by the signal input by the second input means and the phase difference calculated by the phase difference calculation means to the value obtained by the subtraction.

7. A delay device as described in any one of claims 2 to 6, comprising the first input / output means, the first input means, the second input means, the second input / output means, the output means, the operation time calculation means, the delay amount calculation means, and the adjustment means of at least two or more of the delay devices i out of the N delay devices i.

8. A memory control system comprising: N delay devices i according to any one of claims 2 to 7; the N memories i; and N memory control devices i for controlling the N memories i.

9. A memory control system comprising a plurality of memories whose operations are defined based on the state of signals at terminals, a plurality of memory control devices which control the operations of the memories, and a plurality of delay devices which relay signals between the memories and the memory control devices, wherein the memory control devices are connected to one or more CPUs via a single system bus, wherein each of the delay devices calculates an operation time required for the other memories to complete their operation based on the latency of the operation of the other memories, which is calculated based on a signal input by a first input means which inputs a signal indicating an operation of the other memories connected to the other delay devices, and an execution time of the operation; and calculates an amount of delay for outputting a signal input by the first input / output means, so that the memory starts an operation indicated by a signal input by a first input / output means which inputs / outputs signals to the memory control devices, at the timing when the operation of the other memories is completed, based on an amount of delay indicated by a signal input by a second input means which inputs a signal indicating the amount of delay calculated by the other delay devices, and the operation time of the other memories; A delay method comprising: adjusting a timing at which a signal input by the first input / output means is output from a second input / output means that inputs and outputs signals to the memory based on the delay amount calculated by the delay device; outputting the delay amount calculated by the delay device to the other delay device; and outputting the signal input to the first input / output means, the timing of which has been adjusted, to the memory by the second input / output means.

10. A program that causes a computer to function as a delay device that controls the operation of a plurality of memories, the operation of which is defined based on the state of a terminal signal, and relays signals between a plurality of memory control devices that are connected to one or more CPUs via a single system bus, comprising: a first input / output means that inputs / outputs signals to / from the memory control devices; a first input means that inputs a signal indicating the operation of another memory connected to another delay device; a second input means that inputs a signal indicating the amount of delay calculated by the other delay device; a second input / output means that inputs / outputs signals to / from the memories; an operation time calculation means that calculates the operation time required for the operation of the other memories to be completed based on the latency of the operation of the other memories calculated based on the signal input by the first input means and the execution time of the operation; a delay amount calculation means for calculating a delay amount of timing for outputting the signal input by the first input / output means, so that the memory starts the operation indicated by the signal input by the first input / output means from the memory control device at a timing when the operation of the other memory is completed, based on the delay amount indicated by the signal input by the second input means and the operation time of the other memory calculated by the operation time calculation means; an adjustment means for adjusting the timing at which the signal input by the first input / output means is output from the second input / output means, based on the delay amount calculated by the delay amount calculation means; and an output means for outputting the delay amount calculated by the delay amount calculation means to the other delay device, wherein the second input / output means outputs the signal input to the first input / output means, the timing of which has been adjusted by the adjustment means, to the memory.

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