Multilayer ceramic capacitor

Abstract

Provided is a multilayer ceramic capacitor that can be reduced in size with increased capacity and also has high reliability.　In a laminate 10 of the multilayer ceramic capacitor, when a region in which internal electrode layers 30 overlap with one another when viewed from a lamination direction T is defined as an effective part 11, facing regions which sandwich the effective part 11 from the width direction W are respectively defined as a first side surface-side outer layer portion WG1 and a second side surface-side outer layer portion WG2, and facing regions which sandwich the effective part 11, the first side surface-side outer layer portion WG1, and the second side surface-side outer layer portion WG2 from the lamination direction T are respectively defined as a first main surface-side outer layer portion TG1 and a second main surface-side outer layer portion TG2, the porosity Pw (%) of the first side surface-side outer layer portion or the second side surface-side outer layer portion, and the porosity Pwt (%) of the first main surface-side outer layer portion TG1 or the second main surface-side outer layer portion TG2 satisfy the relational formula (1).　(1): 1.6 ≤ Pwt - Pw ≤ 3.1

Description

Multilayer ceramic capacitors

[0001] The present invention relates to a multilayer ceramic capacitor.

[0002] Conventionally, multilayer ceramic capacitors have been widely used in electronic devices such as mobile phones and portable music players. These capacitors comprise an inner layer portion in which a plurality of dielectric layers and a plurality of internal electrode layers made of ceramic material are laminated to form a capacitance, outer layer portions disposed on both sides of the inner layer portion in the lamination direction, and side margin portions disposed on both sides of the inner layer portion in the width direction.

[0003] In recent years, with the trend toward smaller size and higher performance of electronic devices, etc., there has been a demand for smaller size and larger capacitance of multilayer ceramic capacitors. To achieve smaller size and higher capacitance in multilayer ceramic capacitors, one possible approach is to reduce the thickness of the side margins and increase the area of ​​the internal electrode layers. However, reducing the thickness of the side margins reduces the resistance to moisture that penetrates between the side surfaces of the laminate and the external electrodes and reaches the internal electrode layers on the end faces of the laminate, i.e., moisture resistance, and as a result, it is thought that reliability will decrease.

[0004] Therefore, there is a need to develop a multilayer ceramic capacitor that is highly reliable while being miniaturized and having a large capacitance.

[0005] JP 2014-150240 A

[0006] An object of the present invention is to provide a multilayer ceramic capacitor that is miniaturized, has a large capacitance, and yet has high reliability.

[0007] The present inventors have discovered that in a multilayer ceramic capacitor comprising a laminate including a plurality of laminated dielectric layers and a plurality of internal electrode layers, and external electrodes arranged to be conductive with the internal electrode layers, by adjusting the pore ratio Pw of the first side surface side outer layer portion or the second side surface side outer layer portion and the pore ratio Pwt of the first main surface side outer layer portion or the second main surface side outer layer portion so as to satisfy a predetermined relationship, moisture resistance can be improved and high reliability can be obtained while achieving miniaturization and an increase in capacitance, and have completed the present invention.

[0008] That is, the present invention provides a multilayer ceramic capacitor comprising a laminate including a plurality of laminated dielectric layers and a plurality of internal electrode layers, and external electrodes arranged to be conductive with the internal electrode layers, wherein the laminate comprises a first main surface and a second main surface facing each other in a lamination direction in which the dielectric layers and the internal electrode layers are laminated, a first side surface and a second side surface facing each other in a width direction that is a direction intersecting both the lamination direction and a length direction in which the internal electrode layers extend to the external electrodes, and a first end surface and a second end surface facing each other in a length direction that is a direction intersecting both the lamination direction and the width direction, and the external electrodes are arranged on each of the first end surface and the second end surface, In the laminate, when a region where the internal electrode layers overlap each other as viewed from the stacking direction is defined as an effective portion, opposing regions sandwiching the effective portion in the width direction are defined as a first side surface side outer layer portion and a second side surface side outer layer portion, opposing regions sandwiching the effective portion in the length direction are defined as a first end surface side outer layer portion and a second end surface side outer layer portion, and opposing regions sandwiching the effective portion, the first side surface side outer layer portion, the second side surface side outer layer portion, the first end surface side outer layer portion, and the second end surface side outer layer portion in the stacking direction are defined as a first main surface side outer layer portion and a second main surface side outer layer portion, a pore ratio Pw(%) of the first side surface side outer layer portion or the second side surface side outer layer portion and a pore ratio Pwt(%) of the first main surface side outer layer portion or the second main surface side outer layer portion satisfy the following relational expression (1). 1.6≦Pwt−Pw≦3.1 (1)

[0009] According to the present invention, even when the size and capacity are reduced, the outer layer portion on the side surface of the laminate is formed from a dense dielectric, thereby preventing the intrusion of moisture from the outside, and thus making it possible to provide a multilayer ceramic capacitor with high moisture resistance reliability.

[0010] 1 is an external perspective view of a multilayer ceramic capacitor 1 of the present invention. FIG. 1 is a cross-sectional view of the multilayer ceramic capacitor 1 taken along line II-II shown in FIG. 1. FIG. 1 is a cross-sectional view of the multilayer ceramic capacitor 1 taken along line III-III shown in FIG. 1. FIG. 2 is a cross-sectional view of the multilayer ceramic capacitor 1 taken along line IV-IV shown in FIG. 3. FIG. 3 is a cross-sectional view of the multilayer ceramic capacitor 1 taken along line V-V shown in FIG. 3. FIG. 4 is an exploded perspective view illustrating the stacking state of the laminate 10 of the multilayer ceramic capacitor 1. FIG. 5 is a flowchart illustrating a method for manufacturing the multilayer ceramic capacitor 1. FIG. 6 is a perspective view of a material sheet 203 in which internal electrode layer patterns 103 that become internal electrode layers 30 of the multilayer ceramic capacitor 1 are printed on the surface of a ceramic green sheet 101. FIG. 7 is a perspective view showing a state in which a ceramic paste 102 is arranged on the material sheet 203. FIG. 8 is a view illustrating the stacking state of the material sheet 203.

[0011] Hereinafter, a multilayer ceramic capacitor will be described as an embodiment of the present invention, but the present invention is not limited thereto. Furthermore, the drawings may be drawn in a simplified schematic form to explain the contents of the invention, and the dimensional ratios of the depicted components or between the components may not match the dimensional ratios of those components described in the specification. Furthermore, components described in the specification may be omitted in the drawings, or the number of components may be omitted.

[0012] FIG. 1 is a schematic perspective view of a multilayer ceramic capacitor 1 according to an embodiment. FIG. 2 is a cross-sectional view of the multilayer ceramic capacitor 1 taken along line II-II in FIG. 1. FIG. 3 is a cross-sectional view of the multilayer ceramic capacitor 1 taken along line III-III in FIG. 1. FIG. 4 is a cross-sectional view of the multilayer ceramic capacitor 1 taken along line IV-IV in FIG. 3. FIG. 5 is a cross-sectional view of the multilayer ceramic capacitor 1 taken along line V-V in FIG. 3. FIG. 6 is an exploded perspective view illustrating the lamination state of a laminate 10 of the multilayer ceramic capacitor 1. Note that line II-II passes through the center of the multilayer ceramic capacitor 1 in a length direction L, which will be described later, and line III-II passes through the center of the multilayer ceramic capacitor 1 in a width direction W, which will be described later.

[0013] In the following description, the direction in which a pair of external electrodes 40 are provided is referred to as the length direction L, and the direction in which the dielectric layers 20 and the internal electrode layers 30 are stacked is referred to as the stacking direction T. The direction intersecting both the length direction L and the stacking direction T is referred to as the width direction W. In the embodiment, the length direction L, the stacking direction T, and the width direction W are mutually orthogonal. The cross section shown in FIG. 2 is also referred to as a WT cross section because it is parallel to the width direction W and the length direction L. The cross section shown in FIG. 3 is also referred to as an LT cross section because it is parallel to the length direction L and the stacking direction T. The cross sections shown in FIGS. 4 and 5 are also referred to as LW cross sections because they are parallel to the length direction L and the width direction W.

[0014] (Multilayer Ceramic Capacitor 1) The multilayer ceramic capacitor 1 includes a laminate 10 including a plurality of laminated dielectric layers 20 and a plurality of laminated internal electrode layers 30, and a pair of external electrodes 40 provided on both ends of the laminate 10.

[0015] (Laminate 10) The laminate 10 has a substantially rectangular parallelepiped shape. It is preferable that the corners and ridges of the laminate 10 are rounded. A corner is a portion where three surfaces of the laminate intersect, and a ridge is a portion where two surfaces of the laminate intersect. Note that the dimension of the laminate 10 in the length direction L is not necessarily longer than the dimension in the width direction W. Furthermore, unevenness may be formed on part or all of the surfaces constituting the laminate 10.

[0016] The dimensions of the laminate 10 are not particularly limited, but if the dimension of the laminate 10 in the length direction L is defined as the L dimension, the L dimension is preferably 0.2 mm or more and 10 mm or less. If the dimension of the laminate 10 in the stacking direction T is defined as the T dimension, the T dimension is preferably 0.1 mm or more and 10 mm or less. If the dimension of the laminate 10 in the width direction W is defined as the W dimension, the W dimension is preferably 0.1 mm or more and 10 mm or less.

[0017] As shown in Figures 1 to 3, the laminate 10 has a first main surface TS1 and a second main surface TS2 that face each other in the stacking direction T, a first side surface WS1 and a second side surface WS2 that face each other in a width direction W that intersects with the stacking direction T, and a first end surface LS1 and a second end surface LS2 that face each other in a length direction L that intersects with the stacking direction T and the width direction W.

[0018] (Dielectric Layers 20) The dielectric layers 20 stacked in the laminate 10 can be made of a ceramic material. Examples of the ceramic material include BaTiO ３ The dielectric ceramic mainly contains the above-mentioned compound. Alternatively, the ceramic material may contain at least one of a manganese compound, an iron compound, a chromium compound, a cobalt compound, a nickel compound, and the like.

[0019] The thickness of the dielectric layer 20 is preferably 0.5 μm or more and 72 μm or less. The number of laminated dielectric layers 20 is preferably 10 or more and 700 or less. The number of dielectric layers 20 is the total number of the dielectric layers of the effective portion 11 and the dielectric layers of the main surface side outer layer portion TG constituted by the first main surface side outer layer portion TG1 and the second main surface side outer layer portion TG2.

[0020] (Internal electrode layer 30) The multiple internal electrode layers 30 stacked in the laminate 10 are composed of first internal electrode layers 31 and second internal electrode layers 32. The multiple first internal electrode layers 31 are arranged on the multiple dielectric layers 20, and similarly, the multiple second internal electrode layers 32 are arranged on the multiple dielectric layers 20. The multiple first internal electrode layers 31 and the multiple second internal electrode layers 32 are arranged alternately in the stacking direction T of the laminate 10.

[0021] The first internal electrode layer 31 has a first opposing portion 31A opposing the second internal electrode layer 32, and a first lead portion 31B led from the first opposing portion 31A to the first end face LS1. The first lead portion 31B is exposed at the first end face LS1.

[0022] The second internal electrode layer 32 has a second opposing portion 32A opposing the first internal electrode layer 31 and a second lead portion 32B led from the second opposing portion 32A to the second end face LS2. The second lead portion 32B is exposed at the second end face LS2.

[0023] The first internal electrode layer 31 and the second internal electrode layer 32 are made of an appropriate conductive material, such as a metal such as Ni, Cu, Ag, Pd, or Au, or an alloy containing at least one of these metals. When an alloy is used, the first internal electrode layer 31 and the second internal electrode layer 32 may be made of, for example, an Ag-Pd alloy.

[0024] The thickness of each of the first internal electrode layers 31 and the second internal electrode layers 32 is preferably, for example, about 0.2 μm or more and 3.0 μm or less. The total number of the first internal electrode layers 31 and the second internal electrode layers 32 is preferably 5 or more and 350 or less.

[0025] (External Electrode 40) The external electrode 40 is composed of a first external electrode 40A and a second external electrode 40B.

[0026] The first external electrode 40A is disposed on the first end face LS1 side. The first external electrode 40A is connected to the first internal electrode layer 31. The first external electrode 40A is disposed on the first end face LS1. However, in addition to the first end face LS1, the first external electrode 40A may also be disposed on at least one of the first main face TS1, the second main face TS2, the first side face WS1, and the second side face WS2. In this embodiment, the first external electrode 40A is disposed on the first end face LS1 as well as on a portion of the first main face TS1, a portion of the second main face TS2, a portion of the first side face WS1, and a portion of the second side face WS2. Note that the first external electrode 40A may be disposed, for example, from the first end face LS1 to either the first main face TS1 or the second main face TS2. That is, the cross-sectional shape of the first external electrode 40A may be L-shaped (not shown).

[0027] The second external electrode 40B is disposed on the second end face LS2 side. The second external electrode 40B is connected to the second internal electrode layer 32. The second external electrode 40B is disposed on the second end face LS2. However, in addition to the second end face LS2, the second external electrode 40B may also be disposed on at least one of the first main face TS1, the second main face TS2, the first side face WS1, and the second side face WS2. In this embodiment, the second external electrode 40B is disposed on the second end face LS2 as well as on a portion of the first main face TS1, a portion of the second main face TS2, a portion of the first side face WS1, and a portion of the second side face WS2. Note that the second external electrode 40B may be disposed, for example, from the second end face LS2 to either the first main face TS1 or the second main face TS2. That is, the cross-sectional shape of the second external electrode 40B may be L-shaped (not shown).

[0028] In the laminate 10, a capacitance is formed by the first opposing portion 31A of the first internal electrode layer 31 and the second opposing portion 32A of the second internal electrode layer 32 facing each other via the dielectric layer 20. Therefore, a capacitor function is exerted between the first external electrode 40A connected to the first internal electrode layer 31 and the second external electrode 40B connected to the second internal electrode layer 32.

[0029] The first external electrode 40A and the second external electrode 40B can be formed, for example, by a base electrode layer and a plating layer disposed on the base electrode layer. The base electrode layer is formed by applying a conductive paste containing a metal component and a glass component to the first end surface LS1 and the second end surface LS2 of the laminate 10, followed by baking. Examples of the metal component contained in the conductive paste include metals such as Cu, Ni, Ag, Pd, and Au, and alloys such as Ag and Pd.

[0030] The plating layer disposed on the base electrode layer contains, for example, at least one of metals such as Cu, Ni, Ag, Pd, and Au, or an alloy such as Ag and Pd. The plating layer may have a two-layer structure of, for example, a Ni plating layer and a Sn plating layer. However, the plating layer may be a single layer or multiple layers.

[0031] The laminate 10 has, as regions constituting the laminate 10, an effective portion 11 where the internal electrode layers 30 overlap each other when viewed from the stacking direction T to form a capacitance, a main surface side outer layer portion TG that sandwiches this from the stacking direction T, a side surface side outer layer portion WG that sandwiches it from a width direction W that intersects with the stacking direction T, and an end surface side outer layer portion LG that sandwiches it from a length direction L that intersects with the stacking direction T and the width direction W.

[0032] (Effective portion 11) The effective portion 11 is a portion within the laminate 10 where the first opposing portion 31A of the first internal electrode layer 31 and the second opposing portion 32A of the second internal electrode layer 32 face each other via the dielectric layer 20, thereby generating capacitance and essentially functioning as a capacitor.

[0033] (Side surface outer layer portion WG) The side surface outer layer portion WG is composed of a first side surface outer layer portion WG1 and a second side surface outer layer portion WG2. The first side surface outer layer portion WG1 is located between the effective portion 11 and the first side surface WS1 and includes the dielectric layer 20. The second side surface outer layer portion WG2 is located between the effective portion 11 and the second side surface WS2 and includes the dielectric layer 20. FIG. 2 shows the ranges of the first side surface outer layer portion WG1 and the second side surface outer layer portion WG2 in the WT cross section of the multilayer ceramic capacitor 1. The side surface outer layer portion WG is also called a W gap, a side gap, or a side margin portion.

[0034] (End-Side Outer Layer Portion LG) The end-side outer layer portion LG is composed of a first end-side outer layer portion LG1 and a second end-side outer layer portion LG2. The first end-side outer layer portion LG1 is located between the effective portion 11 and the first end face LS1 and includes the dielectric layer 20. The second end-side outer layer portion LG2 is located between the effective portion 11 and the second end face LS2 and includes the dielectric layer 20. FIG. 3 shows the ranges of the first end-side outer layer portion LG1 and the second end-side outer layer portion LG2 in the LT cross section of the multilayer ceramic capacitor 1. The end-side outer layer portion LG is also referred to as an L gap, end gap, or end margin portion.

[0035] (Main surface side outer layer portion TG) The laminate 10 has a main surface side outer layer portion TG consisting of a first main surface side outer layer portion TG1 and a second main surface side outer layer portion TG2 in opposing regions that sandwich the effective portion 11, the first side surface side outer layer portion WG1, the second side surface side outer layer portion WG2, the first end surface side outer layer portion LG1, and the second end surface side outer layer portion LG2 in the stacking direction T.

[0036] The first main surface side outer layer portion TG1 is located on the first main surface TS1 side of the laminate 10. The first main surface side outer layer portion TG1 can be formed by stacking a plurality of dielectric layers 20 as ceramic layers located between the first main surface TS1 and the internal electrode layer 30 closest to the first main surface TS1. The dielectric layer 20 used in the first main surface side outer layer portion TG1 may be the same as the dielectric layer 20 used in the active portion 11.

[0037] The second main surface side outer layer portion TG2 is located on the second main surface TS2 side of the laminate 10. The second main surface side outer layer portion TG2 can be formed by stacking a plurality of dielectric layers 20 as ceramic layers located between the second main surface TS2 and the internal electrode layer 30 closest to the second main surface TS2. The dielectric layer 20 used in the second main surface side outer layer portion TG2 may be the same as the dielectric layer 20 used in the effective portion 11.

[0038] The pore ratio Pw (%) of the first side surface side outer layer portion or the second side surface side outer layer portion and the pore ratio Pwt (%) of the first main surface side outer layer portion or the second main surface side outer layer portion satisfy the following relational expression (1): 1.6≦Pwt−Pw≦3.1 (1)

[0039] The pore ratio Pw of the first side surface side outer layer portion WG1 or the second side surface side outer layer portion WG2 can be determined by calculating the proportion of the area occupied by pores in a WT cross section of a region located at the center in the width direction W and the center in the stacking direction T of the first side surface side outer layer portion WG1 located between the effective portion 11 and the first side surface WS1 or the second side surface side outer layer portion WG2 located between the effective portion 11 and the second side surface WS2. A specific method involves imaging the target WT cross section with a scanning electron microscope (SEM), determining the field of view and the area occupied by pores from analysis of the captured SEM image, and then calculating the pore ratio Pw (%) using the formula: area occupied by pores / area of ​​field of view × 100.

[0040] The pore ratio Pwt of the first main surface side outer layer portion TG1 or the second main surface side outer layer portion TG2 can be determined by calculating the proportion of the area occupied by pores in a WT cross section of a region located in the stacking direction T from the region where the pore ratio Pw was measured in the first side surface side outer layer portion WG1 located between the effective portion 11 and the first side surface WS1 or the second side surface side outer layer portion WG2 located between the effective portion 11 and the second side surface WS2. A specific method involves imaging the target WT cross section with a scanning electron microscope (SEM), determining the field of view and the area occupied by pores from analysis of the captured SEM image, and then calculating the pore ratio Pwt (%) using the formula: area occupied by pores / area of ​​field of view × 100.

[0041] As shown in the relational expression (1), by making the pore ratio Pw smaller than the pore ratio Pwt by a predetermined amount and improving the density of the dielectric layer 20 in the first side surface side outer layer portion WG1 or the second side surface side outer layer portion WG2, it is possible to suppress the penetration of moisture from the outside and improve moisture resistance.

[0042] The pore ratio Pl (%) of the first end face side outer layer portion or the second end face side outer layer portion and the pore ratio Plt (%) of the first main surface side outer layer portion or the second main surface side outer layer portion satisfy the following relational expression (2): 1.6≦Plt−Pl≦3.1 (2)

[0043] The pore fraction Pl of the dielectric constituting the first end face side outer layer portion LG1 or the second end face side outer layer portion LG2 can be determined by calculating the proportion of the area occupied by pores in an LT cross section of a region of the dielectric located at the center in the length direction L and the center in the stacking direction T of the first end face side outer layer portion LG1 located between the effective portion 11 and the first end face LS1 or the second end face side outer layer portion LG2 located between the effective portion 11 and the second end face LS2. A specific method involves imaging the target LT cross section with a scanning electron microscope (SEM), determining the field of view and the area occupied by pores from analysis of the captured SEM image, and then calculating the pore fraction Pl (%) using the formula: area occupied by pores / area of ​​field of view×100.

[0044] The pore ratio Plt of the first main surface side outer layer portion TG1 or the second main surface side outer layer portion TG2 can be determined by calculating the proportion of the area occupied by pores in an LT cross section of a region located in the stacking direction T from the region where the pore ratio Pl of the dielectric was measured in the first end face side outer layer portion LG1 located between the effective portion 11 and the first end face LS1 or the second end face side outer layer portion LG2 located between the effective portion 11 and the second end face LS2, and positioned at the center of the thickness of the first main surface side outer layer portion TG1 or the second main surface side outer layer portion TG2 in the stacking direction T. As a specific method, the target LT cross section is imaged with a scanning electron microscope (SEM), the field of view and the area occupied by pores are determined by analyzing the imaged SEM, and the pore ratio Plt (%) can be calculated using the formula: area occupied by pores / area of ​​field of view×100.

[0045] As shown in the relational expression (2), by making the pore ratio Pl smaller than the pore ratio Plt by a predetermined amount, the density of the dielectric layer 20 in the first end face side outer layer portion LG1 or the second end face side outer layer portion LG2 can be improved, thereby suppressing the penetration of moisture from the outside and improving moisture resistance.

[0046] (Method for Manufacturing the Multilayer Ceramic Capacitor 1) Next, an example of a method for manufacturing the multilayer ceramic capacitor 1 according to the embodiment will be described. FIG.

[0047] (Internal electrode layer pattern forming step S1) First, an internal electrode layer pattern 103 that becomes the internal electrode layer 30 is formed by using a conductive paste on a ceramic green sheet 101 that becomes the dielectric layer 20. Fig. 8 is a perspective view of a material sheet 203 in which the internal electrode layer pattern 103 that becomes the internal electrode layer 30 is printed on the surface of the ceramic green sheet 101.

[0048] (Ceramic Green Sheet 101) The ceramic green sheet 101 is a strip-shaped sheet formed by forming a ceramic slurry containing ceramic powder, a binder, and a solvent onto a carrier film using a die coater, gravure coater, microgravure coater, or the like.

[0049] (Internal Electrode Layer Pattern 103) The internal electrode layer pattern 103 is formed by printing such as screen printing, gravure printing, or relief printing.

[0050] Here, the internal electrode layer pattern 103 forms a step 104 due to its thickness on the ceramic green sheet 101. In this embodiment, the step 104 is an inclined surface.

[0051] (Ceramic Paste Arranging Step S2) Next, the ceramic paste 102 forming the dielectric layer is arranged on the material sheet 203 so as to fill the step 104 caused by the thickness of the internal electrode layer pattern 103. Fig. 9 is a perspective view showing a state in which the ceramic paste 102 is arranged on the material sheet 203.

[0052] The ceramic paste 102 has a lower polyvinyl chloride (PVC) content and a relatively higher ceramic content than the ceramic green sheets 101 and the ceramic slurries forming the upper outer layer portion ceramic green sheets 212 and the lower outer layer portion ceramic green sheets 213 described below. Therefore, when fired in the firing step S6 described below, dense dielectric layers are formed in the side surface side outer layer portions WG and end surface side outer layer portions LG of the laminate 10 to which the ceramic paste 102 is applied. This allows the pore fraction Pw of the side surface side outer layer portions WG and the pore fraction Pl of the end surface side outer layer portions LG to be kept lower than the pore fractions Pwt and Plt of the main surface side outer layer portions TG.

[0053] The ceramic paste 102 is applied by printing, for example, screen printing, gravure printing, letterpress printing, etc. The thickness of the ceramic paste 102 is preferably 0.4 to 0.8 times the thickness of the ceramic green sheet 101.

[0054] (Laminating step S3) Fig. 10 is a diagram illustrating the lamination state of the material sheets 203. As shown in Fig. 10, the material sheets 203 are arranged such that the internal electrode layer patterns 103 adjacent to each other in the lamination direction T are alternately shifted in the length direction L.

[0055] Furthermore, a ceramic green sheet 212 for the upper outer layer portion, which will become the first main surface side outer layer portion TG1, is stacked on one side of the multiple laminated material sheets 203, and a ceramic green sheet 213 for the lower outer layer portion, which will become the second main surface side outer layer portion TG2, is stacked on the other side.

[0056] (Mother Block Forming Step S4) Subsequently, the upper outer layer ceramic green sheet 212, the stacked plurality of material sheets 203, and the lower outer layer ceramic green sheet 213 are isostatically pressed to form a mother block.

[0057] (Mother block dividing step S5) Next, the mother block is cut at positions Z shown in Fig. 10. Although only the cutting positions Z in the length direction L are shown, the laminate 10 is also cut at predetermined cutting positions in the width direction W that extend in a direction perpendicular to the position Z extending in the width direction W, and a plurality of rectangular laminates 10 before firing are manufactured.

[0058] 6 is an exploded perspective view for schematically explaining the lamination state of the dielectric layers 20 and the internal electrode layers 30 in the laminate 10. During the manufacture of the multilayer ceramic capacitor 1, a ceramic paste 102 is printed in an area where the internal electrode layer pattern 103 is not arranged on a material sheet 203 on which an internal electrode layer pattern 103 to be the internal electrode layer 30 is printed on a ceramic green sheet 101 to be the dielectric layer 20. The material sheet 203 on which the internal electrode layer pattern 103 and the ceramic paste 102 are printed is laminated on such a ceramic green sheet 101, and is fired in a firing step S6 described later to form the laminate 10.

[0059] Since the ceramic paste 102 is applied to the periphery of the internal electrode layer pattern 103, even when pressed from the stacking direction T during lamination, the periphery of the internal electrode layer pattern 103 does not extend, and the shape of the internal electrode layer pattern 103 can be maintained. Therefore, when the laminate 10 is viewed in a cross section parallel to the width direction W and the stacking direction T at the center of the length direction L, the width direction length of the range where one end of the internal electrode layers 30 in the width direction W is lined up can be set to 1 μm or more and 15 μm or less. This allows the effective portion 11 that generates capacitance to be accurately formed, thereby enabling the multilayer ceramic capacitor 1 to be miniaturized and have an increased capacitance.

[0060] Furthermore, when the laminate 10 is viewed in a cross section parallel to the width direction W and the stacking direction T at the center of the length direction L, the length Ew in the width direction W of the internal electrode layer 30 located in the center of the stacking direction T and the length Es in the width direction W of the internal electrode layer 30 closest to the first main surface TS1 or the second main surface TS2 satisfy the following relational expression (3) for Es / Ew×100(%): 95≦Es / Ew×100≦101 (3)

[0061] By disposing the ceramic paste 102 and filling the step 104 caused by the thickness of the internal electrode layer pattern 103, it is possible to suppress the flow of the internal electrode layer pattern 103 during press working. In this way, by suppressing the flow of the internal electrode layer pattern 103, it is possible to control the width dimension of the effective portion 11 and satisfy the relational expression (3). Furthermore, by satisfying the relational expression (3), it is possible to reduce the volume of the side surface outer layer portion WG and ensure a large effective portion 11.

[0062] (Firing step S6) In the firing step, the laminated chip is subjected to a binder removal process and a firing process to form an element part. The firing process causes the conductive paste layer and the green sheet for the dielectric layer to be co-sintered to form the internal electrode layer 30 and the dielectric layer 20, respectively. The conditions for the binder removal process can be determined depending on the type of organic binder contained in the green sheet and the conductive paste layer. The firing process can also be carried out at a temperature at which the laminated chip is sufficiently densified. The firing temperature depends on the materials of the dielectric and the internal electrode layer, but is preferably 900°C to 1400°C.

[0063] (External Electrode Forming Step S7) In the external electrode forming step, external electrodes 40 are formed on the laminate 10 to form the multilayer ceramic capacitor 1. The external electrodes 40 may be formed by a known method. For example, a base electrode layer, a conductive resin layer, or a direct plating layer is formed on the end surfaces LS where the internal electrode layers 30 of the laminate 10 are drawn out and exposed, and further plating layers are provided as necessary. In this embodiment, a Ni plating layer and a Sn plating layer are formed on the baked layer. The Ni plating layer and the Sn plating layer are formed sequentially by, for example, barrel plating. In this manner, a multilayer ceramic capacitor can be obtained.

[0064] Although the embodiments of the present invention have been described above, the present invention is not limited to the embodiments, and can be embodied in various forms without departing from the gist of the present invention.

[0065] REFERENCE SIGNS LIST 1 Multilayer ceramic capacitor 10 Laminate 11 Effective portion 20 Dielectric layer 30 Internal electrode layer 31 First internal electrode layer 31A First opposing portion 31B First lead portion 32 Second internal electrode layer 32A Second opposing portion 32B Second lead portion 40 External electrode 40A First external electrode 40B Second external electrode TS1 First main surface TS2 Second main surface WS1 First side surface WS2 Second side surface LS1 First end surface LS2 Second end surface TG Main surface side outer layer portion TG1 First main surface side outer layer portion TG2 Second main surface side outer layer portion WG Side surface side outer layer portion WG1 First side surface side outer layer portion WG2 Second side surface side outer layer portion LG End surface side outer layer portion LG1 First end surface side outer layer portion LG1 Second end surface side outer layer portion LG2

Claims

1. A multilayer ceramic capacitor comprising a laminate including a plurality of laminated dielectric layers and a plurality of internal electrode layers, and external electrodes arranged to be conductive with the internal electrode layers, wherein the laminate comprises a first main surface and a second main surface facing each other in a lamination direction in which the dielectric layers and the internal electrode layers are laminated, a first side surface and a second side surface facing each other in a width direction that is a direction intersecting both the lamination direction and a length direction in which the internal electrode layers extend to the external electrode, and a first end surface and a second end surface facing each other in a length direction that is a direction intersecting both the lamination direction and the width direction, and the external electrodes are arranged on each of the first end surface and the second end surface, a multilayer ceramic capacitor in which a region where the internal electrode layers overlap each other as viewed from the stacking direction is defined as an effective portion, opposing regions sandwiching the effective portion in the width direction are defined as a first side surface side outer layer portion and a second side surface side outer layer portion, opposing regions sandwiching the effective portion in the length direction are defined as a first end surface side outer layer portion and a second end surface side outer layer portion, and opposing regions sandwiching the effective portion, the first side surface side outer layer portion, the second side surface side outer layer portion, the first end surface side outer layer portion, and the second end surface side outer layer portion in the stacking direction are defined as a first main surface side outer layer portion and a second main surface side outer layer portion, 1.6≦Pwt−Pw≦3.1 (1) 2. A multilayer ceramic capacitor comprising a laminate including a plurality of laminated dielectric layers and a plurality of internal electrode layers, and external electrodes arranged to be conductive with the internal electrode layers, wherein the laminate comprises a first main surface and a second main surface facing each other in a lamination direction in which the dielectric layers and the internal electrode layers are laminated, a first side surface and a second side surface facing each other in a width direction which is a direction intersecting both the lamination direction and a length direction in which the internal electrode layers extend to the external electrode, and a first end surface and a second end surface facing each other in a length direction which is a direction intersecting both the lamination direction and the width direction, and the external electrodes are arranged on each of the first end surface and the second end surface, a multilayer ceramic capacitor in which a region in which the internal electrode layers overlap each other as viewed from the stacking direction is defined as an effective portion, opposing regions sandwiching the effective portion in the width direction are defined as a first side surface side outer layer portion and a second side surface side outer layer portion, opposing regions sandwiching the effective portion in the length direction are defined as a first end surface side outer layer portion and a second end surface side outer layer portion, and opposing regions sandwiching the effective portion, the first side surface side outer layer portion, the second side surface side outer layer portion, the first end surface side outer layer portion, and the second end surface side outer layer portion in the stacking direction are defined as a first main surface side outer layer portion and a second main surface side outer layer portion, 1.6≦Plt−Pl≦3.1 (2) 3. A multilayer ceramic capacitor as claimed in claim 1 or 2, wherein, when the laminate is viewed in a cross section parallel to the width direction and the lamination direction at the center in the longitudinal direction, the length in the width direction of the range in which one end of the internal electrode layers in the width direction are aligned is 1 μm or more and 15 μm or less.

4. The multilayer ceramic capacitor according to claim 1 or 2, wherein, when the laminate is viewed in a cross section parallel to the width direction and the lamination direction at the center in the length direction, the width direction length Ew of the internal electrode layer at the center in the lamination direction and the width direction length Es of the internal electrode layer closest to the first main surface or the second main surface satisfy the following relational expression (3): 95≦Es / Ew×100≦101 ... (3)

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