Photodetector and electronic apparatus

Abstract

There is provided a photodetector. The photodetector according to an embodiment of the present disclosure includes: a semiconductor layer; a plurality of pixels including a first pixel including a photoelectric conversion element provided in the semiconductor layer; and a trench provided between the plurality of pixels adjacent to each other in the semiconductor layer. The first pixel includes a transistor provided on a side of a first surface of the semiconductor layer, a first semiconductor region of a first electrically-conductive type provided on the side of the first surface of the semiconductor layer, and a first contact electrically coupled to the first semiconductor region. The transistor includes a second semiconductor region and a third semiconductor region of a second electrically-conductive type. The first semiconductor region is provided to be adjacent to the second semiconductor region. The second semiconductor region and the third semiconductor region have sizes different from each other.

Description

PHOTODETECTOR AND ELECTRONIC APPARATUSCROSS REFERENCE TO RELATED APPLICATIONS

[0001] This application claims the benefit of Japanese Priority Patent Application JP2023-127887 filed August 4, 2023, the entire contents of which are incorporated herein by reference.

[0002] The present disclosure relates to a photodetector and an electronic apparatus.

[0003] A device has been proposed which includes a GND (ground) contact for each of pixels and photoelectrically converts incident light (PTL 1).

[0004] [PTL 1] International Publication No. WO2019 / 220945Summary

[0005] It is desired for a device that detects light to be adaptable to miniaturization.

[0006] It is desirable to provide a photodetector that is advantageous to miniaturization.

[0007] A photodetector according to an embodiment of the present disclosure includes: a semiconductor layer; a plurality of pixels including a first pixel including a photoelectric conversion element provided in the semiconductor layer; and a trench provided between the plurality of pixels adjacent to each other in the semiconductor layer. The first pixel includes a transistor provided on a side of a first surface of the semiconductor layer, a first semiconductor region of a first electrically-conductive type provided on the side of the first surface of the semiconductor layer, and a first contact electrically coupled to the first semiconductor region. The transistor includes a second semiconductor region and a third semiconductor region of a second electrically-conductive type. The first semiconductor region is provided to be adjacent to the second semiconductor region. The second semiconductor region and the third semiconductor region have sizes different from each other. A photodetector according to an embodiment of the present disclosure includes: a semiconductor layer; a plurality of pixels including a first pixel including a photoelectric conversion element provided in the semiconductor layer; and a trench provided between the plurality of pixels adjacent to each other in the semiconductor layer. The first pixel includes a first semiconductor region of a first electrically-conductive type provided on a side of a first surface of the semiconductor layer, a first contact electrically coupled to the first semiconductor region, a transistor including a second semiconductor region and a third semiconductor region of a second electrically-conductive type each provided in a first region on the side of the first surface of the semiconductor layer, and a separation section provided around the first region. The first semiconductor region is provided to be adjacent to the second semiconductor region. A size of the first region on a side of the second semiconductor region is smaller than a size of the first region on a side of the third semiconductor region. A photodetector according to an embodiment of the present disclosure includes: a semiconductor layer; a plurality of pixels including a first pixel including a first photoelectric conversion element and a second photoelectric conversion element provided in the semiconductor layer; and a trench provided between the plurality of pixels adjacent to each other in the semiconductor layer. The first pixel includes a first transistor provided on a side of a first surface of the semiconductor layer, a first semiconductor region of a first electrically-conductive type provided on the side of the first surface of the semiconductor layer, and a first contact electrically coupled to the first semiconductor region. The first transistor includes a second semiconductor region and a third semiconductor region of a second electrically-conductive type. The first semiconductor region is provided to be adjacent to the second semiconductor region. The second semiconductor region and the third semiconductor region have sizes different from each other. An electronic apparatus according to an embodiment of the present disclosure includes: an optical system; and a photodetector that receives light transmitted through the optical system. The photodetector includes a semiconductor layer, a plurality of pixels including a first pixel including a photoelectric conversion element provided in the semiconductor layer, and a trench provided between the plurality of pixels adjacent to each other in the semiconductor layer. The first pixel includes a transistor provided on a side of a first surface of the semiconductor layer, a first semiconductor region of a first electrically-conductive type provided on the side of the first surface of the semiconductor layer, and a first contact electrically coupled to the first semiconductor region. The transistor includes a second semiconductor region and a third semiconductor region of a second electrically-conductive type. The first semiconductor region is provided to be adjacent to the second semiconductor region. The second semiconductor region and the third semiconductor region have sizes different from each other. An electronic apparatus according to an embodiment of the present disclosure includes: an optical system; and a photodetector that receives light transmitted through the optical system. The photodetector includes a semiconductor layer, a plurality of pixels including a first pixel including a first photoelectric conversion element and a second photoelectric conversion element provided in the semiconductor layer, and a trench provided between the plurality of pixels adjacent to each other in the semiconductor layer. The first pixel includes a first transistor provided on a side of a first surface of the semiconductor layer, a first semiconductor region of a first electrically-conductive type provided on the side of the first surface of the semiconductor layer, and a first contact electrically coupled to the first semiconductor region. The first transistor includes a second semiconductor region and a third semiconductor region of a second electrically-conductive type. The first semiconductor region is provided to be adjacent to the second semiconductor region. The second semiconductor region and the third semiconductor region have sizes different from each other.

[0008] Fig. 1 is a block diagram illustrating an example of a schematic configuration of an imaging device which is an example of a photodetector according to a first embodiment of the present disclosure.Fig. 2 is a diagram illustrating an arrangement example of pixels of the imaging device according to the first embodiment of the present disclosure.Fig. 3 is an explanatory diagram of an example of a circuit configuration of pixels of the imaging device according to the first embodiment of the present disclosure.Fig. 4A is an explanatory diagram of another example of the circuit configuration of the pixels of the imaging device according to the first embodiment of the present disclosure.Fig. 4B is an explanatory diagram of another example of the circuit configuration of the pixels of the imaging device according to the first embodiment of the present disclosure.Fig. 5 is a diagram illustrating an example of a planar configuration of a pixel of the imaging device according to the first embodiment of the present disclosure.Fig. 6 is a diagram illustrating an example of a cross-sectional configuration of a pixel of the imaging device according to the first embodiment of the present disclosure.Fig. 7 is a diagram illustrating an example of a cross-sectional configuration of a pixel of the imaging device according to the first embodiment of the present disclosure.Fig. 8 is a diagram illustrating an arrangement example of pixel transistors of the imaging device according to the first embodiment of the present disclosure.Fig. 9 is a diagram illustrating another arrangement example of the pixel transistors of the imaging device according to the first embodiment of the present disclosure.Fig. 10 is a diagram illustrating another arrangement example of the pixel transistors of the imaging device according to the first embodiment of the present disclosure.Fig. 11 is a diagram illustrating an example of a cross-sectional configuration of the imaging device according to the first embodiment of the present disclosure.Fig. 12 is a diagram illustrating an example of a planar configuration of a pixel of an imaging device according to Modification Example 1 of the present disclosure.Fig. 13 is a diagram illustrating an example of a planar configuration of a pixel of an imaging device according to Modification Example 2 of the present disclosure.Fig. 14 is a diagram illustrating another example of the planar configuration of the pixel of the imaging device according to Modification Example 2 of the present disclosure.Fig. 15A is a diagram illustrating an example of a planar configuration of a pixel of an imaging device according to Modification Example 3 of the present disclosure.Fig. 15B is a diagram illustrating an example of a planar configuration of the pixel of the imaging device according to Modification Example 3 of the present disclosure.Fig. 16 is a diagram illustrating an example of a planar configuration of a pixel of an imaging device according to Modification Example 4 of the present disclosure.Fig. 17 is a diagram illustrating an example of a cross-sectional configuration of the pixel of the imaging device according to Modification Example 4 of the present disclosure.FIG. 18A is a diagram illustrating another example of the cross-sectional configuration of the pixel of the imaging device according to Modification Example 4 of the present disclosure.FIG. 18B is a diagram illustrating another example of the cross-sectional configuration of the pixel of the imaging device according to Modification Example 4 of the present disclosure.Fig. 19A is a diagram illustrating another example of the planar configuration of the pixel of the imaging device according to Modification Example 4 of the present disclosure.Fig. 19B is a diagram illustrating another example of the planar configuration of the pixel of the imaging device according to Modification Example 4 of the present disclosure.Fig. 20 is a diagram illustrating an example of a planar configuration of a pixel of an imaging device according to Modification Example 5 of the present disclosure.Fig. 21 is a diagram illustrating an arrangement example of pixels of an imaging device according to a second embodiment of the present disclosure.Fig. 22 is a diagram illustrating an example of a planar configuration of a pixel of the imaging device according to the second embodiment of the present disclosure.Fig. 23 is a diagram illustrating another example of the planar configuration of the pixel of the imaging device according to the second embodiment of the present disclosure.Fig. 24 is a diagram illustrating an example of a planar configuration of a pixel of an imaging device according to Modification Example 6 of the present disclosure.Fig. 25 is a diagram illustrating an example of a planar configuration of a pixel of an imaging device according to Modification Example 7 of the present disclosure.Fig. 26 is a diagram illustrating an example of a planar configuration of a pixel of an imaging device according to Modification Example 8 of the present disclosure.Fig. 27A is a diagram illustrating another example of the planar configuration of the pixel of the imaging device according to Modification Example 8 of the present disclosure.Fig. 27B is a diagram illustrating another example of the planar configuration of the pixel of the imaging device according to Modification Example 8 of the present disclosure.Fig. 28 is a diagram illustrating another example of the planar configuration of the pixel of the imaging device according to Modification Example 8 of the present disclosure.Fig. 29 is a diagram illustrating an example of a planar configuration of a pixel of an imaging device according to Modification Example 9 of the present disclosure.Fig. 30 is a diagram illustrating an example of a planar configuration of the pixel of the imaging device according to Modification Example 9 of the present disclosure.Fig. 31A is a diagram illustrating another example of the planar configuration of the pixel of the imaging device according to Modification Example 9 of the present disclosure.Fig. 31B is a diagram illustrating another example of the planar configuration of the pixel of the imaging device according to Modification Example 9 of the present disclosure.Fig. 32 is a diagram illustrating an example of a planar configuration of a pixel of an imaging device according to Modification Example 10 of the present disclosure.Fig. 33A is a diagram illustrating another example of the planar configuration of the pixel of the imaging device according to Modification Example 10 of the present disclosure.Fig. 33B is a diagram illustrating another example of the planar configuration of the pixel of the imaging device according to Modification Example 10 of the present disclosure.Fig. 33C is a diagram illustrating another example of the planar configuration of the pixel of the imaging device according to Modification Example 10 of the present disclosure.Fig. 33D is a diagram illustrating another example of the planar configuration of the pixel of the imaging device according to Modification Example 10 of the present disclosure.Fig. 33E is a diagram illustrating another example of the planar configuration of the pixel of the imaging device according to Modification Example 10 of the present disclosure.Fig. 33F is a diagram illustrating another example of the planar configuration of the pixel of the imaging device according to Modification Example 10 of the present disclosure.Fig. 34 is a block diagram illustrating a configuration example of an electronic apparatus including an imaging device.Fig. 35 is a block diagram depicting an example of schematic configuration of a vehicle control system.Fig. 36 is a diagram of assistance in explaining an example of installation positions of an outside-vehicle information detecting section and an imaging section.Fig. 37 is a view depicting an example of a schematic configuration of an endoscopic surgery system.Fig. 38 is a block diagram depicting an example of a functional configuration of a camera head and a camera control unit (CCU).

[0009] Hereinafter, description is given in detail of embodiments of the present disclosure with reference to the drawings. It is to be noted that the description is given in the following order. 1. First Embodiment 2. Second Embodiment 3. Application Example 4. Practical Application Examples <1. First Embodiment>

[0010] Fig. 1 is a block diagram illustrating an example of a schematic configuration of an imaging device which is an example of a photodetector according to a first embodiment of the present disclosure. The photodetector is a device that is able to detect incident light. An imaging device 1, which is a photodetector, includes a plurality of pixels P each including a photoelectric conversion section (photoelectric conversion element), and is configured to photoelectrically convert incident light and generate a signal. The imaging device 1 may receive light transmitted through an optical system (unillustrated) including an optical lens and generate a signal.

[0011] The imaging device 1 is configured using, for example, a semiconductor substrate (e.g., a silicon substrate) provided with the plurality of pixels P. The photoelectric conversion section of each of the pixels P of the imaging device 1 is, for example, a photodiode (PD), and is configured to be able to photoelectrically convert light. The imaging device 1 includes, as an imaging area, a region (a pixel section 100) in which the plurality of pixels P is two-dimensionally arranged in matrix. The pixel section 100 of the imaging device 1 can also be referred to as a pixel array in which the plurality of pixels P is arranged. The photoelectric conversion section of each of the pixels P can also be referred to as a photoelectric conversion region.

[0012] The imaging device 1 takes in incident light (image light) from a subject, which is a measurement target, via the optical system including the optical lens. The imaging device 1 captures an image of the subject formed by the optical lens. The imaging device 1 may photoelectrically convert received light (e.g., visible light, infrared light, etc.) and generate a pixel signal. The imaging device 1, which is a photodetector, is a device that is able to receive incident light and generate a signal. The imaging device 1 can also be referred to as a light-receiving device.

[0013] As an example, the imaging device 1 (photodetector) may be configured as an image sensor. The imaging device 1 is, for example, a CMOS (Complementary Metal Oxide Semiconductor) image sensor. The imaging device 1 is usable for various electronic apparatuses such as a digital still camera, a video camera, and a mobile phone.

[0014] As an example, the imaging device 1 includes a pixel section 100, a pixel drive section 111, a signal processing section 112, a control section 113, and a processing section 114, as in the example illustrated in Fig. 1. In addition, the imaging device 1 is provided with, for example, a plurality of control lines L1 and a plurality of signal lines L2.

[0015] The control line L1 is a signal line that is able to convey a signal to control the pixel P, and is coupled to the pixel drive section 111 and the pixel P of the pixel section 100. In the example illustrated in Fig. 1, the plurality of control lines L1 is wired for respective pixel rows configured by the plurality of pixels P arranged in a horizontal direction (row direction) in the pixel section 100. The control line L1 is configured to transmit a control signal for reading a signal from the pixel P.

[0016] As an example, the plurality of control lines L1 for the respective pixel rows of the imaging device 1 includes wiring that transmits a signal to control a transfer transistor, wiring that transmits a signal to control a selection transistor, wiring that transmits a signal to control a reset transistor, and the like. The control line L1 can also be referred to as a drive line (pixel drive line) that transmits a signal to drive the pixel P.

[0017] The signal line L2 is a signal line that is able to convey a signal from the pixel P, and is coupled to the pixels P of the pixel section 100 and the signal processing section 112. In the pixel section 100, for example, the signal lines L2 are wired for respective pixel columns configured by the plurality of pixels P arranged in a vertical direction (column direction). The signal line L2 is a vertical signal line, and is configured to transmit a signal outputted from the pixel P.

[0018] The pixel drive section 111 is configured to be able to drive each of the pixels P of the pixel section 100. The pixel drive section 111 is a drive circuit, and is configured by a plurality of circuits including a buffer, a shift register, an address decoder, and the like, for example. The pixel drive section 111 generates a signal for driving the pixel P, and outputs the generated signal to each of the pixels P of the pixel section 100 via the control line L1. The pixel drive section 111 is controlled by the control section 113, and controls the pixel P of the pixel section 100.

[0019] The pixel drive section 111 generates, for example, a signal to drive the pixel P, such as a signal to control a transfer transistor of the pixel P, a signal to control a selection transistor, and a signal to control a reset transistor, and supplies the generated signal to each of the pixels P by the control line L1. The pixel drive section 111 may perform a control to read a pixel signal from each of the pixels P. The pixel drive section 111 can also be referred to as a pixel control section configured to be able to control each of the pixels P. It is to be noted that the pixel drive section 111 and the control section 113 can also be collectively referred to as the pixel control section.

[0020] The signal processing section 112 is configured to be able to execute signal processing on an inputted pixel signal. The signal processing section 112 is a signal processing circuit, and includes, for example, a load circuit, an AD (Analog Digital) conversion circuit, a horizontal selection switch, and the like. As an example, the load circuit is configured by a current source that is able to supply a current to an amplification transistor of the pixel P. The load circuit constitutes a source follower circuit together with the amplification transistor of the pixel P, for example.

[0021] The signal processing section 112 may include an amplification circuit configured to amplify a signal read from the pixel P via the signal line L2. The load circuit, the amplification circuit, the AD conversion circuit, and the like are provided for each of the plurality of signal lines L2, for example. For each of the pixel columns of the pixel section 100, the load circuit, the amplification circuit, the AD conversion circuit, and the like may be provided.

[0022] The signal outputted from each of the pixels P selectively scanned by the pixel drive section 111 is inputted to the signal processing section 112 via the signal line L2. The signal processing section 112 may perform, for example, signal processing such as CDS (Correlated Double Sampling: correlated double sampling) and AD conversion of a signal of the pixel P. The signal of each of the pixels P transmitted through each of the signal lines L2 is subjected to signal processing by the signal processing section 112, and is outputted to the processing section 114.

[0023] The processing section 114 is configured to be able to execute signal processing on an inputted signal. The processing section 114 is a signal processing circuit, and is configured by, for example, a circuit that performs various types of signal processing on a pixel signal. The processing section 114 may include a processor and a memory. The processing section 114 performs signal processing on the pixel signal inputted from the signal processing section 112, and outputs the processed pixel signal. The processing section 114 may perform, for example, various types of signal processing such as noise reduction processing or gradation correction processing.

[0024] The control section 113 is configured to be able to control each section of the imaging device 1. The control section 113 may receive a clock applied from the outside, data ordering an operation mode, or the like, and output data such as internal information on the imaging device 1. The control section 113 is a control circuit, and includes, for example, a timing generator configured to be able to generate various timing signals.

[0025] The control section 113 controls driving of the pixel drive section 111, the signal processing section 112, and the like on the basis of the various timing signals (pulse signals, clock signals, etc.) generated by the timing generator. It is to be noted that the control section 113 and the processing section 114 may be integrally configured.

[0026] The pixel drive section 111, the signal processing section 112, the control section 113, the processing section 114, and the like may be provided in one semiconductor substrate or may be provided separately in a plurality of semiconductor substrates. The imaging device 1 may have a structure (stacked structure) configured by stacking a plurality of substrates. Some or all of the signal processing section 112, the control section 113, and the processing section 114 may be integrally configured.

[0027] Fig. 2 is a diagram illustrating an arrangement example of pixels of the imaging device according to the first embodiment. The pixel P of the imaging device 1 includes a photoelectric conversion section 12, a lens 21, and a filter 22. It is to be noted that, as illustrated in Fig. 2, a direction in which light from a subject is incident is defined as a Z-axis direction; a right-left direction on the sheet orthogonal to the Z-axis direction is defined as an X-axis direction; and an up-down direction on the sheet orthogonal to the Z-axis direction and the X-axis direction is defined as a Y-axis direction. In the following drawings, the arrow directions in Fig. 2 may be used, in some cases, as a standard to express directions.

[0028] In the imaging device 1, for example, the lens 21 and the filter 22 may be provided on a side on which light from an optical system such as an imaging lens is incident (see also Fig. 11 described later). The lens 21 (lens section) is a lens that condenses light, and is an optical member also referred to as an on-chip lens. The lens 21 is provided above the photoelectric conversion section 12, for example, for each of the pixels P or for every plurality of pixels P.

[0029] Light from a subject, which is a measurement target, is incident on the lens 21 via the optical system such as the imaging lens. The lens 21 guides incident light toward a side of the photoelectric conversion section 12 of the pixel P. The photoelectric conversion section 12 of the pixel P photoelectrically converts incident light via the lens 21 and the filter 22.

[0030] The filter 22 is configured to selectively transmit light of a specific wavelength region of incident light. The filter 22 is, for example, an RGB color filter, or a filter that transmits infrared light. The filter 22 is provided above the photoelectric conversion section 12, for example, for each of the pixels P or for every plurality of pixels P.

[0031] The plurality of the pixel P provided in the pixel section 100 of the imaging device 1 includes, as an example, a pixel (R pixel) provided with the filter 22 that transmits red (R) light, a pixel (G pixel) provided with the filter 22 that transmits green (G) light, and a pixel (B pixel) provided with the filter 22 that transmits blue (B) light. In the pixel section 100, a plurality of R pixels, a plurality of G pixels, and a plurality of B pixels are repeatedly arranged.

[0032] The R pixel, the G pixel, and the B pixel are arranged in accordance with a Bayer arrangement, for example. The R pixel, the G pixel, and the B pixel may generate an R component pixel signal, a G component pixel signal, and a B component pixel signal, respectively. The imaging device 1 is able to obtain RGB pixel signals. It is to be noted that the arrangement of pixels is not limited to the above-described example, and may be set optionally.

[0033] As an example, the R pixels, the G pixels, and the B pixels may each be arranged in 2 × 2 pixel units. For example, in the pixel section 100, four adjacent R pixels, four adjacent G pixels, and four adjacent B pixels are repeatedly arranged. It can also be said that the R pixels, the G pixels, and the B pixels are each arranged cyclically in two rows × two columns.

[0034] The filter 22 provided in the pixel P of the pixel section 100 is not limited to the primary (RGB) color filter, and may be a complementary color filter such as Cy (cyan), Mg (magenta), or Ye (yellow). A filter corresponding to W (white), i.e., a filter that transmits light beams in all wavelength regions of incident light may be arranged. The filter 22 may be a filter that transmits infrared light.

[0035] It is to be noted that, the filter 22 may be omitted as needed in the imaging device 1. The filter 22 may not be provided in some or all of the pixels P of the imaging device 1. For example, the filter 22 may not be provided in the pixel P in which white (W) light is received to perform photoelectric conversion.

[0036] Fig. 3 is an explanatory diagram of an example of a circuit configuration of pixels of the imaging device according to the first embodiment. The pixel P of the imaging device 1 includes the photoelectric conversion section 12 (photoelectric conversion element), a transfer transistor TR, a floating diffusion FD, and a readout circuit 20. The photoelectric conversion section 12 is configured to receive light and generate a signal. The photoelectric conversion section 12 is a light-receiving section (light-receiving element), and is configured to be able to generate electric charge by photoelectric conversion.

[0037] The readout circuit 20 is configured to be able to output a signal based on the photoelectrically converted electric charge. The readout circuit 20 may read a pixel signal based on the electric charge photoelectrically converted by the photoelectric conversion section 12. In the imaging device 1, the readout circuit 20 is provided for the plurality of pixels P. The imaging device 1 has a configuration in which the plurality of pixels P shares one readout circuit 20. This makes it possible to reduce the number of elements (e.g., the number of transistors) per pixel P (or per photoelectric conversion section 12). The imaging device 1 may have a structure that is advantageous to pixel miniaturization.

[0038] In the example illustrated in Fig. 3, the readout circuit 20 is arranged for every four pixels P (referred to as "pixels Pa to Pd"). The pixel Pa, the pixel Pb, the pixel Pc, and the pixel Pd share one readout circuit 20. For example, 2 × 2 pixels configured by adjacent pixels Pa to Pd share one readout circuit 20.

[0039] The imaging device 1 may operate the readout circuit 20 time-divisionally to thereby read respective pixel signals of the 2 × 2 pixels. In addition, the imaging device 1 is also able to read pixel signals to which the respective signals of the 2 × 2 pixels are added. For example, the imaging device 1 may read pixel signals corresponding to electric charge to which electric charge photoelectrically converted by the respective 2 × 2 pixels are added.

[0040] In the example illustrated in Fig. 3, the photoelectric conversion section 12 is a photodiode (PD), and converts incident light into electric charge. The photoelectric conversion section 12 (a photodiode PD of the pixel Pa to a photodiode PD of the pixel Pd in Fig. 3) may perform photoelectric conversion to generate electric charge corresponding to a received light amount.

[0041] The transfer transistor TR (the transfer transistor TR of the pixel Pa to the transfer transistor TR of the pixel Pd in Fig. 3) is configured to be able to transmit electric charge photoelectrically converted by the photoelectric conversion section 12 to the floating diffusion FD. The transfer transistor TR is controlled by a signal STR, and electrically couples or decouples the photoelectric conversion section 12 and the floating diffusion FD to and from each other. The transfer transistor TR may transfer electric charge photoelectrically converted by and accumulated in the photoelectric conversion section 12 to the floating diffusion FD.

[0042] In the example illustrated in Fig. 3, the transfer transistors TR of the respective pixels Pa to Pd are controlled ON / OFF by signals different from each other. The transfer transistor TR of the pixel Pa is controlled by a signal STR1, and the transfer transistor TR of the pixel Pb is controlled by a signal STR2. In addition, the transfer transistor TR of the pixel Pc is controlled by a signal STR3, and the transfer transistor TR of the pixel Pd is controlled by a signal STR4.

[0043] The floating diffusion FD is an accumulation section, and is configured to accumulate the transferred electric charge. The floating diffusion FD may accumulate the electric charge photoelectrically converted by the photoelectric conversion section 12. The floating diffusion FD can also be referred to as a holding section that is able to hold the transferred electric charge. The floating diffusion FD accumulates the transferred electric charge, and converts the electric charge into a voltage corresponds to capacitance of the floating diffusion FD.

[0044] As an example, the readout circuit 20 includes an amplification transistor AMP, a selection transistor SEL, and a reset transistor RST, as illustrated in Fig. 3. The amplification transistor AMP is configured to generate and output a signal based on the electric charge accumulated in the floating diffusion FD. The amplification transistor AMP may generate and output a signal based on the electric charge converted by the photoelectric conversion section 12.

[0045] As illustrated in Fig. 3, a gate of the amplification transistor AMP is electrically coupled to the floating diffusion FD of each of the pixels P, and receives an input of the voltage converted by the floating diffusion FD. A drain of the amplification transistor AMP is coupled to a power supply line to be supplied with a power supply voltage VDD.

[0046] A source of the amplification transistor AMP is coupled to the signal line L2 via the selection transistor SEL. The amplification transistor AMP is configured to generate a signal based on the electric charge accumulated in the floating diffusion FD, i.e., a signal based on the voltage of the floating diffusion FD and to output the generated signal to the signal line L2.

[0047] The selection transistor SEL is configured to be able to control the output of the pixel signal. The selection transistor SEL is electrically coupled in series to the amplification transistor AMP, for example, as in the example illustrated in Fig. 3. The selection transistor SEL is controlled by a signal SSEL, and is configured to be able to output the signal from the amplification transistor AMP to the signal line L2. The selection transistor SEL may control an output timing of the pixel signal.

[0048] The selection transistor SEL is configured to be able to output the signal based on the electric charge converted by the photoelectric conversion section 12. The selection transistor SEL may output the pixel signal of the pixel P to the signal line L2. It is to be noted that the selection transistor SEL may be electrically coupled between the power supply line to which the power supply voltage VDD is applied and the amplification transistor AMP. In addition, the selection transistor SEL may be omitted as needed.

[0049] The reset transistor RST is configured to be able to reset the voltage of the floating diffusion FD. In the example illustrated in Fig. 3, the reset transistor RST is electrically coupled to the power supply line to which the power supply voltage VDD is applied, and is configured to reset the electric charge of the pixel P.

[0050] The reset transistor RST may be controlled by the signal SRST to reset the electric charge accumulated in the floating diffusion FD and to reset the voltage of the floating diffusion FD. In the example illustrated in Fig. 3, the reset transistor RST may electrically couple the power supply line and the floating diffusion FD to each other and discharge the electric charge accumulated in the floating diffusion FD. It is to be noted that the reset transistor RST may discharge the electric charge accumulated in the photoelectric conversion section 12 via the transfer transistor TR.

[0051] Fig. 4A is an explanatory diagram of another example of the circuit configuration of the pixels of the imaging device according to the first embodiment. The readout circuit 20 may include a transistor FDG, as in the example illustrated in Fig. 4A. As an example, the transistor FDG is configured to be able to electrically couple the floating diffusion FD and the reset transistor RST to each other. For example, the transistor FDG is controlled by a signal SFDG to electrically couple or decouple the floating diffusion FD and the reset transistor RST to and from each other.

[0052] The transistor FDG coming into an ON state increases capacitance to be added to the floating diffusion FD of the pixel P, thus switching conversion efficiency (gain) upon conversion of the electric charge into the voltage. The transistor FDG is a switching transistor to be used for setting of the conversion efficiency. The transistor FDG may switch capacitance to be coupled to the gate of the amplification transistor AMP to change the conversion efficiency.

[0053] The transistor FDG may be electrically coupled in series to the reset transistor RST, or may be electrically coupled in parallel to the reset transistor RST. The transistor FDG may be configured to be able to electrically couple the floating diffusion FD and a capacitor C1 to each other, as in the example illustrated in Fig. 4B. For example, the transistor FDG is controlled by the signal SFDG to electrically couple or decouple the floating diffusion FD and the capacitor C1 to and from each other. Switching a coupling state of the capacitor C1 makes it possible to change the conversion efficiency.

[0054] The transfer transistor TR, the amplification transistor AMP, the selection transistor SEL, the transistor FDG (switching transistor), and the reset transistor RST, which are described above, are each a MOS transistor (MOSFET) having terminals of a gate, a source, and a drain.

[0055] In the examples illustrated in Figs. 3, 4A, and 4B, the transfer transistor TR, the amplification transistor AMP, the selection transistor SEL, the transistor FDG, and the reset transistor RST are each configured by an NMOS transistor. It is to be noted that the transistor of the pixel P may also be configured by a PMOS transistor. The transistors of the pixel P may be configured as a 3D transistor, e.g., a Fin transistor (Fin FET).

[0056] The imaging device 1 may have a configuration in which five or more pixels P, e.g., eight pixels P share one readout circuit 20. For example, in the imaging device 1, the readout circuit 20 is disposed for every eight pixels P, and 2 × 4 pixels share one readout circuit 20.

[0057] The pixel drive section 111 of the imaging device 1 (see Fig. 1) supplies a control signal to gates of the transfer transistor TR, the selection transistor SEL, the transistor FDG, the reset transistor RST, and the like of each of the pixels P via the above-described control line L1 to bring the transistors into an ON state (electrically-conductive state) or an OFF state (non-electrically-conductive state).

[0058] The plurality of control lines L1 for the respective pixel rows of the imaging device 1 includes, as an example, wiring that transmits the signal STR to control the transfer transistor TR, wiring that transmits the signal SSEL to control the selection transistor SEL, wiring that transmits the signal FDG to control the signal SFDG, and wiring that transmits the signal SRST to control the reset transistor RST.

[0059] The transfer transistor TR, the selection transistor SEL, the transistor FDG, the reset transistor RST, and the like are controlled ON / OFF by the pixel drive section 111. The pixel drive section 111 controls the readout circuit 20 of each of the pixels P to thereby allow the pixel signal to be outputted from each of the pixels P to the signal line L2. The pixel drive section 111 may perform a control to read the pixel signal of each of the pixels P to the signal line L2.

[0060] Fig. 5 is a diagram illustrating an example of a planar configuration of the pixel of the imaging device according to the first embodiment. Figs. 6 and 7 are each a diagram illustrating an example of a cross-sectional configuration of the pixel of the imaging device. Fig. 6 illustrates a configuration example of the pixel in a direction along a line A-A' illustrated in Fig. 5. In addition, Fig. 7 illustrates a configuration example of the pixel in a direction along a line B-B' illustrated in Fig. 5.

[0061] Each of the pixels P of the imaging device 1 has structures illustrated in Figs. 5 to 7, for example. The pixel P includes the photoelectric conversion section 12, the transfer transistor TR, the floating diffusion FD, a pixel transistor 30, and a semiconductor region 35. The pixel transistor 30 is, for example, a transistor of the readout circuit 20 described above.

[0062] The pixel transistor 30 is used as the amplification transistor AMP, the selection transistor SEL, the transistor FDG, the reset transistor RST, or the like. It is to be noted that the pixel transistors 30 of some of the pixels P may be dummy transistors. The readout circuit 20 may include a dummy transistor as the pixel transistor 30.

[0063] Each transistor such as the amplification transistor AMP, the selection transistor SEL, the transistor FDG, or the reset transistor RST of the readout circuit 20 is provided as the pixel transistor 30 separately in the plurality of pixels P, and is shared by the plurality of pixels P. Such a configuration of the imaging device 1 makes it possible to reduce the number of transistors in one pixel P.

[0064] The imaging device 1 is configured using a substrate 101 including a semiconductor layer 110. The substrate 101 is configured by, for example, a semiconductor substrate such as an Si (Silicone) substrate. For example, the photoelectric conversion section 12, the readout circuit 20, and the like described above are formed in the substrate 101 including the semiconductor layer 110.

[0065] It is to be noted that the substrate 101 may be configured using an SOI (Silicon On Insulator) substrate, an SiGe (silicon germanium) substrate, another compound semiconductor material, or the like. In the examples illustrated in Figs. 5 to 7, the substrate 101 includes the semiconductor layer 110 and a wiring layer 120.

[0066] The semiconductor layer 110 has a surface 11S1 and a surface 11S2 opposed to each other, as illustrated in Figs. 6 and 7. The surface 11S2 is a surface on a side opposite to the surface 11S1. The surface 11S1 of the semiconductor layer 110 is, for example, an element formation surface on which an element such as a transistor is formed. A gate electrode, a gate insulating film (e.g., a gate oxide film), and the like are provided on the surface 11S1 of the semiconductor layer 110. The surface 11S2 of the semiconductor layer 110 is, for example, a light-receiving surface (light incident surface).

[0067] In the semiconductor layer 110, a plurality of photoelectric conversion sections 12 (photoelectric conversion elements) is provided along the surface 11S1 and the surface 11S2 of the semiconductor layer 110. For example, the plurality of photoelectric conversion sections 12 is formed to be embedded in the semiconductor layer 110. The photoelectric conversion section 12 can also be referred to as a photoelectric conversion layer. The photoelectric conversion section 12 is provided between the surface 11S1 and the surface 11S2 of the semiconductor layer 110.

[0068] As in the example illustrated in Figs. 6 and 7, the semiconductor layer 110 includes a well 25. For example, the well 25 is a p-type semiconductor region, and is a p-type well (p-well). In the example illustrated in Figs. 6 and 7, the well 25, which is a p-type well region, is provided in the semiconductor layer 110. The photoelectric conversion section 12 includes a semiconductor region 15 provided in the well 25. For example, the semiconductor region 15 is an n-type semiconductor region.

[0069] The transfer transistor TR, the floating diffusion FD, the pixel transistor 30, the semiconductor region 35, and the like are provided on a side of the surface 11S1 of the semiconductor layer 110. As illustrated in Fig. 7, for example, the floating diffusion FD includes the n-type semiconductor region.

[0070] As illustrated in Figs. 5 to 7, the imaging device 1 is provided with a trench 91 and a trench 92. The trench 91 and the trench 92 are each provided between a plurality of pixels P adjacent to each other in the semiconductor layer 110. The trench 91 and the trench 92 are each provided between the respective photoelectric conversion sections 12 of the plurality of pixels P adjacent to each other to separate the pixels P (or the photoelectric conversion sections 12) from each other. The pixel P can also be said to have a structure partitioned by the trench 91 and the trench 92.

[0071] The trench 91 and the trench 92 are each a separation section (groove), and is configured using an insulating material, for example. At least a portion of each of the trench 91 and the trench 92 is provided at a boundary between the pixels P (or the photoelectric conversion sections 12) adjacent to each other. The trench 91 has an STI (Shallow Trench Isolation) structure, and is provided on the side of the surface 11S1 of the semiconductor layer 110. The trench 92 has an FTI (Full Trench Isolation) structure, and is provided to penetrate the semiconductor layer 110.

[0072] In the examples illustrated in Figs. 5 to 7, the trench 91 is provided, in the semiconductor layer 110, to surround the transfer transistor TR, the floating diffusion FD, the pixel transistor 30, the semiconductor region 35, and the like. In addition, the trench 92 is provided, in the semiconductor layer 110, to surround the photoelectric conversion section 12. The trench 91 and the trench 92 are disposed in a lattice pattern in a plan view to surround the photoelectric conversion section 12 of each of the pixels P. Each of the trench 91 and the trench 92 can also be referred to as an inter-pixel separation section or an inter-pixel separation wall.

[0073] As an example, an insulating film (insulator) such as an oxide film (e.g., silicon oxide film) or a nitride film (e.g., silicon nitride film) is provided in the trench 91 and the trench 92. The trench 91 and the trench 92 may be filled with polysilicon, a metal material, another insulating material, or the like. In addition, an air gap (cavity) may be provided in the trench 91 and the trench 92. The trench 92 may be formed in the trench 91. For example, the trench 92 may be provided from within the trench 91, which is provided on the side of the surface 11S1 of the semiconductor layer 110, to the surface 11S2 of the semiconductor layer 110.

[0074] In addition, the imaging device 1 is provided with a trench 93. The trench 93 is a separation section (groove) having the STI structure, for example. For example, an insulating film such as an oxide film (e.g., silicon oxide film) or a nitride film (e.g., silicon nitride film) is provided in the trench 93. The trench 93 (separation section) is provided on the side of the surface 11S1 of the semiconductor layer 110 to separate elements from each other. The trench 93 is formed between the pixel transistor 30 and the floating diffusion FD, between the pixel transistor 30 and the transfer transistor TR, between the transfer transistor TR and the semiconductor region 35, or between other elements.

[0075] The imaging device 1 is provided with a plurality of regions (active regions) partitioned by the separation section (trench). The imaging device 1 includes, for example, an active region 81 and an active region 82 provided in the semiconductor layer 110 of the substrate 101. As an example, the active region 81 and the active region 82 surrounded by the trench 93 (or the trench 91) are formed in each of the pixels P of the imaging device 1, as illustrated in Fig. 5. The active regions 81 and 82 are each a region separated by the trench 93, for example.

[0076] The active region 81 and the active region 82 are, for example, regions of the semiconductor layer 110 (or the well 25 of the semiconductor layer 110) electrically separated by the trench 93 and the trench 91, and are island-shaped regions. As in the example illustrated in Figs. 5 and 6, the pixel transistor 30 and the semiconductor region 35 are provided in the active region 81. In addition, the transfer transistor TR and the floating diffusion FD are provided in the active region 82.

[0077] The transfer transistor TR has a gate insulating film 45 and a gate electrode 46. The transfer transistor TR includes, as an example, a vertical gate structure. At least a portion of each of the gate insulating film 45 and the gate electrode 46 of the transfer transistor TR is provided in the semiconductor layer 110. At least a portion of each of the gate insulating film 45 and the gate electrode 46 is provided to be dug into the semiconductor layer 110, for example, as in the example illustrated in Fig. 7.

[0078] As an example, the gate electrode 46 and the gate insulating film 45 of the transfer transistor TR may be formed to reach the photoelectric conversion section 12 in the semiconductor layer 110. The transfer transistor TR has a vertical gate (VG: Vertical Gate) structure, and can also be referred to as a vertical transistor. In the example illustrated in Fig. 7, a portion of each of the gate electrode 46 and the gate insulating film 45 of the transfer transistor TR is disposed to be embedded in the semiconductor layer 110, for example.

[0079] The gate electrode 46 of the transfer transistor TR may be provided, in the semiconductor layer 110, from between the floating diffusion FD and the trench 91 to the region of the photoelectric conversion section 12, for example, as in the example illustrated in Fig. 7. The gate insulating film 45 is formed along the gate electrode 46 in the semiconductor layer 110. It is to be noted that the transfer transistor TR may have a planar gate structure. The transfer transistor TR may be configured as a planar transistor, for example.

[0080] The semiconductor region 35 is a semiconductor region of the same electrically-conductive type as that of the well 25, and is provided on the side of the surface 11S1 of the semiconductor layer 110. The semiconductor region 35 is provided for the well 25 in the active region 81 to be electrically coupled to the well 25. For example, the semiconductor region 35 is a p-type semiconductor region, and is a region formed using p-type impurities.

[0081] The semiconductor region 35 has an impurity concentration higher than an impurity concentration of the well 25, for example, and is a p+ semiconductor region. The semiconductor region 35, which is a p+ region, is a p+ diffusion region, and can also be referred to as a p+ electrically-conductive region. In addition, the semiconductor region 35 is electrically coupled to a contact 55. The contact 55 is provided in the wiring layer 120 of the substrate 101.

[0082] In the example illustrated in Fig. 6, the semiconductor region 35 is coupled to the contact 55 provided on the semiconductor region 35, and is electrically coupled to wiring (unillustrated) of the wiring layer 120 via the contact 55. The contact 55 is electrically coupled to the well 25 by the semiconductor region 35.

[0083] For example, the contact 55 is ohmically coupled to the semiconductor region 35, and is electrically coupled to the well 25 via the semiconductor region 35. A region of the well 25 electrically coupled to the semiconductor region 35 is supplied with a predetermined potential (voltage) by the wiring of the wiring layer 120, the contact 55, and the like.

[0084] The contact 55 is a well contact, and the semiconductor region 35 is a well contact region. The contact 55 and the semiconductor region 35 are arranged for each of the pixels P, for example. It is to be noted that the semiconductor region 35 and the contact 55 can also be collectively referred to as the well contact region.

[0085] For example, the semiconductor region 35 is electrically coupled to a reference potential line in the wiring layer 120 via the contact 55, and a reference potential is applied to the semiconductor region 35 and the well 25. As an example, a GND potential (ground potential) is applied to the semiconductor region 35 and the well 25 via the contact 55.

[0086] The pixel transistor 30 includes a semiconductor region 31, a semiconductor region 32, a semiconductor region 33, a gate insulating film 41, and a gate electrode 42. The semiconductor regions 31 to 33 are each provided for the well 25 in the active region 81. It can also be said that the semiconductor regions 32, 33, and the like are arranged to replace a portion of the well 25. The semiconductor region 31 and the semiconductor region 32 (or the semiconductor region 33) have electrically-conductive types different from each other.

[0087] The semiconductor region 31 is a region (channel region) where a channel is formed. The semiconductor region 31 is formed in a region below the gate electrode 42 and the gate insulating film 41, for example, as in the example schematically illustrated with a broken line in Fig. 5. For example, the semiconductor region 31 is a p-type semiconductor region, and is a region formed using p-type impurities. The semiconductor region 31 is a p-type diffusion region, and can also be referred to as a p-type electrically-conductive region.

[0088] The semiconductor region 32 and the semiconductor region 33 are a source region and a drain region of the pixel transistor 30. One of the semiconductor regions 32 and 33 is the source region of the pixel transistor 30, and another of the semiconductor regions 32 and 33 is the drain region of the pixel transistor 30. The semiconductor region 32 and the semiconductor region 33 may be configured to have sizes (widths, areas, etc.) different from each other, as in the example illustrated in Fig. 5.

[0089] For example, tyhe semiconductor region 32 and the semiconductor region 33 are each an n-type semiconductor region, and is a region formed using n-type impurities. The semiconductor region 32 and the semiconductor region 33 are formed, for example, by doping (adding) the n-type impurities into the region of the semiconductor layer 110. The semiconductor region 32 and the semiconductor region 33 are each an n-type diffusion region, and can also be referred to as an n-type electrically-conductive region.

[0090] The semiconductor region 32 is coupled to a contact 52 provided on the semiconductor region 32, and is electrically coupled to wiring (unillustrated) of the wiring layer 120 via the contact 52. The semiconductor region 33 is coupled to a contact 53 provided on the semiconductor region 33, and is electrically coupled to wiring of the wiring layer 120 via the contact 53.

[0091] The semiconductor region 32 and the semiconductor region 33 are arranged around the gate electrode 42 of the pixel transistor 30. The pixel transistor 30 including the semiconductor regions 32 and 33 is formed in a region around the transfer transistor TR. The pixel transistor 30 is configured as a planar transistor, for example. It is to be noted that the shape of the pixel transistor 30 is not limited to the example illustrated in Fig. 5, and is appropriately changeable.

[0092] The gate insulating film 41 of the pixel transistor 30 is disposed on the channel region (semiconductor region 31) of the pixel transistor 30. The gate insulating film 41 (e.g., gate oxide film) is provided between the semiconductor region 31, which is the channel region, and the gate electrode 42. The gate electrode 42 is provided on the gate insulating film 41. The gate electrode 42 is provided above the semiconductor region 31 of the semiconductor layer 110 with the gate insulating film 41 interposed therebetween.

[0093] It is to be noted that the pixel transistor 30 may be configured as a Fin transistor. For example, the gate electrode 42 of the pixel transistor 30 is provided to sandwich a portion of the semiconductor layer 110 on the side of the surface 11S1 of the semiconductor layer 110. As an example, a portion of the gate electrode 42 is provided, in the semiconductor layer 110, to sandwich a portion of the semiconductor layer 110 to be the channel region of the pixel transistor 30, with gate insulating film 41 interposed therebetween.

[0094] For example, the gate electrode 42 and the semiconductor region 31 to be the channel region of the pixel transistor 30 may each have a fin shape. The pixel transistor 30 may have, as a fin part, a portion of the gate electrode 42 provided to be dug into the semiconductor layer 110. The pixel transistor 30 may have a dug gate structure. For example, the pixel transistor 30 has a dug Fin structure, and can also be referred to as a dug Fin transistor.

[0095] The gate insulating film 41 of the pixel transistor 30 and the gate insulating film 45 of the transfer transistor TR are each configured by, for example, a monolayer film including one of silicon oxide (SiO), silicon oxynitride (SiON), hafnium oxide (HfO), or the like, or a stacked film including two or more thereof. The gate insulating films 41 and 45 may be formed using a high-permittivity material having a higher permittivity than a permittivity of silicon oxide, such as a hafnium-based insulating film.

[0096] The gate electrode 42 of the pixel transistor 30 and the gate electrode 46 of the transfer transistor TR are each configured using polysilicon (Poly-Si), for example. The gate electrode 42 and the gate electrode 46 may each be configured using a metal material or a metal compound. The gate electrodes 42 and 46 may each be configured by titanium nitride (TiN), tantalum nitride (TaN), tungsten (W), or the like, for example. It is to be noted that a sidewall may be provided on each of a side surface of the gate electrode 42 and a side surface of the gate electrode 46.

[0097] The contact 52, the contact 53, and the contact 55 are each configured using an electrically-conductive material. For example, the contacts 52, 53, and 55 are each formed by embedding (filling) an electrically-conductive material such as tungsten (W) into a contact hole. It is to be noted that each of the contacts 52, 53, and 55 may be configured by a metal material such as aluminum (Al) or copper (Cu), or may be configured using another material.

[0098] In the imaging device 1, the semiconductor region 35 is provided to be adjacent to the pixel transistor 30. For example, the semiconductor region 35 is provided, in the pixel P, to be adjacent to the source region or the drain region of the pixel transistor 30. The semiconductor region 35 and the source region or the drain region of the pixel transistor 30 are provided in the active region 81, as illustrated in Fig. 5 or other drawings. For example, the semiconductor region 35 is disposed, on the side of the surface 11S1 of the semiconductor layer 110, to be adjacent to the semiconductor region 33 of the pixel transistor 30 with a portion of the well 25 interposed therebetween.

[0099] The semiconductor region 35 is provided, for example, to be adjacent to an end (side part) of the semiconductor region 33 which is the source region or the drain region of the pixel transistor 30. It is to be noted that the semiconductor region 35 may be disposed to be adjacent to the semiconductor region 32. In addition, the semiconductor region 35 may be provided near the gate of the pixel transistor 30.

[0100] In the imaging device 1, the semiconductor region 35 is provided to be adjacent to the pixel transistor 30. This enables the imaging device 1 to have a structure advantageous to the miniaturization. It becomes possible to increase an area of a region in which the transistors or the like are arranged in the pixel P, as compared with a case where the semiconductor region 35 and the pixel transistor 30 are provided in different active regions. It becomes possible to increase the size (e.g., gate width, gate length, etc.) of the transistor arranged in the pixel P.

[0101] In the present embodiment, as in the example illustrated in Fig. 5, it is possible to increase an area of the pixel transistor 30. It is therefore possible to increase the size of the transistor, e.g., the amplification transistor AMP of the readout circuit 20. This makes it possible to suppress a noise being mixed into the pixel signal.

[0102] In particular, it is possible to improve area efficiency in a fine pixel and thus to increase the size of the pixel transistor 30. It is therefore possible to improve characteristics of the transistors (the amplification transistor AMP, the selection transistor SEL, the transistor FDG, the reset transistor RST, etc.) of the readout circuit 20.

[0103] In addition, the imaging device 1 according to the present embodiment is configured to allow the source region and the drain region of the pixel transistor 30 to have sizes different from each other. For example, in the imaging device 1, among the semiconductor region 32 and the semiconductor region 33 of the pixel transistor 30, the size of the semiconductor region 33 adjacent to the semiconductor region 35, which is a well contact region, is smaller than the size of the semiconductor region 32.

[0104] In the example illustrated in Fig. 5, the semiconductor region 33 and the semiconductor region 35 are provided to be adjacent to each other in the X-axis direction. As in the example illustrated in Fig. 5, the width of the semiconductor region 33 in the X-axis direction may be smaller than the width of the semiconductor region 32 in the X-axis direction. Among the semiconductor region 32 and the semiconductor region 33, the size (e.g., width) of the semiconductor region 33 is made to be relatively small. It is to be noted that, in a case where the semiconductor region 35 is disposed to be adjacent to the semiconductor region 32, the size (width, etc.) of the semiconductor region 32 may be smaller than the size of the semiconductor region 33.

[0105] As described above, in the imaging device 1, the semiconductor region 33 has a size or a shape different from that of the semiconductor region 32. For example, the size of the semiconductor region 33 is determined to secure an interval (distance) between the semiconductor region 35, which is a well contact region, and the semiconductor region 33 which is a source region (or a drain region). It is therefore possible to relax an electric field (potential gradient) between the well contact region and the semiconductor region 33. This makes it possible to suppress a noise being mixed into the pixel signal, and thus to suppress degradation in image quality.

[0106] In particular, also in a fine pixel, it is possible to relax an electric field generated between the well contact region (the semiconductor region 35) and the semiconductor region 33 (or the semiconductor region 32). It is therefore possible to suppress degradation in quality of the pixel signal, and thus to suppress degradation in image quality. For example, it is possible to suppress occurrence of defects (flaws) such as a white spot in an image caused by a strong electric field between the well contact region and the source region (or drain region) of the pixel transistor 30.

[0107] Fig. 8 is a diagram illustrating an arrangement example of pixel transistors of the imaging device according to the first embodiment. Fig. 8 illustrates 2 × 2 pixels in which four pixels P as the pixels Pa to Pd share the readout circuit 20. Another plurality of pixels P in the imaging device 1 may also have a configuration similar to the configuration illustrated in Fig. 8.

[0108] In the example illustrated in Fig. 8, the pixel Pa is provided with the amplification transistor AMP as the pixel transistor 30. The pixel Pb is provided with the selection transistor SEL as the pixel transistor 30. The pixel Pc is provided with the reset transistor RST as the pixel transistor 30. In addition, the pixel Pd is provided with a dummy transistor as the pixel transistor 30.

[0109] The imaging device 1 is provided with wiring L3, for example, as in the example illustrated in Fig. 8. The respective floating diffusions FD of the plurality of pixels P sharing the readout circuit 20 are electrically coupled to the transistors of the readout circuit 20 via the wiring L3. In the example illustrated in Fig. 8, the respective floating diffusions FD of the pixels Pa to Pd are electrically coupled to the gate electrode of the amplification transistor AMP, which is the pixel transistor 30, of the pixel Pa via the wiring L3.

[0110] The wiring L3 is wiring to be shared among the four pixels Pa to Pd. The wiring L3 is formed using a metal material such as aluminum (Al) or tungsten (W), for example. It is to be noted that the wiring L3 may be configured using a polysilicon (Poly-Si) or another electrically-conductive material.

[0111] Fig. 9 and Fig. 10 are each a diagram illustrating another arrangement example of the pixel transistors of the imaging device according to the first embodiment. The transistors of the readout circuit 20 may be arranged as illustrated in Fig. 9 or 10. In the example illustrated in Fig. 9, the readout circuit 20 includes the amplification transistor AMP, the selection transistor SEL, the reset transistor RST, and the transistor FDG.

[0112] In the example illustrated in Fig. 9, the pixel Pa includes the amplification transistor AMP as the pixel transistor 30. The pixel Pb includes the selection transistor SEL as the pixel transistor 30. The pixel Pc includes the reset transistor RST as the pixel transistor 30. In addition, the pixel Pd includes the transistor FDG as the pixel transistor 30.

[0113] The readout circuit 20 may include a plurality of amplification transistors AMP (an amplification transistor AMP1 and an amplification transistor AMP2 in Fig. 10) electrically coupled in parallel to each other. In the example illustrated in Fig. 10, the amplification transistor AMP1 is arranged in the pixel Pa, and the amplification transistor AMP2 is arranged in the pixel Pb. In the readout circuit 20, the amplification transistors AMP1 and AMP2 coupled in parallel to each other may generate and output pixel signals. This makes it possible to reduce a noise being mixed into the pixel signal.

[0114] Fig. 11 is a diagram illustrating an example of a cross-sectional configuration of the imaging device according to the first embodiment. For example, as illustrated in Fig. 11, the imaging device 1 includes a light-guiding section 90, the semiconductor layer 110, and the wiring layer 120. The imaging device 1 has a configuration in which the light-guiding section 90, the semiconductor layer 110, and the wiring layer 120 are stacked in the Z-axis direction.

[0115] In the example illustrated in Fig. 11, the wiring layer 120 is provided on the side of the surface 11S1 of the semiconductor layer 110. The light-guiding section 90 is provided on a side of the surface 11S2 of the semiconductor layer 110. The light-guiding section 90 is provided on a side on which light from an optical system is incident, and the wiring layer 120 is provided on a side opposite to the side on which light is incident. The imaging device 1 is a so-called back side illumination imaging device.

[0116] The wiring layer 120 includes, for example, a conductive film and an insulating film, and includes a plurality of pieces of wiring, a via (VIA), and the like. The wiring layer 120 includes wiring of two or more layers, or three or more layers, for example. The wiring layer 120 may include wiring of five or more layers. The wiring layer 120 has a configuration in which a plurality of pieces of wiring is stacked with an insulating film, as an interlayer insulating film (interlayer insulating layer), being interposed therebetween. The insulating film of the wiring layer 120 may also be referred to as an interlayer insulating film (interlayer insulating layer).

[0117] The wiring of the wiring layer 120 is formed using a metal material such as aluminum (Al), tungsten (W), or copper (Cu), for example. The wiring of the wiring layer 120 may be configured using polysilicon (Poly-Si) or another electrically-conductive material. The interlayer insulating film is formed using silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), or the like, for example.

[0118] The semiconductor layer 110 and the wiring layer 120 are provided with the photoelectric conversion section 12, the readout circuit 20, and the like, for example, as described above. In addition, the pixel drive section 111, the signal processing section 112, the control section 113, the processing section 114, and the like described above may be provided in a substrate different from the semiconductor layer 110 or in the semiconductor layer 110 and the wiring layer 120.

[0119] The trench 91 and the trench 92 are provided between the photoelectric conversion sections 12 adjacent to each other to separate the photoelectric conversion sections 12 from each other. The trench 91 and the trench 92 are provided to surround the photoelectric conversion section 12 in the semiconductor layer 110. It is to be noted that, as illustrated in Fig. 8 or other drawings, the trench 91 and the trench 92 are formed in a lattice pattern in a plan view, and are arranged to surround each of the plurality of photoelectric conversion sections 12.

[0120] The light-guiding section 90 illustrated in Fig. 11 is stacked on the semiconductor layer 110 in a thickness direction orthogonal to the surface 11S2 of the semiconductor layer 110. The light-guiding section 90 includes, for example, the lens 21 and the filter 22, and guides incident light to a side of the semiconductor layer 110.

[0121] The lens 21 is provided on the filter 22, for example, for each of the pixels P or for every plurality of pixels P. Light from a subject is incident on the lens 21 via an optical system such as an imaging lens. The photoelectric conversion section 12 photoelectrically converts incident light via the lens 21 and the filter 22.

[0122] As illustrated in Fig. 11, the imaging device 1 is provided with a light-blocking section 23. The light-blocking section 23 (light-blocking film) is configured by a member that blocks light, and is provided at a boundary between the plurality of pixels P adjacent to each other. For example, at least a portion of the light-blocking section 23 (light-blocking member) may be provided between the filters 22 adjacent to each other, and may be positioned at a boundary between the filters 22 adjacent to each other.

[0123] The light-blocking section 23 is configured by a metal material that blocks light (aluminum (Al), tungsten (W), copper (Cu), etc.), for example. The light-blocking section 23 may be configured by a material that absorbs light. The light-blocking section 23 may be configured using polysilicon, for example. In the imaging device 1, providing the light-blocking section 23 suppresses leakage of light to surrounding pixels P. It becomes possible to suppress leakage of unnecessary light to the surroundings, and thus to suppress occurrence of color mixture.

[0124] It is to be noted that the imaging device 1 may include at least one of a fixed charge film or an antireflection film. The fixed charge film and the antireflection film are provided on the side of the surface 11S2 of the semiconductor layer 110, for example. The fixed charge film is a film having fixed electric charge, and may be formed using a high-permittivity material. As an example, the fixed charge film is configured by a metal oxide such as hafnium oxide or aluminum oxide.

[0125] The fixed charge film is, for example, a film having negative fixed electric charge. As an example, the fixed charge film is provided between the semiconductor layer 110 and the filter 22. Providing the fixed charge film suppresses generation of a dark current at an interface of the semiconductor layer 110. It is to be noted that the fixed charge film may be configured by another metal oxide film, or may be configured using a metal nitride film or a metal oxynitride film. A film having positive fixed electric charge may be provided as the fixed charge film.

[0126] As an example, the antireflection film may be configured using an insulating material such as silicon nitride (SiN) or silicon oxide (SiO). The antireflection film is provided to be stacked on the fixed charge film, for example. The antireflection film is provided, for example, between the semiconductor layer 110 and the filter 22 to reduce (suppress) reflection. It is to be noted that the antireflection film may be configured using a metal compound (metal oxide, metal nitride, etc.) such as aluminum oxide, hafnium oxide, or tantalum oxide, or may be configured using another material.Workings and Effects

[0127] The photodetector according to the present embodiment includes a semiconductor layer (semiconductor layer 110), a plurality of pixels including a first pixel (e.g., pixel Pa) including a photoelectric conversion element (photoelectric conversion section 12) provided in a semiconductor layer, and a trench (trenches 91 and 92) provided between the plurality of pixels adjacent to each other in the semiconductor layer. The first pixel includes a transistor (pixel transistor 30) provided on a side of a first surface of the semiconductor layer, a first semiconductor region (semiconductor region 35) of a first electrically-conductive type provided on the side of the first surface of the semiconductor layer, and a first contact (contact 55) electrically coupled to the first semiconductor region. The transistor includes a second semiconductor region and a third semiconductor region (semiconductor region 32 and semiconductor region 33) of a second electrically-conductive type. The first semiconductor region is provided to be adjacent to the second semiconductor region (e.g., semiconductor region 33). The second semiconductor region and the third semiconductor region have sizes different from each other.

[0128] In the photodetector (imaging device 1) according to the present embodiment, the semiconductor region 35 is provided to be adjacent to the semiconductor region 33 which is the source region or the drain region of the pixel transistor 30. The semiconductor region 33 and the semiconductor region 32 have sizes different from each other. This enables the imaging device 1 to have a structure advantageous to pixel miniaturization. It becomes possible to relax the electric field between the semiconductor region 35 and the semiconductor region 33. It becomes possible to achieve the photodetector advantageous to the miniaturization.

[0129] Next, description is given of modification examples of the present disclosure. Hereinafter, components similar to those in the foregoing embodiment are denoted by the same reference numerals, and descriptions thereof are omitted as appropriate. (1-1. Modification Example 1)

[0130] Fig. 12 is a diagram illustrating an example of a planar configuration of a pixel of an imaging device according to Modification Example 1 of the present disclosure. The imaging device 1 may be configured to allow a size (area, width, etc.) of the active region 81 on a side of the source region and a size of the active region 81 on a side of the drain region to differ from each other. The active region 81 is configured, for example, to have different sizes (e.g., widths) on the side of the source region and on the side of the drain region of the pixel transistor 30.

[0131] In the imaging device 1, as an example, the size of the active region 81 on a side of the semiconductor region 33 close to the semiconductor region 35, which is the well contact region, may be smaller than the size of the active region 81 on a side of the semiconductor region 32. As in the example illustrated in Fig. 12, a width W1 of the active region 81 in the X-axis direction on the side of the semiconductor region 33 may be smaller than a width W2 of the active region 81 in the X-axis direction on the side of the semiconductor region 32.

[0132] In addition, in the imaging device 1, the size of the semiconductor region 33 close to the semiconductor region 35, which is the well contact region, may be smaller than the size of the semiconductor region 32. In the example illustrated in Fig. 12, the width of the semiconductor region 33 in the X-axis direction is smaller than the width of the semiconductor region 32 in the X-axis direction.

[0133] It is to be noted that, in a case where the semiconductor region 35 is disposed to be adjacent to the semiconductor region 32, the size of the active region 81 on the side of the semiconductor region 32 close to the semiconductor region 35 may be smaller than the size of the active region 81 on the side of the semiconductor region 33. For example, the width of the active region 81 on the side of the semiconductor region 32 may be smaller than the width of the active region 81 on the side of the semiconductor region 33.

[0134] In a photodetector according to the present modification example, a first pixel (pixel P) includes a first region (active region 81) of a semiconductor layer provided with a second semiconductor region and a third semiconductor region (semiconductor region 32 and semiconductor region 33), and a separation section (trench 93) provided around the first region. A size of the first region on a side of the second semiconductor region is smaller than a size of the first region on a side of the third semiconductor region.

[0135] In the photodetector (imaging device 1) according to the present modification example, the size of the active region 81 on the side of the semiconductor region 33 is smaller than the size of the active region 81 on the side of the semiconductor region 32, for example, in a region where the pixel transistor 30 is disposed. It is therefore possible to relax the electric field between the semiconductor region 35 and the semiconductor region 33. It becomes possible to suppress a noise being mixed into the pixel signal, and thus to suppress degradation in image quality. (1-2. Modification Example 2)

[0136] Fig. 13 is a diagram illustrating an example of a planar configuration of a pixel of an imaging device according to Modification Example 2. Among a portion of the active region 81 near the semiconductor region 35 and the semiconductor region 33 (or the semiconductor region 32), only the portion of the active region 81 may be made to be smaller, as in the example illustrated in Fig. 13.

[0137] For example, the size of the active region 81 on the side of the semiconductor region 33 close to the semiconductor region 35 is smaller than the size of the active region 81 on the side of the semiconductor region 32. In the example illustrated in Fig. 13, the width W1 of the active region 81 in the X-axis direction on the side of the semiconductor region 33 is smaller than the width W2 of the active region 81 in the X-axis direction on the side of the semiconductor region 32.

[0138] The size of the semiconductor region 33 close to the semiconductor region 35 may be substantially the same as the size of the semiconductor region 32, or may be larger than the size of the semiconductor region 32. It is to be noted that, in a case where the semiconductor region 35 is provided to be adjacent to the semiconductor region 32, the size of the active region 81 on the side of the semiconductor region 32 close to the semiconductor region 35 may be smaller than the size of the active region 81 on the side of the semiconductor region 33.

[0139] The photodetector according to the present modification example includes a semiconductor layer (semiconductor layer 110), a plurality of pixels including a first pixel including a photoelectric conversion element provided in the semiconductor layer, and a trench (trenches 91 and 92) provided between the plurality of pixels adjacent to each other in the semiconductor layer. The first pixel includes a first semiconductor region (semiconductor region 35) of a first electrically-conductive type provided on a side of a first surface of the semiconductor layer, a first contact (contact 55) electrically coupled to the first semiconductor region, a transistor (pixel transistor 30) including a second semiconductor region and a third semiconductor region (semiconductor region 32 and semiconductor region 33) of a second electrically-conductive type, which are each provided in a first region on the side of the first surface of the semiconductor layer, and a separation section (trench 93) provided around the first region (active region 81). The first semiconductor region is provided to be adjacent to the second semiconductor region. A size of the first region on a side of the second semiconductor region is smaller than a size of the first region on a side of the third semiconductor region.

[0140] In the photodetector (imaging device 1) according to the present modification example, for example, the size of the active region 81 on the side of the semiconductor region 33 is smaller than the size of the active region 81 on the side of the semiconductor region 32. It is therefore possible to relax the electric field between the semiconductor region 35 and the semiconductor region 33. It becomes possible to suppress a noise being mixed into the pixel signal, and thus to suppress degradation in image quality.

[0141] Fig. 14 is a diagram illustrating another example of the planar configuration of the pixel of the imaging device according to Modification Example 2. In the imaging device 1, the width of the active region 81 in the X-axis direction (or Y-axis direction) may be gradually smaller (narrower), for example, as schematically illustrated by a dotted line in Fig. 14. In the example illustrated in Fig. 14, the active region 81 includes a portion P1 of which a width becomes smaller as being closer to the semiconductor region 35. Also in this case, it is possible to relax the electric field between the well contact region and the source region (or drain region) of the pixel transistor 30, and thus to suppress occurrence of defects such as a white spot in an image. (1-3. Modification Example 3)

[0142] Figs. 15A and 15B are each a diagram illustrating an example of a planar configuration of a pixel of an imaging device according to Modification Example 3. The shape of the semiconductor region 31 to be a channel region is not limited to the above-described example. The shape of the active region 81 below the gate electrode 42 of the pixel transistor 30 and the shape of the semiconductor region 31 are changeable as appropriate.

[0143] In the imaging device 1, the width of the semiconductor region 31 in the X-axis direction (or Y-axis direction) may become smaller as being closer to the semiconductor region 33 (or the semiconductor region 32) adjacent to the semiconductor region 35 which is the well contact region. In the example illustrated in Fig. 15A, it can also be said that the width of the semiconductor region 31 in the X-axis direction becomes smaller as being away from the semiconductor region 32.

[0144] The semiconductor region 31 may have a trapezoidal shape, for example, as in the example illustrated in Fig. 15A. The semiconductor region 31 may have a polygonal shape or another shape. As illustrated in Fig. 15B, the semiconductor region 31 may have a pentagonal shape in a plan view.

[0145] In the photodetector (imaging device 1) according to the present modification example, a size of a channel region (semiconductor region 31) on a side of a second semiconductor region (e.g., semiconductor region 33) is smaller than a size of a channel region on a side of a third semiconductor region (e.g., semiconductor region 32). Also in the present modification example, it is possible to relax the electric field between the semiconductor region 35 and the semiconductor region 33. It becomes possible to suppress a noise being mixed into the pixel signal, and thus to suppress degradation in image quality. (1-4. Modification Example 4)

[0146] Fig. 16 is a diagram illustrating an example of a planar configuration of a pixel of an imaging device according to Modification Example 4. Fig. 17 is a diagram illustrating an example of a cross-sectional configuration of a pixel of the imaging device. Fig. 17 schematically illustrates a configuration example of the pixel in a direction along a line A-A' illustrated in Fig. 16.

[0147] In the imaging device 1 according to the present modification example, a conductor region 36 is provided, as illustrated in Figs. 16 and 17. The conductor region 36 is provided around the semiconductor region 35. At least a portion of the conductor region 36 is provided in contact with the semiconductor region 35. The conductor region 36 is formed to be adjacent to the semiconductor region 35, for example, on the side of the surface 11S1 of the semiconductor layer 110. In the example illustrated in Fig. 17, the conductor region 36 is positioned above the inside of the trenches 91 and 92.

[0148] The conductor region 36 is configured by polysilicon to which impurities are doped (added), for example. It is to be noted that the conductor region 36 (electrically-conductive section) may be configured using another electrically-conductive material (e.g., metal material, etc.). The conductor region 36 has a higher impurity concentration than an impurity concentration of the well 25, for example.

[0149] The contact 55 is provided on the conductor region 36. The contact 55 is electrically coupled to the semiconductor region 35 and the well 25 via the conductor region 36. In the imaging device 1 according to the present modification example, the semiconductor region 35 provided in the well 25 and the contact 55 are electrically coupled to each other via the conductor region 36. Allowing the well contact and the well contact region to have a side contact structure makes it possible to improve area efficiency in the pixel P.

[0150] In addition, it is possible to reduce an impurity concentration of the semiconductor region 35 necessary to be electrically coupled to the contact 55. Reducing the impurity concentration of the semiconductor region 35 makes it possible to reduce the electric field between the semiconductor region 35 and the semiconductor region 33 (source region or drain region) of the pixel transistor 30. It is therefore possible to suppress occurrence of flaws in the pixel transistor 30. It becomes possible to prevent an increase in a noise being mixed in the pixel signal.

[0151] In the imaging device 1, respective semiconductor regions 35 of the plurality of pixels P (e.g., pixels Pa to Pd in Figs. 8, 9, etc.) adjacent to each other may be electrically coupled to the contact 55 via the common conductor region 36. In addition, the conductor region 36 may be positioned above the inside of the trench 91, as illustrated in Fig. 17. In this case, it is possible to prevent occurrence of unnecessary parasitic capacitance in the imaging device 1. For example, it is possible to avoid addition of the unnecessary parasitic capacitance to the transistor of the readout circuit 20.

[0152] Figs. 18A and 18B are each a diagram illustrating another example of the cross-sectional configuration of the pixel of the imaging device according to Modification Example 4. As illustrated in Fig. 18A, the conductor region 36 may be provided on the surface 11S1 of the semiconductor layer 110. In the example illustrated in Fig. 18A, the conductor region 36 is provided in the wiring layer 120. As in the example illustrated in Fig. 18B, a portion of the conductor region 36 may be provided in the semiconductor layer 110. A portion of the conductor region 36 may be formed in the trench 91.

[0153] Figs. 19A and 19B are each a diagram illustrating another example of the planar configuration of the pixel of the imaging device according to Modification Example 4. The imaging device 1 may be configured to allow the size (area, width, etc.) of the active region 81 on the side of the source region and the size of the active region 81 on the side of the drain region to differ from each other. For example, as in the example illustrated in Fig. 19A, in the region where the pixel transistor 30 is disposed, the width of the active region 81 on the side of the semiconductor region 33 close to the semiconductor region 35, which is the well contact region, may be smaller than the width of the active region 81 on the side of the semiconductor region 32.

[0154] It is to be noted that the shape of the active region 81 below the gate electrode 42 of the pixel transistor 30 and the shape of the semiconductor region 31 are not limited to the example illustrated in Fig. 19A. The semiconductor region 31 to be a channel region may have a trapezoidal shape, as illustrated in Fig. 19B. The semiconductor region 31 may have a pentagonal shape or another shape in a plan view. (1-5. Modification Example 5)

[0155] Fig. 20 is a diagram illustrating an example of a planar configuration of a pixel of an imaging device according to Modification Example 5. As illustrated in Fig. 20, the imaging device 1 may include a semiconductor region 37. The semiconductor region 37 is provided around the floating diffusion FD in the semiconductor layer 110. As an example, the semiconductor region 37 is configured by polysilicon doped with impurities. It is to be noted that the semiconductor region 37 may be configured using another electrically-conductive material. At least a portion of the semiconductor region 37 is provided in contact with the floating diffusion FD.

[0156] The respective floating diffusions FD of the plurality of pixels P (pixel Pa to pixel Pd in Fig. 8, etc.) sharing the readout circuit 20 may be electrically coupled to each other via the semiconductor region 37. The respective floating diffusions FD of the pixels Pa to Pd are electrically coupled to the amplification transistor AMP, the reset transistor RST, and the like of the readout circuit 20 via the semiconductor region 37.

[0157] In the imaging device 1 according to the present modification example, allowing the floating diffusion FD and the semiconductor region 37 to have the side contact structure makes it possible to improve the area efficiency in the pixel P, as described above. It becomes possible to secure the area of a region where the transistor and the like are arranged in the pixel P. <2. Second Embodiment>

[0158] Next, description is given of a second embodiment of the present disclosure. Hereinafter, components similar to those in the foregoing embodiment are denoted by the same reference numerals, and descriptions thereof are omitted as appropriate.

[0159] Fig. 21 is a diagram illustrating an arrangement example of pixels of an imaging device according to the second embodiment of the present disclosure. The pixel P of the imaging device 1 includes the plurality of photoelectric conversion sections 12 (a photoelectric conversion section 12a and a photoelectric conversion section 12b in the example illustrated in Fig. 21). The photoelectric conversion section 12b is provided next to the photoelectric conversion section 12a. It can also be said that a pixel including the photoelectric conversion section 12a and a pixel including the photoelectric conversion section 12b are provided.

[0160] In the present embodiment, one lens 21 (lens section) is provided for the plurality of photoelectric conversion sections 12, e.g., for two photoelectric conversion sections 12 (photoelectric conversion section 12a and photoelectric conversion section 12b). The photoelectric conversion section 12a and the photoelectric conversion section 12b receive light having passed through regions of different optical systems such as imaging lenses to perform pupil division.

[0161] It is possible to obtain phase difference data (phase difference information) by using a first pixel signal based on electric charge photoelectrically converted by the photoelectric conversion section 12a and a second pixel signal based on electric charge photoelectrically converted by the photoelectric conversion section 12b. Use of the phase difference data makes it possible to perform phase difference AF (Auto Focus).

[0162] The readout circuit 20 is configured to be able to output the first pixel signal and the second pixel signal of the respective pixels P sharing the readout circuit 20. In addition, the readout circuit 20 may read a pixel signal corresponding to electric charge which is the sum of the electric charge converted by the photoelectric conversion section 12a and the electric charge converted by the photoelectric conversion section 12b.

[0163] Fig. 22 is a diagram illustrating an example of a planar configuration of a pixel of the imaging device according to the second embodiment. The pixel P of the imaging device 1 includes transfer transistors Tra and TRb, floating diffusions FDa and FDb, pixel transistors 30a and 30b, and the semiconductor region 35.

[0164] The transfer transistor TRa is configured to be able to transfer the electric charge photoelectrically converted by the photoelectric conversion section 12a to the floating diffusion FDa. In addition, the transfer transistor TRb is configured to be able to transfer the electric charge photoelectrically converted by the photoelectric conversion section 12b to the floating diffusion FDb.

[0165] The floating diffusion FDa may accumulate the electric charge photoelectrically converted by the photoelectric conversion section 12a. In addition, the floating diffusion FDb may accumulate the electric charge photoelectrically converted by the photoelectric conversion section 12b. The transfer transistor TRa and the floating diffusion FDa are provided in an active region 82a, for example. In addition, the transfer transistor TRb and the floating diffusion FDb are provided in an active region 82b, for example.

[0166] The readout circuit 20 is configured to be able to output, for example, a pixel signal based on the electric charge accumulated in the floating diffusion FDa, a pixel signal based on the electric charge accumulated in the floating diffusion FDb, and the like. In addition, for example, the readout circuit 20 is configured to be able to output a pixel signal corresponding to electric charge which is the sum of the electric charge accumulated in the floating diffusion FDa and the electric charge accumulated in the floating diffusion FDb.

[0167] The pixel transistor 30a and the pixel transistor 30b are transistors of the readout circuit 20, for example. A semiconductor region 32a and a semiconductor region 33a are a source region and a drain region of the pixel transistor 30a. One of the semiconductor regions 32a and 33a is the source region of the pixel transistor 30a, and another of the semiconductor regions 32a and 33a is the drain region of the pixel transistor 30a.

[0168] In addition, a semiconductor region 32b and a semiconductor region 33b are a source region and a drain region of the pixel transistor 30b. One of the semiconductor regions 32b and 33b is the source region of the pixel transistor 30b, and another of the semiconductor regions 32b and 33b is the drain region of the pixel transistor 30b.

[0169] The pixel transistors 30a and 30b are each used as the amplification transistor AMP, the selection transistor SEL, the transistor FDG, the reset transistor RST, or the like. It is to be noted that the pixel transistor 30a or the pixel transistor 30b of some of the pixels P may be a dummy transistor. The readout circuit 20 may include a dummy transistor as the pixel transistor 30a or the pixel transistor 30b.

[0170] Fig. 23 is a diagram illustrating another example of the planar configuration of the pixel of the imaging device according to the second embodiment. The imaging device 1 may include a separation section 95a and a separation section 95b, as in the example illustrated in Fig. 23. The separation section 95a and the separation section 95b each include a trench, for example. For example, the separation section 95a and the separation section 95b are each provided between the photoelectric conversion section 12a and the photoelectric conversion section 12b in the semiconductor layer 110.

[0171] The separation section 95a and the separation section 95b may be configured using an insulating material, or may be configured by a semiconductor region formed by ion implantation. For example, the separation section 95a and the separation section 95b may be configured by a p-type semiconductor region or an n-type semiconductor region.

[0172] For example, the separation section 95a is provided between a plurality of floating diffusions FD adjacent to each other on the side of the surface 11S1 of the semiconductor layer 110. In the example illustrated in Fig. 23, the separation section 95a is formed between the floating diffusion FDa and the floating diffusion FDb.

[0173] The separation section 95b is provided between the plurality of pixel transistors 30 adjacent to each other on the side of the surface 11S1 of the semiconductor layer 110. In the example illustrated in Fig. 23, the separation section 95b is formed between the pixel transistor 30a and the pixel transistor 30b. For example, as illustrated in Fig. 23, the semiconductor region 35 is provided between the separation section 95a and the separation section 95b in a plan view.

[0174] In the imaging device 1 according to the present embodiment, the semiconductor region 35 is provided to be adjacent to the pixel transistor 30a and the pixel transistor 30b. For example, in the pixel P, the semiconductor region 35 is disposed to be adjacent to the source region or the drain region of the pixel transistor 30a and to be adjacent to the source region or the drain region of the pixel transistor 30b.

[0175] In the example illustrated in Fig. 23, the semiconductor region 35, the source region or the drain region of the pixel transistor 30a, and the source region or the drain region of the pixel transistor 30b are provided in the active region 81, for example. The semiconductor region 35 is provided to be adjacent to the semiconductor region 33a of the pixel transistor 30a, and to be adjacent to the semiconductor region 33b of the pixel transistor 30b. It is to be noted that the semiconductor region 35 may be disposed to be adjacent to the semiconductor regions 32a and 32b.

[0176] As described above, in the present embodiment, the semiconductor region 35 is provided to be adjacent to the pixel transistor 30a and the pixel transistor 30b. This enables the imaging device 1 to have a structure advantageous to the miniaturization. It is possible to increase an area of a region where the transistor and the like are arranged in the pixel P, as compared with a case where the semiconductor region 35 and the pixel transistors 30a and 30b are provided to be distant from each other. It becomes possible to increase the size of a transistor to be arranged in the pixel P.

[0177] In addition, the imaging device 1 is configured to allow each of the pixel transistors 30a and 30b to have a source region and a drain region which have different sizes. For example, among the semiconductor region 32a and the semiconductor region 33a of the pixel transistor 30a, the size (width, area, etc.) of the semiconductor region 33a adjacent to the semiconductor region 35, which is the well contact region, is smaller than the size of the semiconductor region 32a.

[0178] In addition, among the semiconductor region 32b and the semiconductor region 33b of the pixel transistor 30b, the size (width, area, etc.) of the semiconductor region 33b adjacent to the semiconductor region 35, which is the well contact region, is smaller than the size of the semiconductor region 32b. Configuring the imaging device 1 in this manner makes it possible to relax the electric field between the well contact region and the source region (or drain region). It becomes possible to suppress a noise being mixed into the pixel signal. Workings and Effects

[0179] The photodetector according to the present embodiment includes a semiconductor layer (semiconductor layer 110), a plurality of pixels including a first pixel including a first photoelectric conversion element and a second photoelectric conversion element (photoelectric conversion section 12a and photoelectric conversion section 12b) provided in the semiconductor layer, and a trench (trenches 91 and 92) provided between the plurality of pixels adjacent to each other in the semiconductor layer. The first pixel includes a first transistor (e.g., pixel transistor 30a) provided on a side of a first surface of the semiconductor layer, a first semiconductor region (semiconductor region 35) of a first electrically-conductive type provided on the side of the first surface of the semiconductor layer, and a first contact (contact 55) electrically coupled to the first semiconductor region. The first transistor includes a second semiconductor region and a third semiconductor region (semiconductor region 32a and semiconductor region 33a) of a second electrically-conductive type. The first semiconductor region is provided to be adjacent to the second semiconductor region. The second semiconductor region and the third semiconductor region have sizes different from each other.

[0180] In the photodetector (imaging device 1) according to the present embodiment, the semiconductor region 35 is provided to be adjacent to the semiconductor region 33a which is the source region or the drain region of the pixel transistor 30a. The semiconductor region 33a and the semiconductor region 32a have sizes different from each other. It is therefore possible for the imaging device 1 to have a structure advantageous to pixel miniaturization. It becomes possible to relax the electric field between the semiconductor region 35 and the semiconductor region 33a. It becomes possible to achieve the photodetector advantageous to the miniaturization.

[0181] Next, description is given of modification examples of the present disclosure. Hereinafter, components similar to those in the foregoing embodiment are denoted by the same reference numerals, and descriptions thereof are omitted as appropriate. (2-1. Modification Example 6)

[0182] Fig. 24 is a diagram illustrating an example of a planar configuration of a pixel of an imaging device according to Modification Example 6 of the present disclosure. The imaging device 1 may be configured to allow the size of the active region 81 on the side of the source region and the size of the active region 81 on the side of the drain region to differ from each other. For example, as in the example illustrated in Fig. 24, in a region where the pixel transistor 30a is disposed, the width of the active region 81 on a side of the semiconductor region 33a close to the semiconductor region 35, which is the well contact region, may be smaller than the width of the active region 81 on a side of the semiconductor region 32a.

[0183] In addition, the width of the active region 81 on a side of the semiconductor region 33b close to the semiconductor region 35, which is the well contact region, may be smaller than the width of the active region 81 on a side of the semiconductor region 32b. It is to be noted that, in a case where the semiconductor region 35 is disposed adjacent to the semiconductor regions 32a and 32b, the size (width) of the semiconductor region 32a may be smaller than the size of the semiconductor region 33a. In addition, the size of the semiconductor region 32b may be smaller than the size of the semiconductor region 33b. (2-2. Modification Example 7)

[0184] Fig. 25 is a diagram illustrating an example of a planar configuration of a pixel of an imaging device according to Modification Example 7. The active region 81 below a gate electrode 42a of the pixel transistor 30a and the semiconductor region 31a to be a channel region may have a trapezoidal shape, as in the example illustrated in Fig. 25. The active region 81 below a gate electrode 42b of the pixel transistor 30b and the semiconductor region 31b to be a channel region may have a trapezoidal shape. In addition, for example, the active region 81 below the gate electrode 42a (or the gate electrode 42b) and the semiconductor region 31a (or the semiconductor region 31b) may have pentagonal shapes. (2-3. Modification Example 8)

[0185] Fig. 26 is a diagram illustrating an example of a planar configuration of a pixel of an imaging device according to Modification Example 8. The imaging device 1 may have the conductor region 36 that electrically couples the contact 55 and the semiconductor region 35 to each other. As an example, the conductor region 36 is configured by polysilicon doped with impurities. The conductor region 36 may be configured using another electrically-conductive material.

[0186] Each of the pixels P of the imaging device 1 may have a structure illustrated in Fig. 27A or 27B. For example, the size (e.g., width) of the active region 81 on the side of the source region may differ from the size of the active region 81 on the side of the drain region. In addition, the shape of the channel region may be a trapezoidal shape or a pentagonal shape.

[0187] Fig. 28 is a diagram illustrating another example of the planar configuration of the pixel of the imaging device according to Modification Example 8. As in the example illustrated in Fig. 28, the imaging device 1 may include the semiconductor region 37 that electrically couples the plurality of floating diffusions FD to each other. For example, the floating diffusion FDa and the floating diffusion FDb are electrically coupled to each other via the semiconductor region 37.

[0188] In the imaging device 1, the semiconductor region 37 is provided in the semiconductor layer 110, for example. As an example, the semiconductor region 37 is configured by polysilicon doped with impurities. It is to be noted that the semiconductor region 37 may be configured using another electrically-conductive material. The semiconductor region 37 may be formed on the semiconductor layer 110. A portion of the semiconductor region 37 may be provided in the semiconductor layer 110.

[0189] In addition, for example, the semiconductor region 37 may be provided for the plurality of pixels P (e.g., pixels Pa to Pd) adjacent to each other. The respective floating diffusions FD of the plurality of pixels P may be electrically coupled to each other via the common semiconductor region 37. (2-4. Modification Example 9)

[0190] Fig. 29 is a diagram illustrating an example of a planar configuration of a pixel of an imaging device according to Modification Example 9. As illustrated in Fig. 29, the semiconductor region 35 may be provided between the semiconductor region 33a, which is the source region or the drain region of the pixel transistor 30a, and the semiconductor region 33b, which is the source region or the drain region of the pixel transistor 30b. In this case, it is possible to secure a distance between the contact 55 and the channel region of the pixel transistor 30a or 30b.

[0191] It is to be noted that the semiconductor region 35 may be disposed between the semiconductor region 32a, which is the source region or the drain region of the pixel transistor 30a, and the semiconductor region 32b, which is the source region or the drain region of the pixel transistor 30b. As in the example illustrated in Fig. 30, the imaging device 1 may include the separation section 95a and the separation section 95b.

[0192] As illustrated in Fig. 29 or 30, the semiconductor region 35 (or the active region 81) may include a first part 61 and a second part 62. The first part 61 is provided to be adjacent to the pixel transistors 30a and the pixel transistors 30b in the horizontal direction (X-axis direction) in a plan view. For example, the first part 61 is disposed to be adjacent to respective gates of the pixel transistors 30a and 30b.

[0193] In addition, the second part 62 is in contact with the first part 61 in the vertical direction (Y-axis direction). The contact 55 is provided in the second part 62. The contact 55 is provided on the second part 62. The first part 61 has an impurity concentration lower than an impurity concentration of the second part 62, for example.

[0194] The semiconductor region 35 is positioned between the separation section 95a and the separation section 95b, and the contact 55 is distant from respective channel regions of the pixel transistors 30a and 30b. This makes it possible to suppress a noise being mixed into the pixel signal, and thus to suppress a decrease in accuracy of phase difference detection. In addition, the suppression of degradation in image quality is expectable. Further, moving (distancing) the contact 55 away from the channel region also makes it possible to lower an impurity concentration in the vicinity of a location where the channel region and the semiconductor region 35 are adjacent to each other. This enables a design that relaxes generation of a strong electric field.

[0195] In addition, the first part 61 has an impurity concentration lower than an impurity concentration of the second part 62 coupled to the contact 55, for example. Lowering the impurity concentration of the first part 61 makes it possible to suppress the generation of a strong electric field between the first part 61 and the channel region. Therefore, the reduction in a noise being mixed into the pixel signal is expectable.

[0196] Figs. 31A and 31B are each a diagram illustrating another example of the planar configuration of the pixel of the imaging device according to Modification Example 9. The imaging device 1 may be configured to allow the size of the active region 81 on the side of the source region and the size of the active region 81 on the side of the drain region to differ from each other. For example, as in the example illustrated in Fig. 31A, the width of the active region 81 on the side of the semiconductor region 33 relatively close to the semiconductor region 35, which is the well contact region, may be smaller than the width of the active region 81 on the side of the semiconductor region 32.

[0197] It is to be noted that, as schematically illustrated in Fig. 31B, the shape of the active region 81 and the semiconductor region 31a (or the semiconductor region 31b) below the gate electrode 42a (or the gate electrode 42b) of the pixel transistor 30 may be a trapezoidal shape. In addition, the semiconductor region 31a or 31b may have a pentagonal shape or may have another shape. (2-5. Modification Example 10)

[0198] Fig. 32 is a diagram illustrating an example of a planar configuration of a pixel of an imaging device according to Modification Example 10. As in the example illustrated in Fig. 32, one pixel transistor 30 may be provided for the photoelectric conversion sections 12a and 12b. The pixel transistor 30 is, for example, a transistor of the readout circuit 20, and is disposed for each of the pixels P. It is to be noted that the pixel transistors 30 of some the pixels P may be dummy transistors.

[0199] The semiconductor region 35 is provided to be adjacent to the source region or the drain region of the pixel transistor 30, for example, in the pixel P. In the example illustrated in Fig. 32, the semiconductor region 35 is provided to be adjacent to the semiconductor region 33 of the pixel transistor 30. Also in the case of the present modification example, it is possible to increase the size of the transistor disposed in the pixel P, and thus to improve characteristics of the amplification transistor AMP and the like of the readout circuit 20.

[0200] In particular, it is possible to increase the area efficiency in a fine pixel, and thus to increase the size of the pixel transistor 30. It is therefore possible to improve the characteristics of the transistor of the readout circuit 20. It becomes possible to suppress degradation in quality of the pixel signal, and thus to suppress degradation in image quality.

[0201] In addition, the imaging device 1 is configured to allow the source region and the drain region of the pixel transistor 30 to have sizes different from each other. For example, among the semiconductor region 32 and the semiconductor region 33 of the pixel transistor 30, the size of the semiconductor region 33 adjacent to the semiconductor region 35, which is a well contact region, is smaller than the size of the semiconductor region 32.

[0202] In the example illustrated in Fig. 32, the semiconductor region 33 and the semiconductor region 35 are provided to be adjacent to each other in the Y-axis direction. The width of the semiconductor region 33 in the Y-axis direction may be smaller than the width of the semiconductor region 32 in the Y-axis direction. It is to be noted that, in a case where the semiconductor region 35 is disposed to be adjacent to the semiconductor region 32, the size of the semiconductor region 32 may be smaller than the size of the semiconductor region 33.

[0203] As described above, in the imaging device 1, the semiconductor region 33 has a size or a shape different from that of the semiconductor region 32. For example, the size of the semiconductor region 33 is determined to secure an interval (distance) between the semiconductor region 35 and the semiconductor region 33. It is therefore possible to relax an electric field between the well contact region and the semiconductor region 33. This makes it possible to suppress a noise being mixed into the pixel signal, and thus to suppress degradation in image quality.

[0204] In particular, also in a fine pixel, it is possible to relax an electric field generated between the well contact region (the semiconductor region 35) and the semiconductor region 33 (or the semiconductor region 32). It is therefore possible to suppress degradation in quality of the pixel signal, and thus to suppress degradation in image quality. For example, it is possible to suppress occurrence of defects such as a white spot in an image.

[0205] Figs. 33A to 33F are each a diagram illustrating another example of the planar configuration of the pixel of the imaging device according to Modification Example 10. As in the example illustrated in Fig. 33A, the imaging device 1 may be configured to allow the size of the active region 81 on the side of the source region and the size of the active region 81 on the side of the drain region to differ from each other. The semiconductor region 31 of the imaging device 1 may have a trapezoidal shape, as illustrated in Fig. 33B.

[0206] As in the example illustrated in Fig. 33C, the imaging device 1 may include the above-described conductor region 36 that electrically couples the contact 55 and the semiconductor region 35 to each other. It is to be noted that, as in the example illustrated in Fig. 33D, the active region 81 may be configured to have different sizes, shapes, and the like on the side of the source region and on the side of the drain region. As in the example illustrated in Fig. 33E, the semiconductor region 31 of the imaging device 1 may have a trapezoidal shape.

[0207] In addition, as in the example illustrated in Fig. 33F, the imaging device 1 may include the semiconductor region 37 that electrically couples the plurality of floating diffusions FD to each other. For example, the floating diffusion FDa and the floating diffusion FDb are electrically coupled to each other via the semiconductor region 37. <3. Application Example>

[0208] The above-described imaging device 1 or the like is applicable, for example, to any type of electronic apparatus with an imaging function including a camera system such as a digital still camera or a video camera, a mobile phone having an imaging function, and the like. Fig. 34 illustrates a schematic configuration of an electronic apparatus 1000.

[0209] The electronic apparatus 1000 includes, for example, a lens group 1001, the imaging device 1, a DSP (Digital Signal Processor) circuit 1002, a frame memory 1003, a display unit 1004, a recording unit 1005, an operation unit 1006, and a power supply unit 1007. They are coupled to each other via a bus line 1008.

[0210] The lens group 1001 takes in incident light (image light) from a subject, and forms an image on an imaging surface of the imaging device 1. The imaging device 1 converts the amount of incident light formed as an image on the imaging surface by the lens group 1001 into electric signals on a pixel-by-pixel basis, and supplies the DSP circuit 1002 with the electric signals as pixel signals.

[0211] The DSP circuit 1002 is a signal processing circuit that processes signals supplied from the imaging device 1. The DSP circuit 1002 outputs image data obtained by processing the signals from the imaging device 1. The frame memory 1003 temporarily holds the image data processed by the DSP circuit 1002 on a frame-by-frame basis.

[0212] The display unit 1004 includes, for example, a panel-type display device such as a liquid crystal panel or an organic EL (Electro Luminescence) panel, and records image data of a moving image or a still image captured by the imaging device 1 in a recording medium such as a semiconductor memory or a hard disk.

[0213] The operation unit 1006 outputs an operation signal for a variety of functions of the electronic apparatus 1000 in accordance with an operation by a user. The power supply unit 1007 appropriately supplies the DSP circuit 1002, the frame memory 1003, the display unit 1004, the recording unit 1005, and the operation unit 1006 with various kinds of power for operations of these supply targets. <4. Practical Application Examples> (Example of Practical Application to Mobile Body)

[0214] The technology (the present technology) according to the present disclosure is applicable to a variety of products. For example, the technology according to the present disclosure may be achieved as a device mounted on any type of mobile body such as an automobile, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, a personal mobility, an aircraft, a drone, a vessel, or a robot.

[0215] Fig. 35 is a block diagram depicting an example of schematic configuration of a vehicle control system as an example of a mobile body control system to which the technology according to an embodiment of the present disclosure can be applied.

[0216] The vehicle control system 12000 includes a plurality of electronic control units connected to each other via a communication network 12001. In the example depicted in Fig. 35, the vehicle control system 12000 includes a driving system control unit 12010, a body system control unit 12020, an outside-vehicle information detecting unit 12030, an in-vehicle information detecting unit 12040, and an integrated control unit 12050. In addition, a microcomputer 12051, a sound / image output section 12052, and a vehicle-mounted network interface (I / F) 12053 are illustrated as a functional configuration of the integrated control unit 12050.

[0217] The driving system control unit 12010 controls the operation of devices related to the driving system of the vehicle in accordance with various kinds of programs. For example, the driving system control unit 12010 functions as a control device for a driving force generating device for generating the driving force of the vehicle, such as an internal combustion engine, a driving motor, or the like, a driving force transmitting mechanism for transmitting the driving force to wheels, a steering mechanism for adjusting the steering angle of the vehicle, a braking device for generating the braking force of the vehicle, and the like.

[0218] The body system control unit 12020 controls the operation of various kinds of devices provided to a vehicle body in accordance with various kinds of programs. For example, the body system control unit 12020 functions as a control device for a keyless entry system, a smart key system, a power window device, or various kinds of lamps such as a headlamp, a backup lamp, a brake lamp, a turn signal, a fog lamp, or the like. In this case, radio waves transmitted from a mobile device as an alternative to a key or signals of various kinds of switches can be input to the body system control unit 12020. The body system control unit 12020 receives these input radio waves or signals, and controls a door lock device, the power window device, the lamps, or the like of the vehicle.

[0219] The outside-vehicle information detecting unit 12030 detects information about the outside of the vehicle including the vehicle control system 12000. For example, the outside-vehicle information detecting unit 12030 is connected with an imaging section 12031. The outside-vehicle information detecting unit 12030 makes the imaging section 12031 image an image of the outside of the vehicle, and receives the imaged image. On the basis of the received image, the outside-vehicle information detecting unit 12030 may perform processing of detecting an object such as a human, a vehicle, an obstacle, a sign, a character on a road surface, or the like, or processing of detecting a distance thereto.

[0220] The imaging section 12031 is an optical sensor that receives light, and which outputs an electric signal corresponding to a received light amount of the light. The imaging section 12031 can output the electric signal as an image, or can output the electric signal as information about a measured distance. In addition, the light received by the imaging section 12031 may be visible light, or may be invisible light such as infrared rays or the like.

[0221] The in-vehicle information detecting unit 12040 detects information about the inside of the vehicle. The in-vehicle information detecting unit 12040 is, for example, connected with a driver state detecting section 12041 that detects the state of a driver. The driver state detecting section 12041, for example, includes a camera that images the driver. On the basis of detection information input from the driver state detecting section 12041, the in-vehicle information detecting unit 12040 may calculate a degree of fatigue of the driver or a degree of concentration of the driver, or may determine whether the driver is dozing.

[0222] The microcomputer 12051 can calculate a control target value for the driving force generating device, the steering mechanism, or the braking device on the basis of the information about the inside or outside of the vehicle which information is obtained by the outside-vehicle information detecting unit 12030 or the in-vehicle information detecting unit 12040, and output a control command to the driving system control unit 12010. For example, the microcomputer 12051 can perform cooperative control intended to implement functions of an advanced driver assistance system (ADAS) which functions include collision avoidance or shock mitigation for the vehicle, following driving based on a following distance, vehicle speed maintaining driving, a warning of collision of the vehicle, a warning of deviation of the vehicle from a lane, or the like.

[0223] In addition, the microcomputer 12051 can perform cooperative control intended for automated driving, which makes the vehicle to travel automatedly without depending on the operation of the driver, or the like, by controlling the driving force generating device, the steering mechanism, the braking device, or the like on the basis of the information about the outside or inside of the vehicle which information is obtained by the outside-vehicle information detecting unit 12030 or the in-vehicle information detecting unit 12040.

[0224] In addition, the microcomputer 12051 can output a control command to the body system control unit 12020 on the basis of the information about the outside of the vehicle which information is obtained by the outside-vehicle information detecting unit 12030. For example, the microcomputer 12051 can perform cooperative control intended to prevent a glare by controlling the headlamp so as to change from a high beam to a low beam, for example, in accordance with the position of a preceding vehicle or an oncoming vehicle detected by the outside-vehicle information detecting unit 12030.

[0225] The sound / image output section 12052 transmits an output signal of at least one of a sound and an image to an output device capable of visually or auditorily notifying information to an occupant of the vehicle or the outside of the vehicle. In the example of Fig. 35, an audio speaker 12061, a display section 12062, and an instrument panel 12063 are illustrated as the output device. The display section 12062 may, for example, include at least one of an on-board display and a head-up display.

[0226] Fig. 36 is a diagram depicting an example of the installation position of the imaging section 12031.

[0227] In Fig. 36, the imaging section 12031 includes imaging sections 12101, 12102, 12103, 12104, and 12105.

[0228] The imaging sections 12101, 12102, 12103, 12104, and 12105 are, for example, disposed at positions on a front nose, sideview mirrors, a rear bumper, and a back door of the vehicle 12100 as well as a position on an upper portion of a windshield within the interior of the vehicle. The imaging section 12101 provided to the front nose and the imaging section 12105 provided to the upper portion of the windshield within the interior of the vehicle obtain mainly an image of the front of the vehicle 12100. The imaging sections 12102 and 12103 provided to the sideview mirrors obtain mainly an image of the sides of the vehicle 12100. The imaging section 12104 provided to the rear bumper or the back door obtains mainly an image of the rear of the vehicle 12100. The imaging section 12105 provided to the upper portion of the windshield within the interior of the vehicle is used mainly to detect a preceding vehicle, a pedestrian, an obstacle, a signal, a traffic sign, a lane, or the like.

[0229] Incidentally, Fig. 36 depicts an example of photographing ranges of the imaging sections 12101 to 12104. An imaging range 12111 represents the imaging range of the imaging section 12101 provided to the front nose. Imaging ranges 12112 and 12113 respectively represent the imaging ranges of the imaging sections 12102 and 12103 provided to the sideview mirrors. An imaging range 12114 represents the imaging range of the imaging section 12104 provided to the rear bumper or the back door. A bird’s-eye image of the vehicle 12100 as viewed from above is obtained by superimposing image data imaged by the imaging sections 12101 to 12104, for example.

[0230] At least one of the imaging sections 12101 to 12104 may have a function of obtaining distance information. For example, at least one of the imaging sections 12101 to 12104 may be a stereo camera constituted of a plurality of imaging elements, or may be an imaging element having pixels for phase difference detection.

[0231] For example, the microcomputer 12051 can determine a distance to each three-dimensional object within the imaging ranges 12111 to 12114 and a temporal change in the distance (relative speed with respect to the vehicle 12100) on the basis of the distance information obtained from the imaging sections 12101 to 12104, and thereby extract, as a preceding vehicle, a nearest three-dimensional object in particular that is present on a traveling path of the vehicle 12100 and which travels in substantially the same direction as the vehicle 12100 at a predetermined speed (for example, equal to or more than 0 km / hour). Further, the microcomputer 12051 can set a following distance to be maintained in front of a preceding vehicle in advance, and perform automatic brake control (including following stop control), automatic acceleration control (including following start control), or the like. It is thus possible to perform cooperative control intended for automated driving that makes the vehicle travel automatedly without depending on the operation of the driver or the like.

[0232] For example, the microcomputer 12051 can classify three-dimensional object data on three-dimensional objects into three-dimensional object data of a two-wheeled vehicle, a standard-sized vehicle, a large-sized vehicle, a pedestrian, a utility pole, and other three-dimensional objects on the basis of the distance information obtained from the imaging sections 12101 to 12104, extract the classified three-dimensional object data, and use the extracted three-dimensional object data for automatic avoidance of an obstacle. For example, the microcomputer 12051 identifies obstacles around the vehicle 12100 as obstacles that the driver of the vehicle 12100 can recognize visually and obstacles that are difficult for the driver of the vehicle 12100 to recognize visually. Then, the microcomputer 12051 determines a collision risk indicating a risk of collision with each obstacle. In a situation in which the collision risk is equal to or higher than a set value and there is thus a possibility of collision, the microcomputer 12051 outputs a warning to the driver via the audio speaker 12061 or the display section 12062, and performs forced deceleration or avoidance steering via the driving system control unit 12010. The microcomputer 12051 can thereby assist in driving to avoid collision.

[0233] At least one of the imaging sections 12101 to 12104 may be an infrared camera that detects infrared rays. The microcomputer 12051 can, for example, recognize a pedestrian by determining whether or not there is a pedestrian in imaged images of the imaging sections 12101 to 12104. Such recognition of a pedestrian is, for example, performed by a procedure of extracting characteristic points in the imaged images of the imaging sections 12101 to 12104 as infrared cameras and a procedure of determining whether or not it is the pedestrian by performing pattern matching processing on a series of characteristic points representing the contour of the object. When the microcomputer 12051 determines that there is a pedestrian in the imaged images of the imaging sections 12101 to 12104, and thus recognizes the pedestrian, the sound / image output section 12052 controls the display section 12062 so that a square contour line for emphasis is displayed so as to be superimposed on the recognized pedestrian. The sound / image output section 12052 may also control the display section 12062 so that an icon or the like representing the pedestrian is displayed at a desired position.

[0234] The description has been given hereinabove of the mobile body control system to which the technology according to an embodiment of the present disclosure is applicable. The technology according to an embodiment of the present disclosure is applicable to the imaging section 12031, for example, of the configurations described above. Specifically, for example, the imaging device 1 or the like can be applied to the imaging section 12031. Applying the technology according to an embodiment of the present disclosure to the imaging section 12031 enables obtainment of a photographed image having high definition. It becomes possible to perform highly accurate control utilizing the photographed image in the mobile body control system. (Example of Practical Application to Endoscopic Surgery System)

[0235] The technology according to an embodiment of the present disclosure (present technology) is applicable to various products. For example, the technology according to an embodiment of the present disclosure may be applied to an endoscopic surgery system.

[0236] Fig. 37 is a view depicting an example of a schematic configuration of an endoscopic surgery system to which the technology according to an embodiment of the present disclosure (present technology) can be applied.

[0237] In Fig. 37, a state is illustrated in which a surgeon (medical doctor) 11131 is using an endoscopic surgery system 11000 to perform surgery for a patient 11132 on a patient bed 11133. As depicted, the endoscopic surgery system 11000 includes an endoscope 11100, other surgical tools 11110 such as a pneumoperitoneum tube 11111 and an energy device 11112, a supporting arm apparatus 11120 which supports the endoscope 11100 thereon, and a cart 11200 on which various apparatus for endoscopic surgery are mounted.

[0238] The endoscope 11100 includes a lens barrel 11101 having a region of a predetermined length from a distal end thereof to be inserted into a body cavity of the patient 11132, and a camera head 11102 connected to a proximal end of the lens barrel 11101. In the example depicted, the endoscope 11100 is depicted which includes as a rigid endoscope having the lens barrel 11101 of the hard type. However, the endoscope 11100 may otherwise be included as a flexible endoscope having the lens barrel 11101 of the flexible type.

[0239] The lens barrel 11101 has, at a distal end thereof, an opening in which an objective lens is fitted. A light source apparatus 11203 is connected to the endoscope 11100 such that light generated by the light source apparatus 11203 is introduced to a distal end of the lens barrel 11101 by a light guide extending in the inside of the lens barrel 11101 and is irradiated toward an observation target in a body cavity of the patient 11132 through the objective lens. It is to be noted that the endoscope 11100 may be a forward-viewing endoscope or may be an oblique-viewing endoscope or a side-viewing endoscope.

[0240] An optical system and an image pickup element are provided in the inside of the camera head 11102 such that reflected light (observation light) from the observation target is condensed on the image pickup element by the optical system. The observation light is photo-electrically converted by the image pickup element to generate an electric signal corresponding to the observation light, namely, an image signal corresponding to an observation image. The image signal is transmitted as RAW data to a CCU 11201.

[0241] The CCU 11201 includes a central processing unit (CPU), a graphics processing unit (GPU) or the like and integrally controls operation of the endoscope 11100 and a display apparatus 11202. Further, the CCU 11201 receives an image signal from the camera head 11102 and performs, for the image signal, various image processes for displaying an image based on the image signal such as, for example, a development process (demosaic process).

[0242] The display apparatus 11202 displays thereon an image based on an image signal, for which the image processes have been performed by the CCU 11201, under the control of the CCU 11201.

[0243] The light source apparatus 11203 includes a light source such as, for example, a light emitting diode (LED) and supplies irradiation light upon imaging of a surgical region to the endoscope 11100.

[0244] An inputting apparatus 11204 is an input interface for the endoscopic surgery system 11000. A user can perform inputting of various kinds of information or instruction inputting to the endoscopic surgery system 11000 through the inputting apparatus 11204. For example, the user would input an instruction or a like to change an image pickup condition (type of irradiation light, magnification, focal distance or the like) by the endoscope 11100.

[0245] A treatment tool controlling apparatus 11205 controls driving of the energy device 11112 for cautery or incision of a tissue, sealing of a blood vessel or the like. A pneumoperitoneum apparatus 11206 feeds gas into a body cavity of the patient 11132 through the pneumoperitoneum tube 11111 to inflate the body cavity in order to secure the field of view of the endoscope 11100 and secure the working space for the surgeon. A recorder 11207 is an apparatus capable of recording various kinds of information relating to surgery. A printer 11208 is an apparatus capable of printing various kinds of information relating to surgery in various forms such as a text, an image or a graph.

[0246] It is to be noted that the light source apparatus 11203 which supplies irradiation light when a surgical region is to be imaged to the endoscope 11100 may include a white light source which includes, for example, an LED, a laser light source or a combination of them. Where a white light source includes a combination of red, green, and blue (RGB) laser light sources, since the output intensity and the output timing can be controlled with a high degree of accuracy for each color (each wavelength), adjustment of the white balance of a picked up image can be performed by the light source apparatus 11203. Further, in this case, if laser beams from the respective RGB laser light sources are irradiated time-divisionally on an observation target and driving of the image pickup elements of the camera head 11102 are controlled in synchronism with the irradiation timings. Then images individually corresponding to the R, G and B colors can be also picked up time-divisionally. According to this method, a color image can be obtained even if color filters are not provided for the image pickup element.

[0247] Further, the light source apparatus 11203 may be controlled such that the intensity of light to be outputted is changed for each predetermined time. By controlling driving of the image pickup element of the camera head 11102 in synchronism with the timing of the change of the intensity of light to acquire images time-divisionally and synthesizing the images, an image of a high dynamic range free from underexposed blocked up shadows and overexposed highlights can be created.

[0248] Further, the light source apparatus 11203 may be configured to supply light of a predetermined wavelength band ready for special light observation. In special light observation, for example, by utilizing the wavelength dependency of absorption of light in a body tissue to irradiate light of a narrow band in comparison with irradiation light upon ordinary observation (namely, white light), narrow band observation (narrow band imaging) of imaging a predetermined tissue such as a blood vessel of a superficial portion of the mucous membrane or the like in a high contrast is performed. Alternatively, in special light observation, fluorescent observation for obtaining an image from fluorescent light generated by irradiation of excitation light may be performed. In fluorescent observation, it is possible to perform observation of fluorescent light from a body tissue by irradiating excitation light on the body tissue (autofluorescence observation) or to obtain a fluorescent light image by locally injecting a reagent such as indocyanine green (ICG) into a body tissue and irradiating excitation light corresponding to a fluorescent light wavelength of the reagent upon the body tissue. The light source apparatus 11203 can be configured to supply such narrow-band light and / or excitation light suitable for special light observation as described above.

[0249] Fig. 38 is a block diagram depicting an example of a functional configuration of the camera head 11102 and the CCU 11201 depicted in Fig. 37.

[0250] The camera head 11102 includes a lens unit 11401, an image pickup unit 11402, a driving unit 11403, a communication unit 11404 and a camera head controlling unit 11405. The CCU 11201 includes a communication unit 11411, an image processing unit 11412 and a control unit 11413. The camera head 11102 and the CCU 11201 are connected for communication to each other by a transmission cable 11400.

[0251] The lens unit 11401 is an optical system, provided at a connecting location to the lens barrel 11101. Observation light taken in from a distal end of the lens barrel 11101 is guided to the camera head 11102 and introduced into the lens unit 11401. The lens unit 11401 includes a combination of a plurality of lenses including a zoom lens and a focusing lens.

[0252] The number of image pickup elements which is included by the image pickup unit 11402 may be one (single-plate type) or a plural number (multi-plate type). Where the image pickup unit 11402 is configured as that of the multi-plate type, for example, image signals corresponding to respective R, G and B are generated by the image pickup elements, and the image signals may be synthesized to obtain a color image. The image pickup unit 11402 may also be configured so as to have a pair of image pickup elements for acquiring respective image signals for the right eye and the left eye ready for three dimensional (3D) display. If 3D display is performed, then the depth of a living body tissue in a surgical region can be comprehended more accurately by the surgeon 11131. It is to be noted that, where the image pickup unit 11402 is configured as that of stereoscopic type, a plurality of systems of lens units 11401 are provided corresponding to the individual image pickup elements.

[0253] Further, the image pickup unit 11402 may not necessarily be provided on the camera head 11102. For example, the image pickup unit 11402 may be provided immediately behind the objective lens in the inside of the lens barrel 11101.

[0254] The driving unit 11403 includes an actuator and moves the zoom lens and the focusing lens of the lens unit 11401 by a predetermined distance along an optical axis under the control of the camera head controlling unit 11405. Consequently, the magnification and the focal point of a picked up image by the image pickup unit 11402 can be adjusted suitably.

[0255] The communication unit 11404 includes a communication apparatus for transmitting and receiving various kinds of information to and from the CCU 11201. The communication unit 11404 transmits an image signal acquired from the image pickup unit 11402 as RAW data to the CCU 11201 through the transmission cable 11400.

[0256] In addition, the communication unit 11404 receives a control signal for controlling driving of the camera head 11102 from the CCU 11201 and supplies the control signal to the camera head controlling unit 11405. The control signal includes information relating to image pickup conditions such as, for example, information that a frame rate of a picked up image is designated, information that an exposure value upon image picking up is designated and / or information that a magnification and a focal point of a picked up image are designated.

[0257] It is to be noted that the image pickup conditions such as the frame rate, exposure value, magnification or focal point may be designated by the user or may be set automatically by the control unit 11413 of the CCU 11201 on the basis of an acquired image signal. In the latter case, an auto exposure (AE) function, an auto focus (AF) function and an auto white balance (AWB) function are incorporated in the endoscope 11100.

[0258] The camera head controlling unit 11405 controls driving of the camera head 11102 on the basis of a control signal from the CCU 11201 received through the communication unit 11404.

[0259] The communication unit 11411 includes a communication apparatus for transmitting and receiving various kinds of information to and from the camera head 11102. The communication unit 11411 receives an image signal transmitted thereto from the camera head 11102 through the transmission cable 11400.

[0260] Further, the communication unit 11411 transmits a control signal for controlling driving of the camera head 11102 to the camera head 11102. The image signal and the control signal can be transmitted by electrical communication, optical communication or the like.

[0261] The image processing unit 11412 performs various image processes for an image signal in the form of RAW data transmitted thereto from the camera head 11102.

[0262] The control unit 11413 performs various kinds of control relating to image picking up of a surgical region or the like by the endoscope 11100 and display of a picked up image obtained by image picking up of the surgical region or the like. For example, the control unit 11413 creates a control signal for controlling driving of the camera head 11102.

[0263] Further, the control unit 11413 controls, on the basis of an image signal for which image processes have been performed by the image processing unit 11412, the display apparatus 11202 to display a picked up image in which the surgical region or the like is imaged. Thereupon, the control unit 11413 may recognize various objects in the picked up image using various image recognition technologies. For example, the control unit 11413 can recognize a surgical tool such as forceps, a particular living body region, bleeding, mist when the energy device 11112 is used and so forth by detecting the shape, color and so forth of edges of objects included in a picked up image. The control unit 11413 may cause, when it controls the display apparatus 11202 to display a picked up image, various kinds of surgery supporting information to be displayed in an overlapping manner with an image of the surgical region using a result of the recognition. Where surgery supporting information is displayed in an overlapping manner and presented to the surgeon 11131, the burden on the surgeon 11131 can be reduced and the surgeon 11131 can proceed with the surgery with certainty.

[0264] The transmission cable 11400 which connects the camera head 11102 and the CCU 11201 to each other is an electric signal cable ready for communication of an electric signal, an optical fiber ready for optical communication or a composite cable ready for both of electrical and optical communications.

[0265] Here, while, in the example depicted, communication is performed by wired communication using the transmission cable 11400, the communication between the camera head 11102 and the CCU 11201 may be performed by wireless communication.

[0266] The description has been given hereinabove of one example of the endoscopic surgery system, to which the technology according to an embodiment of the present disclosure is applicable. The technology according to an embodiment of the present disclosure is suitably applicable to, for example, the image pickup unit 11402 provided in the camera head 11102 of the endoscope 11100 of the configurations described above. Applying the technology according to an embodiment of the present disclosure to the image pickup unit 11402 makes it possible to provide the endoscope 11100 having high definition.

[0267] Although the description has been given hereinabove of the present disclosure with reference to the embodiment, the modification examples, the application example, and the practical application examples, the present technology is not limited to the foregoing embodiment and the like, and may be modified in a wide variety of ways. For example, although the foregoing modification examples have been described as modification examples of the foregoing embodiments, the configurations of the respective modification examples may be combined as appropriate.

[0268] In the foregoing embodiments and the like, the imaging device has been exemplified for description. However, it is sufficient for the photodetector of the present disclosure to be, for example, a device that receives incident light and converts the light into electric charge. A signal to be outputted may be a signal of image information or a signal of information on a measured distance. The photodetector (imaging device) is applicable to an image sensor, a distance measurement sensor, or the like. It is to be noted that the present disclosure is not limited to a back side illumination image sensor, and is also applicable to a front side illumination image sensor.

[0269] The photodetector according to the present disclosure is also applicable as a distance measurement sensor that enables distance measurement of a TOF (Time Of Flight) method. The photodetector (imaging device) is also applicable as a sensor that is able to detect an event, e.g., an event-driven sensor (referred to as EVS (Event Vision Sensor), EDS (Event Driven Sensor), DVS (Dynamic Vision Sensor), etc.).

[0270] A photodetector according to an embodiment of the present disclosure includes a semiconductor layer, a plurality of pixels including a first pixel including a photoelectric conversion element provided in a semiconductor layer, and a trench provided between the plurality of pixels adjacent to each other in the semiconductor layer. The first pixel includes a transistor provided on a side of a first surface of the semiconductor layer, a first semiconductor region of a first electrically-conductive type provided on the side of the first surface of the semiconductor layer, and a first contact electrically coupled to the first semiconductor region. The transistor includes a second semiconductor region and a third semiconductor region of a second electrically-conductive type. The first semiconductor region is provided to be adjacent to the second semiconductor region. The second semiconductor region and the third semiconductor region have sizes different from each other. This enables the photodetector to have a structure advantageous to pixel miniaturization. It becomes possible to achieve the photodetector advantageous to the miniaturization.

[0271] A photodetector according to an embodiment of the present disclosure includes a semiconductor layer, a plurality of pixels including a first pixel including a photoelectric conversion element provided in the semiconductor layer, and a trench provided between the plurality of pixels adjacent to each other in the semiconductor layer. The first pixel includes a first semiconductor region of a first electrically-conductive type provided on a side of a first surface of the semiconductor layer, a first contact electrically coupled to the first semiconductor region, a transistor including a second semiconductor region and a third semiconductor region of a second electrically-conductive type, which are each provided in a first region on the side of the first surface of the semiconductor layer, and a separation section provided around the first region. The first semiconductor region is provided to be adjacent to the second semiconductor region. A size of the first region on a side of the second semiconductor region is smaller than a size of the first region on a side of the third semiconductor region. This enables the photodetector to have a structure advantageous to pixel miniaturization. It becomes possible to achieve the photodetector advantageous to the miniaturization.

[0272] It is to be noted that the effects described herein are merely exemplary and are not limited to the description, and may further include other effects. In addition, the present disclosure may also have the following configurations. (1) A photodetector including: a semiconductor layer; a plurality of pixels including a first pixel including a photoelectric conversion element provided in the semiconductor layer; and a trench provided between the plurality of pixels adjacent to each other in the semiconductor layer, in which the first pixel includes a transistor provided on a side of a first surface of the semiconductor layer, a first semiconductor region of a first electrically-conductive type provided on the side of the first surface of the semiconductor layer, and a first contact electrically coupled to the first semiconductor region, the transistor includes a second semiconductor region and a third semiconductor region of a second electrically-conductive type, the first semiconductor region is provided to be adjacent to the second semiconductor region, and the second semiconductor region and the third semiconductor region have sizes different from each other. (2) The photodetector according to (1), in which the size of the second semiconductor region is smaller than the size of the third semiconductor region. (3) The photodetector according to (1) or (2), in which the second semiconductor region and the first semiconductor region are provided to be adjacent to each other in a first direction, and a width of the second semiconductor region in the first direction is smaller than a width of the third semiconductor region. (4) The photodetector according to any one of (1) to (3), in which the first pixel includes a first region of the semiconductor layer provided with the second semiconductor region and the third semiconductor region, and a separation section provided around the first region. (5) The photodetector according to (4), in which a size of the first region on a side of the second semiconductor region is smaller than a size of the first region on a side of the third semiconductor region. (6) The photodetector according to (4) or (5), in which the first semiconductor region is provided to be adjacent to the second semiconductor region in the first region. (7) The photodetector according to any one of (4) to (6), in which the first pixel includes a floating diffusion provided in a second region of the semiconductor layer, and a transfer transistor configured to transfer electric charge converted by the photoelectric conversion element to the floating diffusion, and the separation section is provided between the first region and the second region. (8) The photodetector according to any one of (1) to (7), in which the second semiconductor region includes one of a source region or a drain region, and the third semiconductor region includes another of the source region or the drain region. (9) The photodetector according to any one of (1) to (8), in which the first semiconductor region includes a p-type semiconductor region, and the second semiconductor region and the third semiconductor region each include an n-type semiconductor region. (10) The photodetector according to any one of (1) to (9), in which the transistor includes a channel region between the second semiconductor region and the third semiconductor region, and a size of the channel region on the side of the second semiconductor region is smaller than a size of the channel region on the side of the third semiconductor region. (11) The photodetector according to any one of (1) to (10), further including a first well of the first electrically-conductive type provided in the semiconductor layer, in which the first semiconductor region is provided in the first well, and the first contact is electrically coupled to the first well via the first semiconductor region. (12) The photodetector according to any one of (1) to (11), further including a conductor region in contact with a portion of the first semiconductor region and being provided inside the trench, in which the first contact is provided on the conductor region and is electrically coupled to the first semiconductor region via the conductor region. (13) The photodetector according to (12), in which the conductor region is provided in the semiconductor layer. (14) The photodetector according to any one of (1) to (13), in which the plurality of pixels includes a second pixel adjacent to the first pixel, and the first pixel and the second pixel each include the photoelectric conversion element, the floating diffusion, the transistor, and the first semiconductor region. (15) The photodetector according to (14), further including the conductor region that electrically couples the first semiconductor region of the first pixel and the first semiconductor region of the second pixel to each other. (16) The photodetector according to (14) or (15), further including: a fourth semiconductor region that electrically couples the floating diffusion of the first pixel and the floating diffusion of the second pixel to each other; and a second contact electrically coupled to the fourth semiconductor region. (17) The photodetector according to any one of (1) to (16), further including a readout circuit including the transistor and being configured to output a signal based on electric charge photoelectrically converted by the photoelectric conversion element, in which the transistor includes an amplification transistor, a selection transistor, a reset transistor, a switching transistor, or a dummy transistor. (18) The photodetector according to any one of (1) to (17), further including a lens provided on a side of a second surface opposite to the first surface of the semiconductor layer, in which the photoelectric conversion element photoelectrically converts light transmitted through the lens. (19) A photodetector including: a semiconductor layer; a plurality of pixels including a first pixel including a photoelectric conversion element provided in the semiconductor layer; and a trench provided between the plurality of pixels adjacent to each other in the semiconductor layer, in which the first pixel includes a first semiconductor region of a first electrically-conductive type provided on a side of a first surface of the semiconductor layer, a first contact electrically coupled to the first semiconductor region, a transistor including a second semiconductor region and a third semiconductor region of a second electrically-conductive type each provided in a first region on the side of the first surface of the semiconductor layer, and a separation section provided around the first region, the first semiconductor region is provided to be adjacent to the second semiconductor region, and a size of the first region on a side of the second semiconductor region is smaller than a size of the first region on a side of the third semiconductor region. (20) The photodetector according to (19), in which the first pixel includes a floating diffusion provided in a second region of the semiconductor layer, and a transfer transistor configured to transfer electric charge converted by the photoelectric conversion element to the floating diffusion, and the separation section is provided between the first region and the second region. (21) A photodetector including: a semiconductor layer; a plurality of pixels including a first pixel including a first photoelectric conversion element and a second photoelectric conversion element provided in the semiconductor layer; and a trench provided between the plurality of pixels adjacent to each other in the semiconductor layer, in which the first pixel includes a first transistor provided on a side of a first surface of the semiconductor layer, a first semiconductor region of a first electrically-conductive type provided on the side of the first surface of the semiconductor layer, and a first contact electrically coupled to the first semiconductor region, the first transistor includes a second semiconductor region and a third semiconductor region of a second electrically-conductive type, the first semiconductor region is provided to be adjacent to the second semiconductor region, and the second semiconductor region and the third semiconductor region have sizes different from each other. (22) The photodetector according to (21), in which the size of the second semiconductor region is smaller than the size of the third semiconductor region. (23) The photodetector according to (21) or (22), in which the second semiconductor region and the first semiconductor region are provided to be adjacent to each other in a first direction, and a width of the second semiconductor region in the first direction is smaller than a width of the third semiconductor region. (24) The photodetector according to any one of (21) to (23), in which the first pixel includes a first region of the semiconductor layer provided with the second semiconductor region and the third semiconductor region, and a size of the first region on a side of the second semiconductor region is smaller than a size of the first region on a side of the third semiconductor region. (25) The photodetector according to any one of (21) to (24), in which the first pixel includes a second transistor provided on the side of the first surface of the semiconductor layer, the first transistor and the second transistor each include the second semiconductor region and the third semiconductor region of the second electrically-conductive type, and the first semiconductor region is provided to be adjacent to the second semiconductor region of the first transistor and the second semiconductor region of the second transistor. (26) The photodetector according to any one of (21) to (25), in which the first pixel includes the second transistor provided on the side of the first surface of the semiconductor layer, a first separation section provided between the first transistor and the second transistor, a first floating diffusion and a second floating diffusion, and a second separation section provided between the first floating diffusion and the second floating diffusion. (27) The photodetector according to (26), in which the first semiconductor region is provided between the first separation section and the second separation section. (28) An electronic apparatus including: an optical system; and a photodetector that receives light transmitted through the optical system, the photodetector including a semiconductor layer, a plurality of pixels including a first pixel including a photoelectric conversion element provided in the semiconductor layer, and a trench provided between the plurality of pixels adjacent to each other in the semiconductor layer, in which the first pixel includes a transistor provided on a side of a first surface of the semiconductor layer, a first semiconductor region of a first electrically-conductive type provided on the side of the first surface of the semiconductor layer, and a first contact electrically coupled to the first semiconductor region, the transistor includes a second semiconductor region and a third semiconductor region of a second electrically-conductive type, the first semiconductor region is provided to be adjacent to the second semiconductor region, and the second semiconductor region and the third semiconductor region have sizes different from each other. (29) An electronic apparatus including: an optical system; and a photodetector that receives light transmitted through the optical system, the photodetector including a semiconductor layer, a plurality of pixels including a first pixel including a first photoelectric conversion element and a second photoelectric conversion element provided in the semiconductor layer, and a trench provided between the plurality of pixels adjacent to each other in the semiconductor layer, in which the first pixel includes a first transistor provided on a side of a first surface of the semiconductor layer, a first semiconductor region of a first electrically-conductive type provided on the side of the first surface of the semiconductor layer, and a first contact electrically coupled to the first semiconductor region, the first transistor includes a second semiconductor region and a third semiconductor region of a second electrically-conductive type, the first semiconductor region is provided to be adjacent to the second semiconductor region, and the second semiconductor region and the third semiconductor region have sizes different from each other.Reference Numerals List

[0273] 1 imaging device 12 photoelectric conversion section 20 readout circuit 21 lens 25 well 30 pixel transistor 31, 32, 33, 35 semiconductor region 52, 53, 55 contact 91, 92, 93 trench 101 substrate 110 semiconductor layer

Claims

1. A photodetector comprising: a semiconductor layer; a plurality of pixels including a first pixel including a photoelectric conversion element provided in the semiconductor layer; and a trench provided between the plurality of pixels adjacent to each other in the semiconductor layer, wherein the first pixel includes a transistor provided on a side of a first surface of the semiconductor layer, a first semiconductor region of a first electrically-conductive type provided on the side of the first surface of the semiconductor layer, and a first contact electrically coupled to the first semiconductor region, the transistor includes a second semiconductor region and a third semiconductor region of a second electrically-conductive type, the first semiconductor region is provided to be adjacent to the second semiconductor region, and the second semiconductor region and the third semiconductor region have sizes different from each other.

2. The photodetector according to claim 1, wherein the size of the second semiconductor region is smaller than the size of the third semiconductor region.

3. The photodetector according to claim 1, wherein the second semiconductor region and the first semiconductor region are provided to be adjacent to each other in a first direction, and a width of the second semiconductor region in the first direction is smaller than a width of the third semiconductor region.

4. The photodetector according to claim 1, wherein the first pixel includes a first region of the semiconductor layer provided with the second semiconductor region and the third semiconductor region, and a separation section provided around the first region.

5. The photodetector according to claim 4, wherein a size of the first region on a side of the second semiconductor region is smaller than a size of the first region on a side of the third semiconductor region.

6. The photodetector according to claim 4, wherein the first semiconductor region is provided to be adjacent to the second semiconductor region in the first region.

7. The photodetector according to claim 4, wherein the first pixel includes a floating diffusion provided in a second region of the semiconductor layer, and a transfer transistor configured to transfer electric charge converted by the photoelectric conversion element to the floating diffusion, and the separation section is provided between the first region and the second region.

8. The photodetector according to claim 1, wherein the second semiconductor region comprises one of a source region or a drain region, and the third semiconductor region comprises another of the source region or the drain region.

9. The photodetector according to claim 1, wherein the first semiconductor region comprises a p-type semiconductor region, and the second semiconductor region and the third semiconductor region each comprise an n-type semiconductor region.

10. The photodetector according to claim 1, wherein the transistor includes a channel region between the second semiconductor region and the third semiconductor region, and a size of the channel region on a side of the second semiconductor region is smaller than a size of the channel region on a side of the third semiconductor region.

11. The photodetector according to claim 1, further comprising a first well of the first electrically-conductive type provided in the semiconductor layer, wherein the first semiconductor region is provided in the first well, and the first contact is electrically coupled to the first well via the first semiconductor region.

12. The photodetector according to claim 1, further comprising a conductor region in contact with a portion of the first semiconductor region and being provided inside the trench, wherein the first contact is provided on the conductor region and is electrically coupled to the first semiconductor region via the conductor region.

13. The photodetector according to claim 12, wherein the conductor region is provided in the semiconductor layer.

14. The photodetector according to claim 1, wherein the plurality of pixels includes a second pixel adjacent to the first pixel, and the first pixel and the second pixel each include the photoelectric conversion element, a floating diffusion, the transistor, and the first semiconductor region.

15. The photodetector according to claim 14, further comprising a conductor region that electrically couples the first semiconductor region of the first pixel and the first semiconductor region of the second pixel to each other.

16. The photodetector according to claim 14, further comprising: a fourth semiconductor region that electrically couples the floating diffusion of the first pixel and the floating diffusion of the second pixel to each other; and a second contact electrically coupled to the fourth semiconductor region.

17. The photodetector according to claim 1, further comprising a readout circuit including the transistor and being configured to output a signal based on electric charge photoelectrically converted by the photoelectric conversion element, wherein the transistor comprises an amplification transistor, a selection transistor, a reset transistor, a switching transistor, or a dummy transistor.

18. The photodetector according to claim 1, further comprising a lens provided on a side of a second surface opposite to the first surface of the semiconductor layer, wherein the photoelectric conversion element photoelectrically converts light transmitted through the lens.

19. A photodetector comprising: a semiconductor layer; a plurality of pixels including a first pixel including a photoelectric conversion element provided in the semiconductor layer; and a trench provided between the plurality of pixels adjacent to each other in the semiconductor layer, wherein the first pixel includes a first semiconductor region of a first electrically-conductive type provided on a side of a first surface of the semiconductor layer, a first contact electrically coupled to the first semiconductor region, a transistor including a second semiconductor region and a third semiconductor region of a second electrically-conductive type each provided in a first region on the side of the first surface of the semiconductor layer, and a separation section provided around the first region, the first semiconductor region is provided to be adjacent to the second semiconductor region, and a size of the first region on a side of the second semiconductor region is smaller than a size of the first region on a side of the third semiconductor region.

20. The photodetector according to claim 19, wherein the first pixel includes a floating diffusion provided in a second region of the semiconductor layer, and a transfer transistor configured to transfer electric charge converted by the photoelectric conversion element to the floating diffusion, and the separation section is provided between the first region and the second region.

21. A photodetector comprising: a semiconductor layer; a plurality of pixels including a first pixel including a first photoelectric conversion element and a second photoelectric conversion element provided in the semiconductor layer; and a trench provided between the plurality of pixels adjacent to each other in the semiconductor layer, wherein the first pixel includes a first transistor provided on a side of a first surface of the semiconductor layer, a first semiconductor region of a first electrically-conductive type provided on the side of the first surface of the semiconductor layer, and a first contact electrically coupled to the first semiconductor region, the first transistor includes a second semiconductor region and a third semiconductor region of a second electrically-conductive type, the first semiconductor region is provided to be adjacent to the second semiconductor region, and the second semiconductor region and the third semiconductor region have sizes different from each other.

22. The photodetector according to claim 21, wherein the size of the second semiconductor region is smaller than the size of the third semiconductor region.

23. The photodetector according to claim 21, wherein the second semiconductor region and the first semiconductor region are provided to be adjacent to each other in a first direction, and a width of the second semiconductor region in the first direction is smaller than a width of the third semiconductor region.

24. The photodetector according to claim 21, wherein the first pixel includes a first region of the semiconductor layer provided with the second semiconductor region and the third semiconductor region, and a size of the first region on a side of the second semiconductor region is smaller than a size of the first region on a side of the third semiconductor region.

25. The photodetector according to claim 21, wherein the first pixel includes a second transistor provided on the side of the first surface of the semiconductor layer, the first transistor and the second transistor each include the second semiconductor region and the third semiconductor region of the second electrically-conductive type, and the first semiconductor region is provided to be adjacent to the second semiconductor region of the first transistor and the second semiconductor region of the second transistor.

26. The photodetector according to claim 21, wherein the first pixel includes a second transistor provided on the side of the first surface of the semiconductor layer, a first separation section provided between the first transistor and the second transistor, a first floating diffusion and a second floating diffusion, and a second separation section provided between the first floating diffusion and the second floating diffusion.

27. The photodetector according to claim 26, wherein the first semiconductor region is provided between the first separation section and the second separation section.

28. An electronic apparatus comprising: an optical system; and a photodetector that receives light transmitted through the optical system, the photodetector including a semiconductor layer, a plurality of pixels including a first pixel including a photoelectric conversion element provided in the semiconductor layer, and a trench provided between the plurality of pixels adjacent to each other in the semiconductor layer, wherein the first pixel includes a transistor provided on a side of a first surface of the semiconductor layer, a first semiconductor region of a first electrically-conductive type provided on the side of the first surface of the semiconductor layer, and a first contact electrically coupled to the first semiconductor region, the transistor includes a second semiconductor region and a third semiconductor region of a second electrically-conductive type, the first semiconductor region is provided to be adjacent to the second semiconductor region, and the second semiconductor region and the third semiconductor region have sizes different from each other.

29. An electronic apparatus comprising: an optical system; and a photodetector that receives light transmitted through the optical system, the photodetector including a semiconductor layer, a plurality of pixels including a first pixel including a first photoelectric conversion element and a second photoelectric conversion element provided in the semiconductor layer, and a trench provided between the plurality of pixels adjacent to each other in the semiconductor layer, wherein the first pixel includes a first transistor provided on a side of a first surface of the semiconductor layer, a first semiconductor region of a first electrically-conductive type provided on the side of the first surface of the semiconductor layer, and a first contact electrically coupled to the first semiconductor region, the first transistor includes a second semiconductor region and a third semiconductor region of a second electrically-conductive type, the first semiconductor region is provided to be adjacent to the second semiconductor region, and the second semiconductor region and the third semiconductor region have sizes different from each other.

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