High-density interconnected packaging structure and method for chips

Abstract

A high-density interconnected packaging structure and method for chips, which structure and method relate to the technical field of semiconductors, and aim to solve problems in the prior art brought about by poor heat dissipation and warping. The high-density interconnected packaging method for chips comprises: providing a heat dissipation substrate and a plurality of chips, wherein the heat dissipation substrate comprises a plurality of chip-mounting regions used for respectively mounting the chips, and a functional face of each chip has a first pin array of a first density and a second pin array of a second density, the first density being less than the second density; attaching the chips to the chip-mounting regions by means of back faces of the chips; using a plastic packaging material to package the chips and the heat dissipation substrate, and performing curing to form a plastic packaging layer, wherein the first pin arrays and the second pin arrays are exposed from the plastic packaging layer; forming packaging wiring layers on the plastic packaging layer, and connecting the packaging wiring layers to fine interconnection bridges, wherein the fine interconnection bridges are correspondingly connected to the second pin arrays of two adjacent chips, and the packaging wiring layers are correspondingly connected to the first pin arrays of the plurality of chips, so as to form a high-density interconnected packaging structure for the chips.

Description

A chip high-density interconnection packaging structure and method Technical Field

[0001] The present application relates to the field of semiconductor packaging technology, and in particular to a chip fine interconnect packaging structure and method. Background Art

[0002] The semiconductor industry continues to improve the integration and performance of various electronic components, such as transistors, diodes, resistors, and capacitors, by continuously reducing the minimum feature size. This allows more components to be concentrated in a given area, thereby improving the computing power of the chip. However, as the minimum feature size continues to explore the nanoscale, it is approaching the physical limit. At the same time, technologies such as artificial intelligence, the Internet of Things, 5G, autonomous driving, and high-performance cloud computing are in rapid development. In this context, it is necessary to achieve high-density interconnection of multiple chips at the shortest distance while increasing the data transmission bandwidth. That is, to integrate more integrated circuit chips in a smaller space and use shorter distances and higher wiring density to achieve high-density interconnection between integrated circuit chips.

[0003] For this reason, advanced packaging technologies that can achieve high-density interconnection of semiconductor devices have received widespread attention. Among these advanced packaging technologies, the packaging technology that achieves high-density interconnection between chips by embedding silicon bridges has developed into one of the mainstream advanced packaging solutions because it can achieve the optimal balance between chip performance and packaging cost. Among them, the embedded silicon bridge packaging can use the silicon bridge structure as a high-density interconnection layer to achieve high-density interconnection between two or more integrated circuit chips. However, the packaging structure connected by the silicon bridge structure in the prior art does not have a specific heat dissipation structure and cannot dissipate heat well, which greatly limits the performance of the device. In addition, since the packaging structure is a composite material system containing multiple materials with different thermal expansion coefficients, warping is inevitable. When the warping is too large, the line width and line spacing of the packaging wiring layer are severely limited, and the reliability of the electrical connection is also affected.

[0004] Summary of the Invention

[0005] The purpose of this application is to address the deficiencies in the above-mentioned prior art and provide a chip high-density interconnect packaging structure and method to solve the problems of poor heat dissipation and warping in the prior art.

[0006] To achieve the above objectives, the technical solutions adopted in the embodiments of the present application are as follows:

[0007] In one aspect of an embodiment of the present application, a chip high-density interconnection packaging structure is provided, comprising a heat dissipation carrier and a plurality of chips arranged on the heat dissipation carrier, wherein the non-functional surface of the chip contacts the heat dissipation carrier, a plurality of through holes are arranged on the heat dissipation carrier, and the functional surfaces of the plurality of chips have a first pin array of a first density and a second pin array of a second density, wherein the first density is less than the second density, and the high-density interconnection packaging structure further comprises a plastic encapsulation component for encapsulating the chip and the heat dissipation carrier, wherein the plastic encapsulation component is provided with a packaging wiring layer connected to the first pin array and a fine interconnection bridge connected to the second pin array; the process of forming the package component comprises: connecting the functional surface of the chip to the temporary carrier through a temporary bonding material, and using the temporary carrier as a base, filling the molten plastic encapsulation material between the chip and the heat dissipation carrier through the through hole and wrapping the heat dissipation carrier, forming a plastic encapsulation component after the plastic encapsulation material is solidified, and removing the temporary carrier and the temporary bonding material.

[0008] Optionally, the functional surface of the chip includes multiple pins, and the pins are connected to pin pads arranged at the edge of the chip through lead wires, so that the multiple pins are led out to the edge of the functional surface to form a first pin array and a second pin array.

[0009] Optionally, the fine interconnect bridge is provided on the chip and connected to the second density pins of the chip, or the fine interconnect bridge is provided on the package wiring layer and connected to the second density pins through the package wiring layer.

[0010] Optionally, the fine interconnection bridge includes a base material, a fine interconnection line arranged in the base material, and a plurality of interconnections arranged on both sides of the base material to connect the fine interconnection line, and the base material is one of silicon, ceramic, glass, plastic, and resin.

[0011] Optionally, a leveling material is further provided on the plastic package and the chip to fill the height difference between the plastic package and the functional surface of the chip. The first pin array and the second pin array are exposed through the leveling material, and the leveling material has insulating properties.

[0012] Optionally, the packaging wiring layer is arranged on the leveling material, including at least one second insulating layer, and connecting lines formed in the second insulating layer respectively. The connecting lines between the two connected layers are respectively connected, and the connecting lines include fine connecting lines and non-fine connecting lines. Fine interconnection pins connected to the fine connecting lines and non-fine interconnection pins connected to the non-fine connecting lines are also provided on the surface of the packaging wiring layer. The fine connection lines are correspondingly connected to the second pin array, and the non-fine connection lines are correspondingly connected to the first pin array.

[0013] Optionally, the chip high-density interconnection packaging structure further includes an insulating material filled between the fine interconnection bridge and the chip functional surface, or filled between the fine interconnection bridge and the leveling material.

[0014] On the other hand, an embodiment of the present application provides a chip high-density interconnection packaging method, including: providing a heat dissipation carrier and multiple chips, the heat dissipation carrier including multiple patch areas for respectively mounting the chips, the functional surfaces of the multiple chips all having a first pin array of a first density and a second pin array of a second density, the first density being less than the second density; attaching the chip to the patch area through the back of the chip; using a plastic encapsulation material to encapsulate the chip and the heat dissipation carrier and curing it to form a plastic encapsulation layer, with the first pin array and the second pin array exposed from the plastic encapsulation layer; forming a packaging wiring layer on the plastic encapsulation layer and connecting a fine interconnection bridge, the fine interconnection bridge being correspondingly connected to the second pin arrays of two adjacent chips, and the packaging wiring layer being correspondingly connected to the first pin arrays of the multiple chips, to form a chip high-density interconnection packaging structure.

[0015] Optionally, forming a packaging wiring layer on the plastic encapsulation layer and connecting a fine interconnection bridge includes: forming a packaging wiring layer on the plastic encapsulation layer, and the packaging wiring layer is correspondingly connected to the first pin arrays of multiple chips; connecting a fine interconnection bridge on the plastic encapsulation layer, and the fine interconnection bridge is connected to the second pin arrays of two adjacent chips.

[0016] Optionally, forming a packaging wiring layer on the plastic encapsulation layer and connecting a fine interconnection bridge includes: forming a packaging wiring layer on the plastic encapsulation layer, the packaging wiring layer including a first pattern connected to the first pin arrays of multiple chips respectively, and a second pattern connected to the second pin arrays of some chips; connecting a fine interconnection bridge on the packaging wiring layer, the fine interconnection bridge being connected to the second pattern.

[0017] Optionally, a plastic encapsulation material is used to encapsulate the chip and the heat dissipation carrier and is cured to form a plastic encapsulation layer, and the first pin array and the second pin array are exposed from the plastic encapsulation layer, including: the functional surface of the chip is connected to the temporary carrier through a temporary bonding material, and the temporary bonding material is in contact with the first pin array and the second pin array; the chip and the heat dissipation carrier are encapsulated with the plastic encapsulation material and are in contact with the temporary bonding material; and the temporary carrier is removed by removing the temporary bonding material to expose the first pin array and the second pin array from the plastic encapsulation layer.

[0018] Optionally, providing a heat dissipation carrier and multiple chips includes: forming lead wires on the functional surface and multiple pin pads arranged at the edge of the functional surface, one end of the lead wire is connected to the pin, and the other end is connected to the pin pad, so as to lead the pins to the edge of the functional surface to form a first pin array and a second pin array.

[0019] Optionally, the chip is attached to the patch area through the back side of the chip: the second pin arrays of two adjacent chips are close to each other.

[0020] Optionally, after the plastic encapsulation layer forms the packaging wiring layer and connects the fine interconnection bridge, the chip high-density interconnection packaging method further includes: filling an insulating material between the fine interconnection bridge and the plastic encapsulation layer or between the fine interconnection bridge and the functional surface of the chip.

[0021] Optionally, after the chip and the heat sink carrier are wrapped with a plastic encapsulation material and cured to form a plastic encapsulation layer, and the first pin array and the second pin array are exposed from the plastic encapsulation layer, the chip high-density interconnection packaging method further includes: using a leveling material to fill the height difference between the plastic encapsulation part and the functional surface; partially etching the leveling material to expose the first pin array and the second pin array, or partially etching the leveling material to expose the portion of the functional surface where the second pin array is set.

[0022] Optionally, providing a heat sink carrier and multiple chips includes: forming a groove on the surface of the heat sink carrier so that the heat sink carrier has two first planes or second planes of different heights on the same side, the first plane serving as a patch area, or the second plane serving as a patch area.

[0023] Optionally, providing the heat dissipation carrier and the plurality of chips includes: forming a plurality of through holes on the heat dissipation carrier, and the plastic encapsulation material flows into between the temporary carrier and the heat dissipation carrier through the through holes.

[0024] Optionally, the fine interconnection bridge includes at least one first insulating layer, fine interconnection lines formed in the first insulating layer, and multiple interconnections connected to the outermost fine interconnection lines. The fine interconnection lines of two adjacent layers are connected respectively, and the interconnections are used to connect to the second pin arrays of two adjacent chips.

[0025] Optionally, the packaging wiring layer includes at least one second insulating layer, and connecting lines formed respectively in the second insulating layer, and the connecting lines of two adjacent layers are respectively connected to each other, and the connecting lines close to the chip are connected to the first pin arrays of multiple chips, or, the connecting lines close to the chip are respectively connected to the first pin arrays of multiple chips and the second pin arrays of some chips.

[0026] The beneficial effects of this application include:

[0027] The present application provides a chip high-density interconnect packaging structure, comprising: a heat dissipation carrier and a plurality of chips arranged on the heat dissipation carrier, wherein the non-functional surface of the chip contacts the heat dissipation carrier, so that the chip directly contacts the heat dissipation carrier, the heat generated by the chip can be immediately conducted to the heat dissipation carrier, and the heat dissipation carrier can quickly dissipate the heat, thereby improving the heat dissipation effect of the chip high-density interconnect packaging structure. A plurality of through holes are provided on the heat dissipation carrier, the functional surfaces of the plurality of chips each have a first pin array of a first density and a second pin array of a second density, the first density being less than the second density, the high-density interconnect packaging structure also includes a plastic encapsulation member for encapsulating the chip and the heat dissipation carrier, the plastic encapsulation member is provided with a packaging wiring layer connected to the first pin array and a fine interconnection bridge connected to the second pin array; the packaging member forming process comprises: connecting the functional surface of the chip to the temporary carrier through a temporary bonding material, and using the temporary carrier as a base, filling the molten plastic encapsulation material between the chip and the heat dissipation carrier through the through hole and wrapping the heat dissipation carrier, forming the plastic encapsulation member after the plastic encapsulation material is solidified, and removing the temporary carrier and the temporary bonding material. The fine interconnection bridge can achieve fine interconnection between the two chips, thereby improving the signal transmission efficiency of the chip high-density interconnection packaging structure. In addition, the heat dissipation carrier has a certain strength, which can prevent the chip high-density interconnection packaging structure from warping, thereby avoiding the problems caused by warping of materials such as plastic packaging materials. Specifically, warping seriously limits the line width and line spacing of the packaging wiring layer, and also affects the reliability of the electrical connection. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other relevant drawings can be obtained based on these drawings without creative work.

[0029] FIG1 is a schematic diagram of a process for high-density interconnect packaging of chips provided in an embodiment of the present application;

[0030] FIG2 is a schematic diagram of a structure of a chip provided in an embodiment of the present application;

[0031] FIG3 is a second schematic diagram of the structure of a chip provided in an embodiment of the present application;

[0032] FIG4 is a schematic cross-sectional view of a heat dissipation carrier provided in one embodiment of the present application;

[0033] FIG5 is one of the state diagrams of a chip high-density interconnect packaging method provided by an embodiment of the present application;

[0034] FIG6 is a second state diagram of a chip high-density interconnect packaging method provided by an embodiment of the present application;

[0035] FIG7 is a third state diagram of a chip high-density interconnect packaging method provided by an embodiment of the present application;

[0036] FIG8 is a fourth state diagram of a chip high-density interconnect packaging method provided by an embodiment of the present application;

[0037] FIG9 is a fifth state diagram of a chip high-density interconnect packaging method provided by an embodiment of the present application;

[0038] FIG10 is a schematic diagram of a structure in which chip pins are not connected according to an embodiment of the present application;

[0039] FIG11 is a schematic structural diagram of a chip pin connection provided in an embodiment of the present application;

[0040] FIG12 is a sixth state diagram of a chip high-density interconnect packaging method provided by an embodiment of the present application;

[0041] FIG13 is a seventh state diagram of a chip high-density interconnect packaging method provided by an embodiment of the present application;

[0042] FIG14 is an eighth state diagram of a chip high-density interconnect packaging method provided by an embodiment of the present application;

[0043] FIG15 is a ninth state diagram of a chip high-density interconnect packaging method provided by an embodiment of the present application;

[0044] FIG16 is a second cross-sectional schematic diagram of a heat dissipation carrier provided in an embodiment of the present application;

[0045] FIG17 is a third cross-sectional schematic diagram of a heat dissipation carrier provided in an embodiment of the present application;

[0046] FIG18 is a schematic diagram of a structure of a fine interconnect bridge according to an embodiment of the present application;

[0047] FIG19 is a second structural diagram of a fine interconnect bridge provided in an embodiment of the present application;

[0048] FIG20 is a third structural schematic diagram of a fine interconnect bridge provided in an embodiment of the present application.

[0049] Icons: 10-chip high-density interconnection packaging structure; 11-chip; 111-first pin array; 112-second pin array; 12-heat dissipation carrier; 121-patch area; 122-through hole; 13-plastic encapsulation layer; 14-package wiring layer; 141-second insulating layer; 142-connecting line; 15-fine interconnection bridge; 151-first insulating layer; 152-fine interconnection line; 153-interconnection part; 16-temporary bonding material; 17-temporary carrier; 18-pin pad; 19-lead line; 20-insulating material; 21-leveling material. DETAILED DESCRIPTION

[0050] To make the objectives, technical solutions, and advantages of the embodiments of the present application more clear, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Generally, the components of the embodiments of the present application described and shown in the drawings herein can be arranged and designed in various different configurations.

[0051] Therefore, the following detailed description of the embodiments of the present application provided in the accompanying drawings is not intended to limit the scope of the present application as claimed, but merely represents selected embodiments of the present application. It should be noted that, unless there is a conflict, the various features of the embodiments of the present application may be combined with each other, and the combined embodiments are still within the scope of protection of the present application.

[0052] In the description of this application, it should be noted that the terms "center," "upper," "lower," "left," and "right" and the like indicate positions or locations based on the positions shown in the accompanying drawings, or the positions or locations in which the product of this application is typically placed when in use, and therefore should not be construed as limiting this application. Furthermore, the terms "first," "second," and "third," etc., are used solely for purposes of distinction and should not be construed as indicating or implying relative importance.

[0053] It should also be noted that, in the description of this application, unless otherwise specified or limited, the terms "disposed" and "connected" should be understood broadly. For example, they can refer to direct connection, indirect connection through an intermediate medium, or internal connection between two components. Those skilled in the art will understand the specific meanings of these terms in this application.

[0054] In one aspect of an embodiment of the present application, a chip high-density interconnect packaging method is provided. By encapsulating a heat dissipation carrier 12 within a chip high-density interconnect packaging structure 10, heat generated by a chip 11 can be quickly and efficiently dissipated. As shown in FIG1 , the method may schematically include:

[0055] S10: As shown in FIG2 , FIG3 , and FIG4 , a heat sink carrier 12 and a plurality of chips 11 are provided. The heat sink carrier 12 includes a plurality of mounting areas 121 for mounting the chips 11 respectively. Functional surfaces of the plurality of chips 11 each have a first pin array 111 of a first density and a second pin array 112 of a second density, where the first density is smaller than the second density.

[0056] As shown in Figures 2 and 3, area A in Figure 2 represents the first pin array 111, and area B represents the second pin array 112. As can be seen from Figure 2, the first density of the first pin array 111 is less than the second density of the second pin array 112. Therefore, the second pin array 112 can be referred to as a high-density pin array, representing a fine interconnect pin array; the first pin array 111 is referred to as a low-density pin array. The high-density pin array is used to interconnect the chip high-density interconnect package structure 10, improving interconnect density and transmission speed. It should be noted that density refers to the number of pins per unit area, which is related to the size of the pins themselves and the spacing between adjacent pins. As can be seen from Figure 2, the pins in the high-density pin array are smaller, and the spacing between adjacent pins is smaller.

[0057] The embodiment of the present application does not specifically limit the specific type of chip 11, as long as there are multiple chips 11 that need to be connected to each other. For example, they can be integrated circuit chips, passive device chips, sensors, etc.

[0058] Furthermore, it is understood that the heat sink 12 has a heat dissipation function, so the heat sink 12 should have a high thermal conductivity to conduct heat. Specifically, the patch areas 121 of the heat sink 12 are used to mount the chips 11. The heat generated by the chips 11 can be directly transferred to the heat sink 12 and then quickly transferred to the outside world through the heat sink 12. The patch areas 121 on the heat sink 12 can be manually positioned as close as possible to the chips 11 while ensuring normal operation, thereby reducing the volume of the high-density interconnect package structure 10.

[0059] S20: As shown in FIG5 , the chip 11 is attached to the patch area 121 through the back side of the chip 11 ;

[0060] It is understandable that when bonding the back surface of the chip 11 to the patch area 121 of the heat dissipation carrier 12 , insulating glue with good thermal conductivity can be used, or conductive and thermally conductive metal adhesives such as solder paste and silver paste can be used.

[0061] S30: As shown in FIG6 , the chip 11 and the heat dissipation carrier 12 are encapsulated with a plastic material and cured to form a plastic layer 13 , with the first pin array 111 and the second pin array 112 exposed from the plastic layer 13 ;

[0062] The plastic encapsulation layer 13 covers the heat sink substrate 12 and chip 11 to secure and protect the chip 11 attached to the patch area 121 of the heat sink substrate 12. As shown in Figure 6, the plastic encapsulation layer 13 wraps around the heat sink substrate 12 and covers both sides of the chip 11 (the sides connected to the functional surface). The functional surface can be exposed or not, and those skilled in the art can adjust it according to the situation, as long as the first pin array 111 and the second pin array 112 are exposed. The plastic encapsulation layer 13 secures the position of the chip 11 to the heat sink substrate 12 and provides a certain degree of protection for the chip 11.

[0063] It should be noted that the plastic encapsulation material can be prepared using plastic encapsulation materials commonly used in the art, and the embodiments of the present invention do not impose any particular limitation on the specific material.

[0064] S40: As shown in FIG7 , a packaging wiring layer 14 is formed on the plastic encapsulation layer 13 and connected to a fine interconnection bridge 15 . The fine interconnection bridge 15 is correspondingly connected to the second pin arrays 112 of two adjacent chips 11 , and the packaging wiring layer 14 is correspondingly connected to the first pin arrays 111 of the plurality of chips 11 , thereby forming a chip high-density interconnection packaging structure 10 .

[0065] The fine interconnect bridges 15 are used to connect the corresponding second pin arrays 112 of adjacent chips 11, thereby achieving high-density interconnection between two adjacent chips 11, enabling high-density interconnection between chips 11 with different specific functions. The fine interconnect bridges 15 are used to connect the high-density pin arrays of two adjacent chips 11. In applications where multiple chips 11 are included, a fine interconnect bridge 15 is required between each adjacent chip 11 to achieve interconnection between the corresponding chips 11. Therefore, in the chip 11 interconnection packaging method, the number of fine interconnect bridges 15 can be one, two, or more, depending on the number of chips 11 and the interconnection requirements between the chips 11. The embodiments of the present invention do not specifically limit the number of fine interconnect bridges 15 or their specific locations.

[0066] In order to facilitate the lead-out of the package wiring layer 14 , a plurality of pads are provided on the upper surface of the package wiring layer 14 corresponding to the first pin array 111 , which may be solder balls or bumps of a ball grid array (BGA) package, for example.

[0067] In addition, in actual applications, in order to improve the efficiency of interconnection packaging of chips 11, multiple groups of chip groups that need to be interconnected can be packaged on the same heat dissipation carrier 12. After completing step S40, the packaging structure is cut as needed to separate the multiple groups of chip groups, wherein each chip group contains at least two chips 11.

[0068] The present application provides a chip high-density interconnection packaging method, comprising: providing a heat dissipation carrier 12 and a plurality of chips 11, the heat dissipation carrier 12 including a plurality of patch areas 121 for respectively mounting the chips 11, the functional surfaces of the plurality of chips 11 each having a first pin array 111 of a first density and a second pin array 112 of a second density, wherein the first density is less than the second density; attaching the chip 11 to the patch area 121 through the back surface of the chip 11; making the chip 11 directly contact the heat dissipation carrier 12, so that the heat generated by the chip 11 can be immediately conducted to the heat dissipation carrier 12, and the heat dissipation carrier 12 can quickly dissipate the heat, thereby improving the heat dissipation effect of the chip high-density interconnection packaging structure 10; using a plastic encapsulation material to encapsulate the chip 11 and the heat dissipation carrier 12 and solidifying it to form a plastic encapsulation layer 13, the first pin array 11 1 and the second pin array 112 are exposed from the plastic encapsulation layer 13; a packaging wiring layer 14 is formed on the plastic encapsulation layer 13 and connected to a fine interconnection bridge 15, the fine interconnection bridge 15 is correspondingly connected to the second pin arrays 112 of two adjacent chips 11, and the packaging wiring layer 14 is correspondingly connected to the first pin arrays 111 of multiple chips 11 to form a chip high-density interconnection packaging structure 10, the fine interconnection bridge 15 can realize fine interconnection between the two chips 11, thereby improving the signal transmission efficiency of the chip high-density interconnection packaging structure 10, in addition, the heat dissipation carrier 12 has a certain strength, which can prevent the chip high-density interconnection packaging structure 10 from warping, thereby avoiding problems caused by warping of materials such as plastic encapsulation materials. Specifically, warping seriously limits the line width and line spacing of the packaging wiring layer 14, and also affects the reliability of the electrical connection.

[0069] Optionally, forming the package wiring layer 14 on the plastic encapsulation layer 13 and connecting the fine interconnection bridge 15 includes:

[0070] S41: As shown in area C in FIG. 7 , a package wiring layer 14 is formed on the plastic packaging layer 13 , and the package wiring layer 14 is connected to the first pin arrays 111 of the plurality of chips 11 ;

[0071] It can be understood that FIG. 7 is a cross-sectional view of a state diagram of the chip high-density interconnection package structure 10 , and the package wiring layer 14 includes a wiring line connected to each pin in each first pin array 111 .

[0072] S42 : As shown in area C in FIG. 7 , a fine interconnection bridge 15 is connected to the plastic packaging layer 13 , and the fine interconnection bridge 15 is connected to the second pin arrays 112 of two adjacent chips 11 .

[0073] The fine interconnection bridge 15 as a whole is mounted on the second pin array 112 when connection is required, and the interconnection members 153 of the fine interconnection bridge 15 are respectively connected to the second pin array 112 .

[0074] In order to facilitate the installation of the fine interconnection bridge 15 , when forming the package wiring layer 14 , spaces are left at locations where the fine interconnection bridge 15 is to be installed.

[0075] In one achievable manner of the embodiment of the present application, forming the package wiring layer 14 on the plastic encapsulation layer 13 and connecting the fine interconnection bridges 15 includes:

[0076] S43: As shown in area D in FIG7 , a package wiring layer 14 is formed on the plastic layer 13 . The package wiring layer 14 includes a first pattern connected to the first pin arrays 111 of the plurality of chips 11 , and a second pattern connected to the second pin arrays 112 of some chips 11 .

[0077] The first pattern is used to connect to the first pin array 111. Since the first pin array 111 is a non-fine pin array, the first pattern connected to the first pin array 111 is a non-fine interconnect line. The second pattern is used to connect to the second pin array 112. Since the second pin array 112 is a fine pin array, the second pattern connected to the second pin array 112 is a fine interconnect line.

[0078] S44 : As shown in area D in FIG. 7 , a fine interconnection bridge 15 is connected to the package wiring layer 14 , and the fine interconnection bridge 15 is connected to the second pattern.

[0079] The second pin array 112 is a fine pin array, and the second pattern is led out through the fine interconnection bridge 15 to achieve the lead-out of the second pins.

[0080] It should be noted that steps S41-S42 and steps S43-S44 can be applied separately to a chip 11 interconnection packaging method, or can be applied together to a chip high-density interconnection packaging method. Those skilled in the art can make a choice based on actual conditions.

[0081] Optionally, the chip 11 and the heat dissipation carrier 12 are encapsulated with a plastic material and cured to form a plastic layer 13, and the first pin array 111 and the second pin array 112 are exposed from the plastic layer 13, including:

[0082] S31: As shown in FIG8 , the functional surface of the chip 11 is connected to the temporary carrier 17 via the temporary bonding material 16 , and the temporary bonding material 16 is in contact with the first pin array 111 and the second pin array 112 ;

[0083] The temporary carrier 17 plays a temporary supporting role, and its material can be silicon, silicon dioxide, glass, etc.

[0084] S32: As shown in FIG9 , the chip 11 and the heat dissipation carrier 12 are encapsulated with a plastic encapsulation material and are in contact with a temporary bonding material 16 ;

[0085] When the temporary carrier 17 is provided, the temporary material also serves as a barrier during the molding process, so that the molding material does not contaminate the surfaces of the first pin array 111 and the second pin array 112 and affect the electrical transmission between the first pin array 111 and the second pin array 112 .

[0086] S33 : As shown in FIG. 6 , the temporary carrier 17 is removed by removing the temporary bonding material 16 so that the first pin array 111 and the second pin array 112 are exposed from the plastic packaging layer 13 .

[0087] The temporary bonding material 16 is used to connect the temporary carrier 17 and the first pin array 111 and the second pin array 112 on the functional surface of the chip 11. When the temporary bonding material 16 is a release material, when the temporary carrier 17 is removed to expose the first pin array 111 and the second pin array 112, it can be removed by release, thereby reducing the impact on the first pin array 111 and the second pin array 112, thereby improving the stability of the interconnection of the chip 11. Among them, the release material can be a laser release material, a thermal release material, etc. Specifically, laser release removal, thermal release removal, etc. can be adopted. When selecting the removal method, it can be adaptively selected according to the specific material of the release material, and this application does not limit it.

[0088] When the temporary bonding material 16 is a bonding material, when the temporary carrier 17 is removed to expose the first pin array 111 and the second pin array 112 , the bonding material can be etched. Specifically, dry etching or wet etching can be used for removal.

[0089] Optionally, providing the heat dissipation carrier 12 and the plurality of chips 11 includes:

[0090] S11: As shown in Figures 10 and 11, a lead wire 19 and a plurality of pin pads 18 arranged at the edge of the functional surface are formed on the functional surface, one end of the lead wire 19 is connected to the pin, and the other end is connected to the pin pad 18, so as to lead the pin to the edge of the functional surface to form a first pin array 111 and a second pin array 112.

[0091] Among them, when the pins of multiple chips 11 are randomly distributed on the functional surface, as shown in Figure 10, Figure 10 of chip 11 is the original chip, and multiple pins are randomly distributed on the functional surface, which is not conducive to the connection between the pins and the fine interconnection bridge 15 and the packaging wiring layer 14. In the embodiment of the present application, multiple pins of the original chip are first connected by secondary wiring, so that the first pin array 111 and the second pin array 112 are located at the edge of the chip functional surface, which is convenient for the subsequent installation of the packaging wiring layer 14 and the fine interconnection bridge 15.

[0092] It is understandable that the first pin array 111 and the second pin array 112 may be located on opposite sides of the chip functional surface, which is more conducive to subsequent interconnection.

[0093] Of course, when the pins on the chip 11 are arranged relatively neatly and are located at the edge of the functional surface, there is no need to perform secondary wiring connection on the pins of the chip 11.

[0094] In one achievable method of the embodiment of the present application, the chip 11 is attached to the patch area 121 through the back surface of the chip 11:

[0095] S21: The second pin arrays 112 of two adjacent chips 11 are brought closer together.

[0096] The second pin arrays 112 of two adjacent chips 11 are brought closer together, that is, the high-density pin arrays are brought closer together. As can be seen from the above, the fine interconnect bridge 15 is connected to the high-density pins of the two adjacent chips 11, achieving fine interconnection between the two chips 11. When the high-density pin arrays of the two adjacent chips 11 are brought closer together, the area of ​​the fine interconnect bridge 15 that needs to contact the two chips 11 can be reduced, thereby reducing the area of ​​the fine interconnect bridge 15.

[0097] It should be noted that, when there are multiple chips 11 , two adjacent chips 11 refer to two chips 11 connected to the same fine interconnection bridge 15 , and the second pin arrays 112 connected to the same fine interconnection bridge 15 are close to each other.

[0098] Optionally, after the plastic encapsulation layer 13 forms the packaging wiring layer 14 and connects the fine interconnection bridge 15 , the chip 11 interconnection packaging method further includes:

[0099] S45 : As shown in FIG. 12 , an insulating material 20 is filled between the fine interconnection bridge 15 and the molding layer 13 or between the fine interconnection bridge 15 and the functional surface of the chip 11 .

[0100] The point on the fine interconnection bridge 15 that is electrically connected to the second pin array 112 is usually provided with an interconnection part 153. The interconnection part 153 inevitably has a certain thickness, so that there is a certain gap between the fine interconnection bridge 15 and the plastic encapsulation layer 13, or the fine interconnection bridge 15 and the functional surface of the chip 11. In the embodiment of the present application, an insulating material 20 is filled between the fine interconnection bridge 15 and the plastic encapsulation layer 13 or the fine interconnection bridge 15 and the functional surface of the chip 11. The insulating material 20 can play a role of reinforcement and support to improve the stability of the interconnection between the plastic encapsulation layer 13 and the fine interconnection bridge 15, or the chip 11 and the fine interconnection bridge 15, thereby ensuring the performance and stability of the packaging structure.

[0101] Among them, the insulating material 20 can be made of the same material as the plastic encapsulation layer 13, or a material different from the plastic encapsulation layer 13. For example, an insulating material 20 or other suitable material with better fluidity than the plastic encapsulation layer 13 material in a molten state can be used, so that the insulating material 20 can flow more easily into the bottom of the fine interconnection bridge 15, thereby supporting and reinforcing the fine interconnection bridge 15.

[0102] In one possible implementation of the embodiment of the present application, a plastic encapsulation material is used to wrap the chip 11 and the heat dissipation carrier 12 and solidified to form a plastic encapsulation layer 13. After the first pin array 111 and the second pin array 112 are exposed from the plastic encapsulation layer 13, the chip high-density interconnect packaging method further includes:

[0103] S34: As shown in FIG13 , a leveling material 21 is used to fill the height difference between the plastic package and the functional surface;

[0104] The leveling material 21 fills the height difference between the chip 11 and the upper surface of the plastic encapsulation layer 13, making it as flat as possible. This facilitates the subsequent preparation of the package wiring layer 14 and the connection of the fine interconnect bridges 15. Specifically, after the leveling material 21 is used to fill the height difference between the plastic encapsulation and the functional surface, the height difference of the upper surface of the leveling material does not exceed 5 μm.

[0105] S35: As shown in FIG15 , the leveling material 21 is partially etched to expose the first pin array 111 and the second pin array 112 , or, as shown in FIG14 , the leveling material 21 is partially etched to expose the portion of the functional surface where the second pin array 112 is disposed.

[0106] Optionally, providing the heat dissipation carrier 12 and the plurality of chips 11 includes:

[0107] S12: As shown in Figures 16 and 17, a groove is formed on the surface of the heat dissipation carrier 12 so that the heat dissipation carrier 12 has two first planes or second planes of different heights on the same side, and the first plane serves as the patch area 121, or the second plane serves as the patch area 121.

[0108] It should be understood that the first plane and the second plane are relative to a single chip 11. The chip 11 can be disposed in a recess or on a plane at a higher elevation, depending on the requirements of the high-density interconnect package structure 10. The first planes on which multiple chips 11 are located can be at the same or different elevations.

[0109] The grooves are formed on the heat dissipation carrier 12 so that the chip 11 can be placed according to actual conditions, thereby improving the flexibility of high-density interconnection packaging of the chip.

[0110] In one possible implementation of the embodiment of the present application, providing the heat dissipation carrier 12 and the plurality of chips 11 includes:

[0111] S13 : As shown in FIG. 4 , FIG. 16 and FIG. 17 , a plurality of through holes 122 are formed on the heat dissipation carrier 12 , and the molding material flows into between the temporary carrier 17 and the heat dissipation carrier 12 through the through holes 122 .

[0112] A through hole 122 is formed on the heat dissipation carrier 12. The through hole 122 is used for the plastic material to flow into between the temporary carrier 17 and the heat dissipation carrier 12 during plastic packaging. The through hole 122 is provided to facilitate the flow of plastic material for plastic packaging.

[0113] Optionally, as shown in Figures 18, 19 and 20, the fine interconnection bridge 15 includes at least one first insulating layer 151, fine interconnection lines 152 respectively formed in the first insulating layer 151, and a plurality of interconnections 153 connected to the outermost fine interconnection lines 152. The fine interconnection lines 152 of two adjacent layers are respectively connected correspondingly, and the interconnections 153 are used to connect correspondingly to the second pin arrays 112 of two adjacent chips 11.

[0114] Among them, the material of the first insulating layer 151 is not limited in the embodiment of the present application, and those skilled in the art can select it according to actual conditions. It can be silicon material to form a silicon connecting bridge, or it can be other insulating materials 20 such as glass, plastic, resin, etc. The material of each layer of the first insulating layer 151 can be the same or different.

[0115] Specifically, the preparation method of the fine interconnection bridge 15 includes preparing a first insulating layer 151 on a substrate, and forming micropores at the fine interconnection lines 152 of the first insulating layer 151, and then filling the micropores with metal material to form the fine interconnection lines 152, and then forming a second insulating layer 141 on the first layer of lines, and forming micropores at the fine interconnection lines 152 of the second insulating layer 141, the micropores of the second layer are connected to the first layer of fine interconnection lines 152, and then filling the micropores of the second layer with metal material to form the second layer of fine interconnection lines 152, and so on until all levels of fine interconnection lines 152 are completed, and finally forming interconnections 153 on the last first insulating layer 151.

[0116] As can be seen from the above, the fine interconnection bridge 15 is used for fine interconnection of the high-density pin arrays of two adjacent chips 11, that is, the fine interconnection line 152 in each insulating layer of the fine interconnection bridge 15 is a fine interconnection line, wherein the interconnection member 153 is used to connect to the second pin array 112 of the two adjacent chips 11, and the interconnection member 153 is a fine interconnection member 153, which can be a fine interconnection pad or a fine interconnection bump.

[0117] In one implementable manner of an embodiment of the present application, as shown in Figures 7 and 12, the package wiring layer 14 includes at least one second insulating layer 141, and connecting lines 142 respectively formed in the second insulating layer 141, and the connecting lines 142 of two adjacent layers are respectively connected to each other. The connecting lines 142 close to the chip 11 are connected to the first pin arrays 111 of the multiple chips 11, or the connecting lines 142 close to the chip 11 are respectively connected to the first pin arrays 111 of the multiple chips 11 and the second pin arrays 112 of some chips 11.

[0118] It should be noted that the first pin array 111, the second pin array 112, the fine interconnection bridge 15, and the package wiring layer in the embodiment of the present application are fine interconnections or non-fine interconnections, wherein the fine interconnections can realize the connection of more lines within a limited area, thereby improving the data transmission efficiency. The fine interconnection in the present application refers to a line connection with a line width of less than 5μm.

[0119] On the other hand, an embodiment of the present application provides a chip high-density interconnection packaging structure 10, as shown in Figures 7 and 12, including: a heat dissipation carrier 12 and multiple chips 11 arranged on the heat dissipation carrier 12, the non-functional surface of the chip 11 is in contact with the heat dissipation carrier 12, and multiple through holes 122 are provided on the heat dissipation carrier 11. The functional surfaces of the multiple chips have a first pin array of a first density and a second pin array of a second density, and the first density is less than the second density. The high-density interconnection packaging structure also includes a plastic packaging component that plastic-encapsulates the chip and the heat dissipation carrier, and the plastic packaging component is provided with a packaging wiring layer connected to the first pin array and a fine interconnection bridge connected to the second pin array; the packaging component forming process includes: connecting the functional surface of the chip to the temporary carrier through a temporary bonding material, and using the temporary carrier as a base, filling the molten plastic packaging material between the chip and the heat dissipation carrier through the through hole and wrapping the heat dissipation carrier, forming a plastic packaging component after the plastic packaging material is solidified, and removing the temporary carrier and temporary bonding material. The chip high-density interconnection packaging structure 10 provided in the embodiment of the present application directly contacts the finely interconnected chip 11 with the heat dissipation carrier 12, which can quickly conduct the heat generated by the chip 11 and achieve rapid heat dissipation of the chip 11. In addition, the heat dissipation carrier 12 has a certain strength, which can avoid the problems caused by warping of materials such as plastic packaging materials. Specifically, warping seriously limits the line width and line spacing of the packaging wiring layer 14, and also affects the reliability of the electrical connection.

[0120] Optionally, the functional surface of the chip includes multiple pins, and the pins are connected to pin pads arranged at the edge of the chip through lead wires, so that the multiple pins are led out to the edge of the functional surface to form a first pin array and a second pin array.

[0121] When the pins of multiple chips 11 are randomly distributed on the functional surface, as shown in Figure 10, Figure 10 of the chip 11 is the original chip, and multiple pins are randomly distributed on the functional surface, which is not conducive to the connection between the pins and the fine interconnection bridge 15 and the packaging wiring layer 14. In the embodiment of the present application, multiple pins of the original chip are first connected by secondary wiring, so that the first pin array 111 and the second pin array 112 are located at the edge of the chip functional surface, which is convenient for the subsequent installation of the packaging wiring layer 14 and the fine interconnection bridge 15.

[0122] It is understandable that the first pin array 111 and the second pin array 112 may be located on opposite sides of the chip functional surface, which is more conducive to subsequent interconnection.

[0123] Of course, when the pins on the chip 11 are arranged relatively neatly and are located at the edge of the functional surface, there is no need to perform secondary wiring connection on the pins of the chip 11.

[0124] As an implementable manner, as shown in FIG7 and FIG12 , the fine interconnection bridge 15 is provided on the chip 11 and connected to the second density pins of the chip 11 , or the fine interconnection bridge is provided on the package wiring layer and connected to the second density pins through the package wiring layer.

[0125] Optionally, the fine interconnection bridge 15 includes a base material, a fine interconnection line arranged in the base material, and a plurality of interconnections arranged on both sides of the base material to connect the fine interconnection line. The base material is one of silicon, ceramic, glass, plastic, and resin.

[0126] Specifically, the base material includes at least one first insulating layer, the fine interconnection lines are layered in the first insulating layer, the fine interconnection lines 152 of two adjacent layers are respectively connected, and the interconnection parts 153 are used to connect to the second pin arrays 112 of two adjacent chips 11.

[0127] As an implementable method, a leveling material 21 is further provided on the plastic package 13 and the chip 11 to fill the height difference between the functional surfaces of the plastic package 13 and the chip 11. The first pin array 111 and the second pin array 112 are exposed through the leveling material, and the leveling material 21 is insulating.

[0128] The leveling material 21 fills the height difference between the chip 11 and the upper surface of the plastic encapsulation layer 13, making it as flat as possible. This facilitates the subsequent preparation of the package wiring layer 14 and the connection of the fine interconnect bridges 15. Specifically, after the leveling material 21 is used to fill the height difference between the plastic encapsulation and the functional surface, the height difference of the upper surface of the leveling material does not exceed 5 μm.

[0129] Optionally, the packaging wiring layer 14 is arranged on the leveling material 21, and includes at least one second insulating layer, and connecting lines formed in the second insulating layer respectively. The connecting lines between the two connected layers are respectively connected, and the connecting lines include fine connecting lines and non-fine connecting lines. Fine interconnect pins connected to the fine connecting lines, and non-fine interconnect pins connected to the non-fine connecting lines are also provided on the surface of the packaging wiring layer 14. The fine connection lines are correspondingly connected to the second pin array 112, and the non-fine connection lines are correspondingly connected to the first pin array 111.

[0130] Optionally, an insulating material may be included between the fine interconnection bridge 15 and the functional surface of the chip 11 , or between the fine interconnection bridge 15 and the leveling material 21 .

[0131] The point on the fine interconnection bridge 15 that is electrically connected to the second pin array 112 is usually provided with an interconnection part 153. The interconnection part 153 inevitably has a certain thickness, so that there is a certain gap between the fine interconnection bridge 15 and the plastic encapsulation layer 13, or the fine interconnection bridge 15 and the functional surface of the chip 11. In the embodiment of the present application, an insulating material 20 is filled between the fine interconnection bridge 15 and the plastic encapsulation layer 13 or the fine interconnection bridge 15 and the functional surface of the chip 11. The insulating material 20 can play a role of reinforcement and support to improve the stability of the interconnection between the plastic encapsulation layer 13 and the fine interconnection bridge 15, or the chip 11 and the fine interconnection bridge 15, thereby ensuring the performance and stability of the packaging structure.

[0132] Among them, the insulating material 20 can be made of the same material as the plastic encapsulation layer 13, or a material different from the plastic encapsulation layer 13. For example, an insulating material 20 or other suitable material with better fluidity than the plastic encapsulation layer 13 material in a molten state can be used, so that the insulating material 20 can flow more easily into the bottom of the fine interconnection bridge 15, thereby supporting and reinforcing the fine interconnection bridge 15. Industrial Applicability

[0133] The present application provides a chip high-density interconnect packaging method, comprising: providing a heat dissipation carrier and a plurality of chips, the heat dissipation carrier comprising a plurality of patch areas for respectively mounting the chips, the functional surfaces of the plurality of chips each having a first pin array of a first density and a second pin array of a second density, the first density being less than the second density; attaching the chip to the patch area through the back surface of the chip; making the chip directly contact the heat dissipation carrier, so that the heat generated by the chip can be immediately transferred to the heat dissipation carrier, and the heat dissipation carrier can quickly dissipate the heat, thereby improving the heat dissipation effect of the chip high-density interconnect packaging structure; using a plastic encapsulation material to encapsulate the chip and the heat dissipation carrier and curing to form a plastic encapsulation layer, the first pin array and the second pin array are respectively provided. The pin array is exposed from the plastic encapsulation layer; a packaging wiring layer is formed on the plastic encapsulation layer and connected to a fine interconnection bridge, the fine interconnection bridge is correspondingly connected to the second pin arrays of two adjacent chips, and the packaging wiring layer is correspondingly connected to the first pin arrays of multiple chips to form a chip high-density interconnection packaging structure. The fine interconnection bridge can realize fine interconnection between the two chips, thereby improving the signal transmission efficiency of the chip high-density interconnection packaging structure. In addition, the heat dissipation carrier has a certain strength, which can prevent the chip high-density interconnection packaging structure from warping, thereby avoiding problems caused by warping of materials such as plastic encapsulation materials. Specifically, warping seriously limits the line width and line spacing of the packaging wiring layer, and also affects the reliability of the electrical connection.

Claims

1. A chip high-density interconnect packaging structure, characterized in that: include: A heat sink and a plurality of chips arranged on the heat sink, wherein the non-functional surfaces of the chips are in contact with the heat sink, the heat sink is provided with a plurality of through holes, and the functional surfaces of the plurality of chips all have a first pin array of a first density and a second pin array of a second density, wherein the first density is less than the second density; the high-density interconnect packaging structure further comprises a plastic sealing member for plastic sealing the chips and the heat sink, wherein a packaging wiring layer connected to the first pin array and a fine interconnection bridge connected to the second pin array are provided on the plastic sealing member; Among them, the package forming process includes: connecting the functional surface of the chip to the temporary carrier through a temporary bonding material, and using the temporary carrier as a base, the molten plastic encapsulation material is filled into the space between the chip and the heat dissipation carrier through the through hole and wraps the heat dissipation carrier, the plastic encapsulation material is solidified to form a plastic encapsulation part, and the temporary carrier and the temporary bonding material are removed.

2. The chip high density interconnect packaging structure according to claim 1, characterized in that: The functional surface of the chip includes a plurality of pins, and the pins are connected to pin welding pieces arranged at the edge of the chip through lead wires, so that the plurality of pins are led out to the edge of the functional surface to form a first pin array and a second pin array.

3. The chip high density interconnect packaging structure according to claim 1, characterized in that: The fine interconnection bridge is arranged on the chip and connected to the second density pins of the chip, or the fine interconnection bridge is arranged on the package wiring layer and connected to the second density pins through the package wiring layer.

4. The chip high density interconnect packaging structure according to claim 1, characterized in that: The fine interconnection bridge comprises a base material, a fine interconnection line arranged in the base material, and a plurality of interconnection members arranged on both sides of the base material and connected to the fine interconnection line. The base material is one of silicon, ceramic, glass, plastic, and resin.

5. The chip high density interconnect packaging structure according to claim 1, characterized in that: A leveling material is also provided on the plastic package and the chip to make up for the height difference between the plastic package and the functional surface of the chip. The first pin array and the second pin array are exposed through the leveling material, and the leveling material has insulating properties.

6. The chip high density interconnect packaging structure according to claim 5, characterized in that: The packaging wiring layer is arranged on the leveling material, and includes at least one second insulating layer, and connecting circuits respectively formed in the second insulating layer, the connecting circuits between the two connected layers are respectively connected correspondingly, the connecting circuits include fine connecting circuits and non-fine connecting circuits, and fine interconnection pins connected to the fine connecting circuits and non-fine interconnection pins connected to the non-fine connecting circuits are also arranged on the surface of the packaging wiring layer, the fine connecting circuits are correspondingly connected to the second pin array, and the non-fine connecting circuits are correspondingly connected to the first pin array.

7. The chip high density interconnect packaging structure according to claim 5, characterized in that: The method further includes an insulating material filled between the fine interconnection bridge and the chip functional surface, or filled between the fine interconnection bridge and the planarization material.

8. A chip high density interconnect packaging method, characterized in that: include: A heat dissipation carrier and a plurality of chips are provided, wherein the heat dissipation carrier comprises a plurality of mounting areas for mounting the chips respectively, and the functional surfaces of the plurality of chips each have a first pin array of a first density and a second pin array of a second density, wherein the first density is less than the second density; Adhere the chip to the patch area through the back side of the chip; The chip and the heat dissipation carrier are encapsulated with a plastic encapsulation material and cured to form a plastic encapsulation layer, wherein the first pin array and the second pin array are exposed from the plastic encapsulation layer; A packaging wiring layer is formed on the plastic packaging layer and connected to a fine interconnection bridge, wherein the fine interconnection bridge is correspondingly connected to the second pin arrays of two adjacent chips, and the packaging wiring layer is correspondingly connected to the first pin arrays of multiple chips to form a chip high-density interconnection packaging structure.

9. The chip high density interconnect packaging method according to claim 8, characterized in that: The step of forming a packaging wiring layer on the plastic packaging layer and connecting a fine interconnection bridge comprises: A packaging wiring layer is formed on the plastic packaging layer, and the packaging wiring layer is connected to the plurality of chip pairs. The first pin array should be connected; A fine interconnection bridge is connected to the plastic packaging layer, and the fine interconnection bridge is connected to the second pin arrays of the two adjacent chips.

10. The chip high density interconnect packaging method according to claim 8 or 9, characterized in that: The step of forming a packaging wiring layer on the plastic packaging layer and connecting a fine interconnection bridge comprises: Forming a packaging wiring layer on the plastic packaging layer, the packaging wiring layer comprising first patterns respectively connected to the first pin arrays of a plurality of the chips, and second patterns connected to the second pin arrays of some of the chips; A fine interconnection bridge is connected on the package wiring layer, and the fine interconnection bridge is connected to the second pattern.

11. The chip high density interconnect packaging method according to claim 8, characterized in that: The step of encapsulating the chip and the heat dissipation carrier board with a plastic encapsulation material and curing the plastic encapsulation material to form a plastic encapsulation layer, wherein the first pin array and the second pin array are exposed from the plastic encapsulation layer comprises: A temporary carrier is provided on the functional surface of the chip via a temporary bonding material, wherein the temporary bonding material is in contact with the first pin array and the second pin array; Using a plastic packaging material to plasticize the chip and the heat dissipation carrier and make them contact with the temporary bonding material; The temporary carrier is removed by removing the temporary bonding material so that the first pin array and the second pin array are exposed from the plastic packaging layer.

12. The chip high density interconnect packaging method according to claim 8, characterized in that: Provide heat sink and multiple chips including: Lead wires and a plurality of pin pads arranged at the edge of the functional surface are formed on the functional surface, one end of the lead wire is connected to the pin, and the other end is connected to the pin pad, so as to lead the pin to the edge of the functional surface to form a first pin array and a second pin array.

13. The chip high density interconnect packaging method according to claim 12, characterized in that: The step of attaching the chip to the patch area through the back side of the chip: The second pin arrays of two adjacent chips are close to each other.

14. The chip high density interconnect packaging method according to any one of claims 8 to 10, characterized in that: After the plastic encapsulation layer forms a packaging wiring layer and connects a fine interconnection bridge, the method further includes: An insulating material is filled between the fine interconnection bridge and the plastic encapsulation layer, or between the fine interconnection bridge and the functional surface of the chip.

15. The chip high density interconnect packaging method according to claim 8, characterized in that: The chip and the heat dissipation carrier are wrapped with a plastic material and cured to form a plastic layer, and after the first pin array and the second pin array are exposed from the plastic layer, the method further comprises: Using a leveling material to level the height difference between the plastic sealing part and the functional surface; The planarization material is partially etched to expose the first pin array and the second pin array, or the planarization material is partially etched to expose a portion of the functional surface where the second pin array is disposed.

16. The chip high density interconnect packaging method according to claim 8, characterized in that: Provide heat sink and multiple chips including: A groove is formed on the surface of the heat dissipation carrier so that the heat dissipation carrier has two first planes or second planes with different heights on the same side, and the first plane is used as the patch area, or the second plane is used as the patch area.

17. The chip high density interconnect packaging method according to claim 11, characterized in that: Provide heat sink and multiple chips including: A plurality of through holes are formed on the heat dissipation carrier, and the plastic encapsulation material flows into between the temporary carrier and the heat dissipation carrier through the through holes.

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