Storage apparatus and control method therefor, and electronic device

Abstract

The present application relates to the technical field of storage. Provided are a storage apparatus and a control method therefor, and an electronic device, which can further improve storage density while increasing a current sense margin. The storage apparatus comprises a first storage unit and a differential sensing amplifier electrically connected to the first storage unit. The first storage unit comprises a first floating gate transistor and a second floating gate transistor, wherein the first floating gate transistor and the second floating gate transistor are located at the back end of a line, and use metal-oxide-semiconductor ring channel-type field-effect transistors. The differential sensing amplifier is located at the front end of the line, and is connected to both a source electrode of the first floating gate transistor and a source electrode of the second floating gate transistor.

Description

Storage device, control method thereof, and electronic device

[0001] This application claims priority to the Chinese patent application filed with the China Patent Office on August 11, 2023, with application number 202311016963.6 and invention name “Storage device and its control method, electronic device”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present application relates to the field of storage technology, and in particular to a storage device and a control method thereof, and an electronic device. Background Art

[0003] The memory cells of current mainstream DRAM (dynamic random access memory) products are primarily based on a 1T1C (1 transistor 1 capacitor) structure, meaning that each memory cell contains one transistor and one capacitor. With the evolution of process nodes, the storage density improvement of this 1T1C structure has been limited.

[0004] In recent years, researchers have developed a DRAM product using floating-gate transistors to improve storage density. As shown in Figure 1, in this memory product, memory cell C uses a single floating-gate transistor, fabricated in the front-end process. As shown in Figure 2, memory cell C has a "0" state and a "1" state. Due to process fluctuations, the read current Ird in the two states approximates a normal distribution. The read current Ird in the "0" state is smaller, while the read current Ird in the "1" state is larger. During a read operation, a reference current Iref is set between the maximum read current in the "0" state and the minimum read current in the "1" state. The read current is amplified by a sense amplifier SA (sensing amplifier) ​​and compared with the reference current Iref to read the stored data. In this case, the current sense margin is small, equivalent to half the difference between the maximum read current in the "0" state and the minimum read current in the "1" state. This requires the sense amplifier SA to have very precise sensitivity, placing high demands on the design of the memory device.

[0005] Based on this, the present application provides an improved storage device that can further improve storage density while increasing current sense margin.

[0006] Summary of the Invention

[0007] The present application provides a storage device and a control method thereof, and an electronic device, which can increase current sense margin while further improving storage density.

[0008] The present application provides a storage device comprising a first storage unit and a differential sense amplifier electrically connected to the first storage unit. The first storage unit comprises a first floating-gate transistor and a second floating-gate transistor. The first floating-gate transistor and the second floating-gate transistor are located in a back-end process and employ oxide semiconductor ring-channel field-effect transistors. The differential sense amplifier is located in a front-end process and is connected to the sources of both the first floating-gate transistor and the second floating-gate transistor.

[0009] On the one hand, in the memory device provided by this application, the memory cell uses a first floating-gate transistor and a second floating-gate transistor, and the two floating-gate transistors are connected to the same differential sense amplifier, that is, the memory cell adopts a differential 2T structure. In this way, when performing a data read operation, there is no need to set a reference current. By directly comparing the magnitudes of the read currents of the two floating-gate transistors, the stored data in the memory cell can be obtained, thereby increasing the current reading margin and effectively meeting the reliability and stability of the read operation.

[0010] On the other hand, in the storage device provided in the present application, the first floating-gate transistor and the second floating-gate transistor in the storage cell adopt OS CAA transistors (i.e., floating-gate oxide semiconductor ring channel field-effect transistors). OS CAA transistors can meet the requirements of back-end of line (BEOL) integration. On this basis, the differential sense amplifier is set in the front-end of line (FEOL), thereby reducing the area overhead of the differential sense amplifier and thus improving the storage density. Of course, the use of OS CAA transistors also has the advantages of low leakage, good retention characteristics, and low-temperature preparation.

[0011] In some possible implementations, the above-mentioned storage device includes a first storage array; the first storage array includes: a plurality of floating-gate transistors arranged in an array, a plurality of word lines, a plurality of plate lines, and a plurality of bit lines. In the first storage array, the gates of the floating-gate transistors located in different rows are respectively connected to different word lines, the drains of the floating-gate transistors located in different rows are respectively connected to different plate lines; the sources of the floating-gate transistors located in different columns are respectively connected to different bit lines. Among the plurality of floating-gate transistors arranged in the array, two adjacent floating-gate transistors located in the same row serve as the first floating-gate transistor and the second floating-gate transistor in the first storage unit, respectively, and the two bit lines connected to the first floating-gate transistor and the second floating-gate transistor are connected to the same differential sense amplifier. The first storage units located in different columns are connected to different differential sense amplifiers through bit lines.

[0012] In some possible implementations, a storage device includes: a first storage array and a second storage array arranged in the same layer. The first storage array and the second storage array both include: a plurality of floating gate transistors, a plurality of word lines, a plurality of plate lines, and a plurality of bit lines arranged in an array. In the first storage array and the second storage array: the gates of the plurality of floating gate transistors located in different columns are connected to different word lines, the drains of the plurality of floating gate transistors located in different columns are connected to different plate lines; and the sources of the plurality of floating gate transistors located in different rows are connected to different bit lines. The two floating gate transistors at corresponding positions in the first storage array and the second storage array serve as the first floating gate transistor and the second floating gate transistor in the first storage cell, respectively, and the two bit lines connected to the first floating gate transistor and the second floating gate transistor are connected to the same differential sense amplifier.

[0013] In some possible implementations, the first storage array and the second storage array are located on the same layer.

[0014] In some possible implementations, the first storage array and the second storage array are located in different layers.

[0015] Compared to the first storage array and the second storage array being integrated in the same layer, the storage density can be further improved by arranging the first storage array and the second storage array in different layers.

[0016] In some possible implementations, the first floating gate transistor includes: a stacked structure, a first trench, a gate, a floating gate, a gate insulating layer, and a channel layer. The stacked structure is arranged on a silicon substrate, and the stacked structure includes a source layer and a drain layer, and the source layer is closer to the silicon substrate relative to the drain layer. The first trench is arranged on the stacked structure, and the first trench extends at least into the source layer. The gate is arranged in the first trench and extends to the depth where the source layer is located. The floating gate is arranged in the first trench, and the floating gate is arranged around the gate. The gate insulating layer is located between the gate and the floating gate. The channel layer covers the inner wall of the first trench and connects the source layer and the drain layer.

[0017] The present application further provides a method for controlling a storage device as provided in any of the aforementioned possible implementations, the method comprising:

[0018] During a write operation, a high voltage is applied to the gate of the selected first floating-gate transistor, and a low voltage is applied to the source and drain; a high voltage is applied to the source and drain of the selected second floating-gate transistor, and a low voltage is applied to the gate. Alternatively, a high voltage is applied to the source and drain of the selected first floating-gate transistor, and a low voltage is applied to the gate; a high voltage is applied to the gate of the selected second floating-gate transistor, and a low voltage is applied to the source and drain.

[0019] When performing a read operation: a high voltage is applied to the gates of the selected first floating-gate transistor and the second floating-gate transistor, and a read voltage is applied to the drains of the selected first floating-gate transistor and the second floating-gate transistor; the source currents of the selected first floating-gate transistor and the second floating-gate transistor are amplified by a differential sensitive amplifier; and based on the magnitudes of the source currents of the selected first floating-gate transistor and the second floating-gate transistor, the storage data in the selected first storage unit is determined.

[0020] In some possible implementations, the above-mentioned applying a high voltage to the gate of the selected first floating-gate transistor and a low voltage to the source and drain; and applying a high voltage to the source and drain of the selected second floating-gate transistor and a low voltage to the gate, may include: applying a high voltage to the gate of the selected first floating-gate transistor and a low voltage to the source and drain to write "1" in the selected first floating-gate transistor; applying a high voltage to the source and drain of the selected second floating-gate transistor and a low voltage to the gate to write "0" in the selected second floating-gate transistor; in this case, the storage data "1" is written in the selected first storage cell.

[0021] In some possible implementations, the above-mentioned applying a high voltage to the source and drain of the selected first floating-gate transistor and a low voltage to the gate; applying a high voltage to the gate of the selected second floating-gate transistor and a low voltage to the source and drain may include: applying a high voltage to the source and drain of the selected first floating-gate transistor and a low voltage to the gate to write "0" in the selected first floating-gate transistor; applying a high voltage to the gate of the selected second floating-gate transistor and a low voltage to the source and drain to write "1" in the selected second floating-gate transistor; in this case, the storage data "0" is written in the selected first storage cell.

[0022] In some possible implementations, the above-mentioned determination of the storage data in the selected first storage cell based on the source current sizes of the selected first floating-gate transistor and the second floating-gate transistor may include: if the source current of the selected first floating-gate transistor is greater than the source current of the selected second floating-gate transistor, determining that the storage data in the selected first storage cell is "1"; if the source current of the selected first floating-gate transistor is less than the source current of the selected second floating-gate transistor, determining that the storage data in the selected first storage cell is "0".

[0023] The present application also provides an electronic device, which includes a circuit board and a storage device provided in any of the possible implementation methods described above, wherein the storage device is electrically connected to the circuit board. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] FIG1 is a schematic structural diagram of a storage unit provided in the prior art;

[0025] FIG2 is a read current distribution curve and current read margin of a memory cell provided in the prior art;

[0026] FIG3 is a schematic structural diagram of a storage unit provided in an embodiment of the present application;

[0027] FIG4 is a read current distribution curve and current read margin of a memory cell provided in an embodiment of the present application;

[0028] FIG5 is a schematic diagram of the structure of a floating-gate transistor in a memory cell provided by an embodiment of the present application;

[0029] FIG6 is a circuit diagram of a memory array provided in an embodiment of the present application;

[0030] FIG7 is a schematic diagram of the structure of a storage array provided in an embodiment of the present application;

[0031] FIG8 is a circuit diagram of a memory array provided in an embodiment of the present application;

[0032] FIG9 is a schematic diagram of the structure of a storage array provided in an embodiment of the present application;

[0033] FIG10 is a schematic diagram of the structure of a storage array provided in an embodiment of the present application;

[0034] FIG11 is a schematic diagram of a write operation control of a storage unit provided in an embodiment of the present application;

[0035] FIG12 is a schematic diagram of a write operation control of a storage unit provided in an embodiment of the present application;

[0036] FIG13 is a schematic diagram of a read operation control of a storage unit provided in an embodiment of the present application. DETAILED DESCRIPTION

[0037] To make the objectives, technical solutions, and advantages of this application more clear, the technical solutions in this application will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the embodiments described are only part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0038] The terms "first", "second", etc. in the specification, embodiments, claims, and drawings of this application are only used for the purpose of distinguishing descriptions and cannot be understood as indicating or implying relative importance, nor can they be understood as indicating or implying an order. "And / or" is used to describe the association relationship of associated objects, indicating that three relationships may exist. For example, "A and / or B" can mean: only A exists, only B exists, and A and B exist at the same time, where A and B can be singular or plural. The character " / " generally indicates that the objects associated before and after are in an "or" relationship. "At least one (item)" means one or more, and "multiple" means two or more. "Installation", "connection", "connected", etc. should be understood in a broad sense, for example, it can be an electrical connection or a mechanical connection; it can be a fixed connection, a detachable connection, or an integral connection; it can be a direct connection, an indirect connection through an intermediate medium, or a connection between two elements. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, including a series of steps or units. Methods, systems, products, or devices are not necessarily limited to the steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to the processes, methods, products, or devices. "Up," "down," "left," "right," etc. are used only with respect to the orientation of components in the drawings. These directional terms are relative concepts and are used for relative description and clarification. They may change accordingly depending on the orientation of the components in the drawings.

[0039] An embodiment of the present application provides an electronic device, which may be a mobile phone, a tablet computer, a personal computer (PC), a car computer, a smart watch, a smart bracelet, a server, or other electronic products. The present application does not limit the setting form of the electronic device.

[0040] The electronic device is provided with a circuit board and a storage device electrically connected to the circuit board. Of course, according to actual needs, the electronic device may also be provided with other devices, such as a processor, input and output (I / O) devices, a positioning module, a Bluetooth module, a sensor, a Wi-Fi module, etc.

[0041] In order to solve the problems of small current read margin (sense margin) and low storage density in existing storage devices, an embodiment of the present application provides a new type of storage device, in which the storage unit adopts a differential 2T structure based on a floating-gate oxide semiconductor (oxide semiconductor, OS) ring channel (channel all around, CAA) field-effect transistor (which can be referred to as a floating-gate OS CAA transistor). The storage unit using this differential 2T structure can increase the current read margin (sense margin) while improving the storage density.

[0042] The storage device provided in the embodiments of the present application can be a device with storage function such as DRAM, cache, content addressable memory, etc. The present application does not limit the configuration form of the storage device. The following embodiments are all described using the storage device as DRAM as an example.

[0043] The specific structure of the storage device provided in the embodiment of the present application is described below.

[0044] Schematically, an embodiment of the present application provides a memory device that utilizes a novel memory cell structure (also referred to as a first memory cell). As shown in FIG3 , the memory cell C1 includes a first floating-gate transistor T1 and a second floating-gate transistor T2, both of which are disposed in a back-end of line (BEOL) process. The first floating-gate transistor T1 and the second floating-gate transistor T2 are both oxide semiconductor (OS) channel-on-a-loop (CAA) field-effect transistors, referred to as floating-gate OS CAA transistors.

[0045] It should be understood that during the manufacturing process of existing memory devices, transistors in memory cells are manufactured through a front end of line (FEOL) process, that is, a plurality of transistors are fabricated on a substrate through the front end of line (FEOL) process.

[0046] In contrast, the transistors (T1, T2) in the memory cell C1 of this application use floating gate OS CAA transistors, which can be integrated in the back-end of the line (BEOL). In addition, the use of floating gate OS CAA transistors also has the advantages of low leakage, good retention characteristics, and low temperature fabrication. 2 It has great potential in DRAM applications. Where F is the feature size at the process node.

[0047] Schematically, as shown in FIG3 , in the memory cell C1, the gates of the first floating-gate transistor T1 and the second floating-gate transistor T2 can be connected to a word line WL, and the drains of the first floating-gate transistor T1 and the second floating-gate transistor T2 can be connected to a plate line PL. The sources of the first floating-gate transistor T1 and the second floating-gate transistor T2 are connected to a differential sensing amplifier 100 via different bit lines BL.

[0048] In this way, when writing data to memory cell C1, data can be written by writing "0" and "1" into the two transistors (T1, T2), respectively. For details, please refer to the following description. When reading data from memory, the differential sense amplifier 100 can compare the read currents of the two transistors (T1, T2). Based on the magnitude of the read currents of the two transistors (T1, T2), the data stored in memory cell C1 can be obtained.

[0049] Referring to Figures 2 and 4, compared to the existing current sense margin that is only equivalent to half of the current difference between the maximum read current of the transistor in the "0" state and the minimum read current in the "1" state, the present application is based on a differential 2T structure and does not need to set a reference current Iref. When reading the stored data, the storage data in the memory cell C1 can be obtained by directly comparing the magnitudes of the read currents of the two transistors (T1, T2).

[0050] That is to say, the current sense margin of the present application is approximately the difference between the maximum sense current of the transistor's "0" state and the minimum sense current of the "1" state, which is equivalent to twice the existing current sense margin, with a significant improvement, thereby greatly improving the reliability and stability of the read operation.

[0051] In the present application, for the write operation of the memory cell C1 using a differential 2T structure, the data written into the memory cell C1 can be defined by writing “1” and “0” into the first floating gate transistor T1 and the second floating gate transistor T2 respectively.

[0052] For example, in some possible implementations, if "1" is written in the first floating gate transistor T1 and "0" is written in the second floating gate transistor T2, the written data in the memory cell C1 is defined as "1"; and if "0" is written in the first floating gate transistor T1 and "1" is written in the second floating gate transistor T2, the written data in the memory cell C1 is defined as "0".

[0053] Schematically, the control process of writing a "1" or "0" into a floating-gate transistor is described using the first floating-gate transistor T1 as an example. Referring to FIG3 , when writing a "1" into the first floating-gate transistor T1, a high voltage can be applied to the gate of the first floating-gate transistor T1 via the word line WL, and low voltages (e.g., ground) can be applied to the drain and source of the first floating-gate transistor T1 via the plate line PL and the bit line BL0, respectively. In this case, electron tunneling occurs between the floating gate and the channel, causing a large number of electrons to enter the channel. When the voltage is removed, the electrons remain in the floating gate, and the written state is now 1. When writing a "0" into the first floating-gate transistor T1, a low voltage (e.g., ground) can be applied to the gate of the first floating-gate transistor T1 via the word line WL, and high voltages can be applied to the drain and source of the first floating-gate transistor T1 via the plate line PL and the bit line BL0, respectively. In this case, electrons tunnel from the floating gate through the oxide layer into the channel, causing electrons to be removed from the floating gate, and the written state is now 0.

[0054] Of course, in other possible implementation methods, "1" can be written in the first floating gate transistor T1 and "0" can be written in the second floating gate transistor T2, defining the written data in the storage cell C1 as "0"; while "0" can be written in the first floating gate transistor T1 and "1" can be written in the second floating gate transistor T2, defining the written data in the storage cell C1 as "1".

[0055] It should be understood that in the present application, although the threshold voltage (Vt) of the floating-gate OS CAA transistor (T1, T2) is easily drifted due to the high temperature of the subsequent process, resulting in an increase in the process deviation of the threshold voltage (Vt), the differential 2T memory cell based on the present application can well meet the reliability and stability of the read operation by greatly improving the current read margin (sense margin).

[0056] Furthermore, in this application, because the floating-gate OS CAA transistors (T1, T2) are integrated in the back-end-of-line (BEOL) process, the differential sense amplifier 100 can be integrated in the front-end-of-line (FEOL) process. Specifically, the differential sense amplifier 100 is fabricated directly on the substrate in the front-end-of-line (FEOL) process, and then the memory cell C1 is integrated above the differential sense amplifier 100 in the back-end-of-line (BEOL) process. This reduces the area overhead of the differential sense amplifier 100 and, in turn, improves storage density.

[0057] The following briefly describes the structure of the floating-gate OS CAA transistors ( T1 , T2 ) integrated in the back-end process.

[0058] Schematically, an embodiment of the present application provides a floating-gate OS CAA transistor, as shown in FIG5 . The floating-gate OS CAA transistor may include a silicon substrate 10 and a stacked structure 20 disposed on the silicon substrate 10 .

[0059] As shown in FIG5 , the stacked structure 20 includes a source layer S and a drain layer D. The source layer S is closer to the silicon substrate 10 than the drain layer D. The source layer S serves as the source of the floating-gate OS CAA transistor, while the drain layer D serves as the drain of the floating-gate OS CAA transistor. Of course, other layers, such as a dielectric layer, may be disposed between the source layer S and the drain layer D.

[0060] As shown in Figure 5, a first trench 200 is provided on the stacked structure 20, and the first trench 200 extends to the depth region where the source layer S is located. The gate G (gate), floating gate FG (floating gate), gate insulation layer 201, and channel layer 202 of the floating gate OS CAA transistor are provided in the first trench 200. The floating gate FG is provided around the gate G. The gate insulation layer 201 is filled between the gate G and the floating gate FG. The channel layer 202 covers the inner wall of the first trench 200 and connects the source layer S and the drain layer D. Of course, according to actual needs, some structures (such as the gate G) can extend to the outside of the first trench 200 to connect with other wirings.

[0061] In addition, the differential 2T structure memory cell used in this application can be differentiated in a single memory array or in two memory arrays. The following describes the two array integration methods through specific embodiments.

[0062] Example 1

[0063] Schematically, this embodiment 1 provides a storage device, as shown in FIG6 , which includes a storage array A1 (also referred to as a first storage array), and the storage unit C1 implements differential in the storage array A1 .

[0064] Schematically, as shown in FIG6 , the memory array A1 (Array) includes: a plurality of floating-gate transistors arranged in an array, a plurality of word lines (WL0, WL1, WL2, WL3), a plurality of plate lines (PL0, PL1, PL2, PL3), and a plurality of bit lines (BL0, BL1, BL2, BL3, BL4, BL5). Among the plurality of floating-gate transistors arranged in an array, the plurality of floating-gate transistors along the row direction may be first floating-gate transistors T1 and second floating-gate transistors T2 alternately arranged in sequence, and the adjacent first floating-gate transistors T1 and second floating-gate transistors T2 form a memory cell C1. Along the column direction, the plurality of floating-gate transistors T1 and T2 may all be first floating-gate transistors T1 or second floating-gate transistors T2. In this case, a plurality of memory cells C1 arranged in an array are formed in the memory array A1.

[0065] As shown in Reference 6, in the storage array A1:

[0066] The gates of floating-gate transistors (T1, T2) in different rows are connected to different word lines (WL0, WL1, WL2, WL3). For example, the gates of the floating-gate transistors (T1, T2) in the first row are connected to word line WL0, while the gates of the floating-gate transistors (T1, T2) in the second row are connected to word line WL1.

[0067] The drains of floating-gate transistors (T1, T2) in different rows are connected to different plate lines (PL0, PL1, PL2, PL3). For example, the drains of the floating-gate transistors (T1, T2) in the first row are connected to plate line PL0, while the drains of the floating-gate transistors (T1, T2) in the second row are connected to plate line PL1.

[0068] The sources of floating-gate transistors (T1, T2) in different columns are connected to different bit lines (BL0, BL1, BL2, BL3, BL4, BL5). For example, the sources of the plurality of first floating-gate transistors T1 in the first column are connected to the bit line BL0, and the drains of the plurality of second floating-gate transistors T2 in the second column are connected to the bit line BL1.

[0069] As shown in FIG6 , the two bit lines (BL0 and BL1, BL2 and BL3, BL4 and BL5) connected to the same column of memory cells C1 are connected to the same differential sense amplifier 100, while the bit lines connected to different memory cells C1 are connected to different differential sense amplifiers 100. For example, the two bit lines (BL0, BL1) connected to the first column of memory cells C1 are connected to one differential sense amplifier 100, while the two bit lines (BL2, BL3) connected to the second column of memory cells C1 are connected to another differential sense amplifier 100.

[0070] FIG7 is a cross-sectional schematic diagram of a storage device provided in the first embodiment.

[0071] 7 , in some possible implementations, for the storage device in the first embodiment, a front-end-of-line (FEOL) process may be used to fabricate a plurality of differential sense amplifiers 100 on a substrate. Subsequently, a back-end-of-line (BEOL) process may be used to form the aforementioned storage array A1 and related signal lines (word lines WL, plate lines PL, bit lines BL), etc., in the direction of the plurality of differential sense amplifiers 100.

[0072] Example 2

[0073] Schematically, this second embodiment provides a storage device, which includes a first storage array A1 and a second storage array A2, and a storage unit C1 is differentially implemented in the two storage arrays (A1, A2).

[0074] The following describes the configuration of the first storage array A1 and the second storage array A2 respectively.

[0075] Schematically, as shown in FIG8 , the first memory array A1 includes a plurality of first floating-gate transistors T1 arranged in an array, a plurality of word lines (WLL0, WLL1, WLL2, WLL3), a plurality of plate lines (PLL0, PLL1, PLL2, PLL3), and a plurality of bit lines (BLL0, BLL1, BLL2, BLL3, BLL4, BLL5).

[0076] In the first storage array A1:

[0077] The gates of the first floating-gate transistors T1 in different columns are connected to different word lines (WLL0, WLL1, WLL2, WLL3). For example, the gates of the first floating-gate transistors T1 in the first column are connected to the word line WLL0, and the gates of the first floating-gate transistors T1 in the second column are connected to the word line WLL1.

[0078] The drains of the first floating-gate transistors T1 in different columns are connected to different plate lines (PLL0, PLL1, PLL2, PLL3). For example, the drains of the first floating-gate transistors T1 in the first column are connected to the word line PLL0, and the drains of the first floating-gate transistors T1 in the second column are connected to the word line PLL1.

[0079] The sources of the first floating-gate transistors T1 in different rows are connected to different bit lines (BLL0, BLL1, BLL2, BLL3, BLL4, BLL5). For example, the sources of the first floating-gate transistors T1 in the first row are connected to the bit line BLL0, and the drains of the first floating-gate transistors T1 in the second row are connected to the bit line BLL1.

[0080] 8 , the second memory array A2 includes a plurality of second floating-gate transistors T2 arranged in an array, a plurality of word lines (WLR0, WLR1, WLR2, WLR3), a plurality of plate lines (PLR0, PLR1, PLR2, PLR3), and a plurality of bit lines (BLR0, BLR1, BLR2, BLR3, BLR4, BLR5).

[0081] In the first storage array A2:

[0082] The gates of the second floating-gate transistors T2 in different columns are connected to different word lines (WLR0, WLR1, WLR2, and WLR3). For example, the gates of the second floating-gate transistors T2 in the first column are connected to the word line WLR0, and the gates of the second floating-gate transistors T2 in the second column are connected to the word line WLR1.

[0083] The drains of the second floating-gate transistors T2 in different columns are connected to different plate lines (PLR0, PLR1, PLR2, PLR3). For example, the drains of the second floating-gate transistors T2 in the first column are connected to the word line PLR0, while the drains of the second floating-gate transistors T2 in the second column are connected to the word line PLR1.

[0084] The sources of the second floating-gate transistors T2 in different rows are connected to different bit lines (BLR0, BLR1, BLR2, BLR3, BLR4, and BLR5). For example, the sources of the second floating-gate transistors T2 in the first row are connected to the bit line BLR0, and the drains of the second floating-gate transistors T2 in the second row are connected to the bit line BLR1.

[0085] On this basis, as shown in FIG8 , two floating-gate transistors in corresponding positions in the first memory array A1 and the second memory array A2 can be used as the first floating-gate transistor T1 and the second floating-gate transistor T2 in the first memory cell C1, respectively. For example, the first floating-gate transistor T1 located in the first row and first column of the first memory array A1 and the second floating-gate transistor T2 located in the first row and first column of the second memory array A2 form a memory cell C1. The first floating-gate transistor T1 located in the first row and second column of the first memory array A1 and the second floating-gate transistor T2 located in the first row and second column of the second memory array A2 form a memory cell C1.

[0086] Of course, the two floating-gate transistors ( T1 , T2 ) in the memory cell C1 may also be distributed in non-corresponding positions in the two memory arrays ( A1 , A2 ), and this application does not impose any limitation on this.

[0087] In this case, as shown in FIG8 , the two bit lines connected to the two floating-gate transistors (T1, T2) in the same memory cell C1 should be connected to the same differential sense amplifier 100. For example, the bit line BLL0 connected to the first floating-gate transistor T1 in the first row and first column of the first memory array A1 and the bit line BLR0 connected to the second floating-gate transistor T2 in the first row and first column of the second memory array A2 are connected to the same differential sense amplifier 100. The bit line BLL1 connected to the first floating-gate transistor T1 in the second row and first column of the first memory array A1 and the bit line BLR1 connected to the second floating-gate transistor T2 in the second row and first column of the second memory array A2 are connected to the same differential sense amplifier 100.

[0088] In addition, in the second embodiment, the first storage array A1 and the second storage array A2 can be integrated in the same layer or in different layers. This application does not impose any restrictions on this, and they can be set as needed in practice.

[0089] For example, as shown in FIG9 , in some possible implementations, the first memory array A1 and the second memory array A2 can be integrated on the same layer. In this case, a front-end-of-line (FEOL) process can be used to fabricate multiple differential sense amplifiers 100 (only one is shown in FIG9 ) on a substrate. Subsequently, a back-end-of-line (BEOL) process can be used to fabricate the first and second memory arrays A1 and A2, arranged on the same layer, above the multiple differential sense amplifiers 100, along with associated signal lines (word lines WL, plate lines PL, bit lines BL).

[0090] For another example, as shown in FIG10 , in some possible implementations, the first memory array A1 and the second memory array A2 can be integrated on different layers, and the second memory array A2 can be located between the first memory array A1 and the differential sense amplifier 100. In this case, a front-end-of-line (FEOL) process can be used to fabricate multiple differential sense amplifiers 100 (only one is shown in FIG10 ) on a substrate. Subsequently, the second memory array A2 can be fabricated above the multiple differential sense amplifiers 100 in a back-end-of-line (BEOL) process, and then the first memory array A1 can be fabricated above the second memory array A2. Of course, the associated signal lines (word lines WL, plate lines PL, and bit lines BL) can also be fabricated in the back-end-of-line (BEOL) process.

[0091] It can be understood here that, compared to the first storage array A1 and the second storage array A2 being integrated in the same layer, the storage density can be further improved by arranging the first storage array A1 and the second storage array A2 in different layers.

[0092] Schematically, this second embodiment further provides a method for controlling read and write operations of a storage device as shown in FIG8 , which may be specifically as follows: (the floating-gate transistor marked with a dotted box represents a selected floating-gate transistor)

[0093] When writing "1":

[0094] As shown in FIG11 , in the first memory array A1, a high voltage (indicated as 1) is applied to the gate of the selected first floating-gate transistor T1 via word line WLL0, and a low voltage (indicated as 0) is applied to the source and drain of the selected first floating-gate transistor T1 via plate line PLL0 and bit line BLL0, which may be grounded. A high voltage (1) is input to the other unselected bit lines, and a low voltage (0) can be input to the other unselected word lines and plate lines. In this case, "1" is written into the selected first floating-gate transistor T1.

[0095] As shown in FIG11 , in the second memory array A2, a low voltage (0) is applied to the gate of the selected second floating-gate transistor T2 via word line WLR0, which may be grounded. A high voltage (1) is applied to the source and drain of the selected second floating-gate transistor T2 via plate line PLR0 and bit line BLR0. Low voltages (0) may be input to other unselected word lines, plate lines, and bit lines. In this case, "0" is written into the selected second floating-gate transistor T2.

[0096] The selected first floating gate transistor T1 and the selected second floating gate transistor T2 are two transistors in the selected memory cell C1. When "1" is written in the first floating gate transistor T1 and "0" is written in the second floating gate transistor T2, "1" is written in the selected memory cell C1.

[0097] When writing "1":

[0098] As shown in FIG12 , in the first memory array A1, a low voltage (0) is applied to the gate of the selected first floating-gate transistor T1 via word line WLL0, which may be grounded. A high voltage (1) is applied to the source and drain of the selected first floating-gate transistor T1 via plate line PLL0 and bit line BLL0. Low voltages (0) may be input to other unselected word lines, plate lines, and bit lines. In this case, "0" is written into the selected first floating-gate transistor T1.

[0099] As shown in FIG12 , in the second memory array A2, a high voltage (indicated as 1) is applied to the gate of the selected second floating-gate transistor T2 via word line WLR0, and a low voltage (indicated as 0) is applied to the source and drain of the selected second floating-gate transistor T2 via plate line PLR0 and bit line BLR0, which may be grounded. A high voltage (1) is input to the other unselected bit lines, and a low voltage (0) can be input to the other unselected word lines and plate lines. In this case, "1" is written into the selected second floating-gate transistor T2.

[0100] The selected first floating gate transistor T1 and the selected second floating gate transistor T2 are two transistors in the selected memory cell C1. When "0" is written in the first floating gate transistor T1 and "1" is written in the second floating gate transistor T2, "0" is written in the selected memory cell C1.

[0101] Of course, in other possible implementations, when "1" is written in the first floating-gate transistor T1 and "0" is written in the second floating-gate transistor T2 in the memory cell C1, the storage data written in the memory cell C1 is defined as "0"; and when "1" is written in the first floating-gate transistor T1 and "0" is written in the second floating-gate transistor T2, the storage data written in the selected memory cell C1 is defined as "1".

[0102] Referring to Figure 13, during a read operation:

[0103] A high voltage is applied to the gates of the selected first and second floating gate transistors T1 and T2 through word lines WLL0 and WLR0, respectively, and a read voltage is applied to the drains of the selected first and second floating gate transistors T1 and T2 through plate lines PLL0 and PLR0, respectively.

[0104] The source currents of the selected first floating-gate transistor T1 and the second floating-gate transistor T2 are read and amplified by the differential sense amplifier 100 .

[0105] The storage data in the selected memory cell C1 is determined according to the source currents of the selected first floating-gate transistor T1 and the second floating-gate transistor T2 .

[0106] Illustratively, in some possible implementations, if the source current of the selected first floating-gate transistor T1 is greater than the source current of the selected second floating-gate transistor T2, this means that the first floating-gate transistor T1 is "1" and the second floating-gate transistor T2 is "0." In this case, the data stored in the selected memory cell C1 can be determined to be "1." Correspondingly, if the source current of the selected first floating-gate transistor T1 is less than the source current of the selected second floating-gate transistor T2, this means that the first floating-gate transistor T1 is "0" and the second floating-gate transistor T2 is "1." In this case, the data stored in the selected memory cell C1 is determined to be "0."

[0107] Of course, in other possible implementations, if the source current of the selected first floating-gate transistor T1 is greater than the source current of the selected second floating-gate transistor T2, the data stored in the selected memory cell C1 can be determined to be "0"; and if the source current of the selected first floating-gate transistor T1 is less than the source current of the selected second floating-gate transistor T2, the data stored in the selected memory cell C1 can be determined to be "1". In practice, the design can be customized according to needs.

[0108] For the storage device using a single storage array in the first embodiment, the control method of its read and write operations is similar to that in the second embodiment, with the only difference being that data can be written to the two floating-gate transistors (T1, T2) in the selected storage cell C1 twice. For example, the first time, "1" is written to the first floating-gate transistor T1, and the second time, "0" is written to the second floating-gate transistor T2. For specific instructions, please refer to the corresponding part in the second embodiment and will not be repeated here.

[0109] It should be noted that the connection method of the source and drain of the transistors (T1, T2) involved in this application is only an example. In some cases, the source and drain of the transistors (T1, T2) involved in this application may not be clearly distinguished, so the corresponding connection relationship can also be interchanged.

[0110] It should also be noted that the "rows" and "columns" referred to in this application are merely relative directions, and this application does not impose any particular restrictions on this. In some cases, the "row" direction is horizontal and the "column" direction is vertical; in some cases, the "row" direction is vertical and the "column" direction is horizontal.

[0111] The above description is merely a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this application should be included in the scope of protection of this application. Therefore, the scope of protection of this application should be based on the scope of protection of the claims.

Claims

1. A storage device, characterized in that: It includes a first storage unit and a differential sensitive amplifier; The first storage unit includes a first floating gate transistor and a second floating gate transistor located in a back-end process; wherein the first floating gate transistor and the second floating gate transistor are oxide semiconductor ring channel field effect transistors; The source of the first floating gate transistor and the source of the second floating gate transistor are both connected to the differential sense amplifier, and the differential sense amplifier is located in the front-end process.

2. The storage device according to claim 1, characterized in that The storage device comprises a first storage array; The first memory array comprises: a plurality of floating gate transistors, a plurality of word lines, a plurality of plate lines, and a plurality of bit lines arranged in an array; In the first storage array, the gates of the floating gate transistors located in different rows are respectively connected to different word lines, the drains of the floating gate transistors located in different rows are respectively connected to different plate lines; the sources of the floating gate transistors located in different columns are respectively connected to different bit lines; Among the plurality of floating gate transistors arranged in the array, two adjacent floating gate transistors located in the same row serve as the first floating gate transistor and the second floating gate transistor in the first storage unit respectively, and the two bit lines connected to the first floating gate transistor and the second floating gate transistor are connected to the same differential sense amplifier; The first storage cells located in different columns are connected to different differential sense amplifiers through the bit lines.

3. The storage device according to claim 1, characterized in that: The storage device comprises: a first storage array and a second storage array arranged in the same layer; The first memory array and the second memory array both include: a plurality of floating gate transistors, a plurality of word lines, a plurality of plate lines, and a plurality of bit lines arranged in an array; In the first memory array and the second memory array: the gates of the plurality of floating gate transistors located in different columns are connected to different word lines, the drains of the plurality of floating gate transistors located in different columns are connected to different plate lines; the sources of the plurality of floating gate transistors located in different rows are connected to different bit lines; The two floating gate transistors at corresponding positions in the first storage array and the second storage array serve as the first floating gate transistor and the second floating gate transistor in the first storage unit respectively, and the two bit lines connected to the first floating gate transistor and the second floating gate transistor are connected to the same differential sense amplifier.

4. The storage device according to claim 3, characterized in that: The first storage array and the second storage array are located in the same layer.

5. The storage device according to claim 3, characterized in that: The first storage array and the second storage array are located in different layers.

6. The storage device according to any one of claims 1 to 5, characterized in that: The first floating gate transistor comprises: A stacked structure disposed on a silicon substrate, the stacked structure comprising a source layer and a drain layer, the source layer being closer to the silicon substrate than the drain layer; A first trench, wherein the first trench is disposed on the stacked structure and the first trench at least extends into the source layer; A gate, the gate being disposed in the first trench and extending to a depth where the source layer is located; A floating gate, wherein the floating gate is disposed in the first trench and surrounds the gate; a gate insulating layer, the gate insulating layer being located between the gate and the floating gate; A channel layer covers an inner wall of the first trench and connects the source layer and the drain layer.

7. A method for controlling a storage device according to any one of claims 1 to 6, characterized in that: include: When performing a write operation: Applying a high voltage to the gate of the selected first floating-gate transistor, and applying a low voltage to the source and drain; and applying a high voltage to the source and drain of the selected second floating-gate transistor, and applying a low voltage to the gate; Applying a high voltage to the source and drain of the selected first floating-gate transistor, and applying a low voltage to the gate; applying a high voltage to the gate of the selected second floating-gate transistor, and applying a low voltage to the source and drain; During a read operation: A high voltage is applied to the gates of the selected first floating-gate transistor and the second floating-gate transistor, and a high voltage is applied to the selected first floating-gate transistor. A read voltage is applied to the drains of the transistor and the second floating-gate transistor; amplifying the source current of the selected first floating-gate transistor and the second floating-gate transistor by the differential sense amplifier; Storage data in the selected first storage unit is determined according to the magnitude of the source current of the selected first floating-gate transistor and the selected second floating-gate transistor.

8. The control method of the storage device according to claim 7, characterized in that: The step of applying a high voltage to the gate of the selected first floating-gate transistor and applying a low voltage to the source and drain; and applying a high voltage to the source and drain of the selected second floating-gate transistor and applying a low voltage to the gate comprises: Applying a high voltage to the gate of the selected first floating-gate transistor and applying a low voltage to the source and drain to write "1" in the selected first floating-gate transistor; Applying a high voltage to the source and drain of the selected second floating-gate transistor and a low voltage to the gate to write "0" in the selected second floating-gate transistor; The storage data "1" is written into the selected first storage unit.

9. The control method of the storage device according to claim 7 or 8, characterized in that: The step of applying a high voltage to the source and drain of the selected first floating-gate transistor and applying a low voltage to the gate; and applying a high voltage to the gate of the selected second floating-gate transistor and applying a low voltage to the source and drain comprises: Applying a high voltage to the source and drain of the selected first floating-gate transistor and a low voltage to the gate to write "0" in the selected first floating-gate transistor; Applying a high voltage to the gate of the selected second floating-gate transistor and applying a low voltage to the source and drain to write "1" in the selected second floating-gate transistor; The storage data "0" is written into the selected first storage unit.

10. The control method of a storage device according to any one of claims 7 to 9, characterized in that: The step of determining the storage data in the selected first storage unit according to the source current magnitudes of the selected first floating-gate transistor and the selected second floating-gate transistor comprises: When the source current of the selected first floating-gate transistor is greater than the source current of the selected second floating-gate transistor, it is determined that the storage data in the selected first storage unit is "1"; When the source current of the selected first floating-gate transistor is smaller than the source current of the selected second floating-gate transistor, it is determined that the storage data in the selected first storage unit is “0”.

11. An electronic device, characterized in that: It comprises a circuit board and a storage device as claimed in any one of claims 1 to 6, wherein the storage device is electrically connected to the circuit board.

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