Package

Abstract

Disclosed in the present disclosure is a package, comprising a first bearing portion, a second bearing portion and a plurality of pins. The first bearing portion is provided with a first upper metal layer and a first lower metal layer, the first lower metal layer being connected to and overlapping the first upper metal layer, and corresponding to the first upper metal layer in terms of position. The second bearing portion is laterally separated from the first bearing portion, and is provided with a second metal layer. The plurality of pins are laterally separated from the first bearing portion and the second bearing portion; and in a top view, the ratio of the maximum length of the second metal layer to the maximum length of the package is greater than 2 / 3.

Description

Package Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a package body for packaging semiconductor elements. Background Art

[0002] With the increasing demand for high-electron-mobility devices in today's semiconductor industry, high-electron-mobility transistors (HEMTs) fabricated using III-V materials (such as gallium nitride) are gaining increasing attention, and as a result, their packaging methods are also gaining importance. HEMTs can be primarily categorized as enhancement-mode (E-Mode HEMT) and depletion-mode (D-Mode HEMT). Common HEMT packaging types include the transistor outline package (TO), dual flat no-lead package (DFN), and quad flat no-lead package (QFN).

[0003] The maximum gate-source voltage of a typical HEMT (e.g., a GaN transistor) can withstand is approximately -10V to 7V. To prevent the maximum external drive voltage from being directly applied to the HEMT and potentially damaging the device, a protection element is often placed between the HEMT package and the drive voltage to ensure normal operation of the HEMT.

[0004] However, additional protection components require additional space for circuit layout on the circuit board and increase the complexity of the overall circuit design. Therefore, it is necessary to propose a package that integrates the high electron mobility transistor and its protection components to overcome the above technical deficiencies.

[0005] Summary of the Invention

[0006] In view of this, the present disclosure provides a package that can integrate a high electron mobility transistor and a protection element thereof to improve the deficiencies of the prior art.

[0007] To achieve this objective, the present disclosure discloses a package comprising a first carrier portion, a second carrier portion, and a plurality of pins. The first carrier portion comprises a first upper metal layer and a first lower metal layer, the first lower metal layer being connected to and overlapping the first upper metal layer and corresponding to the position of the first upper metal layer. The second carrier portion is laterally separated from the first carrier portion, and the second carrier portion comprises a second metal layer. The plurality of pins are laterally separated from the first carrier portion and the second carrier portion, wherein, in a top view, the ratio of the maximum length of the second metal layer to the maximum length of the package is greater than 2 / 3. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] To facilitate understanding of the following, the present disclosure may be read with reference to the accompanying drawings and their detailed descriptions. The present disclosure is described in detail through the specific embodiments herein and with reference to the corresponding drawings, thereby illustrating the specific embodiments of the present disclosure and illustrating the working principles of the specific embodiments of the present disclosure. Furthermore, for the sake of clarity, the features in the drawings may not be drawn to scale, and therefore the dimensions of some features in some drawings may be intentionally exaggerated or reduced.

[0009] FIG. 1 is a top view of the front and back surfaces of a package according to an embodiment of the present disclosure.

[0010] FIG. 2 is a top view of the front side of a package according to another embodiment of the present disclosure.

[0011] FIG. 3 is a top view of the front and back surfaces of a package body according to an embodiment of the present disclosure.

[0012] FIG. 4 is a front plan view and cross-sectional views corresponding to multiple cutting lines of a package body according to an embodiment of the present disclosure.

[0013] FIG5 is a cross-sectional view of a package body according to an embodiment of the present disclosure.

[0014] 6A and 6B are respectively front plan views of a package body including a stacked structure according to an embodiment of the present disclosure.

[0015] FIG. 7 is a circuit diagram of a package including a stacked structure according to the present disclosure.

[0016] 8A and 8B are respectively front plan views of a package including an enhanced high electron mobility transistor according to an embodiment of the present disclosure.

[0017] FIG. 9 is a circuit diagram of a package including an enhanced high electron mobility transistor according to the present disclosure.

[0018] [Description of symbols] 1, 2, 3, 4: Package body 1A, 2A, 3A, 4A: Front view 1B: Back view 10, 10': First carrier 11: Recessed portion 12, 12': First side 13: Molded structure 13A: Upper molded structure 13B: Lower molded structure 14, 14': Second side 16: Protrusion 20, 20': Second carrier 21: Branch 22: Protrusion 30: Pin 30P, 30P': Protrusion 31: First group of pins 32: Second group of pins 40: Depletion mode high electron mobility transistor 50: Field effect transistor 60: Enhanced mode high electron mobility transistor Mobility transistor 70: resistor 81: first Zener diode 82: second Zener diode 90: capacitor 110: first upper metal layer 120: first lower metal layer 210: second metal layer 310: third upper metal layer 320: third lower metal layer 410: fourth upper metal layer 420: fourth lower metal layer 510: fifth upper metal layer 520: fifth lower metal layer 710: source terminal 712: drain terminal 714: gate terminal A1, A2, A3, A4, A5: front area A-A', B-B', C-C', D-D', E-E': section line D: drain D A , D B :Distance D1 - 、D2 - : cathode D1 + 、D2 + : Anode G: Gate K: Metal lines L, L2, L3, L4, L5, L6: Length S: Source W, W1: Width DETAILED DESCRIPTION

[0019] The present disclosure provides several different embodiments that can be used to implement different features of the present disclosure. For the sake of simplicity of description, the present disclosure also describes examples of specific components and arrangements. The purpose of providing these embodiments is only for illustration and not for limitation. For example, the description below of "a first feature is formed on or above a second feature" may mean "the first feature is in direct contact with the second feature" or "there are other features between the first feature and the second feature", so that the first feature and the second feature are not in direct contact. In addition, various embodiments in the present disclosure may use repeated reference symbols and / or text annotations. The use of these repeated reference symbols and annotations is to make the description more concise and clear, rather than to indicate the relationship between different embodiments and / or configurations.

[0020] Furthermore, when spatially relative terms such as "below," "lower," "below," "above," "upper," "down," "top," "bottom," and similar terms are used throughout this disclosure to describe the relative relationship of one element or feature to another element or feature in the accompanying drawings for ease of description. In addition to the orientations shown in the accompanying drawings, these spatially relative terms are also used to describe possible orientations of semiconductor components during use and operation. Spatially relative terms used to describe different orientations of the semiconductor component (rotated 90 degrees or in other positions) should be interpreted in a similar manner.

[0021] Although the present disclosure uses terms such as first, second, and third to describe various elements, components, regions, layers, and / or sections, it should be understood that these elements, components, regions, layers, and / or sections should not be limited by these terms. These terms are merely used to distinguish a certain element, component, region, layer, and / or section from another element, component, region, layer, and / or section, and do not themselves represent any preceding ordinal number for the element, nor do they represent the order in which a certain element is arranged relative to another element, or the order in which a manufacturing method is used. Therefore, without departing from the scope of the specific embodiments of the present disclosure, the first element, component, region, layer, or section discussed below may also be described by the term second element, component, region, layer, or section.

[0022] The terms "about" or "substantially" mentioned in this disclosure generally mean within 20%, preferably within 10%, and more preferably within 5%, or within 3%, or within 2%, or within 1%, or within 0.5% of a given value or range. It should be noted that the quantities provided in the specification are approximate quantities, that is, even if "about" or "substantially" is not specifically stated, the meaning of "about" or "substantially" may still be implied.

[0023] Although the invention disclosed herein is described below with reference to specific embodiments, the principles of the invention disclosed herein may also be applied to other embodiments. In addition, in order not to obscure the spirit of the invention, certain details may be omitted, and these omitted details belong to the knowledge scope of those skilled in the art.

[0024] FIG1 is a front plan view and a back plan view of a package body according to an embodiment of the present disclosure, wherein the left side of FIG1 is a front plan view 1A of the package body 1, and the right side of FIG1 is a back plan view 1B of the package body 1. Referring to FIG1 , the package body 1 at least includes a first carrier portion 10, a second carrier portion 20 laterally separated from the first carrier portion 10, and a plurality of pins 30 laterally separated from the first carrier portion 10 and the second carrier portion 20. The first carrier portion 10, the second carrier portion 20, and the plurality of pins 30 can be separated from each other along a certain direction (for example, the Y-axis direction) without direct contact. According to one embodiment, there may be an additional molded structure 13 that covers the front of the first carrier portion 10, the front of the second carrier portion 20, and the front of the plurality of pins 30.

[0025] Referring simultaneously to the front view 1A and the back view 1B of the package body 1, the first carrier portion 10 includes a first upper metal layer 110 and a first lower metal layer 120. The first lower metal layer 120 is electrically connected to the first upper metal layer 110. According to one embodiment, the first lower metal layer 120 and the first upper metal layer 110 may be directly connected and overlapped, and correspond to the position of the first upper metal layer 110. According to another embodiment, there may be an additional connection portion between the first upper metal layer 110 and the first lower metal layer 120, the connection portion connecting the first upper metal layer 110 and the first lower metal layer 120. The front surface of the first upper metal layer 110 can be used to dispose semiconductor devices or electronic devices, such as transistors, diodes, resistors, or capacitors. The back surface of the first lower metal layer 120 can be used for external electrical connection or heat dissipation, etc., which will be described in detail later. The back surface area of ​​the first lower metal layer 120 can be smaller than the front surface area of ​​the first upper metal layer 110. According to one embodiment, when the package 1 includes the molding structure 13, the back surface of the first lower metal layer 120 is exposed outside the molding structure 13, but the front surface of the first upper metal layer 110 is covered by the molding structure 13. According to one embodiment, the front and back surfaces of the first upper metal layer 110 are covered by the molding structure 13, while the front surface of the first lower metal layer 120 is covered by the molding structure 13 and the back surface is exposed outside the molding structure 13.

[0026] The second carrier part 20 includes a second metal layer 210. The front of the second metal layer 210 can be used to set semiconductor elements or electronic elements, such as transistors, diodes, resistors or capacitors. When the package body 1 includes a molded structure 13, the front and back of the second metal layer 210 will be covered by the molded structure 13 as a whole, and the back will not be exposed outside the molded structure 13. In addition to being used to carry semiconductor elements or electronic elements, the first upper metal layer 110 of the first carrier part 10 and the second metal layer 210 of the second carrier part 20 can also be used as the terminal fixing position of the wire for wire bonding. Therefore, the area size of the first upper metal layer 110 and the second metal layer 210 must be sufficient to meet the above requirements. According to one embodiment, in order to meet the layout differences between components caused by different circuit requirements in the package body 1, the first upper metal layer 110 and the second metal layer 210 must meet specific size requirements. Taking the second metal layer 210 as an example, the size ratio between the second metal layer 210 and the package body 1 can be greater than a certain value. For example, the ratio of the maximum length L2 of the second metal layer 210 to the maximum length L of the package body 1 is greater than 2 / 3. In this disclosure, the length of each component refers to the dimension parallel to the X-axis, and the width of each component refers to the dimension parallel to the Y-axis. Therefore, the length and width of each component are not distinguished based on their relative sizes.

[0027] In one embodiment, the plurality of pins 30 can be used for internal and external electrical connections. The plurality of pins 30 can be grouped, for example, into a first group of pins 31 and a second group of pins 32 disposed opposite each other along the Y-axis. The first group of pins 31 is located on one side of the package 1, while the second group of pins 32 is located on the opposite side of the package 1. When the package 1 includes a molded structure 13, the back surfaces of the pins 30 are exposed outside the molded structure 13.

[0028] The first group of pins 31 may include an upper metal layer extending along the X-axis, such as a fifth upper metal layer 510 and at least one fifth lower metal layer 520 (e.g., four laterally separated fifth lower metal layers 520). The fifth upper metal layer 510 may be used for wire bonding to internal components of the package 1. The fifth lower metal layer 520 may be used for external electrical connection. When the package 1 includes a molded structure 13, the front surface of the fifth upper metal layer 510 will be covered by the molded structure 13 and will not be exposed outside the molded structure 13. However, the back surface of the fifth lower metal layer 520 will be exposed outside the molded structure 13.

[0029] According to one embodiment, the second group of pins 32 may include a third upper metal layer 310, a third lower metal layer 320, at least one fourth upper metal layer 410, and at least one fourth lower metal layer 420 (e.g., two fourth upper metal layers 410 and two fourth lower metal layers 420). The third upper metal layer 310 and the two fourth upper metal layers 410 are located on the same side of the package 1. The fourth upper metal layers 410 are separated from each other and may be located on either side of the third upper metal layer 310. The third lower metal layer 320 and the fourth lower metal layer 420 may correspond to and overlap the third upper metal layer 310 and the fourth upper metal layer 410, respectively. According to one embodiment, the number of the fifth upper metal layer 510, the fifth lower metal layer 520, the third upper metal layer 310, or the third lower metal layer 320 is not limited to one, but may be multiple. The number of the fifth upper metal layers 510 and the fifth lower metal layers 520 may be one-to-many, many-to-one, or a many-to-many overlapping arrangement.

[0030] According to one embodiment, for the package body 1 of Figure 1, its process can be exemplified as including the following steps. First, a metal sheet is obtained. The composition of the metal sheet may include materials such as silver, copper, iron, iron-nickel alloy or copper alloy, and the surface may include an electroplating layer, such as a silver layer. Then, the metal sheet is subjected to a patterning process. The patterning method includes performing a stamping process on the metal sheet to form multiple parts. The patterning process may also include an etching process to form the first carrier part 10, the second carrier part 20, and the wire bracket of the multiple pins 30. In the etching process, the metal sheets of multiple parts can be etched to form upper and lower layers of different sizes or shapes connected up and down, forming the upper and lower metal layers of the first carrier part 10 and the multiple pins 30. In the etching step of forming the second carrier part 20, the lower part of the metal sheet is removed by etching to reduce the thickness of the metal sheet in this area to form the second metal layer 210 of the second carrier part 20. Electronic components are then sequentially placed on the first carrier portion 10, the second carrier portion 20, and / or the leads 30, followed by a molded structure covering the lead frame and electronic components. Finally, the leads protruding from the molded structure are trimmed to obtain the structure shown in Figure 1. In this embodiment, the upper and lower metal layers between the first carrier portion 10 and the plurality of leads 30 are formed integrally with patterned metal sheets of the same material. Of course, the formation of the upper and lower metal layers in this application is not limited to this method; the upper and lower metal sheets can also be composed of different materials.

[0031] 1 , in one embodiment, the ratio of the maximum width W1 of the first upper metal layer 110 to the maximum width W of the package body 1 is between 30% and 50%, so as to facilitate the design of the package body and the carrying of electronic components. According to one embodiment, the first carrier portion 10 is located between the first group of pins 31 and the second carrier portion 20, and the second carrier portion 20 is located between the first carrier portion 10 and the second group of pins 32. According to one embodiment, when a high electron mobility transistor is provided on the front side of the first carrier portion 10, since the first group of pins 31 can be configured to be electrically connected to a high potential, such as a drain potential, and the second group of pins 32 can be configured to be electrically connected to a low potential, such as a source potential or a gate potential, in order to meet the withstand voltage requirements of the package body 1, the shortest distance D between the first group of pins 31 and the first carrier portion 10 is greater than or equal to 0. A is greater than the shortest distance D between the second set of pins 32 and the first carrier portion 10 B .

[0032] The front plan view shape of the first carrier part 10 and the second carrier part 20 is not limited to the shape shown in Figure 1, but can also be adjusted according to actual needs. Referring to Figure 2, it is a front plan view 2A of the package body 2 of another embodiment of the present disclosure. The difference between the package body 2 and the package body 1 is that the second carrier part 20' may have a branch part 21, and the branch part 21 extends toward the first carrier part 10' along the Y-axis direction. The corresponding part of the first carrier part 10' will be recessed to form a recessed part 11 to accommodate the branch part 21. The second carrier part 20' and the first carrier part 10' are separated from each other and are not directly electrically connected. In other embodiments, the number of branches 21 and recessed parts 11 is not limited to one, but can be multiple, depending on actual needs.

[0033] In one embodiment, referring to FIG. 3 , the package body 1 further includes two first side edges 12 , 12 ′ disposed opposite to each other in the Y-axis direction, and two second side edges 14 , 14 ′ disposed opposite to each other in the X-axis direction, wherein one end of each second side edge 14 , 14 ′ is adjacent to the first side edge 12 , and the other end is adjacent to the first side edge 12 ′.

[0034] According to one embodiment, referring to FIG. 3 , in a top view 1A of the front side of the package 1 and in conjunction with a top view 1B of the back side, the third upper metal layer 310 and the fourth upper metal layer 410 of the second set of pins 32 are separated from each other, allowing them to be configured to transmit different electrical signals. Alternatively, through wire bonding, the third upper metal layer 310 and a fourth upper metal layer 410 can be configured to transmit the same electrical signal or have the same potential. The third upper metal layer 310 and the fourth upper metal layer 410 are located on the same side of the package 1, such as the first side 12. The two fourth upper metal layers 410 can be separated from each other and located on either side of the third upper metal layer 310. The maximum length L3 of the third upper metal layer 310 is at least twice the maximum length L4 of each fourth upper metal layer 410.

[0035] According to one embodiment, when looking down at the front side 1A of the package body 1, in addition to including a third upper metal layer 310 and a fourth upper metal layer 410 located on the same side (i.e., located on the first side 12), the plurality of pins 30 may further include a fifth upper metal layer 510 located on the opposite side of the third upper metal layer 310 and the two fourth upper metal layers 410 (i.e., located on the first side 12').

[0036] Referring to the back view 1B of Figure 3 and the front view 1A, the third lower metal layer 320 and the fourth lower metal layer 420 correspond to and overlap with the third upper metal layer 310 and the fourth upper metal layer 410 respectively, and the maximum length L5 of the third lower metal layer 320 can be more than twice the maximum length L6 of each fourth lower metal layer 420.

[0037] According to one embodiment, referring to the front top view 1A of Figure 3, the first carrier part 10 is mainly used to carry electronic components with larger top view dimensions, such as high electron mobility transistors. Depending on the application requirements, the package body 1 may include other electronic components, which are arranged on the second carrier part 20. Considering that the front top view area of ​​the second carrier part 20 is smaller than that of the first carrier part 10, the second carrier part 20 can be used to carry electronic components with top view dimensions smaller than high electron mobility transistors, such as low voltage field effect transistors, diodes, resistors and / or capacitors. The upper metal layer of multiple pins 30 can be used as welding points for welding wires or direct welding points for specific end points of electronic components. In order to meet the above requirements, the front area A1 of the first upper metal layer 110 will be larger than the front area A2 of the second metal layer 210, and the front area A2 of the second metal layer 210 will also be larger than the front area of ​​at least one of the multiple pins 30. For example, the front surface area A2 of the second metal layer 210 may be greater than the front surface area A3 of the third upper metal layer 310, greater than the front surface area A4 of the fourth upper metal layer 410, and / or greater than the front surface area A5 of the fifth upper metal layer 510. Because the third upper metal layer 310 and the fourth upper metal layer 410 primarily serve as bonding points for wire bonds or direct bonding points for specific terminals of electronic components, their respective front surface areas may be smaller than the front surface areas of the first and second carrier portions 10 and 20. According to one embodiment, the sum of the front surface areas A3 of the third upper metal layer 310 and A4 of the fourth upper metal layer 410 of the second group of pins 32 is smaller than the front surface area A2 of the second metal layer 210. In addition to the above, the shapes of the third upper metal layer 310 and the fourth upper metal layer 410 may be adjusted according to actual needs.

[0038] FIG4 is a front view and cross-sectional views corresponding to various tangent lines of the package 1. The front view 1A is substantially identical to the front view 1A shown in FIG1 , while the cross-sectional views AA' to EE' correspond to the sectional lines AA' to EE' in the front view 1A.

[0039] Referring to cross-section AA' in Figure 4 , the first upper metal layer 110 of the first carrier portion 10 has a greater width in the Y-axis direction than the first lower metal layer 120, and the fourth upper metal layer 410 has a greater width in the Y-axis direction than the fourth lower metal layer 420. Furthermore, the back surface of the second metal layer 210 is higher than the back surface of the first lower metal layer 120. Referring to cross-section BB' in Figure 4 , the back surface of the fifth upper metal layer 510 is higher than the back surface of the first lower metal layer 120. Referring to cross-section C-C' and the front plan view 1A in Figure 4 , the fifth upper metal layer 510 and the fifth lower metal layer 520 extend in the Y-axis direction to the first side 12', forming the lead 30 located on the first side 12'. The portion of the fifth upper metal layer 510 and the fifth lower metal layer 520 that protrudes toward the first side 12' constitutes the protrusion 30P' of the lead 30, and one edge of the protrusion 30P' may be flush with the first side 12'. The third upper metal layer 310 and the third lower metal layer 320 extend in the Y-axis direction to the first side 12 to form the lead 30 located on the first side 12. The portion of the third upper metal layer 310 and the third lower metal layer 320 that protrudes toward the first side 12 may constitute a protrusion 30P of the lead 30, and an edge of the protrusion 30P may be flush with the first side 12.

[0040] Referring to cross-section DD' in Figure 4 , two protrusions 16 are formed at opposite ends of the first upper metal layer 110 of the first carrier portion 10. These protrusions extend in the X-axis direction toward the second side edges 14 and 14', respectively, and are aligned with the two second side edges 14 and 14', respectively. Referring to cross-section EE' in Figure 4 , the second carrier portion 20 includes two protrusions 22, extending from opposite end regions of the second metal layer 210 in the X-axis direction toward the two second side edges 14 and 14', respectively, and are aligned with the two second side edges 14 and 14', respectively. Regarding the protrusions 16 and 22 shown in cross-sections DD' and EE', during the fabrication process, the corresponding portions of the lead frame are half-etched to reduce the thickness of the protrusions 16 and 22. Furthermore, before forming the molded structure 13, the protrusions 16 and 22 can serve as part of the support structure, allowing the first and second carrier portions 10 and 20 to be supported by the outer frame of the lead frame via the support structure. After the molded structure 13 is formed, the support structure protruding from the molded structure 13 is cut and trimmed to form protrusions 16 and 22 .

[0041] FIG5 is a cross-sectional view of a package body according to an embodiment of the present disclosure, which roughly corresponds to the cross-sectional view B-B' of FIG4 . According to one embodiment, as shown in FIG5 , the package body 1 may further include a plurality of electronic components and bonding wires, such as electronic components including a high electron mobility transistor 40, a field effect transistor 50, and a resistor 70, and a plurality of conductive connecting wires K. In addition, the molded structure 13 may also include an upper molded structure 13A and a lower molded structure 13B formed integrally. The upper molded structure 13A completely covers the front surface of the first upper metal layer 110 of the first carrier part 10, the front surface of the second metal layer 210 of the second carrier part 20, the upper metal layers 310 and 510 of the plurality of pins 30, the high electron mobility transistor 40, the field effect transistor 50, and the resistor 70, and covers the conductive connecting wires K. The lower molded structure 13B covers the backside of the second metal layer 210 and the backside of the fifth metal layer 510 of the second carrier portion 20, filling the entire backside of the second metal layer 210 of the second carrier portion 20 and the backsides of the first lower metal layer 120 and the third lower metal layer 320. In contrast, because the first lower metal layer 120 of the first carrier portion 10 and the third lower metal layer 320 of the pins 30 are configured to electrically connect to external circuits, the backsides of the first lower metal layer 120 and the third lower metal layer 320 are exposed outside the lower molded structure 13B. When the thickness of the lower molded structure 13B is less than that of the first lower metal layer 120 and the third lower metal layer 320, the backsides and portions of the side surfaces of the first lower metal layer 120 and the third lower metal layer 320 are exposed outside the lower molded structure 13B.

[0042] According to one embodiment, before forming the molded structure 13, a wire bonding process is performed to electrically connect the electronic components disposed on the first carrier portion 10, the second carrier portion 20, and the leads 30. For example, a wire bonding machine can be used to solder one end of at least one conductive wire K to the electronic component and the other end to the metal layer of the first carrier portion 10, the second carrier portion 20, or the leads 30. The conductive wire K can be made of a conductive material such as gold or copper. After the wire bonding process, a molding material is heated and injected into a mold using transfer molding to cover the first carrier portion 10, the second carrier portion 20, the plurality of leads 30, and the electronic components, thereby forming the molded structure 13. The encapsulation material can be primarily composed of epoxy resin or other suitable polymers.

[0043] The package disclosed herein can be applied to a dual flat no-lead package for packaging a high electron mobility transistor (HEMT). The HEMT can be an enhancement-mode HEMT (E-HEMT) or a depletion-mode HEMT (D-HEMT), wherein the E-HEMT or D-HEMT can be a GaN-based HEMT or other suitable III-V semiconductor HEMT.

[0044] Refer to Figures 6A, 6B, and 7. Figure 6A is a front view of a package 3 in a cascode structure. Figure 7 is an example circuit diagram corresponding to package 3. Package 3 differs from package 1 in that it also includes a depletion-mode high-electron-mobility transistor 40, a field-effect transistor 50, and a resistor 70. The depletion-mode high-electron-mobility transistor 40 is disposed on the first upper metal layer 110 and has a source, a gate, and a drain. The source is electrically connected to the second metal layer 210 via a bonding wire, the gate is electrically connected to the field-effect transistor 50 via a bonding wire, and the drain is electrically connected to the fifth upper metal layer 510 via a bonding wire. The field-effect transistor 50 is disposed on the second metal layer 210 and has a source, a gate, and a drain. The source of the field-effect transistor 50 is electrically connected to the gate of the depletion-mode high-electron-mobility transistor 40 and the third upper metal layer 310 via different bonding wires, respectively. The gate of the field-effect transistor 50 is electrically connected to the fourth upper metal layer 410 adjacent to the second side 14'. The resistor 70 is disposed adjacent to the second side 14 , and two ends of the resistor 70 are respectively connected across the second metal layer 210 and the fourth upper metal layer 410 adjacent to the second side 14 .

[0045] According to one embodiment, to accommodate various applications, the multiple pins 30 of the disclosed D-HEMT package may include two non-adjacent fourth upper metal layers 410, one located on either side of the third upper metal layer 310. Consequently, electronic component placement is less restricted by the pin locations, increasing the flexibility of electronic component layout. For example, in another embodiment, referring to FIG. 6B , the electronic component configuration of FIG. 6B is similar to that of FIG. 6A , with the primary difference being that the field-effect transistor 50 is disposed adjacent to the second side 14 , and its gate is electrically connected to the fourth upper metal layer 410 adjacent to the second side 14 via a bonding wire. Furthermore, the resistor 70 is disposed adjacent to the second side 14 ′, with its two terminals respectively connecting across the second metal layer 210 and the fourth upper metal layer 410 adjacent to the second side 14 ′.

[0046] FIG7 illustrates a corresponding circuit diagram for the structure shown in FIG6A and FIG6B . Referring to FIG7 , the drain D of the depletion-mode high electron mobility transistor 40 is electrically connected to the drain terminal 712 of the package 1. The gate G of the depletion-mode high electron mobility transistor 40 is electrically connected to the source S of the field-effect transistor 50 and one end of the resistor 70. The source S of the field-effect transistor 50 is also electrically connected to the source terminal 710 of the package 1. The source S of the depletion-mode high electron mobility transistor 40 is electrically connected to the drain D of the field-effect transistor 50 and the other end of the resistor 70. The gate G of the field-effect transistor 50 is electrically connected to the gate terminal 714 of the package 1. By integrating the two electronic components, the depletion-mode high-electron-mobility transistor 40 and the field-effect transistor 50, into the package 3, the space occupied by the wiring of the individual components on the circuit board can be reduced. Furthermore, the package 3 directly integrates the stacked depletion-mode high-electron-mobility transistor 40 and the field-effect transistor 50 therein, allowing users to directly utilize the package 3 to achieve the functionality of an E-mode HEMT without the need for external electronic components.

[0047] Referring to Figure 8A , a front view 4A of a package 4 for an enhancement mode high electron mobility transistor (EMHMT) is shown. Package 4 includes an EMHMT 60, a first Zener diode 81, a second Zener diode 82, a resistor 70, and a capacitor 90. EMHMT 60 is disposed on a first upper metal layer 110 and has a source, a gate, and a drain. Its source is electrically connected to the third upper metal layer 310 via a bonding wire, its gate is electrically connected to the second metal layer 210 via a bonding wire, and its drain is electrically connected to the fifth upper metal layer 510 via a bonding wire. First Zener diode 81 is disposed on the second metal layer 210, with its cathode electrically connected to the second metal layer 210. Second Zener diode 82 is disposed on the first upper metal layer 110, with its cathode electrically connected to the first upper metal layer 110. The anode of first Zener diode 81 can be further electrically connected to the anode of second Zener diode 82. The package body 4 further includes an RC circuit for filtering. For example, a resistor 70 and a capacitor 90 may be connected across the second metal layer 210 and the fourth upper metal layer 410 respectively.

[0048] Since the maximum gate-source voltage of an enhancement-mode high-electron-mobility transistor (EMHMT), such as an EM GaN transistor, can withstand is approximately -10V to 7V, the typical power conversion control circuit outputs a drive voltage of approximately 0V to 20V. Directly applying the maximum external drive voltage to the EMHMT can easily damage the EMHMT. Therefore, a protection circuit is often provided between the EMHMT and the drive voltage to ensure normal operation of the EMHMT. In this embodiment, the EMHMT 60 and the electronic components of the protection circuit are integrated into the package 4, which can reduce the space occupied by the individual component traces on the circuit board. According to one embodiment, when the drive voltage of a drive signal exceeds the normal operating voltage range of the EMHMT 60, the first Zener diode 81, the second Zener diode 82, the resistor 70, and the capacitor 90 are used to protect the EMHMT 60 from burnout and maintain normal operation of the EMHMT 60. In other words, the first Zener diode 81 , the second Zener diode 82 , the resistor 70 and the capacitor 90 may serve as a protection circuit for the enhanced high electron mobility transistor 60 .

[0049] According to one embodiment, to accommodate various applications, the multiple pins 30 of the disclosed E-HEMT package may include two non-adjacent fourth upper metal layers 410, each located on either side of the third upper metal layer 310. Consequently, the placement of the electronic component is less restricted by the location of the pins, increasing the flexibility of the electronic component layout. For example, in another embodiment, referring to FIG8B , the electronic component configuration of FIG8B is similar to that of FIG8A , with the primary difference being that the gate of the enhancement-mode high-electron-mobility transistor 60 is electrically connected to the fourth upper metal layer 410 adjacent to the second side 14′ via a bonding wire. Furthermore, the two ends of the resistor 70 and the two ends of the capacitor 90 are connected across the second metal layer 210 and the fourth upper metal layer 410 adjacent to the second side 14, respectively.

[0050] 8A and 8B, the corresponding circuit is shown in FIG9. Referring to FIG9, the drain D of the enhanced high electron mobility transistor 60 is electrically connected to the drain terminal 712 of the package 4, and the source S thereof is connected to the cathode D2 of the second Zener diode 82. - The source terminal 710 of the package body 4 is electrically connected to the gate G thereof and the cathode D1 of the first Zener diode 81. - The first Zener diode 81 and the second Zener diode 82 are connected in series in reverse order, so that the anode D1 of the first Zener diode 81 is connected to the gate terminal 714 of the package body 4. + The anode D2 of the second Zener diode 82 is electrically connected to+ The package 4 including the enhanced high electron mobility transistor 60 can be further electrically connected to an external circuit, for example, the external circuit including a resistor and a diode can be electrically connected via the gate terminal 714 of the package 4 .

[0051] The packages 1 , 2 , 3 , and 4 disclosed above can be used in package types such as DFN or QFN.

[0052] Although the embodiments of the present disclosure and their advantages have been described in detail, it should be understood that various changes, substitutions, and modifications may be made to the present disclosure without departing from the spirit of the present disclosure and the scope defined by the claims. The described embodiments are for illustrative purposes only and are not intended to limit the present disclosure in all respects. The scope of protection of the present disclosure shall be as defined by the appended claims. Those skilled in the art will make minor changes and modifications without departing from the spirit and scope of the present disclosure.

[0053] The above descriptions are merely preferred embodiments of the present disclosure, and all equivalent changes and modifications made in accordance with the claims of the present disclosure should fall within the scope of the present disclosure.

Claims

1. A package comprising: A first carrying portion, the first carrying portion comprising a first upper metal layer and a first lower metal layer, the first lower metal layer is connected to and overlaps the first upper metal layer and corresponds to the position of the first upper metal layer; A second bearing portion, laterally separated from the first bearing portion, the second bearing portion comprising a second metal layer; as well as A plurality of pins are laterally separated from the first carrying portion and the second carrying portion, Wherein, in the top view, the ratio of the maximum length of the second metal layer to the maximum length of the package body is greater than 2 / 3.

2. The package body as described in claim 1, in the top view, the front area of ​​the second metal layer is smaller than the front area of ​​the first upper metal layer, and the front area of ​​the second metal layer is larger than the front area of ​​at least one of the plurality of pins.

3. The package as claimed in claim 1, further comprising, in a top view: two opposite first sides; Two opposite second sides are adjacent to each of the first sides, in, The two protrusions extend from two opposite end regions of the second metal layer toward the two second sides respectively, and are respectively aligned with the two second sides.

4. The package as claimed in claim 1, wherein the plurality of pins further comprises a first group of pins and a second group of pins opposite to each other, the second carrier portion is located between the first carrier portion and the second group of pins, wherein: The shortest distance between the first group of pins and the first carrying portion is greater than the shortest distance between the second group of pins and the first carrying portion. 5 . The package as claimed in claim 1 , further comprising a mold packaging structure, wherein a back surface of the first lower metal layer and back surfaces of the plurality of leads are exposed outside the mold packaging structure.

6. A package as described in claim 5, wherein the molding structure includes an upper molding structure and a lower molding structure, the upper molding structure covers the front side of the first supporting part, the front side of the second supporting part and the front side of the plurality of pins, and the lower molding structure covers the entire back side of the second metal layer. 7 . The package as claimed in claim 1 , wherein a ratio of the maximum width of the first upper metal layer to the maximum width of the package is between 30% and 50%.

8. The package as claimed in claim 1, wherein the plurality of pins include a third upper metal layer and at least one fourth upper metal layer, the third upper metal layer and the at least one fourth upper metal layer are located on the same side of the package, and the maximum length of the third upper metal layer is more than twice the maximum length of the fourth upper metal layer. 9 . The package as claimed in claim 8 , wherein a sum of front surface areas of the third upper metal layer and the at least one fourth upper metal layer is smaller than the front surface area of ​​the second metal layer. 10 . The package as claimed in claim 8 , wherein the at least one fourth upper metal layer comprises two fourth upper metal layers separated from each other and respectively located on two sides of the third upper metal layer.

11. The package as claimed in claim 8, further comprising a third lower metal layer and at least one fourth lower metal layer, respectively corresponding to and overlapping the third upper metal layer and the at least one fourth upper metal layer, wherein the maximum length of the third lower metal layer is more than twice the maximum length of the fourth lower metal layer. 12 . The package body according to claim 1 , wherein the package body is applied to a dual flat no-lead package.

13. The package of claim 8, wherein the at least one fourth upper metal layer comprises two fourth upper metal layers separated from each other, and the plurality of pins further comprises a fifth upper metal layer relative to the third upper metal layer and the two fourth upper metal layers, and the package further comprises: A depletion-type high electron mobility transistor is disposed on the first upper metal layer, the depletion-type high electron mobility transistor comprises a source, a drain and a gate, the source is electrically connected to the second metal layer, and the drain is electrically connected to the fifth upper metal layer; A field effect transistor is disposed on the second metal layer, the field effect transistor comprises a drain, a source and a gate, the drain of the field effect transistor is electrically connected to the second metal layer, the source of the field effect transistor is electrically connected to the gate of the depletion-mode high-power transistor and the third upper metal layer respectively, and the gate of the field effect transistor is electrically connected to one of the two fourth upper metal layers; as well as The resistor is connected between the second metal layer and the other of the two fourth upper metal layers.

14. The package of claim 8, wherein the at least one fourth upper metal layer comprises two fourth upper metal layers separated from each other, the plurality of pins further comprises a fifth upper metal layer relative to the third upper metal layer and the two fourth upper metal layers, and the package further comprises: an enhanced high electron mobility transistor, disposed on the first upper metal layer, the enhanced high electron mobility transistor comprising a source, a gate and a drain, the source being electrically connected to the third upper metal layer, the gate being electrically connected to the second metal layer, and the drain being electrically connected to the fifth upper metal layer; A first Zener diode is disposed on the second metal layer, and one end of the first Zener diode is electrically connected to the second metal layer; A second Zener diode is disposed on the first upper metal layer and one end of the second Zener diode is electrically connected to the first upper metal layer. Layer; and The resistor and the capacitor are respectively connected between the second metal layer and one of the two fourth upper metal layers. 15 . The package as claimed in claim 13 , wherein the enhancement mode high electron mobility transistor or the depletion mode high electron mobility transistor is a GaN-based high electron mobility transistor.

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