Dry etching method and semiconductor process equipment

Abstract

Disclosed in the embodiments of the present application are a dry etching method and semiconductor process equipment. The dry etching method is used for selectively etching a laminated structure comprising Si layers and SiGe layers which are alternately stacked, and comprises: when an SiGe layer of the laminated structure is selectively etched, subjecting the laminated structure to plasma etching by using a first etching gas, wherein the first etching gas comprises a fluorine-containing gas and a first auxiliary etching gas; and when an Si layer of the laminated structure is selectively etched, subjecting the laminated structure to plasma etching by using a second etching gas, wherein the second etching gas comprises the fluorine-containing gas and a second auxiliary etching gas. The first auxiliary etching gas and the second auxiliary etching gas are used for adjusting the etching selection ratio between SiGe and Si.

Description

Dry etching method and semiconductor process equipment Technical Field

[0001] The present application belongs to the field of semiconductor technology, and specifically relates to a dry etching method and semiconductor process equipment. Background Art

[0002] With the continuous advancement of Moore's Law, after the semiconductor process has developed to the 3nm node, the ring gate type (Gate All Around, GAA) transistor is considered to be an effective replacement for the fin field effect transistor (FinFET). In the GAA manufacturing process engineering, horizontal stacked nanosheets of the sacrificial layer with high selectivity are crucial. The industry usually produces vertically stacked Si or SiGe nanowires by selectively removing SiGe or Si in the Si and SiGe multilayer stack. Usually, nFET is formed by selectively removing SiGe in the Si and SiGe multilayer stack to produce vertically stacked Si nanosheets, and pFET is formed by selectively removing Si material to produce vertically stacked SiGe nanosheets. In order to reduce the subsequent negative impact on the device, SiGe and Si materials need to have a very high selectivity relative to each other during the etching process to avoid or reduce damage to the channel.

[0003] Currently, the industry generally uses wet etching processes to achieve high selectivity for SiGe and Si materials. However, wet etching easily distorts the etched pattern and makes it difficult to achieve precise etching results. Dry etching processes, on the other hand, face the dilemma of low selectivity.

[0004] Summary of the Invention

[0005] The embodiments of the present application disclose a dry etching method and semiconductor process equipment to solve the problems in the related art of low etching selectivity and low productivity when selectively etching a Si layer or a SiGe layer from a stacked structure of a Si layer and a SiGe layer.

[0006] To solve the above technical problems, according to a first aspect, an embodiment of the present application discloses a dry etching method for selectively etching a stacked structure including alternating Si layers and SiGe layers, the method comprising:

[0007] When selectively etching the SiGe layer from the stacked structure, plasma etching is performed on the stacked structure using a first etching gas, wherein the first etching gas includes a fluorine-containing gas and a first auxiliary etching gas;

[0008] When selectively etching the Si layer from the stacked structure, plasma etching the stacked structure using a second etching gas, wherein the second etching gas includes the fluorine-containing gas and a second auxiliary etching gas;

[0009] The first auxiliary etching gas and the second auxiliary etching gas are used to adjust the etching selectivity ratio between SiGe and Si, and the first auxiliary etching gas is different from the second auxiliary etching gas.

[0010] In some embodiments, the first auxiliary etching gas includes at least one of He and Ar; or

[0011] The second auxiliary etching gas includes oxygen and nitrogen.

[0012] In some embodiments, the fluorine-containing gas includes a fluorocarbon gas.

[0013] In some embodiments, the fluorocarbon gas includes at least one of CF4, C4F8, C3F6, CHF3, CH2F2, and CH3F.

[0014] In some embodiments, the second auxiliary etching gas includes at least one of N2, O2, NO, and NO2.

[0015] In some embodiments, in the first etching gas, a ratio of the fluorine-containing gas to the first auxiliary etching gas ranges from 0.1 to 10.

[0016] In some embodiments, in the second etching gas, the ratio of the content of the fluorine element to the content of the oxygen element ranges from 0.1 to 10; or

[0017] The content ratio of the fluorine element to the nitrogen element ranges from 0.1 to 10.

[0018] In some embodiments, in the step of performing plasma etching on the stacked structure using the first etching gas, the pressure of the process chamber is 100 mTorr to 5000 mTorr; or

[0019] In the step of performing plasma etching on the stacked structure using the second etching gas, the pressure of the process chamber is 100 mTorr to 5000 mTorr.

[0020] In some embodiments, in the step of performing plasma etching on the stacked structure using a first etching gas, a flow rate of the first etching gas is in a range of 10 sccm to 4000 sccm; or

[0021] In the step of performing plasma etching on the stacked structure using a second etching gas, a flow rate of the second etching gas ranges from 10 sccm to 4000 sccm.

[0022] In some embodiments, in the step of performing plasma etching on the stacked structure using the first etching gas, the plasma etching is isotropic etching; or

[0023] In the step of performing plasma etching on the stacked structure using the second etching gas, the plasma etching is isotropic etching.

[0024] In some embodiments, before the step of plasma etching the stacked structure using the first etching gas, or before the step of plasma etching the stacked structure using the second etching gas, the method further includes:

[0025] The natural oxide layer on the surface of the Si layer or SiGe layer is removed.

[0026] In some embodiments, the fluorine-containing gas is used to perform anisotropic plasma etching on the native oxide layer of the stacked structure.

[0027] According to a second aspect, an embodiment of the present application provides a semiconductor process equipment, including:

[0028] A process chamber comprising a wafer carrier and a perforated partition, wherein the perforated partition is arranged parallel to a carrying surface of the wafer carrier to separate a cavity of the process chamber into a first area located at an upper side of the process chamber and a second area located at a lower side of the process chamber, wherein the wafer carrier is located in the second area;

[0029] The control device includes at least one memory and at least one processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the dry etching method described in any one of the first aspects above.

[0030] In some embodiments, the semiconductor process equipment further comprises:

[0031] The remote plasma device is used to excite the introduced process gas into plasma, and the remote plasma device is connected to the first area.

[0032] In some embodiments, the remote plasma device is a microwave source.

[0033] In some embodiments, the perforated partition includes multiple layers, and at least some of the through-holes of the perforated partitions of adjacent layers are not aligned with each other.

[0034] In some embodiments, the perforated partition is grounded or has a predetermined voltage applied thereto.

[0035] In the dry etching method and semiconductor process equipment of the embodiments of the present application, a first etching gas is used to selectively etch the SiGe layer from a stacked structure of alternating Si layers and SiGe layers, and a second etching gas is used to selectively etch the Si layer from the stacked structure. The main etching gas (i.e., both are fluorine-containing gases) used for selectively etching the SiGe layer and the selective etching of the Si layer are the same, and only the auxiliary etching gas is different. This enables the selective etching of the SiGe layer and the Si layer to be completed separately in the same process chamber, without the need to transfer the wafer back and forth between different process chambers, thereby improving production capacity and having a good etching selectivity ratio. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] FIG1A is a schematic diagram showing a stacked structure used in a dry etching method according to an embodiment of the present application;

[0037] FIG1B is a schematic diagram showing selective etching of the SiGe layer from the stacked structure shown in FIG1A ;

[0038] FIG1C is a schematic diagram showing selective etching of the Si layer from the stacked structure shown in FIG1A ;

[0039] FIG2 shows an electron microscope image obtained after selectively etching the SiGe layer from the stacked structure using the dry etching method according to an embodiment of the present application;

[0040] FIG3 shows an electron microscope image obtained after selectively etching the Si layer from the stacked structure using the dry etching method according to an embodiment of the present application;

[0041] FIG4 shows a schematic diagram of a semiconductor process equipment according to an embodiment of the present application;

[0042] FIG5 shows a schematic top view of a perforated partition according to an embodiment of the present application. DETAILED DESCRIPTION

[0043] To make the purpose, technical solutions, and advantages of this application more clear, the technical solutions in the embodiments of this application will be clearly and completely described below in conjunction with the drawings in the embodiments of this application. Obviously, the described embodiments are part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0044] It should be understood by those skilled in the art that the embodiments of the present application are merely illustrations of the structures and methods for which the present application may be implemented in various forms. In addition, each example provided in conjunction with the various embodiments is intended to be illustrative, not restrictive. In addition, the drawings are not necessarily drawn to scale, and some features may be exaggerated to show the details of specific components. Therefore, the specific structural and functional details in the embodiments of the present application should not be interpreted as restrictive, but merely as a representative basis for teaching those skilled in the art to adopt the methods and structures of the embodiments of the present application in different ways. It should also be noted that identical and corresponding elements are represented by the same reference numerals.

[0045] In the following description, many specific details are set forth, such as specific structures, components, materials, dimensions, processing steps and techniques, in order to provide an understanding of the various embodiments of the present application. However, it should be understood by those skilled in the art that the various embodiments of the present application can be practiced without these specific details. In other cases, well-known structures or processing steps are not described in detail to avoid obscuring the present application.

[0046] For the purposes of the following description, the terms "upper," "right," "left," "vertical," "horizontal," "top," "bottom," and their derivatives shall relate to the orientation of the structures and methods disclosed in the drawings of the specification. It will be understood that when an element as a layer, region, or substrate is referred to as being "on" another element, the element can be directly on the other element or intervening elements may be present. In contrast, when an element is referred to as being "directly on" another element, there are no intervening elements between the two. It will also be understood that when an element is referred to as being "under" another element, the element can be directly under the other element or intervening elements may be present. Conversely, when an element is referred to as being "directly under" another element, there are no intervening elements between the two.

[0047] The technical solutions disclosed in the embodiments of the present application will be described in detail below with reference to the accompanying drawings.

[0048] Figure 1A shows a stacked structure applied to the dry etching method provided in an embodiment of the present application, which may include alternately stacked Si layers 101 and SiGe layers 102. A hard mask layer 103 may be provided above the alternately stacked Si layers 101 and SiGe layers 102. The hard mask layer 103 may be a silicon oxide layer, a silicon nitride layer, or a stack of silicon oxide layers and silicon nitride layers. The Si layer 101 and the SiGe layer 102 are etched using the hard mask layer 103 as an etching mask to form a fin-type stacked structure as shown in Figure 1A. In subsequent semiconductor processes, the SiGe layer 102 in the stacked structure is selectively removed to retain the Si layer 101 as the channel of the GAA-FET to be formed to produce an nFET, or the Si layer 101 in the stacked structure is selectively removed to retain the SiGe layer 102 as the channel of the GAA-FET to be formed to produce a pFET. In the stacked structure shown in Figure 1A, the Si layer 101 and the SiGe layer 102 can be formed on the surface of the substrate 104 by epitaxial growth. In the example of Figure 1A, the substrate 104 is Si. Those skilled in the art should understand that the material of the substrate 104 is not limited to this, and can also be other elemental or compound semiconductor materials, such as Ge, SiGe, GaAs, InSb, GaP, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb or InP, etc.

[0049] To fabricate an nFET, the SiGe layer 102 must be selectively etched from the stack, as shown in Figure 1B ; while to fabricate a pFET, the Si layer 101 must be selectively etched from the stack, as shown in Figure 1C . The industry's common approach is to selectively remove the SiGe layer 102 using wet etching and the Si layer 101 using dry etching. This requires transferring the wafer back and forth between different process chambers, significantly impacting production capacity. Furthermore, due to the limitations of the wet etching process, it cannot be used in processes at advanced technology nodes.

[0050] The industry has been exploring the use of dry etching processes to selectively remove SiGe layers. The inventors of the present application have learned that the etching gases used in these dry etching schemes for selectively removing SiGe layers are very different from those used in dry etching schemes for selectively removing Si layers. Therefore, it is still necessary to transfer the wafer back and forth between different process chambers, which seriously affects production capacity. In addition, there are no reports on achieving a high etching selectivity ratio.

[0051] In order to solve the above technical problems, a dry etching method proposed in an embodiment of the present application has the main idea of ​​using etching gases that are as similar as possible to selectively etch the SiGe layer and the Si layer of the stacked structure respectively, so that the selective etching of the SiGe layer and the Si layer can be completed separately in the same process chamber, without the need to transfer the wafer back and forth between different process chambers, thereby improving production capacity and achieving high selectivity etching at the same time.

[0052] First, the technical solution for selectively etching a SiGe layer from a stacked structure according to an embodiment of the present application will be described in detail. In this embodiment, the stacked structure is plasma etched using a first etching gas, which includes a fluorine-containing gas and a first auxiliary etching gas. The fluorine-containing gas is the primary etching gas. Upon excitation, the fluorine ions and fluorine-containing radicals generated by the fluorine-containing gas react with the film to be etched to achieve etching. The first auxiliary gas is used to adjust the etching selectivity between SiGe and Si, thereby achieving selective etching of the SiGe layer.

[0053] In some embodiments, the fluorine-containing gas may include a carbon fluorine gas, more specifically at least one of CF4, C4F8, C3F6, CHF3, CH2F2, and CH3F, and the first auxiliary etching gas may include at least one of He and Ar.

[0054] FIG2 shows an electron microscope image obtained after selectively etching the SiGe layer from the stacked structure using the dry etching method provided in an embodiment of the present application. For comparison, the inventors of the present application conducted an experiment in which only fluorine-containing gas was used to etch the stacked structure. The results showed that the etching selectivity of SiGe relative to Si was relatively low, and the Si layer was severely damaged while removing the SiGe layer. Since the remaining Si layer needs to serve as the channel of the GAA-FET, the severely damaged Si layer will seriously affect the performance of the GAA-FET. It can be clearly seen from FIG2 that the dry etching method of the embodiment of the present application, since a first auxiliary etching gas is also added, can greatly improve the etching selectivity of SiGe relative to Si, and ensure that the loss of the Si layer is small while removing the SiGe layer. At the same time, it can be seen that the sidewalls of the etched recessed SiGe layer are relatively smooth. Therefore, the dry etching method of the embodiment of the present application is also very suitable for removing SiGe layers of a predetermined thickness. In the subsequent GAA-FET manufacturing process, an insulating layer such as silicon oxide or silicon nitride can be used to fill the space after removing the SiGe layer of a predetermined thickness. The filled insulating layer can be used to prevent the gate structure of the subsequently formed GAA-FET from being conductive with the source region or the drain region.

[0055] The inventors of this application have discovered that changing the flow ratio of the fluorine-containing gas to the first auxiliary etching gas in the first etching gas can affect the morphology of the laminated structure after etching. In some embodiments, when the flow ratio of the fluorine-containing gas to the first auxiliary etching gas is in the range of 0.1 to 10, the morphology of the laminated structure after etching can be further improved.

[0056] The inventors of this application have also discovered that the process chamber pressure also affects the etch rate and the morphology of the laminated structure after etching. Increasing the process chamber pressure can increase the etch rate, but excessive process chamber pressure can deteriorate the morphology of the laminated structure after etching. In some embodiments, the process chamber pressure ranges from 100 mTorr to 5000 mTorr. In some embodiments, the flow rate of the first etching gas ranges from 10 sccm to 4000 sccm.

[0057] In some embodiments, the power range for exciting the plasma is 100 W to 3000 W, and the lower electrode bias power is 0 to 100 W, so that the plasma etching is isotropic or substantially isotropic. The plasma can be excited using an upper electrode radio frequency coil or a remote plasma. In the embodiments of the present application, remote plasma is preferably used, and more preferably, a microwave source is used to excite the plasma.

[0058] In some embodiments, the temperature of the wafer carrier, such as an electrostatic chuck, is between 0 and 100°C.

[0059] Hereinafter, the technical solution for selectively etching the Si layer from the stacked structure according to an embodiment of the present application will be described in detail. In this embodiment, the stacked structure is plasma etched using a second etching gas, and the second etching gas includes a fluorine-containing gas and a second auxiliary etching gas, wherein the fluorine-containing gas used in the technical solution for selectively etching the Si layer is the same as the fluorine-containing gas used in the technical solution for selectively etching the SiGe layer. The fluorine-containing gas is the main etching gas, and the fluorine ions and fluorine-containing free radicals generated by the fluorine-containing gas after being excited react with the film layer to be etched to achieve etching. The second auxiliary gas is used to adjust the etching selectivity between SiGe and Si, thereby achieving selective etching of the Si layer. In this embodiment, since the main etching gas used for selectively etching the SiGe layer and the selective etching of the Si layer is the same, only the auxiliary etching gas used is different. Therefore, it is possible to achieve selective etching of the SiGe layer and the Si layer separately in the same process chamber, without having to transfer the wafer back and forth between different process chambers, thereby improving production capacity.

[0060] In some embodiments, the fluorine-containing gas may also include a carbon fluorine gas, more specifically, may include at least one of CF4, C4F8, C3F6, CHF3, CH2F2, CH3F, and the second auxiliary etching gas includes oxygen and nitrogen elements, more specifically, the second auxiliary etching gas may include at least one of N2, O2, NO, and NO2.

[0061] Figure 3 shows an electron microscope image obtained after selectively etching the Si layer from a stacked structure using the dry etching method of an embodiment of the present application. As can be clearly seen from Figure 3, the dry etching method of an embodiment of the present application, due to the addition of a second auxiliary etching gas, can significantly improve the etching selectivity of Si relative to SiGe, while ensuring minimal loss of the SiGe layer while removing the Si layer. As mentioned above, since the remaining SiGe layer needs to serve as the channel of the GAA-FET, the dry etching method of an embodiment of the present application can effectively improve the performance of the subsequently manufactured GAA-FET.

[0062] The inventors of this application have discovered that the oxygen and nitrogen elements in the second etching gas can effectively adjust the etching rate and etching selectivity of the stacked structure. When the oxygen content in the second etching gas increases, the etching rates of both the SiGe layer and the Si layer increase, but the etching selectivity between Si and SiGe does not change much. When the nitrogen content in the second etching gas increases, the etching rate of Si is accelerated and the etching selectivity of Si relative to SiGe increases. When the nitrogen content in the second etching gas decreases, the etching of both Si and SiGe is suppressed, and the etching selectivity of Si relative to SiGe decreases. In some embodiments, the ratio of fluorine to oxygen in the second etching gas ranges from 0.1 to 10. Within this range, a faster etching rate and better etching selectivity can be achieved. In some embodiments, the ratio of fluorine to nitrogen in the second etching gas ranges from 0.1 to 10. Within this range, the etching selectivity of Si relative to SiGe can be effectively improved, while removing the Si layer while ensuring minimal loss of the SiGe layer.

[0063] The inventors of this application also discovered that in the technical solution for selectively etching the Si layer, the pressure of the process chamber also affects the etching rate and the morphology of the laminated structure after etching. Increasing the process chamber pressure can increase the etching rate, but excessive process chamber pressure can deteriorate the morphology of the laminated structure after etching. In some embodiments, the process chamber pressure ranges from 100mTorr to 5000mTorr. In some embodiments, the flow rate of the second etching gas ranges from 10sccm to 4000sccm.

[0064] In some embodiments, the power range for exciting the plasma is 100 W to 3000 W, and the lower electrode bias power is 0 to 100 W, so that the plasma etching is isotropic or substantially isotropic. Similarly, the plasma can be excited using an upper electrode radio frequency coil or a remote plasma. In the embodiments of the present application, remote plasma is preferably used, and more preferably, a microwave source is used to excite the plasma.

[0065] In some embodiments, the temperature of the wafer carrier, such as an electrostatic chuck, is between 0 and 100°C.

[0066] Furthermore, before performing selective plasma etching on the stacked structure, the dry etching method of the embodiment of the present application may further include: removing the natural oxide layer on the surface of the Si layer or the SiGe layer.

[0067] In this embodiment, a fluorine-containing gas can be used to remove the natural oxide layer on the surface of the stacked structure. The fluorine-containing gas can be the same as the fluorine-containing gas used for selectively etching the SiGe layer and selectively etching the Si layer, thereby enabling the steps of removing the natural oxide layer, selectively etching the SiGe layer, and selectively etching the Si layer to be completed in the same process chamber, without the need to transfer the wafer back and forth between different process chambers, thereby improving production capacity.

[0068] In some embodiments, the fluorine-containing gas may include a fluorine-containing gas, more specifically at least one of CF4, C4F8, C3F6, CHF3, CH2F2, and CH3F. Unlike the steps of selectively etching the SiGe layer and the selective etching of the Si layer, in the step of removing the native oxide layer, a bottom electrode bias power is applied to make the plasma etching anisotropic.

[0069] In some embodiments, in the step of removing the natural oxide layer, the process chamber pressure is 0 to 2000 mTorr, the applied upper electrode RF power is 10W to 2000 W, the lower electrode RF bias power is 20W to 2000 W, the RF frequency of the upper electrode and the lower electrode can be, for example, 2 MHz, 400 KHz, 13.56 MHz or 27 MHz, etc., the total flow rate of the process gas is 10 sccm to 1000 sccm, and the temperature of the wafer carrier such as an electrostatic chuck is 0 to 100°C.

[0070] Accordingly, an embodiment of the present application also provides a semiconductor process equipment, and the dry etching method of the embodiment of the present application can be implemented, for example, using the semiconductor process equipment shown in Figure 4. As shown in Figure 4, the semiconductor process equipment may include a process chamber 210, and the process chamber 210 may include a wafer carrier 211 and a perforated partition 212. The wafer carrier 211 may include, for example, an electrostatic chuck, a vacuum adsorption chuck or a mechanical chuck, etc., for carrying the wafer to be processed. The semiconductor process equipment may use an upper electrode RF coil to excite plasma, or use remote plasma. In some embodiments, the semiconductor process equipment may also include a remote plasma (RPS) device 220, wherein the remote plasma device 220 is used to excite the introduced process gas into plasma. In some embodiments, the semiconductor process equipment may also include an RF power supply connected to the wafer carrier 211 for providing an RF bias.

[0071] The perforated partition 212 is generally plate-shaped. In the example of FIG4 , two layers of perforated partitions are shown. However, the present application is not limited thereto. One or more layers of perforated partitions may also be provided. As shown in FIG5 , the perforated partition 212 is provided with a number of through holes. The number, shape, and size of the through holes are not limited here. Preferably, the through holes are evenly distributed on the perforated partition 212. The perforated partition 212 is provided parallel to the supporting surface of the wafer carrier 211 to separate the cavity of the process chamber into a first area 213 located on the upper side of the process chamber and a second area 214 located on the lower side of the process chamber. The wafer carrier 211 is located in the second area 214, and the remote plasma device 220 is connected to the first area 213. The remote plasma device 220 may be, for example, a microwave source, which can excite more free radicals and is more conducive to achieving selective etching.

[0072] The plasma generated by the remote plasma device 220 is transported to the first region 213. At this time, the plasma includes active substances such as high-energy electrons, ions, and free radicals. The perforated partition 212 is grounded or applied with a predetermined voltage, so that electrons and charged ions are filtered out when passing through the perforated partition 212. Since free radicals are uncharged, they can pass through the perforated partition 212 and reach the second region 214. Therefore, most of the reactive substances in the second region 214 are free radicals. Therefore, in the dry etching method of the embodiment of the present application, free radicals are mainly used to achieve selective etching of the SiGe layer or selective etching of the Si layer from the stacked structure of alternating Si layers and SiGe layers.

[0073] In some embodiments, the perforated baffles 212 are multi-layered, and at least some of the through-holes in adjacent layers of the perforated baffles 212 are misaligned. Preferably, all of the through-holes in adjacent layers of the perforated baffles 212 are misaligned, as shown in FIG4 . This prevents the plasma from passing through the multi-layer perforated baffles 212 in a straight line, thereby extending the plasma's path, allowing more electrons and charged ions to be filtered or attenuated, and further increasing the proportion of free radicals in the second region 214. Furthermore, the through-holes can be specially designed, such as being curved, to extend the plasma's path, allowing more electrons and charged ions to be filtered or attenuated, and further increasing the proportion of free radicals in the second region 214, thereby enabling better selective etching.

[0074] The semiconductor process equipment of the embodiment of the present application may further include a control device (not shown), which may be, for example, a lower computer or a higher computer of the semiconductor process equipment. The control device may include at least one memory and at least one processor, wherein a computer program is stored in the memory, and the processor executes the computer program to implement the dry etching method described above.

[0075] In the control device, the processor can be a central processing unit (CPU), other general-purpose processors, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components and other chips, or a combination of the above chips.

[0076] The memory may include a high-speed random access memory and may also include a non-transitory memory, such as at least one disk storage device, a flash memory device, or other non-transitory solid-state storage device. In some optional embodiments, the memory may also include a memory remotely arranged relative to the processor, and these remote memories may be connected to the processor via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and a combination thereof. The memory, as a non-transitory computer-readable storage medium, may be used to store non-transitory software programs, non-transitory computer executable programs, and modules, such as the program instructions corresponding to the dry etching method in the embodiment of the present application, such as controlling the opening of the corresponding valve to allow the etching gas of the corresponding type and flow to enter the remote plasma device 220, controlling the remote plasma device 220 to ignite the plasma at a predetermined power, controlling the heater of the wafer carrier 211 to heat to a predetermined temperature, controlling the exhaust device of the process chamber to make the process chamber reach a predetermined pressure, and so on. The processor executes various functional applications and data processing of the processor by running the non-transitory program instructions stored in the memory, that is, implementing the dry etching method in the above-mentioned method embodiment.

[0077] The specific details of the above-mentioned semiconductor process equipment can be understood by referring to the corresponding descriptions and effects in the dry etching method embodiment described above, and will not be repeated here.

[0078] The above embodiments of this application focus on the differences between the various embodiments. As long as the different optimization features between the various embodiments are not contradictory, they can be combined to form a better embodiment. Considering the simplicity of the text, they will not be repeated here.

[0079] The foregoing is merely an embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various changes and variations. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present application should all be included within the scope of the claims of the present application.

Claims

1. A dry etching method for selectively etching a stacked structure comprising alternately stacked Si layers and SiGe layers, characterized in that: The method comprises: When selectively etching the SiGe layer from the stacked structure, plasma etching is performed on the stacked structure using a first etching gas, wherein the first etching gas includes a fluorine-containing gas and a first auxiliary etching gas; When the Si layer is selectively etched from the stacked structure, the stacked structure is plasma etched using a second etching gas, wherein the second etching gas includes the fluorine-containing gas and a second auxiliary etching gas; The first auxiliary etching gas and the second auxiliary etching gas are used to adjust the etching selectivity ratio between SiGe and Si, and the first auxiliary etching gas is different from the second auxiliary etching gas.

2. The dry etching method according to claim 1, characterized in that: The first auxiliary etching gas includes at least one of He and Ar; or The second auxiliary etching gas includes oxygen and nitrogen.

3. The dry etching method according to claim 2, characterized in that: The fluorine-containing gas includes fluorine-containing gas.

4. The dry etching method according to claim 3, characterized in that: The carbon-fluorine gas includes at least one of CF4, C4F8, C3F6, CHF3, CH2F2, and CH3F.

5. The dry etching method according to claim 2, characterized in that: The second auxiliary etching gas includes at least one of N2, O2, NO, and NO2.

6. The dry etching method according to claim 1, characterized in that: In the first etching gas, a flow ratio of the fluorine-containing gas to the first auxiliary etching gas ranges from 0.1 to 10.

7. The dry etching method according to claim 2, characterized in that: In the second etching gas, the content ratio of the fluorine element to the oxygen element is in a range of 0.1 to 10; or The content ratio of the fluorine element to the nitrogen element ranges from 0.1 to 10.

8. The dry etching method according to claim 1, characterized in that: In the step of performing plasma etching on the stacked structure using the first etching gas, the pressure of the process chamber is 100 mTorr to 5000 mTorr; or In the step of performing plasma etching on the stacked structure by using the second etching gas, the pressure of the process chamber is 100 mTorr to 5000 mTorr.

9. The dry etching method according to claim 1, characterized in that: In the step of performing plasma etching on the stacked structure using a first etching gas, a flow rate of the first etching gas ranges from 10 sccm to 4000 sccm; or In the step of performing plasma etching on the stacked structure using a second etching gas, a flow rate of the second etching gas ranges from 10 sccm to 4000 sccm.

10. The dry etching method according to claim 1, characterized in that: In the step of performing plasma etching on the stacked structure using the first etching gas, the plasma etching is isotropic etching; or In the step of performing plasma etching on the stacked structure by using the second etching gas, the plasma etching is isotropic etching.

11. The dry etching method according to any one of claims 1 to 10, characterized in that: Before the step of plasma etching the stacked structure using the first etching gas, or before the step of plasma etching the stacked structure using the second etching gas, the method further includes: The natural oxide layer on the surface of the Si layer or the SiGe layer is removed.

12. The dry etching method according to claim 11, characterized in that: The natural oxide layer of the stacked structure is anisotropically etched by using the fluorine-containing gas.

13. A semiconductor process equipment, characterized in that: include: A process chamber, comprising a wafer carrier and a perforated partition, wherein the perforated partition is arranged parallel to the carrying surface of the wafer carrier to separate the cavity of the process chamber into a first area located at the upper side of the process chamber and a second area located at the lower side of the process chamber, and the wafer carrier is located in the second area; A control device comprises at least one memory and at least one processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the dry etching method according to any one of claims 1 to 12.

14. The semiconductor process equipment according to claim 13, characterized in that: Also includes: The remote plasma device is used to excite the introduced process gas into plasma, and the remote plasma device is connected to the first area.

15. The semiconductor process equipment according to claim 14, characterized in that: The remote plasma device is a microwave source.

16. The semiconductor process equipment according to claim 13, characterized in that: The perforated partition plate includes multiple layers, and at least some of the through holes of the perforated partition plates of adjacent layers are not aligned with each other.

17. The semiconductor process equipment according to claim 13, characterized in that: The perforated partition is grounded or has a predetermined voltage applied thereto.

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