Method and apparatus for eliminating wafer surface defects, medium and wafer manufacturing method

Abstract

Disclosed in the embodiments of the present application are a method and apparatus for eliminating wafer surface defects, a medium and a wafer manufacturing method. The method for eliminating wafer surface defects comprises: acquiring an associated defect type having a quantity correlation with a line defect; determining a causative defect of the line defect from the associated defect type, the causative defect being a first cause for forming the line defect; acquiring a second cause of the line defect in a wafer processing process; and, for the first cause and the second cause, respectively generating a first elimination measure for reducing the number of the causative defects and a second elimination measure for instructing modifying processing parameters in the wafer processing process, wherein the first elimination measure and the second elimination measure can reduce the number of the line defects on the surface of the wafer.

Description

Method, device, medium and wafer manufacturing method for eliminating wafer surface defects

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to Chinese patent application No. 202311076184.5 filed in China on August 24, 2023, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The embodiments of the present application relate to the field of semiconductor processing technology, and in particular to a method, device, medium, and wafer manufacturing method for eliminating wafer surface defects. Background Art

[0004] With the continuous advancement of semiconductor manufacturing technology, defects on wafers have an increasingly greater impact on device performance, so it is particularly important to strictly control wafer defects.

[0005] Wafer surface defects directly impact the quality and reliability of semiconductor manufacturing processes, such as photolithography, thin film deposition, corrosion and etching, and metal electrode preparation. However, with the continuous advancement of manufacturing processes, existing methods for controlling wafer surface defects have become ineffective, necessitating more sophisticated and rigorous methods for controlling wafer surface defects.

[0006] Summary of the Invention

[0007] In view of this, the embodiments of the present application hope to provide a method, device, medium and wafer manufacturing method for eliminating wafer surface defects; which can reduce the occurrence of small-size defects on the silicon wafer surface and improve the quality and reliability of the wafer.

[0008] The technical solution of the embodiment of the present application is implemented as follows:

[0009] In a first aspect, an embodiment of the present application provides a method for eliminating wafer surface defects, the method comprising:

[0010] Obtaining associated defect types that have quantitative correlation with linear defects;

[0011] Determining a causal defect of the linear defect from the associated defect types; wherein the causal defect is a first cause of the linear defect;

[0012] Obtaining a second cause of the linear defect during wafer processing;

[0013] For the first cause and the second cause, a first elimination measure for reducing the number of the causal defects and a second elimination measure for indicating modification of processing parameters during wafer processing are generated respectively; wherein, the first elimination measure and the second elimination measure can reduce the number of linear defects on the wafer surface.

[0014] In some examples, in the defect type pair, the number of the linear defects is positively correlated with the number of the cause defects.

[0015] In some examples, the causative defect is a residue defect.

[0016] In some examples, determining the defect causing the linear defect from the associated defect types includes:

[0017] During the wafer polishing process, the filler present in the tiny cracks at a local position on the wafer surface reacts chemically and physically with the tiny cracks due to the high temperature generated by polishing to form a linear defect, and the residual defect is determined to be the causal defect of the linear defect.

[0018] In some examples, obtaining a second cause of the linear defect during wafer processing includes:

[0019] During the wafer polishing process, the consistency between the movement direction of polishing particles at the wafer edge and the direction of the linear defect is determined as the second generation cause.

[0020] In some examples, generating, for the first cause and the second cause, a first elimination measure for reducing the number of defects caused by the first cause and a second elimination measure for instructing modification of processing parameters during wafer processing, respectively, includes:

[0021] According to the first generation cause, determining that the first elimination measure is to reduce the residual defect by reducing the amount of organic matter residue on the wafer surface;

[0022] According to the second generation cause, it is determined that the second elimination measure is to change the movement trajectory of the polishing particles at the edge of the wafer.

[0023] In some examples, the second elimination measure includes:

[0024] During the wafer polishing process, spherical polishing particles are used to polish the wafer surface to change the movement trajectory of the polishing particles at the edge of the wafer.

[0025] In a second aspect, an embodiment of the present application provides a device for eliminating wafer surface defects, the device comprising:

[0026] A first acquisition part, a determination part, a second acquisition part, and a measure generation part, wherein,

[0027] The first acquisition part is configured to acquire associated defect types having a quantity correlation with linear defects;

[0028] The determining portion is configured to determine a causal defect of the linear defect from the associated defect types; wherein the causal defect is a first cause of the linear defect;

[0029] The second acquiring part is configured to acquire a second cause of the linear defect during wafer processing;

[0030] The measure generating part is configured to generate, for the first cause and the second cause, a first elimination measure for reducing the number of defects caused by the cause and a second elimination measure for indicating modification of processing parameters during wafer processing; wherein, the first elimination measure and the second elimination measure can reduce the number of linear defects on the wafer surface.

[0031] In a third aspect, an embodiment of the present application provides a computing device comprising: a processor and a memory; the processor is used to execute instructions stored in the memory to implement the method for eliminating wafer surface defects as described in the first aspect and any example in the first aspect.

[0032] In a fourth aspect, an embodiment of the present application provides a computer storage medium, wherein the storage medium stores at least one instruction, and the at least one instruction is used to be executed by a processor to implement the method for eliminating wafer surface defects described in the first aspect and any example in the first aspect.

[0033] In a fifth aspect, an embodiment of the present application provides a computer program product, which includes computer instructions stored in a computer-readable storage medium; a processor of an electronic device reads the computer instructions from the computer-readable storage medium, and the processor executes the computer instructions, so that the electronic device executes to implement the method for eliminating wafer surface defects as described in the first aspect and any example in the first aspect.

[0034] In a sixth aspect, an embodiment of the present application provides a wafer manufacturing method, the method comprising:

[0035] According to the method for eliminating wafer surface defects described in the first aspect and any example of the first aspect, determining a first elimination measure and a second elimination measure for eliminating linear defects;

[0036] During wafer processing, the first elimination measure and the second elimination measure are adopted to eliminate the linear defects on the wafer surface.

[0037] The present invention provides a method, apparatus, medium, and wafer manufacturing method for eliminating wafer surface defects. The method determines the causal defects of linear defects based on quantitative correlation, reduces the number of causal defects, and modifies processing parameters during wafer processing based on the production mechanism of linear defects during wafer processing. By combining these two measures, the number of small-scale defects on the wafer surface is reduced, and the processing quality of the wafer is improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] FIG1 is a schematic flow chart of a method for eliminating wafer surface defects provided by an embodiment of the present application;

[0039] FIG2 is a schematic diagram of defect merging statistics of multiple polished wafers provided in an embodiment of the present application;

[0040] FIG3 is a schematic diagram of the correlation between the number of two defects provided in an embodiment of the present application;

[0041] Figures 4(A) and (B) are schematic diagrams of residue defects provided in an embodiment of the present application;

[0042] FIG5 is a schematic diagram of the distribution of linear defects provided in an embodiment of the present application;

[0043] FIG6 is a schematic diagram of the composition of a polishing device provided in an embodiment of the present application;

[0044] FIG7 is a schematic diagram of the movement direction of polishing particles provided in an embodiment of the present application;

[0045] FIG8 is a schematic diagram of a discontinuous linear defect morphology provided in an embodiment of the present application;

[0046] FIG9 is a schematic diagram of a spherical polishing particle provided in an embodiment of the present application;

[0047] FIG10 is a schematic diagram of a device for eliminating wafer surface defects provided in an embodiment of the present application;

[0048] FIG11 is a schematic diagram of the structure of a computing device provided in an embodiment of the present application;

[0049] FIG12 is a schematic flow chart of a wafer manufacturing method provided in an embodiment of the present application. DETAILED DESCRIPTION

[0050] The technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application.

[0051] While wafer surface defect control measures can eliminate large defects, the reliability requirements of advanced processes necessitate more sophisticated and stringent control measures. Improving the control of small defects on the wafer surface is one such approach.

[0052] For small-sized defects on the wafer surface, the present application embodiment aims to determine measures to eliminate small-sized defects on the wafer surface by combining the correlation between the number of defects and the defect generation mechanism during the wafer processing process. This will reduce the number of small-sized defects on the wafer surface and improve the processing quality of the wafer.

[0053] Based on this, referring to FIG. 1 , a method for eliminating wafer surface defects provided by an embodiment of the present application is shown. The method can be applied to a computing device, and the method includes:

[0054] S101: Obtaining associated defect types that are quantitatively correlated with linear defects;

[0055] Normally, after the wafer processing is completed and before shipment, the wafer needs to be detected for defects. Taking the polished wafer as an example, the last processing process is the cleaning process. When the cleaning process is completed, the surface of the polished wafer to be tested can be detected using a scanning electron microscope (SEM) to obtain an image of the polished wafer surface. Subsequently, the location of the defect can be determined on the polished wafer surface image. Then, at the corresponding defect location, based on the image features corresponding to different defect types (such as aspect ratio, edge slope, near-circularity, slope variance group statistics), machine learning models, classification algorithms, etc. are used to determine the type of defects at each defect location, and the number of defects of each type is counted.

[0056] Each polished wafer that completed the cleaning process was inspected for defects using the aforementioned method, and the inspection results were combined and statistically analyzed. Common surface defects on polished wafers include particle defects, line jut defects, fat jut defects, mechanical pit defects, residual defects, and scratch defects. In some examples, these defects from multiple polished wafers were combined and statistically analyzed. The results are shown in Figure 2, which shows that the primary defect type on the polished wafer surface is line jut defects.

[0057] In some examples, the defect type and defect number of each polished wafer are counted separately. As shown in Figure 3, taking defect detection of 13 polished wafers as an example, the number of line jut defects and residual defects shows a positive correlation, that is, the more line jut defects there are, the more residual defects there are; and the fewer line jut defects there are, the fewer residual defects there are.

[0058] S102: Determine the defect causing the linear defect from the associated defect types;

[0059] Wherein, the causal defect is the first cause of the linear defect;

[0060] In the embodiments of the present application, due to the quantitative correlation between linear defects and residue defects, it can be indicated that the generation of these two types of defects is caused by the same poor process. Furthermore, there is a certain degree of causal relationship between the defects with quantitative correlation. That is, if the number of one type of defect (such as defect A) in the defect type pair is reduced, then even if no additional treatment is performed on the other type of defect (such as defect B), the number of this type of defect (defect B) will also be reduced accordingly. Based on this, the causal defect is defect A and the linear defect is defect B. In some examples, this causal relationship can be determined based on the mechanism of defect formation, thereby determining that the residue defect is the causal defect of the linear defect. The specific determination process can be referred to the subsequent implementation method and example of this step.

[0061] S103: Obtaining a second cause of the linear defect during wafer processing;

[0062] In the embodiments of the present application, linear defects can be caused by more than one factor. In addition to the residual defects described in the aforementioned steps, the processing techniques and methods used during wafer processing can also contribute to the generation of linear defects. In some examples, a second cause of linear defects during wafer processing can be determined based on the distribution of linear defects on the wafer surface image, combined with the processing trajectory and the physical and chemical changes that occur during wafer processing. In some examples, the process for determining the second cause can also be found in the subsequent implementation and examples of this step.

[0063] S104: For the first cause and the second cause, generate a first elimination measure for reducing the number of defects caused by the cause and a second elimination measure for instructing to modify the processing parameters during the wafer processing process; wherein the first elimination measure and the second elimination measure can reduce the number of linear defects on the wafer surface.

[0064] In the embodiments of the present application, in some examples, according to the first cause obtained in the above S102, the number of causal defects can be reduced based on the causal relationship between the causal defects and the linear defects, thereby correspondingly reducing the number of linear defects. Therefore, only one measure is needed to effectively and significantly reduce the number of two types of defects, thereby improving the quality of the wafer.

[0065] In some examples, based on the second cause of occurrence obtained in S103, the wafer processing process and process parameters can be modified to eliminate the linear defects generated during wafer processing. In this example, the process parameters need not be considered based on the defect's cause; instead, the process parameters only need to consider the mechanism by which the linear defects occur during processing. This reduces the coupling between the two elimination measures, preventing the generated elimination measures from introducing additional defects during execution.

[0066] The above technical solution identifies the causal defects of linear defects based on quantitative correlation, and reduces the number of linear defects by reducing the number of causal defects. Furthermore, based on the production mechanism of linear defects during wafer processing, the processing parameters are modified. This combination of measures reduces the number of small defects on the wafer surface and improves wafer processing quality.

[0067] Based on the above technical solution, in some possible implementations, determining the defect causing the linear defect from the associated defect types includes:

[0068] During the wafer polishing process, the filler present in the tiny cracks at a local position on the wafer surface reacts chemically and physically with the tiny cracks due to the high temperature generated by polishing to form a linear defect, and the residual defect is determined to be the causal defect of the linear defect.

[0069] Specifically, during the wafer polishing process, dislocations are generated on the silicon wafer surface. These dislocations propagate and aggregate to form larger linear cracks. Most of these cracks are microcracks that extend beyond a critical fracture size, ultimately leading to surface breakage. Furthermore, a small number of cracks, due to impurities or pinning effects between cracks, do not reach the critical size and thus do not form microcracks. Consequently, these cracks remain in their corresponding localized locations.

[0070] During the polishing process, silicon chips mixed in the polishing slurry, additives in the polishing slurry, such as acid-base regulators, and other organic media will fill these small cracks. As the polishing process progresses, these small crack locations react with the fillers at the cracks due to the local high temperature generated by polishing, thereby enhancing the adhesion of the fillers. Referring to the schematic diagrams of residual defects shown in Figures 4 (A) and (B), based on the above explanation, the morphology of this defect in the image is similar to that of linear defects. Therefore, there is a positive correlation between the number of residual defects and the number of linear defects. That is, the more residuals, such as residues caused by organic matter, the more organic matter will enter the cracks, thereby forming more linear defects.

[0071] Based on the above explanation, for the pair of defect types, residual defects and linear defects, residual defects are one of the causes of linear defects. Therefore, the causative defect is the residual defect.

[0072] Based on the above technical solution, in some possible implementations, obtaining the second cause of the linear defect during wafer processing includes:

[0073] During the wafer polishing process, the consistency between the movement direction of polishing particles at the wafer edge and the direction of the linear defect is determined as the second generation cause.

[0074] Regarding the above implementation, in combination with the aforementioned implementation, specifically, cracks with fillers should be evenly distributed on the wafer surface. In other words, linear defects should also be evenly distributed on the wafer surface. However, referring to the distribution diagram of linear defects in the image shown in FIG5 , it can be seen that: on the one hand, linear defects do not exhibit a uniform distribution characteristic, but rather exhibit a characteristic of having a smaller number of linear defects at the center of the wafer and a larger number at the edge of the wafer. On the other hand, the direction of linear defects at the edge is relatively consistent with the tangent direction of the wafer edge, while the direction of linear defects closer to the center of the wafer loses this directional regularity.

[0075] To analyze the distribution diagram of linear defects described above, we first need to analyze the polishing process. In the embodiment of the present application, as shown in FIG6 , the polishing apparatus generally comprises an upper platen 61, a wafer carrier 62, and a lower platen 63. The upper platen 61 and the lower platen 63 rotate in opposite directions, and polishing slurry flows down from the cavities 64 evenly distributed in the upper platen 61. The relative rotation of the upper and lower plates and the polishing slurry polish the wafer surface, thereby eliminating mechanical damage and defects on the wafer surface.

[0076] Based on the schematic description of the polishing apparatus described above, since the cavities 64 on the upper platen 61 are evenly distributed, the polishing slurry should also be evenly distributed across the wafer surface. However, during the polishing process, the direction of movement of the polishing particles in the polishing slurry is determined by the combined velocity direction of the centrifugal velocity v1 and the linear velocity v2 of the relative rotation of the upper and lower platens. As shown in FIG7 , starting from the moment the platen begins rotating, in the first stage, when the platen rotation duration is less than a predetermined critical time 1 / w, v2 is less than v1, and the combined velocity direction (i.e., the direction of movement of the polishing particles) deviates toward the linear velocity v2. Then, in the second stage, when the platen rotation duration exceeds the critical time, the combined velocity direction (i.e., the direction of movement of the polishing particles) deviates toward the centrifugal velocity v1. Therefore, after polishing begins, polishing particles near the center of the wafer have ample time to complete the combined velocity direction changes described in the two stages. Polishing particles closer to the wafer edge, however, only experience the combined velocity direction of the first stage before being thrown off the wafer by centrifugal force. Therefore, the movement direction of polishing particles at the wafer edge is tangential to their edge.

[0077] When the direction of movement of the polishing particles is inconsistent with the direction of the filled crack, the filled crack (i.e., linear defect) is polished away. Therefore, the closer to the center of the wafer, the fewer linear defects there are. This characteristic is verified by the intermittent linear defect morphology shown in Figure 8. In Figure 8, the linear defect is interrupted into multiple defects. This is because the direction of movement of the polishing particles is not parallel to the direction of the linear defect, causing the polishing particles to polish away the defect laterally. However, since the polishing particles are not densely distributed and there are gaps between the particles, the linear defect is not completely polished away, resulting in an intermittent morphology.

[0078] When the movement direction of the polishing particles is consistent with the direction of the crack with filler, the linear defects in the gaps will not be polished away due to the gaps between the polishing particles. Therefore, the linear defects are distributed along the tangent of the wafer edge. That is, most of the linear defects on the wafer surface that are inconsistent with the movement direction of the polishing particles will be polished away, and only the linear defects at the edge of the wafer and along the tangent direction will not be polished away.

[0079] In summary, the consistency between the movement direction of the polishing particles at the wafer edge and the direction of the linear defect can be determined as another cause of the linear defect.

[0080] Based on the above solution and its implementation, in some possible implementations, generating, for the first cause and the second cause, a first elimination measure for reducing the number of defects caused by the cause and a second elimination measure for instructing modification of processing parameters during wafer processing, respectively, includes:

[0081] According to the first generation cause, determining that the first elimination measure is to reduce the residual defect by reducing the amount of organic matter residue on the wafer surface;

[0082] According to the second generation cause, it is determined that the second elimination measure is to change the movement trajectory of the polishing particles at the edge of the wafer.

[0083] Regarding the above example, it should be noted that after determining the cause of the linear defect through the above solution, measures to eliminate the linear defect can be determined based on the cause. The first elimination measure for the first cause, in order to reduce the amount of residual organic matter on the wafer surface, can be used to reduce the waiting time between the polishing process (the final machining step) and the cleaning process. This reduces the amount of residual organic matter on the wafer surface and prevents the organic matter from filling the cracks.

[0084] As a second solution to the second cause, the shape of the polishing particles can be designed to change their trajectory, disrupting the consistency of their directional distribution, thereby uniformly polishing and eliminating linear defects in all directions on the wafer surface. In some examples, polishing particles with inconsistent end surface areas can be used to polish the wafer surface during the wafer polishing process to change the trajectory of the polishing particles at the wafer edge. For example, the black truncated spherical polishing particles shown in Figure 9 have different end surfaces at both ends. One end has a larger contact surface, resulting in greater friction, which enables the polishing particle to rotate itself, thereby changing the direction of movement of the polishing particle, and thus changing the direction of movement of the polishing particle at the wafer edge. In addition, if the end with the larger contact surface randomly contacts the upper or lower fixed plate, there will be a large number of polishing particles moving in opposite directions at the same time, which can disrupt the direction of movement of the polishing particles, resulting in a more uniform polishing and defect elimination effect. In addition, conical and truncated cone-shaped polishing particles are also polishing particles with inconsistent end surface areas, which will not be described in detail in the present embodiment.

[0085] In some examples, the larger end surface area represents the frictional force available to the polishing particle, which in turn determines its rotational speed, resulting in different removal effects on linear defects. In practice, polishing particles with varying end surface areas can be designed and formulated to achieve even better linear defect removal results.

[0086] Based on the same inventive concept as the aforementioned technical solution, referring to FIG10 , a device 100 for eliminating wafer surface defects provided by an embodiment of the present application is shown, which may include: a first acquisition part 1001, a determination part 1002, a second acquisition part 1003, and a measure generation part 1004, wherein:

[0087] The first acquisition part 1001 is configured to: acquire associated defect types having a quantity correlation with linear defects;

[0088] The determining part 1002 is configured to determine a causal defect of the linear defect from the associated defect types; wherein the causal defect is a first cause of the linear defect;

[0089] The second acquiring part 1003 is configured to acquire a second cause of the linear defect during wafer processing;

[0090] The measure generating part 1004 is configured to generate a first elimination measure for reducing the number of the causal defects and a second elimination measure for indicating modification of processing parameters during wafer processing based on the first cause and the second cause; wherein the first elimination measure and the second elimination measure can reduce the number of linear defects on the wafer surface.

[0091] In some examples, in the defect type pair, the number of the linear defects is positively correlated with the number of the cause defects.

[0092] In some examples, in the pair of defect types, the causal defect is a residue defect.

[0093] In some examples, the determining portion 1002 is configured to:

[0094] During the wafer polishing process, the filler present in the tiny cracks at a local position on the wafer surface reacts chemically and physically with the tiny cracks due to the high temperature generated by polishing to form a linear defect, and the residual defect is determined to be the causal defect of the linear defect.

[0095] In some examples, the second obtaining portion 1003 is configured to:

[0096] During the wafer polishing process, the consistency between the movement direction of polishing particles at the wafer edge and the direction of the linear defect is determined as the second generation cause.

[0097] In some examples, the measure generation portion 1004 is configured to:

[0098] According to the first generation cause, determining that the first elimination measure is to reduce the residual defect by reducing the amount of organic matter residue on the wafer surface;

[0099] According to the second generation cause, it is determined that the second elimination measure is to change the movement trajectory of the polishing particles at the edge of the wafer.

[0100] In some examples, the second elimination measure includes:

[0101] During the wafer polishing process, polishing particles with inconsistent end surface areas are used to polish the wafer surface to change the movement trajectory of the polishing particles at the edge of the wafer.

[0102] Please refer to Figure 11, which shows a block diagram of a computing device provided by an exemplary embodiment of the present application. The computing device in the present application may include one or more of the following components: a processor 1110 and a memory 1120.

[0103] Optionally, the processor 1110 utilizes various interfaces and lines to connect various parts of the entire computing device, and performs various functions of the computing device and processes data by running or executing instructions, programs, code sets, or instruction sets stored in the memory 1120, and calling data stored in the memory 1120. Optionally, the processor 1110 can be implemented in at least one hardware form of digital signal processing (DSP), field-programmable gate array (FPGA), and programmable logic array (PLA). The processor 1110 can integrate one or a combination of a central processing unit (CPU), a graphics processing unit (GPU), a neural network processing unit (NPU), and a baseband chip. Among them, the CPU mainly processes the operating system, user interface, and application programs; the GPU is responsible for rendering and drawing the content required to be displayed on the touch screen; the NPU is used to implement artificial intelligence (AI) functions; and the baseband chip is used to handle wireless communication. It is understandable that the above-mentioned baseband chip may not be integrated into the processor 1110, but may be implemented by a separate chip.

[0104] The memory 1120 may include a random access memory (RAM) or a read-only memory (ROM). Optionally, the memory 1120 includes a non-transitory computer-readable storage medium. The memory 1120 may be used to store instructions, programs, codes, code sets, or instruction sets. The memory 1120 may include a program storage area and a data storage area, wherein the program storage area may store instructions for implementing an operating system, instructions for at least one function (such as a touch function, a sound playback function, an image playback function, etc.), instructions for implementing the aforementioned various method embodiments, etc.; the data storage area may store data created according to the use of the computing device, etc.

[0105] In addition, those skilled in the art will understand that the structure of the computing device shown in the above figures does not constitute a limitation of the computing device. The computing device may include more or fewer components than shown, or a combination of certain components, or a different arrangement of components. For example, the computing device also includes a display screen, a camera assembly, a microphone, a speaker, a radio frequency circuit, an input unit, sensors (such as an accelerometer, an angular velocity sensor, a light sensor, etc.), an audio circuit, a WiFi module, a power supply, a Bluetooth module, and other components, which will not be described in detail here.

[0106] An embodiment of the present application further provides a computer-readable storage medium storing at least one instruction, wherein the at least one instruction is used to be executed by a processor to implement the method for eliminating wafer surface defects as described in the above embodiments.

[0107] An embodiment of the present application also provides a computer program product, which includes computer instructions stored in a computer-readable storage medium; a processor of a computing device reads the computer instructions from the computer-readable storage medium, and the processor executes the computer instructions, so that the computing device executes the method for eliminating wafer surface defects provided in various optional implementations of the above aspects.

[0108] Those skilled in the art will appreciate that in one or more of the above examples, the functions described in the embodiments of the present application can be implemented using hardware, software, firmware, or any combination thereof. When implemented using software, these functions can be stored in a computer-readable medium or transmitted as one or more instructions or codes on a computer-readable medium. Computer-readable media include computer storage media and communication media, wherein communication media include any media that facilitates the transmission of computer programs from one place to another. The storage medium can be any available medium that can be accessed by a general-purpose or special-purpose computer.

[0109] Based on the method for eliminating wafer surface defects described above, referring to FIG12 , a wafer manufacturing method provided by an embodiment of the present application is shown. The method may include:

[0110] S1210: Determine a first elimination measure and a second elimination measure for eliminating linear defects according to the method for eliminating wafer surface defects described in any of the aforementioned embodiments;

[0111] S1220: During wafer processing, the first elimination measure and the second elimination measure are used to eliminate linear defects on the surface of the wafer.

[0112] It should be noted that the technical solutions described in the embodiments of this application can be combined arbitrarily without conflict.

[0113] The above description is merely a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this application should be included in the scope of protection of this application. Therefore, the scope of protection of this application should be based on the scope of protection of the claims.

Claims

1. A method for eliminating wafer surface defects, the method comprising: Obtaining associated defect types that have quantitative correlation with linear defects; Determining a causal defect of the linear defect from the associated defect types; wherein the causal defect is a first cause of the linear defect; Obtaining a second cause of the linear defect during wafer processing; For the first cause and the second cause, a first elimination measure for reducing the number of defects caused by the cause and a second elimination measure for indicating modification of processing parameters during wafer processing are generated respectively; wherein the first elimination measure and the second elimination measure can reduce the number of linear defects on the wafer surface.

2. The method according to claim 1, wherein: The number of the linear defects is positively correlated with the number of the causal defects.

3. The method according to claim 1 or 2, wherein: The defect caused by the defect is a residual defect.

4. The method according to claim 3, wherein: The step of determining the cause of the linear defect from the associated defect types includes: During the wafer polishing process, the residual defect is determined to be the causative defect of the linear defect based on the chemical and physical reaction between the filler present in the micro cracks at the local position of the wafer surface and the micro cracks due to the high temperature generated by polishing to form a linear defect.

5. The method according to claim 3, wherein: The obtaining of the second cause of the linear defect during wafer processing includes: During wafer polishing, the consistency between the movement direction of polishing particles at the wafer edge and the direction of the linear defect is determined as the second generation cause.

6. The method according to claim 3, wherein: The generating of a first elimination measure for reducing the number of defects caused by the first generation cause and a second elimination measure for indicating modification of processing parameters in a wafer processing process respectively for the first generation cause and the second generation cause includes: According to the first generation cause, determining that the first elimination measure is to reduce the residual defect by reducing the amount of organic residue on the surface of the wafer; According to the second generation cause, it is determined that the second elimination measure is to change the movement trajectory of the polishing particles at the edge of the wafer.

7. The method according to claim 6, wherein: The second elimination measure comprises: During the wafer polishing process, polishing particles with inconsistent end surface areas are used to polish the wafer surface to change the movement trajectory of the polishing particles at the edge of the wafer.

8. A device for eliminating wafer surface defects, the device comprising: A first acquisition part, a determination part, a second acquisition part and a measure generation part, wherein: The first acquisition part is configured to acquire associated defect types having a quantitative correlation with linear defects; The determining part is configured to determine a causal defect of the linear defect from the associated defect types; wherein the causal defect is a first cause of the linear defect; The second acquisition part is configured to acquire a second cause of the linear defect during wafer processing; The measure generating part is configured to generate, for the first cause and the second cause, a first elimination measure for reducing the number of defects caused by the cause and a second elimination measure for indicating modification of processing parameters during wafer processing, respectively; wherein the first elimination measure and the second elimination measure can reduce the number of linear defects on the wafer surface.

9. A computing device, comprising: Processor and memory; The processor is used to execute instructions stored in the memory to implement the method for eliminating wafer surface defects as described in any one of claims 1 to 7.

10. A computer storage medium storing at least one instruction, wherein the at least one instruction is used to be executed by a processor to implement the method for eliminating wafer surface defects according to any one of claims 1 to 7.

11. A wafer manufacturing method, the method comprising: According to the method for eliminating wafer surface defects according to any one of claims 1 to 7, determining a first elimination measure and a second elimination measure for eliminating linear defects; During wafer processing, the first elimination measure and the second elimination measure are used to eliminate linear defects on the surface of the wafer.

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