Power conversion device and aircraft equipped with power conversion device

Abstract

Provided is a power conversion device (2) that is disposed between a DC source (1) and a load (3) and converts power from the DC source (1) and supplies the power to the load (3), the power conversion device (2) comprising: a plurality of semiconductor elements (Q1-Q4, Q11, Q12); and a control device (20) that generates a drive signal for controlling the ON / OFF of the gates of the semiconductor elements (Q1-Q4, Q11, Q12). The plurality of semiconductor elements (Q1-Q4, Q11, Q12) include a semiconductor element that has a different failure rate caused by cosmic rays when the same gate-off voltage is applied to the semiconductor elements on the basis of the drive signal generated by the control device (20). Gate-off voltages applied to the respective semiconductor elements (Q1-Q4, Q11, Q12) are controlled such that the failure rates of the respective semiconductor elements, said failure rates being caused by cosmic rays, are equivalent.

Description

Power conversion device and aircraft equipped with the power conversion device

[0001] The present disclosure relates to a power conversion device and an aircraft equipped with the power conversion device.

[0002] In recent years, from the perspective of environmental issues, CO2 emissions from aircraft have ２ Due to the trend toward reducing power consumption, development toward electrification is progressing. The power conversion equipment installed in electric aircraft is expected to be used in high-altitude environments, and it is known that cosmic rays (neutrons, heavy particles, etc.) can cause accidental failure of the power modules equipped with the power conversion equipment. Therefore, measures to prevent accidental failures, as well as lightweight and reliable power conversion equipment, are required.

[0003] For example, in a power conversion system composed of multiple types of semiconductor devices, if some of the semiconductor devices fail due to cosmic rays, the power conversion system will no longer function even if other semiconductor devices remain unfailed, resulting in a loss of reliability. Furthermore, using shielding material to block cosmic rays to reduce the effects of cosmic rays increases the weight of the system and reduces the fuel efficiency of aircraft. Therefore, it is necessary to ensure that the probability of random failure due to cosmic rays for the multiple types of semiconductor devices that make up the power conversion system is equivalent to that of the other semiconductor devices that make up the power conversion system.

[0004] In response to this, the applicant has proposed a power conversion device that includes a three-phase inverter and three single-phase inverters connected to the three-phase inverter, in which the failure rates due to cosmic rays of the semiconductor devices that make up the three-phase inverter and the single-phase inverter are made equal to ensure reliability (see, for example, Patent Document 1).

[0005] International Publication No. 2022 / 054155

[0006] The power conversion device disclosed in Patent Document 1 controls the voltage between the drain and source of a semiconductor device, and reduces the risk of failure of the power conversion device by equalizing the failure rate of SEB (Single Event Burnout), one of the random failures caused by cosmic rays in multiple types of semiconductor devices.In addition to SEB, random failures caused by cosmic rays include SEGR (Single Event Gate Rupture), which causes dielectric breakdown of the gate of a semiconductor device, and measures to prevent failure of SEGR are required.

[0007] The present disclosure discloses a technology for solving the above-mentioned problems, and aims to provide a power conversion device that reduces SEGR failures caused by cosmic rays and enables the device to be made lighter.

[0008] A power conversion device according to the present disclosure is a power conversion device that is disposed between a DC source and a load, converts power from the DC source, and supplies the power to the load, and includes: a power converter having a plurality of semiconductor elements whose gates are controlled to be turned on and off by a drive signal; and a control device that generates the drive signal, wherein a gate-on voltage that turns on a gate and a gate-off voltage that turns off a gate are applied to the plurality of semiconductor elements based on the drive signal generated by the control device, and the plurality of semiconductor elements include first and second semiconductor elements that have different probabilities of failure due to cosmic rays when the same gate-off voltage is applied, and the different gate-off voltages are applied to the first and second semiconductor elements so that the plurality of semiconductor elements have equal probabilities of failure due to cosmic rays for the respective gate-off voltages applied based on the drive signal.

[0009] According to the present disclosure, it is possible to provide a power conversion device that can reduce SEGR failures caused by cosmic rays and reduce the weight of the device.

[0010] 1 is a schematic configuration diagram showing the configuration of a power conversion system according to a first embodiment. FIG. 2 is a diagram showing an example of a circuit configuration of a power conversion device according to the first embodiment. FIG. 3 is a diagram showing an example of a semiconductor element used in the power conversion device according to the first embodiment. FIG. 4 is a diagram showing an example of a hardware configuration of a control device for the power conversion devices according to the first to fifth embodiments. FIG. 5 is a diagram showing the relationship between the absolute value of the gate-off voltage of a semiconductor element and the SEGR failure probability for semiconductor elements with different withstand voltages. FIG. 6 is a diagram showing the relationship between the absolute value of the gate-off voltage of a semiconductor element and the SEGR failure probability for semiconductor elements of different types. FIG. 7 is a diagram showing the relationship between the absolute value of the gate-off voltage of a semiconductor element and the SEGR failure probability for semiconductor elements of different types. FIG. 8 is a diagram showing the relationship between the absolute value of the gate-off voltage of a semiconductor element and the SEGR failure probability for semiconductor elements of different types.

[0011] The present embodiment will be described below with reference to the drawings. In each drawing, the same reference numerals indicate the same or corresponding parts. In this embodiment, cosmic rays refer to high-energy radiation including neutrons and heavy particles.

[0012] First Embodiment A power conversion device according to the first embodiment will be described below with reference to the drawings. FIG. 1 is a schematic configuration diagram showing an example of a power conversion system using a power conversion device 2 according to the first embodiment. In the diagram, the power conversion device 2 is connected between a DC source 1 and a load 3. The power conversion device 2 includes a DC / DC converter 10, which is a power converter that converts power from the DC source 1, which is a DC voltage, into a predetermined power and a different DC voltage and outputs the converted power to the load 3, and a control device 20, which is a control unit for the DC / DC converter 10. Note that in the first embodiment, the power converter will be described using the DC / DC converter 10 as an example, but the DC / DC converter 10 may also have a circuit configuration such as a DC / AC inverter.

[0013] The DC source 1 may be a battery, a battery system such as a DC power supply and a solar cell, a DC voltage obtained by rectifying an AC voltage, or a DC power distribution network. The load 3 may be a DC load, or an AC load such as a motor may be connected using an inverter that converts DC voltage to AC voltage.

[0014] 2 is a diagram showing an example of the circuit configuration of the power conversion device 2. The DC / DC converter 10 is an isolated DC / DC converter that uses a transformer Tr for insulation, and with the transformer Tr as the reference, the DC source 1 side is called the primary side of the transformer Tr, and the load 3 side is called the secondary side of the transformer Tr. The primary side of the transformer Tr forms a full bridge circuit 11 with four semiconductor elements Q1 to Q4. The secondary side of the transformer Tr forms a center tap circuit 12 with two semiconductor elements Q11 and Q12.

[0015] Here, the semiconductor elements Q1 to Q4, Q11, and Q12 have one of the following configurations: a configuration in which a diode is connected in anti-parallel to a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor), a configuration in which only a MOSFET is used, or a configuration in which a diode is connected in anti-parallel to an IGBT (Insulated Gate Bipolar Transistor). When the semiconductor elements are only MOSFETs, the body diode of the MOSFET is used instead of the anti-parallel diode.

[0016] 2, the semiconductor elements Q1 to Q4 are each made up of MOSFETs only, and the semiconductor elements Q11 and Q12 are each made up of MOSFETs with diodes connected in antiparallel. The semiconductor elements are not limited to MOSFETs using Si semiconductors, and may be replaced with MOSFETs or the like configured using wide bandgap semiconductors.

[0017] The primary side of the transformer Tr is provided with gate drive circuits Q1g to Q4g for driving four semiconductor elements Q1 to Q4, respectively. The secondary side of the transformer Tr is provided with gate drive circuits Q11g and Q12g for driving two semiconductor elements Q11 and Q12, respectively. The gate drive circuits Q1g to Q4g, Q11g, and Q12g function to output gate-on voltages for turning on and gate-off voltages for turning off the semiconductor elements Q1 to Q4, Q11, and Q12, respectively. The gate drive circuits Q1g to Q4g, Q11g, and Q12g are configured to variably output the gate-on and gate-off voltages in response to signals (drive signals) from the control device 20. Here, the gate-on voltage is a voltage equal to or greater than the threshold voltage Vth required to turn on the MOSFET, and the gate-off voltage is a voltage less than the threshold voltage Vth.

[0018] The load 3 side of center tap circuit 12 is provided with a reactor Lf and capacitor Cf as a filter section to smooth the voltage and current. Although not shown, the input side of DC / DC converter 10 may be provided with at least one or all of a normal mode filter, common mode, and smoothing capacitor. Similarly, the output side of DC / DC converter 10 may be provided with at least one or all of a normal mode filter, common mode, and smoothing capacitor.

[0019] FIG. 3 is a diagram showing an example of semiconductor elements applied to semiconductor elements Q1 to Q4 constituting a full bridge circuit 11 on the primary side of a transformer Tr and semiconductor elements Q11 and Q12 constituting a center tap circuit 12 on the secondary side of the transformer Tr. In FIG. 3, the semiconductor element is composed of a MOSFET 15 having a drain terminal D, a gate terminal G, and a source terminal S, and a body diode 16 formed in the structure of the MOSFET. MOSFET 15 may be a Si-MOSFET or, for example, a SiC-MOSFET using a wide bandgap semiconductor. Alternatively, the semiconductor element may be composed of a diode 17 connected in anti-parallel to MOSFET 15 and body diode 16 formed in the structure of the MOSFET. Diode 17 may be a Si-diode or, for example, a SiC-diode using a wide bandgap semiconductor.

[0020] <Configuration and Function of Control Device 20> Next, a description will be given of the configuration and function of the control device 20. The control device 20 is provided to control the DC / DC converter 10. An example of the hardware configuration of the control device 20 is shown in Fig. 4, and the control device 20 includes a processor 1000 such as a CPU (Central Processing Unit), a storage device 2000 that exchanges data with the processor 1000, an input / output interface 3000 that inputs and outputs signals between the processor 1000 and the outside, and the like.

[0021] The processor 1000 may include a field programmable gate array (FPGA), a digital signal processor (DSP), an application specific integrated circuit (ASIC), an integrated circuit (IC), various logic circuits, signal processing circuits, etc. Furthermore, the processor 1000 may include a plurality of processors of the same type or different types, and each process may be shared among them.

[0022] The storage device 2000 comprises a volatile storage device such as a random access memory configured to be readable and writable, and a non-volatile auxiliary storage device such as a flash memory. Alternatively, a hard disk auxiliary storage device may be used instead of the flash memory. The processor 1000 executes a program input from the storage device 2000. In this case, the program is input to the processor 1000 from the auxiliary storage device via the volatile storage device. Furthermore, the processor 1000 may output data such as calculation results to the volatile storage device of the storage device 2000, or may store the data in the auxiliary storage device via the volatile storage device.

[0023] The input / output interface 3000 is composed of, for example, an A / D converter that inputs signals output from voltage detection means, current detection means, temperature detection means, and altitude detection means that detect the environment in which the power conversion device 2 is installed, which are provided in the DC / DC converter 10, to the processor 1000, and a circuit that outputs signals to the gate drive circuit to drive each switching element.

[0024] The control device 20 performs output voltage control and current control based on, for example, the input voltage, output voltage, and current of the DC / DC converter 10. The current may be the primary current of the transformer Tr or the current of the reactor Lf.

[0025] The control device 20 outputs gate signals (drive signals) for driving the semiconductor elements Q1 to Q4 of the full-bridge circuit 11 of the DC / DC converter 10 and the semiconductor elements Q11 and Q12 of the center-tap circuit 12. The gate signals are generated using a triangular wave comparison method such as PWM (Pulse Width Modulation) control. Meanwhile, the semiconductor elements Q11 and Q12 of the center-tap circuit 12 may be synchronously rectified to reduce conduction loss due to the diode voltage. The gate signals may be generated using PFM (Pulse Frequency Modulation) control, which is a frequency control method, instead of duty cycle control using PWM control. The pulse width of the gate signal output to the full-bridge circuit 11 may be controlled to output symmetric pulses, or may be controlled to output asymmetric pulses for soft switching or the like. Furthermore, a mechanism for changing the on / off voltage of the gate drive circuit may be provided in the input / output interface 3000.

[0026] The control device 20 includes means for calculating the SEGR-induced failure rate of each of the semiconductor elements Q1 to Q4 of the full-bridge circuit 11 and the semiconductor elements Q11 and Q12 of the center tap circuit 12 of the DC / DC converter 10 from the SEGR-induced semiconductor failure data, environmental parameters, and control parameters. The environmental parameters include, for example, temperature, altitude, cosmic radiation, and atmospheric pressure. The control parameters include the drain-source voltage applied to each semiconductor element and the gate-off voltage of each semiconductor element. The cosmic radiation dose may be estimated from the altitude of the power conversion device. Although not shown in FIG. 2 , sensors for detecting the environmental parameters and control parameters are built into each element or are provided within the circuit. The SEGR-induced semiconductor failure data is data showing the relationship between each parameter and the failure rate of the semiconductor element due to SEGR, as described below. The failure rate of the semiconductor element versus gate voltage for each parameter is typically shown as a graph or map.

[0027] <Correlation Between Each Parameter and Semiconductor Element Failure Rate> Next, the correlation between each parameter and the failure rate of semiconductor elements due to SEGR generation will be described. The correlation between the amount of cosmic rays and the failure rate is such that the failure rate increases in proportion to an increase in the amount of cosmic rays. The correlation between the amount of cosmic rays and the failure rate is such that the failure rate increases in proportion to an increase in altitude, since the amount of cosmic rays increases exponentially with an increase in altitude. The correlation between the temperature and the failure rate is such that the failure rate decreases in inverse proportion to an increase in temperature. Here, temperature refers to the junction temperature of the semiconductor element or the ambient temperature, etc. The correlation between the voltage value applied between the drain and source of a semiconductor element and the failure rate is such that the failure rate increases in proportion to an increase in the drain-source voltage value. The correlation between the gate-off voltage value applied to a semiconductor element and the failure rate is such that the failure rate increases in proportion to the absolute value of the gate-off voltage value. Note that the terms "proportional" and "inversely proportional" here refer not only to a linear increase or decrease, but also to an exponential increase or decrease.

[0028] Based on the above correlation, it is possible to calculate a failure rate due to SEGR for each semiconductor element according to the environmental parameters. Then, a target failure rate is set so that the failure rates due to SEGR for each semiconductor element obtained by the calculation result become the same failure rate. The control device 20 calculates a gate-off voltage command for each semiconductor element so that the gate-off voltage of each semiconductor element becomes the target failure rate, and outputs the calculated signal to the gate drive circuit of each semiconductor element. Although the semiconductor elements may be of the same type or different types, the gate-on voltage command is input to the gate drive circuit that drives each semiconductor element so that the semiconductor elements become the same target failure rate, so that the semiconductor failure rates due to SEGR for each semiconductor element can be made equal according to the environmental parameters.

[0029] If a target failure rate is determined and then the gate-off voltage of each semiconductor element is calculated according to the target failure rate, there may be cases where a solution for the gate-off voltage that satisfies the target failure rate does not exist. Therefore, the range of gate-off voltages for each semiconductor element and the settable failure rates can be obtained in advance, and a range that achieves an equivalent failure rate can be determined. The gate-on voltage is generally controlled within a range from the gate threshold voltage Vth to the maximum rated gate-source voltage VGSS_P, which is determined for each semiconductor device. The gate threshold voltage Vth is the voltage at which current begins to flow between the drain and source when a voltage is applied between the gate and source. Furthermore, the gate threshold voltage Vth tends to decrease as the junction temperature increases. The maximum rated gate-source voltage VGSS_P is the maximum voltage allowed between the gate and source when the drain and source are short-circuited. The gate-off voltage is generally controlled within a range from the maximum rated gate-source negative bias voltage VGSS_N to less than the gate threshold voltage Vth, which is determined for each semiconductor device. The maximum rated gate-source negative bias voltage VGSS_N is the maximum value of the negative voltage allowed between the gate and the source.

[0030] Next, we will explain the relationship between the probability of occurrence of random failure (SEGR) of semiconductor elements due to cosmic rays and the absolute value of the gate-off voltage for different types of semiconductor elements. For example, cosmic rays are incident on a SiC-MOSFET with a gate-off voltage of -5V applied between the gate and source. When cosmic rays pass through the neck region between the source and drain directly below the gate, an ionization effect generates electron-hole pairs, and the electrons or holes move toward the drain and gate, accumulating at the interface between the semiconductor SiC and the gate oxide film. At this time, because electrons or holes are accumulated in the gate, the resulting electric field causes dielectric breakdown of the oxide film, shorting the gate and semiconductor SiC and resulting in element destruction. This is the SEGR phenomenon, in which semiconductor elements are destroyed by cosmic rays.

[0031] In this case, the larger the absolute value of the gate-off voltage, the higher the probability that the gate and semiconductor will short-circuit when cosmic rays are incident. This failure due to SEGR occurs probabilistically, and as mentioned above, the failure probability increases in proportion to the amount of cosmic rays, so it is known that the failure probability increases with increasing altitude.

[0032] <Method of Adjusting Target Failure Rate and Gate-Off Voltage> Below, a method of adjusting the target failure rate and gate-off voltage between different types of semiconductor elements will be explained using diagrams. Here, different types refer to semiconductor element structures that are different, such as IGBTs and MOSFETs, semiconductor element materials that are different, such as Si-MOSFETs and SiC-MOSFETs, semiconductor element types with different model numbers, and semiconductor element types with different breakdown voltages. As will be described later, these types have different correlation curves in the relationship between the absolute value of the gate-off voltage and the SEGR occurrence probability.

[0033] 5 is a diagram showing the relationship between the absolute value of the gate-off voltage and the SEGR occurrence probability for two semiconductor elements QH and QL that have different breakdown voltages but the same drain-source voltage. The semiconductor elements QH and QL have the same semiconductor element structure, materials, etc., except for the breakdown voltage. For example, when the absolute value of the gate-off voltage of each semiconductor element is Va, the lower the semiconductor element breakdown voltage, the higher the SEGR occurrence probability. Furthermore, the SEGR occurrence probability of these semiconductor elements decreases exponentially as the absolute value of the gate-off voltage decreases.

[0034] 5, if the failure probability of semiconductor element QH is set to a set value A, the absolute value of the gate-off voltage of semiconductor element QH at set value A is Va. If semiconductor element QL is driven at gate-off voltage Va, the probability of SEGR occurring will be higher than that of semiconductor element QH. Here, by lowering the absolute value of the gate-off voltage of semiconductor element QL to Vb, the failure probability can be adjusted to set value A. In other words, the failure probabilities of semiconductor elements QH and QL can be made equal.

[0035] 6 and 7 are diagrams showing the relationship between the absolute value of the gate-off voltage and the SEGR occurrence probability for two semiconductor elements QA and QB, which have the same withstand voltage but different types other than the withstand voltage and have the same drain-source voltage. In FIG. 6, when the absolute value of the gate-off voltage of the semiconductor element is Vc, the SEGR occurrence probability of semiconductor element QB is higher than that of semiconductor element QA. If the failure probability of semiconductor element QA is set to a set value B, the absolute value of the gate-off voltage of semiconductor element QA at set value B is Vc. The failure probability of semiconductor element QB can be adjusted to set value B by lowering the absolute value of the gate-off voltage to Vd.

[0036] 7 shows the same curve as FIG. 6, but when the failure rate is set to a set value C that is smaller than set value B, the absolute value of the gate-off voltage of semiconductor element QA becomes Ve, but the SEGR occurrence probability is such that the failure rate of semiconductor element QA is set value C, and the absolute value of the gate-off voltage of semiconductor element QB is increased to Vf, thereby adjusting the SEGR occurrence probability to set value C. In other words, semiconductor elements QA and QB can be adjusted to have the same failure probability.

[0037] 8 shows the relationship between the absolute value of the gate-off voltage and the SEGR occurrence probability for two semiconductor elements QA and QB, which have the same MOSFET structure but are made of different materials and have different element breakdown voltages and drain-source voltages Vds. In the figure, semiconductor element QA is a Si-MOSFET with a breakdown voltage of 300 V and a drain-source voltage Vds of 50 V, while semiconductor element QB is a SiC-MOSFET with a breakdown voltage of 1.2 kV and a drain-source voltage Vds of 600 V. When an absolute value Vg of the gate-off voltage is applied, the SEGR occurrence probability of semiconductor element QB is greater than that of semiconductor element QA. By setting the failure rate set value E, the absolute value of the gate-off voltage of semiconductor element QB to Vh and the absolute value of the gate-off voltage of semiconductor element QA to Vg, which is greater than Vh, the failure probabilities of both elements can be made equal.

[0038] As described above, according to the first embodiment, a power conversion device is provided between a DC source and a load, converting power from the DC source and supplying it to the load, the power conversion device including a plurality of semiconductor elements whose gates are controlled to be turned on and off by a drive signal, and a control device that generates the drive signal, wherein a gate-on voltage that turns on the gate of each of the plurality of semiconductor elements and a gate-off voltage that turns off the gate of each of the plurality of semiconductor elements are applied based on the drive signal generated by the control device, and the plurality of semiconductor elements include first and second semiconductor elements that have different cosmic ray failure probabilities when the same gate-off voltage is applied, and the first and second semiconductor elements are configured to have the different gate-off voltages applied to them so that the cosmic ray failure probabilities for each of the plurality of semiconductor elements are equalized for each gate-off voltage applied based on the drive signal. This configuration eliminates variations in the SEGR failure probabilities of the plurality of semiconductor elements and equalizes the SEGR failure probabilities, thereby reducing the SEGR failure probability of the power conversion device, thereby ensuring reliability and suppressing increases in the size, weight, and cost of the device.

[0039] It goes without saying that when adjusting the failure probability to be the same, it is desirable to adjust the gate-off voltage to match that of an element with a low failure probability. Furthermore, "equal" does not necessarily mean a perfect match, but also includes a slight difference within the range where the same effect is achieved.

[0040] Second Embodiment. A power conversion device according to a second embodiment will be described below with reference to the drawings. In the first embodiment, the gate-off voltages for different types of semiconductor elements were adjusted to equalize the SEGR occurrence probabilities. In the second embodiment, the on-resistance values ​​resulting from conduction losses that occur while current is flowing through each semiconductor element are further adjusted by the gate-on voltage, thereby equalizing the losses in each semiconductor element and equalizing the failure rates caused by heat generation due to losses for each semiconductor element, thereby improving reliability. The configuration of the power conversion device is the same as that shown in FIG. 2 of the first embodiment, and therefore a description thereof will be omitted.

[0041] FIG. 9 is a diagram showing the relationship between the absolute value of the gate-on voltage and the on-resistance for different types of semiconductor elements QC and QD. In FIG. 9, semiconductor element QC is a Si-MOSFET with a breakdown voltage of 300 V, and semiconductor element QD is a SiC-MOSFET with a breakdown voltage of 1.2 kV. When the absolute value of the gate-on voltage of semiconductor element QC is Vj, the on-resistance is Rd. When the absolute value of the gate-on voltage of semiconductor element QD is Vj, the on-resistance is Ra. To make the on-resistances of semiconductor element QC and semiconductor element QD the same, the absolute value of the gate-on voltage of semiconductor element QC is changed to Vi, which results in the on-resistance Rb, and the absolute value of the gate-on voltage of semiconductor element QD is changed to Vk, which results in the on-resistance Rb. In other words, the on-resistances of different types of semiconductor elements can be made the same by adjusting the absolute value of the gate-on voltage. As described above, to turn on the gate, that is, to allow current to flow between the drain and source, it is necessary to apply a gate-on voltage equal to or greater than the gate threshold voltage Vth between the gate and source of the semiconductor element.

[0042] In addition, the loss Eq of the semiconductor element is expressed as follows, where Rq is the on-resistance of the semiconductor element and Iq is the current flowing through the semiconductor element: Eq = Rq x Iq ２ ...expressed as formula (1) Therefore, in order to equalize the losses between different types of semiconductor elements, it is sufficient to detect the current Iq flowing through the semiconductor element and adjust the on-resistance Rq.

[0043] For example, let us use semiconductor element QD as semiconductor elements Q1 to Q4 in FIG. 2 and the absolute value of the gate-on voltage be Vj, and semiconductor element QC as semiconductor elements Q11 and Q12 in FIG. 2 and the absolute value of the gate-on voltage be Vj. In this case, if the losses of semiconductor elements Q1 to Q4 are greater than the losses of semiconductor elements Q11 and Q12, then increasing the absolute value of the gate-on voltage of semiconductor element QD, which is semiconductor elements Q1 to Q4, from Vj to Vk will reduce the on-resistance from Ra to Rb, thereby suppressing the losses. Furthermore, if the absolute value of the gate-on voltage is Vk but the losses of semiconductor elements Q1 to Q4 are greater than the losses of semiconductor elements Q11 and Q12, then the absolute value of the gate-on voltage of semiconductor elements Q1 to Q4 can be increased to Vm, further reducing the on-resistance to Rc, thereby suppressing the losses.

[0044] 2, the absolute value of the gate-on voltage is Vj, and semiconductor element QC is the semiconductor elements Q11 and Q12 of FIG. 2, and the absolute value of the gate-on voltage is Vj. In this case, if the losses in semiconductor elements Q11 and Q12 are greater than the losses in semiconductor elements Q1 to Q4, the absolute value of the gate-on voltage of semiconductor element QC, which is semiconductor elements Q11 and Q12, can be increased from Vj to Vk, thereby lowering the on-resistance from Rd to Re and suppressing the losses. Furthermore, if the absolute value of the gate-on voltage is Vk but the losses in semiconductor elements Q11 and Q12 are greater than the losses in semiconductor elements Q1 to Q4, the absolute value of the gate-on voltage of semiconductor elements Q11 and Q12 can be increased to Vm, further lowering the on-resistance to Rf, and suppressing the losses.

[0045] In the configuration of FIG. 2, the current flowing through the semiconductor elements is determined according to the turns ratio of the transformer Tr between the full bridge circuit 11 and the center tap circuit 12. Therefore, the current flowing through the semiconductor elements Q11 and Q12 using the semiconductor element QC is larger than the current flowing through the semiconductor elements Q1 to Q4 using the semiconductor element QD, and the loss can be significantly reduced simply by slightly reducing the on-resistance of the semiconductor elements Q11 and Q12.

[0046] The gate-on voltage is adjusted using the control device 20, as in the first embodiment. Although not shown in Fig. 2, loss in the semiconductor elements, i.e., the amount of heat generated, is detected by providing a temperature sensor built into or adjacent to each semiconductor element, and inputting the detected value into the control device 20 for calculation.

[0047] As described above, according to the second embodiment, in the power conversion device of the first embodiment, the heat generation amount due to loss of the plurality of semiconductor elements is controlled by calculating the heat generation amount due to loss of the first and second semiconductor elements based on the on-resistances of the first and second semiconductor elements, which are different from each other when the same gate on-voltage is applied. This makes it possible to equalize the heat generation amount due to loss of the plurality of semiconductor elements, smooth the heat generation distribution, and equalize the probability of failure due to heat generation. As a result, it is possible to suppress increases in size, weight, and cost of devices such as coolers while ensuring reliability in the power conversion device.

[0048] Furthermore, if the current flowing through each semiconductor element is detected and the amount of heat generated is calculated based on the current and the on-resistance, it becomes possible to easily control the gate on voltage so that the amounts of heat generated are equal.

[0049] Furthermore, when the power converter of the power conversion device is an isolated DC / DC converter having a full bridge circuit and a center tap circuit sandwiched between them by a transformer, the current flowing through the semiconductor elements of the full bridge circuit and the semiconductor elements of the center tap circuit is determined by the turns ratio of the transformer. Therefore, if the semiconductor elements that make up the full bridge circuit are made of wide bandgap semiconductors and the semiconductor elements that make up the center tap circuit are made of Si semiconductors, it becomes possible to more easily control the amount of heat generated.

[0050] It goes without saying that when adjusting the semiconductor loss, i.e., the heat generation, to be equivalent, it is desirable to adjust the gate-on voltage to match that of an element with low loss. Furthermore, "equivalent" does not necessarily mean a perfect match, but also includes cases where there is some difference as long as the same effect is achieved.

[0051] Third Embodiment. A power conversion device according to a third embodiment will be described below with reference to the drawings. In the second embodiment, the on-resistance value resulting from conduction loss occurring while current is flowing through each semiconductor element is adjusted by the gate-on voltage, thereby equalizing the losses in each semiconductor element and making the failure rates due to conduction loss equal for each semiconductor element. In the third embodiment, the gate-on voltage value is adjusted according to the output power and the amount of drain current flowing through the semiconductor element. When the output power is high, i.e., the amount of conduction current is large, the gate-on voltage is increased to decrease the gate-on resistance and suppress heat generation, thereby making the failure rates due to conduction loss equal for each semiconductor element. Note that the configuration of the power conversion device is the same as that shown in FIG. 2 of the first embodiment, and therefore a description thereof will be omitted.

[0052] 10 is a diagram showing the relationship between the output power, the effective values ​​of the drain currents flowing through the semiconductor elements Q1 to Q4 and the semiconductor elements Q11 and Q12, and the gate-on voltages of the respective semiconductor elements in the power conversion device 2 according to the third embodiment. When the input voltage and output voltage of the power conversion device 2 are constant and power is required for a load, the output power and the amount of drain current of the semiconductor elements increase (time 0 to t1), as shown in FIG. 10. Thereafter, a high output power Ph is supplied to the load for a certain period from time t1 to time t2, and an output power P0 lower than the output power Ph is supplied to the load from time t2 to time t3.

[0053] When each of the semiconductor elements Q1 to Q4, Q11, and Q12 is driven at a constant gate-on voltage to achieve this output power pattern, the loss Eq of the semiconductor element increases in proportion to the square of the drain current, as shown in equation (1). Therefore, since the drain current is also large from time t1 to time t2, which is the period of high output power Ph, the loss Eq of the semiconductor element can be suppressed by increasing the gate-on voltage of the semiconductor element and lowering the on-resistance of the semiconductor element, as shown in FIG.

[0054] The gate-on voltages of the semiconductor elements Q1 to Q4, Q11, and Q12 may be adjusted individually. As shown in FIG. 10 and as described above, the drain current flowing through the semiconductor elements Q11 and Q12 of the center tap circuit 12 in the power conversion device 2 is larger, so the gate-on voltages of the semiconductor elements Q11 and Q12 may be adjusted to be larger.

[0055] 10 , the output power pattern shows that from time t3 to time t4, the output power increases again from output power P0 to output power Ph, and then the output power decreases to 0. Since the effective value of the drain current also increases in the period from time t3 to time t4, the gate on voltage of the semiconductor element is increased as in the period from time t1 to time t2, and the on resistance of the semiconductor element is reduced, thereby suppressing the loss Eq of the semiconductor element.

[0056] As described above, according to the third embodiment, in a power conversion device configured using a plurality of semiconductor elements, the loss (heat generation amount) of the semiconductor element can be suppressed by adjusting the on-resistance using the gate on-voltage applied according to the output power and the drain current of the semiconductor element. Therefore, it is possible to provide a highly efficient and reliable power conversion device that enables a predetermined output power and has a reduced failure rate due to heat generation.

[0057] 10 corresponds to the output power pattern required to be supplied to a load during a series of operations from takeoff ascent to cruising and then takeoff descent when the power conversion device 2 is installed on an aircraft. Therefore, it is possible to control the gate-on voltages of the multiple semiconductor elements of the power conversion device in accordance with the flight of the aircraft, thereby suppressing the amount of heat generated due to loss in the semiconductor elements.

[0058] Fourth Embodiment. An aircraft according to a fourth embodiment will now be described with reference to the drawings. FIG. 11 is a block diagram showing an example of an aircraft 22 according to the fourth embodiment, and is a state in which a power conversion device 2 according to any one of the first to third embodiments is installed. The aircraft 22 is an electric aircraft, and its propulsion power system 100 includes a power source 21, a DC source 1 connected to the power source 21, a DC / DC converter 10 connected to the DC source 1 and converting the DC power to a predetermined voltage, an inverter 30 converting the DC power stepped down by the DC / DC converter 10 into AC power, a load 31 supplied with power from the inverter 30, and a control device 20 controlling the DC / DC converter 10 and the inverter 30. Here, the load 31 is a propulsion load for generating propulsion force, such as an electric motor. Unlike the first embodiment, the control device 20 controls the operation of not only the DC / DC converter 10 but also the inverter 30.

[0059] The DC / DC converter 10 of the power conversion device 2 according to the first to third embodiments is used as the DC / DC converter 10 for an electric aircraft in a propulsion power system 100 mounted on an aircraft 22. Because cosmic rays increase in intensity in proportion to altitude, when a conventional power conversion device is mounted on an object flying in the sky, such as an aircraft, the probability of failure due to SEGR increases compared to when the power conversion device is used on the ground. By mounting the power conversion device 2 according to the first embodiment, which takes into account failure due to cosmic rays, on a propulsion power system 100, the probability of failure of semiconductor elements used in the DC / DC converter 10 for an electric aircraft can be reduced, and the probability of failure of the semiconductor elements can be kept the same, thereby preventing increases in size, weight, and cost of the device while ensuring reliability.

[0060] Furthermore, by installing the power conversion device 2 described in the second and third embodiments in a propulsion power system 100, it is possible to further reduce losses in semiconductor elements and reduce heat generation, thereby preventing increases in size, weight, and cost of devices including coolers while ensuring reliability. This also improves the fuel efficiency of the electric aircraft. In particular, as shown in the output power pattern in Figure 10, it is possible to control the output power according to the aircraft's flight and reduce heat generation.

[0061] Furthermore, by controlling the gate-off voltage of the semiconductor elements used in the inverter 30 so as to equalize the failure probabilities, as described in the first to third embodiments, it is possible to reduce the failure probability of the inverter 30 and suppress increases in the size, weight, and cost of the device while ensuring reliability. Furthermore, by controlling the semiconductor elements used in the inverter 30 to reduce the on-resistance as described in the second and third embodiments, it is possible to reduce loss and heat generation in the semiconductor elements and suppress increases in the size, weight, and cost of the device, including the cooler, while ensuring reliability. This also improves the fuel efficiency of the electric aircraft.

[0062] Fifth Embodiment. An aircraft according to a fifth embodiment will now be described with reference to the drawings. FIG. 12 is a diagram showing an example of an aircraft 25 according to the fifth embodiment, and is a block diagram showing a state in which a power conversion device 2 according to any one of the first to third embodiments is installed. The aircraft 25 is an electric aircraft, and its equipment power system 200 includes a power source 23, an AC / DC converter 24 connected to the power source 23 and converting AC power to DC power, a DC source 1 connected to the AC / DC converter 24, a DC / DC converter 10 connected to the DC source 1 and converting the DC power to a predetermined voltage, an inverter 30 converting the DC power stepped down by the DC / DC converter 10 into AC power, a load 31 supplied with power from the inverter 30, and a control device 20 controlling the DC / DC converter 10, the inverter 30, and the AC / DC converter 24. Here, the load 31 is an equipment load, and refers to, for example, an electric motor used to drive an air conditioner, an engine starter, or an auxiliary power device. Furthermore, unlike the first embodiment, the control device 20 controls the operation of not only the DC / DC converter 10 but also the inverter 30 and the AC / DC converter 24.

[0063] As in the fourth embodiment, the DC / DC converter 10 of the power conversion device 2 according to any one of the first to third embodiments is used as the DC / DC converter 10 for an electric aircraft in an equipment power system 200 mounted on an aircraft 25. Since cosmic rays increase in proportion to altitude, when a conventional power conversion device is mounted on an object that flies in the sky, such as an aircraft, the probability of failure due to SEGR generation increases compared to when the power conversion device is used on the ground. By mounting the conventional power conversion device on an equipment power system 200 that includes the power conversion device 2 according to the first embodiment, which takes into account failure due to cosmic rays, the same effects as those of the fifth embodiment can be achieved.

[0064] Furthermore, by installing the power conversion device 2 described in the second and third embodiments in the equipment power system 200, it is possible to further reduce losses in the semiconductor elements and reduce the amount of heat generated, thereby preventing increases in the size, weight, and cost of the device, including the cooler, while ensuring reliability. This also improves the fuel efficiency of the electric aircraft. In particular, as shown in the output power pattern in Figure 10, it is possible to control the output power according to the aircraft's flight and reduce the amount of heat generated.

[0065] Furthermore, by controlling the gate-off voltage of the semiconductor elements used in the AC / DC converter 24 and the inverter 30 so as to equalize the failure probabilities, as described in the first to third embodiments, it is possible to reduce the failure probability of the AC / DC converter 24 and the inverter 30, and to prevent increases in the size, weight, and cost of the device while ensuring reliability. Furthermore, by controlling the semiconductor elements used in the AC / DC converter 24 and the inverter 30 to reduce the on-resistance as described in the second and third embodiments, it is possible to reduce loss and heat generation in the semiconductor elements, and to prevent increases in the size, weight, and cost of the device, including the cooler, while ensuring reliability. This also improves the fuel efficiency of the electric aircraft.

[0066] Other Embodiments (1) When multiple power conversion devices are provided, such as in the aircraft according to the fourth and fifth embodiments, it is desirable to design the power conversion devices so that the failure probabilities of semiconductor elements are equalized between the power conversion devices.

[0067] (2) In the above embodiment, the DC / DC converter 10 is an isolated DC / DC converter including the full-bridge circuit 11 and the center tap circuit 12 connected via the transformer Tr. However, the present invention is not limited to this. A non-isolated DC / DC converter may also be used, and multiple types of DC / DC converters may be installed on the aircraft.

[0068] Although various exemplary embodiments and examples are described in this disclosure, the various features, aspects, and functions described in one or more embodiments are not limited to the application of a particular embodiment, but may be applied to the embodiments alone or in various combinations. Therefore, countless variations not illustrated are anticipated within the scope of the technology disclosed in this specification. For example, this includes cases where at least one component is modified, added, or omitted, or where at least one component is extracted and combined with components of another embodiment.

[0069] 1: DC source, 2: Power conversion device, 3, 31: Load, 10: DC / DC converter, 11: Full bridge circuit, 12: Center tap circuit, 15: MOSFET, 16: Body diode, 17: Diode, 20: Control device, 21: Power source, 22: Aircraft, 23: Power source, 24: AC / DC converter, 25: Aircraft, 30: Inverter, 100: Propulsion power system, 200: Equipment power system, 1000: Processor, 2000: Storage device, 3000: Input / output interface, Cf: Capacitor, Lf: Reactor, Q1 to Q4, Q11, Q12, QH, QL, QA, QB, QC, QD: Semiconductor elements, Tr: Transformer.

Claims

1. A power conversion device that is arranged between a DC source and a load, converts power from the DC source and supplies it to the load, comprising: a power converter having a plurality of semiconductor elements whose gates are controlled to be turned on and off by a drive signal; and a control device that generates the drive signal, wherein a gate-on voltage that turns on a gate and a gate-off voltage that turns off a gate are applied to the plurality of semiconductor elements based on the drive signal generated by the control device, the plurality of semiconductor elements include a first semiconductor element and a second semiconductor element that have different probabilities of failure due to cosmic rays when the same gate-off voltage is applied to the plurality of semiconductor elements, and the different gate-off voltages are applied to the first semiconductor element and the second semiconductor element so that the plurality of semiconductor elements have equal probabilities of failure due to cosmic rays for the respective gate-off voltages applied based on the drive signal.

2. The power conversion device according to claim 1, wherein the first semiconductor element and the second semiconductor element have different on-resistances when the same gate-on voltage is applied, and different gate-on voltages are applied to the first semiconductor element and the second semiconductor element to control the amount of heat generated due to losses in the first semiconductor element and the second semiconductor element, which is calculated based on the respective on-resistances.

3. A power conversion device as described in claim 2, wherein the gate-on voltage is applied to each of the first semiconductor element and the second semiconductor element so that the amounts of heat generated due to losses in the first semiconductor element and the second semiconductor element, calculated based on the current flowing through each of the first semiconductor element and the second semiconductor element and the on-resistance, are equivalent.

4. The power conversion device according to any one of claims 1 to 3, wherein the power converter is an isolated DC / DC converter having a full bridge circuit and a center tap circuit sandwiching a transformer.

5. The power conversion device according to claim 4, wherein the full bridge circuit is composed of a plurality of the first semiconductor elements, and the center tap circuit is composed of a plurality of the second semiconductor elements.

6. A power conversion device according to any one of claims 1 to 5, wherein the first semiconductor element and the second semiconductor element differ in any one of the types of voltage resistance, semiconductor element structure, semiconductor element material, and model number.

7. A power conversion device according to any one of claims 1 to 5, wherein the first semiconductor element is made of a wide band gap semiconductor, and the second semiconductor element is made of a Si semiconductor.

8. An aircraft equipped with a power conversion device according to any one of claims 1 to 7.

9. An aircraft equipped with a power conversion device as described in claim 8, which controls the gate-on voltage of the first semiconductor element and the second semiconductor element of the power conversion device in accordance with the flight of the aircraft, thereby suppressing the amount of heat generated due to losses in the first semiconductor element and the second semiconductor element.

Images