Switching element drive device

Abstract

This switching element drive device for applying a gate voltage to a gate terminal of a semiconductor switching element comprises: a switching speed setting unit for setting a switching speed of the semiconductor switching element to any one of a plurality of speeds; and a diagnosis unit for diagnosing a speed setting operation by the switching speed setting unit. The diagnosis unit includes: a calculation unit for calculating a switching time from one to the other of an ON / OFF state of the semiconductor switching element in an operation condition in which a mirror effect does not occur; and a determination unit for determining an abnormality of the speed setting operation on the basis of the calculated switching time.

Description

Switching element driver

[0001] The present invention relates to a switching element driving device.

[0002] Conventionally, in inverter gate drive circuits, the switching speed of each inverter switching element is set so that surge voltages due to switching within the operating voltage and current range do not exceed the breakdown voltage of the switching element. However, inverter switching elements operate frequently under relatively low current conditions, and under these current conditions, surge voltages are reduced and the switching speed can be increased. Therefore, a method of switching the switching speed depending on the current conditions is known as a means of reducing switching losses and improving inverter efficiency (see Patent Document 1).

[0003] For functional safety reasons, it is necessary to diagnose whether switching speed is properly controlled. In the technology of Patent Document 1, whether the resistor switching timing is properly controlled is diagnosed by checking whether the time lag between the timing at which the voltage at the current sense terminal measured during current flow exceeds a threshold and the timing at which gate resistor switching control is performed is within an allowable range.

[0004] Japanese Patent No. 5810952

[0005] When a switching element is energized, the gate charge fluctuates according to the current due to the Miller effect. Therefore, the timing at which the measured voltage at the current sense terminal exceeds the threshold also shifts according to the current. In particular, the technique described in Patent Document 1 uses a technique called active gate control, which switches the gate resistance value during the switching period. This makes it difficult to diagnose the switching speed change when the current fluctuates constantly.

[0006] A switching element driving device according to an aspect of the present invention is a switching element driving device that applies a gate voltage to the gate terminal of a semiconductor switching element, and includes: a switching speed setting unit that sets the switching speed of the semiconductor switching element to one of a plurality of speeds; and a diagnosis unit that diagnoses the speed setting operation by the switching speed setting unit, wherein the diagnosis unit includes: a calculation unit that calculates the switching time required for the ON / OFF state of the semiconductor switching element to switch from one to the other under operating conditions in which the Miller effect does not occur; and a judgment unit that judges whether there is an abnormality in the speed setting operation based on the calculated switching time.

[0007] According to the present invention, it is possible to accurately diagnose the switching operation of the switching speed.

[0008] 1 is a diagram showing a schematic configuration of a power conversion device that supplies three-phase AC current to a three-phase AC motor. FIG. 2 is a diagram showing the configuration of one phase of the inverter shown in FIG. 1. FIG. 3 is a diagram explaining constant voltage driving. FIG. 4 is a diagram explaining constant current driving. FIG. 5 is a diagram explaining changes in surge voltage due to switching of switching speed. FIG. 6 is a diagram explaining changes in loss due to switching of switching speed. FIG. 7 is a diagram showing gate voltage waveforms at turn-off when the switching speed is low. FIG. 8 is a diagram showing gate voltage waveforms at turn-off when the switching speed is high. FIG. 9 is a diagram showing an example of gate voltage waveforms at turn-off when there is no element conduction. FIG. 10 is a flowchart showing an example of diagnostic processing. FIG. 11 is a diagram explaining diagnostic thresholds. FIG. 12 is a diagram explaining current flow in periods 1 and 2 during current supply operation. FIG. 13 is a diagram explaining current flow in period 3 during current supply operation. FIG. 14 is a diagram explaining example 2 of measures to be taken when diagnosing an abnormality.

[0009] Hereinafter, an embodiment of a semiconductor device according to the present invention will be described with reference to the drawings. The following description and drawings are examples for explaining the present invention, and appropriate omissions and simplifications have been made for clarity of explanation. Furthermore, in the following description, identical or similar elements and processes are given the same reference numerals, and duplicate explanations may be omitted. Note that the content described below merely shows an example of an embodiment of the present invention, and the present invention is not limited to the following embodiment, and can be implemented in various other forms.

[0010] 1 is a diagram showing a schematic configuration of a power conversion device 200 that supplies three-phase AC current to a three-phase AC motor M. The power conversion device 200 converts DC power from a battery 300 into AC power and supplies it to the motor M. The power conversion device 200 includes an inverter 201, a control circuit 202, and a gate drive circuit 203. The control circuit 202 is configured with a microcomputer, a CPU, or the like.

[0011] The inverter 201 includes six switching elements S1 to S6 that constitute upper and lower phase arms. A control circuit 202 generates a PWM signal for supplying three-phase AC current based on the magnetic pole position of the rotor of the motor M detected by a magnetic pole position sensor 301 and the motor current value detected by a current sensor 302. The PWM signal generated by the control circuit 202 is input to a gate drive circuit 203 that includes a gate drive IC.

[0012] Six gate drive ICs (not shown) corresponding to the six switching elements S1 to S6 are provided in the gate drive circuit 203. The gate drive circuit 203 generates gate drive signals for driving the respective switching elements S1 to S6 of the inverter 201 based on the PWM signal, and outputs the signals to the respective switching elements S1 to S6.

[0013] 2 shows switching elements S1 and S2 that constitute the upper and lower arms of one phase (U-phase) of inverter 201 shown in FIG. 1, and the portion of gate drive circuit 203 that corresponds to switching elements S1 and S2. Hereinafter, the portion of gate drive circuit 203 that corresponds to switching elements S1 and S2 will be referred to as gate drive circuit 203U. Gate drive circuit 203U includes two gate drive ICs 10A and 10B. The gate of switching element S1 is driven by gate drive IC 10A. The gate of switching element S2 is driven by gate drive IC 10B.

[0014] The switching elements S1 and S2 are power semiconductor elements such as insulated gate bipolar transistors (IGBTs) and metal oxide semiconductor field effect transistors (MOSFETs) made of SiC, GaN, or the like. Freewheeling diodes D1 and D2 are connected in parallel to each switching element S1 and S2 in the direction opposite to the direction of current flow when the element is switched on. In the case of a MOSFET, a body diode (parasitic diode) is included within the element, and the body diode is used as the freewheeling diode D1 and D2.

[0015] The gate driver ICs 10A and 10B have the same configuration, and the following description will be given using the gate driver IC 10A as an example. The gate driver IC 10A includes an insulated communication circuit between the low-voltage circuit and the high-voltage circuit. The gate driver IC 10A controls the gate of the switching element S1 in response to an upper arm PWM signal (PWM-H signal) input to the IN terminal from the low-voltage control circuit 202.

[0016] A speed command signal SEL-H, which determines whether the switching speed is to be set to high or low, is input from the control circuit 202 to the SEL terminal of the gate driver IC 10A. The gate driver IC 10A has an OUTH terminal, an OUTL terminal, and an OUTL2 terminal that control the gate voltage. When turning on the switching element S1, a control signal is output from the OUTH terminal. When turning off the switching element S1 at a low speed, a control signal is output from the OUTL terminal. On the other hand, when turning off the switching element S1 at a high speed, a control signal is output from the OUTL2 terminal. An on-gate resistor R is connected to the OUTH terminal of the gate driver IC 10A, and off-gate resistors R1 and R2 are connected to the OUTL and OUTL2 terminals, respectively.

[0017] The gate driver IC 10A includes a MON terminal for monitoring the gate voltage of the switching element S1, and an OSFB terminal for feeding back gate information including the monitored gate voltage to the control circuit 202.

[0018] The control circuit 202 includes a CPU 210, a memory 220, etc. The CPU 210 functions as a switching speed setting unit (SW speed setting unit) 211 that sets the above-mentioned switching speed, and a diagnosis unit 212 that diagnoses the setting state of the switching speed. The diagnosis unit 212 includes a calculation unit 212a that calculates the rise time and fall time (to be described later) based on the monitored gate voltage, and a determination unit 212b that determines whether the setting state of the switching speed is normal or abnormal based on the rise time and fall time. The memory 220 stores control parameters and the like, including a diagnostic threshold value td (to be described later).

[0019] The switching element S1 in Fig. 2 performs switching operations by charging and discharging electric charge at its gate terminal. Gate driving ICs 10A and 10B of the gate driving circuit 203U charge and discharge the gate terminals of the switching elements S1 and S2 under the control of the control circuit 202. In this case, the switching speed can be changed by changing the rate at which the gate terminals are charged and discharged. There are two gate voltage driving methods: constant voltage driving shown in Fig. 3 and constant current driving shown in Fig. 4.

[0020] In the constant voltage drive shown in Figure 3, during ON operation (turn-on), the switch S11 corresponding to the switching element S1 is closed to connect the gate terminal to a constant voltage source VCC via an ON gate resistor Ron, thereby charging the gate terminal. The charging rate is controlled by the resistance value of the ON gate resistor Ron. Meanwhile, during OFF operation (turn-off), the switch S12 is closed to connect the emitter terminal and gate terminal via an OFF gate resistor Roff, thereby discharging the gate terminal. The discharging rate is controlled by the resistance value of the OFF gate resistor Roff. Note that in order to stabilize the OFF operation, the gate terminal may be connected to a voltage source lower than the potential of the emitter terminal.

[0021] In the constant current drive shown in Figure 4, in the ON operation, a constant current source I1 is connected to the gate terminal to charge the gate terminal. The charging rate is controlled by controlling the current value. On the other hand, in the OFF operation, a constant current source I2 is connected that draws current from the gate terminal to the emitter terminal, and the charge stored in the gate terminal is discharged. The discharging rate is controlled by controlling the current value.

[0022] The gate drive circuit 203U shown in Fig. 2 uses constant voltage driving. During the OFF operation, the discharge speed (i.e., switching speed) can be switched by discharging the gate terminal through the off-gate resistor R1 or through the off-gate resistor R2. Such switching of the discharge speed is performed based on the speed command signal SEL-H input from the control circuit 202 to the SEL terminal of the gate drive IC 10A.

[0023] 5 and 6 are diagrams illustrating an example of switching speed control. Fig. 5 is a diagram showing the relationship between the current flow and the surge voltage. Line L1 indicates the case where the switching speed is high (SH), and line L2 indicates the case where the switching speed is low (SL). Generally, when setting the switching speed, the switching speed is set to low (SL), as shown by line L2, so that the surge voltage caused by switching does not exceed the withstand voltage of the switching element within the range of normal operating conditions.

[0024] When turning off the switching element S1, the larger the current flowing, the larger the switching surge, so the switching speed is set slow so that the switching surge at the maximum current used does not exceed the withstand voltage of the element. On the other hand, the switching surge at turn-on varies depending on the characteristics of the switching element, and as with turn-off, there are some cases where the surge voltage increases as the current increases, and others where this does not happen.

[0025] For devices in which the surge voltage increases as the current flow increases, there is a margin for the surge voltage relative to the device withstand voltage in the low current range. In the example shown in Figure 5, the line L1 in the case of a high-speed SH switching speed shows that the surge voltage is below the device withstand voltage in the low current range. In other words, in the low current range, it is possible to increase the switching speed as long as the surge voltage does not exceed the device withstand voltage.

[0026] 6 is a diagram showing the relationship between the conduction current and loss. Line L3 represents the loss when the switching speed is high (SH), and line L4 represents the loss when the switching speed is low (SL). In both cases of lines L3 and L4, the loss increases as the conduction current increases. Furthermore, the loss is smaller when the switching speed is high (SH). Therefore, as described above, by increasing the switching speed in the low current range within a range where the surge does not exceed the element's withstand voltage, switching loss can be improved, and efficiency can be improved.

[0027] 5 and 6, when the current passing through the switching element S1 is in the low current range, the switching speed is set to high speed SH, and when the current passing through the switching element S1 exceeds the low current range, the switching speed is set to low speed SL. As a result, it is possible to prevent surges from exceeding the element's withstand voltage and reduce switching losses.

[0028] In the case of a configuration in which switching speeds are switched as described above, diagnosing whether the switching operation is working properly is necessary for functional safety. Different switching speeds result in different rise and fall times of the gate voltage when turned on or off. Therefore, by measuring the rise and fall times at low and high speeds, it is possible to diagnose whether the switching operation is functioning properly.

[0029] However, when the device is energized, the gate charge fluctuates according to the current due to the Miller effect, and the rise / fall time of the gate voltage also fluctuates. Figures 7 and 8 show the waveform of the gate voltage at turn-off. Figure 7 shows the case where the switching speed (SW speed) is slow, and Figure 8 shows the case where the switching speed is fast. In Figures 7 and 8, lines L11 and L21 show the case where the current is large, and lines L12 and L22 show the case where the current is small.

[0030] When the switching element S1 is conducting, the mirror effect appears in the gate voltage waveform. During the mirror period when the mirror effect appears, the gate voltage is constant. When the current flowing is large, the mirror effect appears in the high voltage region, and when the current flowing is small, the mirror effect appears in the low voltage region.

[0031] The time it takes for the gate voltage to change from a high state to a low state (fall time) is t11-t0 for line L11 in Fig. 7, and t12-t0 for line L12. Similarly, the fall time in Fig. 8 is t21-t0 for line L21, and t22-t0 for line L22. In other words, the fall time is shorter as the current flow increases, provided that the switching speed is the same, and shorter as the switching speed is faster, provided that the current flow is the same.

[0032] However, the current flowing through the inverter fluctuates from moment to moment during operation, causing the rise and fall times to fluctuate depending on the current flow. Therefore, it is difficult to determine whether the switching speed is functioning properly from the measured rise and fall times of the gate voltage. The rise time of the gate voltage at turn-on is also affected by the Miller effect, just like the fall time at turn-off.

[0033] However, for example, if there is no element conduction, the Miller effect does not occur during turn-off. FIG. 9 shows an example of a gate voltage waveform during turn-off when there is no element conduction. In FIG. 9 , the solid line L31 indicates a case where the switching speed is slow, and the dashed line L32 indicates a case where the switching speed is fast. The Miller effect does not occur either when the switching speed is slow (L31) or fast (L32). Furthermore, there is almost no variation in the fall time t1 when the switching speed is fast or when the switching speed is slow (t2). Therefore, for example, if the intermediate value (t1 + t2) / 2 of the expected fall times t1 and t2 is set as the diagnostic threshold td, and if t1 td, it can be diagnosed that the switching function is operating normally.

[0034] Thus, when the Miller effect does not occur, the fall time is not affected by the current flow and is determined by the switching speed. Similarly to the fall time when the turn-off occurs, the rise time of the gate voltage at turn-on is also not affected by the current flow when the Miller effect does not occur. Therefore, in this embodiment, the rise / fall time of the gate voltage is measured under operating conditions where the Miller effect does not occur, and the switching function is diagnosed as operating normally based on the measurement results. As a result, the reliability of the diagnosis can be improved.

[0035] (Diagnostic Processing) The diagnostic processing of this embodiment is performed under operating conditions in which the Miller effect does not occur. The operating conditions in which the Miller effect does not occur will be described later. The following describes an example in which the fall time of the gate voltage at turn-off is measured.

[0036] FIG. 10 is a flowchart showing an example of the diagnostic process, which is executed by the control circuit 202. In step S10, the switching speed setting unit 211 of the control circuit 202 inputs a speed command signal SEL-H, which sets the switching speed at turn-off to low, to the SEL terminal of the gate driver IC 10A. For example, in the circuit shown in FIG. 2, the off-gate resistors R1 and R2 are set so that R1 > R2, and when the switching speed is low, the gate terminal is discharged by the off-gate resistor R1. On the other hand, when the switching speed is high, the gate terminal is discharged by the off-gate resistor R2.

[0037] In step S20, the control circuit 202 inputs an ON signal to the IN terminal of the gate driving IC 10A to turn on the switching element S1 that is in the OFF state.

[0038] In step S30, if the switching element S1 is turned ON, the switching element S1 is turned OFF, and the calculation unit 212a calculates the fall time t2 (see FIG. 9) when the low speed setting is used. That is, the control circuit 202 inputs an OFF signal to the IN terminal of the gate driver IC 10A. The calculation unit 212a then calculates the fall time t2 of the gate voltage based on the gate voltage information input from the OSFB terminal of the gate driver IC 10A.

[0039] 10, when turning off the ON state and calculating the fall time t2 of the gate voltage, the switching speed is set first in step S10. However, if the switching speed setting is in time for the turn-off timing when turning off the ON state, the processing may be performed in the order of step S20 → step S10 (switching speed setting) → step S30.

[0040] In step S40, the switching speed setting unit 211 of the control circuit 202 inputs a speed command signal SEL-H, which sets the switching speed at turn-off to high speed, to the SEL terminal of the gate driver IC 10A. When the switching speed is set to high speed, the gate terminal is discharged by the off-gate resistor R2 at turn-off.

[0041] In step S50, the control circuit 202 inputs an ON signal to the IN terminal of the gate driver IC 10A, turning on the switching element S1 that is in the OFF state again.

[0042] In step S60, if the switching element S1 is turned ON, the switching element S1 is turned OFF, and the calculation unit 212a calculates the fall time t1 when the high speed setting is used. That is, the control circuit 202 inputs an OFF signal to the IN terminal of the gate driver IC 10A. The calculation unit 212a then calculates the fall time t1 of the gate voltage based on the gate voltage information input from the OSFB terminal of the gate driver IC 10A.

[0043] As with the processing of steps S10 to S30 described above, when turning off from the ON state, if the switching speed setting is in time for the turn-off timing, the processing of steps S40 to S60 may be performed in the order of step S50 → step S40 (switching speed setting) → step S60.

[0044] In step S70, the determination unit 212b compares the calculated fall times t1 and t2 with a diagnostic threshold td (see FIG. 9) to determine whether the switching function is operating normally. For example, when a diagnostic threshold td is set as shown in FIG. 9, if t1td, the determination unit 212b determines that the switching function is operating normally. Otherwise, the determination unit 212b determines that an abnormality exists.

[0045] Generally, there are individual variations in the switching elements, gate drive circuits, and diagnostic circuits. Therefore, before shipping the device, the rise / fall times for high-speed and low-speed switching devices can be measured, and the diagnostic threshold value td calculated based on the measured values ​​can be stored in the memory 220 of the control circuit 202 and used as the diagnostic threshold value specific to each device. This allows for the setting of a diagnostic threshold appropriate for each device, even when there is significant individual variation among devices. As a result, the reliability of the diagnosis can be improved.

[0046] The diagnostic threshold value td is not limited to the diagnostic threshold value td shown in Fig. 9, and normal diagnostic regions R1 and R2 may be set as shown in Fig. 11. The lower limit values ​​of the diagnostic regions R1 and R2 are R1L and R2L, and the upper limit values ​​are R1U and R2U. If R1L < t1 < R1U and R2L < t2 < R2U, the system is diagnosed as normal, and otherwise as abnormal.

[0047] In the diagnostic process shown in Fig. 10, the rise / fall time is measured only once, but it is also possible to measure the rise / fall time multiple times and then use the averaged results for the judgment. By measuring multiple times, the diagnostic accuracy can be improved.

[0048] Also, instead of measuring the rise / fall times, it is possible to monitor the duty of the gate voltage signal output from the OSFB terminal and diagnose whether the switching operation is normal or not based on that duty, as follows: For example, the switching speed is set to high speed only at turn-off, a PWM signal with a constant duty is input to the IN terminal of the gate driver IC 10A, and diagnosis is performed based on the duty of the gate voltage signal output from the OSFB terminal.

[0049] If the switching speed is set to high only when turning off, the fall time will be shorter than when the speed is set to low, and the gate voltage will reach low level more quickly. As a result, the gate ON time will be shorter and the duty will be lower. In other words, the duty (proportion of high level) of the monitored gate voltage will be higher when the switching speed is set to low than when it is set to high. By using this change in duty, it is possible to detect changes in the fall time and determine whether the switching function is operating normally.

[0050] Note that there is variation in the transmission delay between the gate transition from the CPU 210 side (control circuit 202) via the gate driving IC 10A and the transmission from the gate transition via the OSFB terminal to the CPU 210. Therefore, in order to suppress the variation, multiple pieces of data are acquired and averaged, time constant filter processing, etc. are performed, thereby improving the accuracy of diagnosis.

[0051] (Conditions under which the Miller effect does not occur) This embodiment is characterized in that the rise / fall times are measured under conditions under which the Miller effect does not occur. In this case, there are various conditions under which the Miller effect does not occur, and the following describes typical conditions.

[0052] (A: Freewheeling section during current-carrying operation) As shown in Fig. 2, freewheeling diodes D1 and D2 are connected in parallel to the switching elements S1 and S2 in the opposite direction to the current-carrying direction when the switches are turned on. When a current flows through an inductive load L such as a motor, the current continues to flow through the inductive load L even when the switching element on the opposite arm is turned off, so freewheeling diodes are provided. Note that when the switching element is a MOSFET (Metal Oxide Semiconductor Field Effect Transistor), the element has a body diode (parasitic diode) inside, and this body diode is used as the freewheeling diode.

[0053] 12 and 13 are diagrams illustrating the return section during current application. In these figures, the lower-arm switching element S2 is turned on, causing current to flow through the inductive load L (motor M) from the right to the left in the figure. In this case, the upper-arm switching element S1 is turned off. In PWM control, the on-duty of the switching element S2 is controlled to control the magnitude of the current flowing leftward through the inductive load L.

[0054] 12, the switching element S1 is OFF and the switching element S2 is ON. Current flows from the inductive load L (motor M) to the switching element S2 as shown by the dashed arrow.

[0055] Period 2 in Figure 12 is the freewheeling section, during which both switching elements S1 and S2 are turned OFF. Even when both switching elements S1 and S2 are turned OFF, the current value does not instantly become zero due to the inductive load L, and the current continues to flow as before. Therefore, as shown by the dashed arrow, the current flows through the inductive load L (motor M) to the left in the figure and then flows toward diode D1. In other words, the current freewheels through diode D1.

[0056] Next, as shown in period 3 in Figure 13, switching element S2 is turned on again. When switching element S2 is turned on and enters a conducting state, the current that had been flowing leftward through inductive load L begins to flow through switching element S2. In addition, reverse recovery current Ir flows through diode D1. In other words, period 3 is the reverse recovery period of diode D1. After the reverse recovery period of diode D1 has elapsed, the state returns to that shown in period 1 in Figure 12, that is, a state in which current flows from inductive load L (motor M) to switching element S2.

[0057] 12 (freewheeling section), even if switching element S1 is turned on, no current flows through switching element S1. Therefore, during this freewheeling section, the gate of switching element S1 is switched from ON to OFF or from OFF to ON to measure the fall time or rise time. Because switching element S1 is in a non-conductive state, the Miller effect does not occur, and the rise / fall time can be measured without being affected by the Miller effect.

[0058] When MOSFETs are used for the switching elements S1 and S2, the MOSFETs have reverse conductivity when the gates are ON. Therefore, synchronous rectification may be performed by inserting a section in which switching element S1 is turned ON during period 2 in FIG. 12. That is, the control is performed as follows: period 2 → synchronous rectification section → period 2 → period 3, and the rise / fall times are measured during the timing of period 2 → synchronous rectification section → period 2. In the section in which switching element S1 is ON (synchronous rectification section), the return current flows through switching element S1, which has smaller loss than diode D1, so that the return current can be returned with low loss.

[0059] (B: Three-phase short circuit control operation confirmation period) When the inverter is started, diagnostic operations are performed on various functions within the inverter 201. When the inverter 201 is provided with three-phase short circuit control as a safety operation, it is common to also perform diagnostic processing on the three-phase short circuit control during diagnostic operations when the inverter is started. Since the three-phase short circuit control is a condition under which the Miller effect does not occur, it is possible to perform diagnosis of the function of switching the switching speed without being affected by the Miller effect.

[0060] Three-phase short-circuit control is control in which all of the upper arm switching elements S1, S3, and S5 or the lower arm switching elements S2, S4, and S6 in Fig. 1 are turned ON to short-circuit the windings of the motor M. For example, if the motor M is being rotated by an external force even though the inverter 201 is not functioning, three-phase short-circuit control is performed to prevent the smoothing capacitor of the inverter 201 from being charged by the induced voltage of the motor M. Furthermore, if an overcurrent is detected in the upper arm, three-phase short-circuit control is performed on the lower arm on the opposite arm side.

[0061] For example, in the case of a vehicle equipped with the device shown in Fig. 1, a diagnostic process including a diagnosis of three-phase short circuit control is executed when the vehicle is started (ignition is turned on) (motor is stopped). In the diagnostic sequence, the diagnosis is performed in the following order: all arms OFF → three-phase short circuit (lower arm) → all arms OFF → three-phase short circuit (upper arm) → all arms OFF. Therefore, the function of switching the switching speed can be diagnosed at the timing of three-phase short circuit (lower arm) and three-phase short circuit (upper arm) when the motor is stopped.

[0062] (Example 1 of Actions to be Taken When Diagnosing an Abnormality) This section describes an example of actions to be taken when the diagnosis of the switching speed switching function indicates that the switching speed is stuck on the high speed side. In this case, possible causes include control fixation on the control circuit 202 side or a control malfunction within the gate driver ICs 10A and 10B. In this case, the control circuit 202 performs current limiting as a safety operation. That is, rather than generating a current command in accordance with a torque command from a higher level, the control circuit 202 generates a current command so that the surge voltage during high-speed switching does not exceed an upper limit, and inputs a PWM signal based on the current command to the gate driver ICs 10A and 10B.

[0063] (Countermeasure Example 2 When Diagnosing an Abnormality) In Countermeasure Example 2, a case will be described in which the diagnosis of the switching speed switching function reveals that the switching speed is stuck on the low speed side. In a configuration in which the switching speed can be switched between high and low speeds, the turn-off time is shorter when the high speed setting is used than when the low speed setting is used. Therefore, control to shorten the dead time is also possible with the aim of improving efficiency. In Countermeasure Example 2, when control to shorten the dead time is employed and it is diagnosed that the switching speed is stuck on the low speed side, the shortening of the dead time is canceled.

[0064] 14 shows an example of a timing chart from when the gate of the lower-arm switching element S2 is turned OFF to when the gate of the upper-arm switching element S1 is turned ON. In FIG. 14, the solid line indicates the case where the switching speed is low, and the dashed line indicates the case where the switching speed is high.

[0065] As shown in Figure 14, a dead time DT is provided to prevent short circuits between the upper and lower switching elements. The dead time DT refers to the time during which neither the PWM-H signal nor the PWM-L signal input to the IN terminals of the switching elements S1 and S2 is high. Figure 14 illustrates a scene in which the PWM-L signal is switched from high to low and the PWM-H signal is switched from low to high. The dead time DT shown in Figure 14 is the dead time when the low-speed setting is selected, as indicated by the solid line.

[0066] When the PWM-L signal switches from high to low, the gate voltage Vg-L of the lower arm switching element S2 begins to drop. Even after the gate voltage Vg-L starts to drop, the current I-L flowing through the switching element S2 is maintained for a while, and when the gate voltage Vg-L drops to a certain voltage, the current I-L becomes zero. The time from when the gate voltage Vg-L starts to drop until the current I-L becomes zero is called the turn-off time (Toff).

[0067] When the PWM-L signal goes low and the dead time DT has elapsed, the PWM-H signal, which is the PWM signal for the upper arm, goes high. The time from when the PWM-H signal goes high until the current I-H of the upper arm switching element S1 starts to flow is called the turn-on time (Ton). Vg-H is the gate voltage of the upper arm switching element S1. Normally, the dead time DT is set so that DT > (Ton + Toff) to prevent short circuits between the upper and lower arms.

[0068] On the other hand, when the switching speed is set to high, as shown by the dashed line, the fall time of the gate voltage Vg-L when the switching element S2 is turned off is shorter than when the switching speed is set to low. Therefore, by advancing the timing at which the PWM-H signal goes high, it is possible to shorten the dead time, such as dead time DT1, compared to when the switching speed is set to low. This improves efficiency.

[0069] However, if the switching speed is stuck on the low speed side while dead time shortening is being performed at the high speed setting, an upper and lower short circuit will occur. Therefore, when control to shorten the dead time is adopted, if the diagnostic processing of this embodiment diagnoses that the switching speed is stuck on the low speed side, the shortening of the dead time is stopped. In other words, by setting the dead time DT at both the low speed setting and the high speed setting, it is possible to prevent the occurrence of an upper and lower short circuit.

[0070] In the above-described embodiment, the diagnostic process was described using an example in which the gate driver ICs 10A, 10B are configured with a constant voltage. However, the diagnostic process can also be applied to a constant current configuration. A constant current drive system is less affected by fluctuations in the gate-source voltage Vgs (gate-emitter voltage in the case of an IGBT) of the switching elements S1, S2 and fluctuations in the power supply voltage, allowing the output current dI / dt to be constant. Therefore, the dependency on temperature and Vgs fluctuations is small, and surge voltage can be stabilized, reducing losses.

[0071] Although the Miller effect occurs during current flow in the constant current drive system, the variation in rise / fall times during current flow is reduced compared to the constant voltage drive system. Therefore, even when measuring the rise / fall times during current flow, a significant decrease in diagnostic accuracy can be prevented, and diagnosis is possible when the difference between the rise / fall times is large.

[0072] According to the embodiment of the present invention described above, the following advantageous effects are achieved.

[0073] 1 and 2, a switching element drive device (control circuit 202 and gate drive circuit 203) that applies a gate voltage to the gate terminal of semiconductor switching element S1 includes a switching speed setting unit 211 that sets the switching speed of semiconductor switching element S1 to one of a plurality of speeds (low speed and high speed), and a diagnosis unit 212 that diagnoses the speed setting operation by switching speed setting unit 211. The diagnosis unit 212 includes a calculation unit 212a that calculates the switching time (rise / fall time) required for the ON / OFF state of semiconductor switching element S1 to switch from one to the other under operating conditions that do not cause the Miller effect, and a determination unit 212b that determines whether there is an abnormality in the speed setting operation based on the calculated switching time.

[0074] As described above, the rise and fall times of the gate voltage are calculated under operating conditions where the Miller effect does not occur, and an abnormality in the speed setting operation is determined based on the measurement results. This makes it possible to calculate the rise and fall times of the gate voltage more accurately, thereby improving the reliability of the diagnosis of the switching speed setting operation.

[0075] In the above-described embodiment, the switching speed is set to one of two speeds, low and high. However, the configuration may also be such that three speeds, such as low, medium, and high, or even four or more speeds are set. Furthermore, while the control circuit 202 calculates the switching time (rise / fall time) and determines whether or not an abnormality has occurred, the calculation and determination functions may be assigned to the gate drive circuit (gate drive IC 10A). For example, a timer may be provided in the gate drive IC 10A to measure the switching time (rise / fall time).

[0076] (C2) In (C1) above, as shown in Figures 2, 12, 13, etc., the calculation unit 212a calculates the switching time during period 2 (freewheel period) when the switching element S1 connected to the inductive load L (M) is alternately energized and de-energized. During the freewheel period, the Miller effect does not occur in the gate voltage when the switching element S1 is switched ON / OFF, so the rise / fall times can be calculated with high accuracy. As a result, the switching speed switching operation (speed setting operation) can be diagnosed with high accuracy.

[0077] (C3) In (C1) above, as shown in Fig. 4 etc., a gate drive circuit 203U of a constant current drive type may be provided, and the gate voltage may be applied to the gate terminal of the switching element S1 by the gate drive circuit 203U. In the case of a constant current drive type, the current precision of the gate current is high, and the surge voltage can be made constant, thereby reducing losses.

[0078] Compared to the constant voltage drive method, the constant current drive method is less affected by the Miller effect, and the variation in rise / fall time during current flow is reduced. Therefore, even if the rise / fall time is calculated while current is flowing, a significant decrease in diagnostic accuracy can be prevented, and diagnosis is possible when the difference between the rise / fall time is large.

[0079] (C4) In (C1) above, as shown in Figures 1 and 2, etc., a gate drive circuit 203 is provided that applies gate voltages to switching elements S1 to S6 of an inverter 201 connected to a motor M, and a calculation unit 212a calculates the switching time during three-phase short-circuit control of the inverter 201 when the motor M is not rotating. By calculating the switching time during three-phase short-circuit control, it is possible to calculate rise / fall times that are not affected by the Miller effect, and diagnostic reliability can be improved.

[0080] (C5) In (C1) above, it is preferable that the calculation unit 212a calculates the switching time multiple times, and the determination unit 212b determines whether there is an abnormality in the speed setting operation based on the multiple switching times, as shown in Figure 2 etc. By measuring multiple times, it is possible to improve the accuracy of the diagnosis.

[0081] (C6) In (C1) above, as shown in FIGS. 2, 14, etc., a monitor terminal (MON terminal) for monitoring the gate voltage may be provided instead of the calculation unit 212a, and the determination unit 212b may determine an abnormality in the speed setting operation based on a change in the duty (DUTY) of the monitored gate voltage before and after the setting change by the switching speed setting unit 211.

[0082] When a PWM signal with a constant duty is input to the IN terminal of the gate driver IC 10A, the duty of the monitored gate voltage is higher when the switching speed is slow than when it is fast. By utilizing this change in duty, it is possible to detect changes in the fall time and determine whether the switching function is operating normally.

[0083] (C7) In (C1) above, as shown in Figures 1, 2, 9, etc., a memory 220 may be provided that stores an abnormality diagnostic threshold (diagnostic threshold td) specific to the switching element drive device (control circuit 202 and gate drive circuit 203), and the determination unit 212b may determine an abnormality in the speed setting operation based on the switching time and the diagnostic threshold td. This makes it possible to set a diagnostic threshold appropriate for each device, even when there is significant variation between individual devices, thereby improving the reliability of the diagnosis.

[0084] (C8) In the above (C1), as shown in Fig. 2 etc., the switching speed setting unit 211 sets the switching speed to either high or low, and the determination unit 212b determines whether the switching speed is fixed to high or low in addition to determining whether there is an abnormality in the speed setting operation. Then, when the determination unit 212b determines that the switching speed is fixed to high, the control circuit 202 may control the application of gate voltage so as to limit the current flow.

[0085] If it is determined that the switching speed is stuck on the high speed side, possible causes include a stuck control on the control circuit 202 side or a control malfunction within the gate driver ICs 10A and 10B. Therefore, it is preferable to limit the current flow as a safety operation. For example, safety can be ensured by having the control circuit 202 generate a current command so that the surge voltage during high-speed switching does not exceed an upper limit, rather than generating a current command according to a torque command from a higher level.

[0086] (C9) In (C8) above, a dead time setting unit (control circuit 202) is further provided that sets the dead time from when one switching element S2 of the upper and lower arms starts to turn on until the other switching element S1 starts to turn on to a first dead time DT when the switching speed is set to low, and sets it to a second dead time DT1 that is shorter than the first dead time DT when the switching speed is set to high, as shown in Figures 2, 14, etc. Then, when the determination unit 212b determines that the switching speed is stuck at low, the control circuit 202 sets the dead time to the first dead time DT regardless of the setting of the switching speed setting unit 211.

[0087] In a configuration in which the dead time is set to the first dead time DT when the switching speed is low and to the second dead time DT1 (<DT) when the switching speed is high, if the switching speed is fixed to low, the dead time is set to the first dead time DT regardless of the setting of the switching speed setting unit 211, thereby making it possible to prevent the occurrence of upper and lower short circuits.

[0088] The above-described embodiments and various modifications are merely examples, and the present invention is not limited to these details as long as the features of the invention are not impaired. Furthermore, although various embodiments and modifications have been described above, the present invention is not limited to these details. Other aspects conceivable within the scope of the technical idea of ​​the present invention are also included within the scope of the present invention.

[0089] 10A, 10B... Gate driving IC, 200... Power conversion device, 201... Inverter, 202... Control circuit, 203, 203U... Gate driving circuit, 210... CPU, 211... Switching speed setting unit, 212... Diagnosis unit, 212a... Calculation unit, 212b... Determination unit, 220... Memory, D1, D2... Diodes, M... Three-phase AC motor (motor), S1 to S6... Switching elements

Claims

1. A switching element drive device that applies a gate voltage to a gate terminal of a semiconductor switching element, comprising: a switching speed setting unit that sets the switching speed of the semiconductor switching element to one of a plurality of speeds; and a diagnosis unit that diagnoses the speed setting operation by the switching speed setting unit, wherein the diagnosis unit comprises: a calculation unit that calculates a switching time required for the ON / OFF state of the semiconductor switching element to be switched from one to the other under operating conditions in which no Miller effect occurs; and a judgment unit that judges whether there is an abnormality in the speed setting operation based on the calculated switching time.

2. A switching element drive device as claimed in claim 1, wherein the calculation unit calculates the switching time during a return period during which the switching element connected to an inductive load is alternately energised and de-energised.

3. A switching element drive device according to claim 1, further comprising a gate drive circuit of a constant current drive type, the gate drive circuit applying a gate voltage to the gate terminal.

4. A switching element drive device as claimed in claim 1, further comprising a gate drive circuit which applies the gate voltage to a switching element of an inverter circuit connected to a motor, and wherein the calculation unit calculates the switching time during three-phase short circuit control of the inverter circuit when the motor is not rotating.

5. A switching element drive device according to claim 1, wherein the calculation section calculates the switching time a plurality of times, and the determination section determines an abnormality in the speed setting operation based on the plurality of switching times.

6. A switching element drive device as described in claim 1, further comprising a monitor terminal for monitoring the gate voltage instead of the calculation section, and the judgment section judges an abnormality in the speed setting operation based on a change in the duty of the monitored gate voltage before and after a setting change made by the switching speed setting section.

7. A switching element drive device as claimed in claim 1, further comprising a memory for storing an abnormality diagnosis threshold specific to said switching element drive device, and said determination unit determines an abnormality in said speed setting operation based on said switching time and said abnormality diagnosis threshold.

8. A switching element drive device as claimed in claim 1, wherein the switching speed setting section sets the switching speed to either a high speed or a low speed, and the determination section, in addition to determining whether the switching speed is fixed to the high speed or the low speed, in addition to determining whether there is an abnormality in the speed setting operation, controls the application of the gate voltage so that the current flow is limited when the determination section determines that the switching speed is fixed to the high speed.

9. A switching element drive device as claimed in claim 8, further comprising a dead time setting section which sets the dead time from the start of turn-on of one of the switching elements of the upper and lower arms to a first dead time when the switching speed is set to the low speed, and sets it to a second dead time shorter than the first dead time when the switching speed is set to the high speed, and wherein the dead time setting section sets the dead time to the first dead time regardless of the setting of the switching speed setting section when it is determined by the determination section that the switching speed is stuck to the low speed.

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