A high order curvature compensated bandgap reference circuit

Abstract

The application relates to a high-order curvature compensation band gap reference circuit, which comprises a first-order band gap reference circuit, a high-temperature region curvature compensation circuit and a starting circuit. The first-order band gap reference voltage is realized by the following technologies: the voltage generated by the current of PMOS tube M4 on resistors R3-R4 and the voltage generated by the current of PMOS tube M6 on resistor R4 both have positive temperature coefficients, the voltage generated by the current of PMOS tube M5 on resistors R3-R4 and the voltage generated by the current of PMOS tube M7 on resistor R4 both have negative temperature coefficients; the working area of NMOS tube M13 gradually changes from the deep triode region, the triode region to the saturation region with the increase of temperature by controlling the working of NMOS tube M13 by the technology that the gate voltage of NMOS tube M12 increases with the increase of temperature, so that the current of PMOS tube M14 is high-order nonlinear with temperature, and the first-order band gap reference voltage is temperature compensated, thereby obtaining the high-order temperature compensation band gap voltage.

Description

Technical Field

[0001] The present invention belongs to the field of integrated circuits, and in particular relates to a high-order curvature compensation bandgap reference circuit. Background Art

[0002] The bandgap reference circuit is an important module of the integrated circuit system. The bandgap reference circuit mainly provides an accurate reference voltage for the integrated circuit system. Therefore, its performance characteristics directly affect the overall performance of the integrated circuit system. This requires improving the performance characteristics of the bandgap reference circuit. Figure 1 This is a traditional reference circuit structure. PMOS transistors M1, M2, and M3 have the same channel width-to-length ratio. The emitter area of ​​PNP transistor Q2 is N times that of PNP transistor Q1. Resistors R1 and R2 are made of the same material. The output voltage V REF for Where q is the electron charge, k is the Boltzmann constant, T is the absolute temperature, and V EB3 is the emitter-base voltage of PNP transistor Q3, N is the ratio of the emitter area of ​​PNP transistor Q2 to that of PNP transistor Q1, R1 is the impedance of resistor R1, and R2 is the impedance of resistor R2. By optimizing the relevant parameters of the resistors, a low-temperature drift reference voltage V can be obtained within a certain temperature range. REF Since the emitter-base voltage of a PNP transistor has temperature nonlinearity, the output voltage of a traditional first-order bandgap reference circuit has a high temperature drift coefficient, which greatly limits its application in high-precision systems. Summary of the Invention

[0003] The present invention aims to solve the above problems of the prior art. A high-order curvature-compensated bandgap reference circuit is proposed. The technical solution of the present invention is as follows:

[0004] A high-order curvature-compensated bandgap reference circuit comprises: a first-order bandgap reference circuit, a high-temperature region curvature compensation circuit, and a startup circuit, wherein a signal output terminal of the first-order bandgap reference circuit is respectively connected to the signal input terminals of the high-temperature region curvature compensation circuit and the startup circuit, the high-temperature region curvature compensation circuit is connected to the electrical signal input terminal of the first-order bandgap reference circuit, and the signal output terminal of the startup circuit is connected to the startup signal input terminal of the first-order bandgap reference circuit; the first-order bandgap reference circuit generates a bandgap reference voltage; the startup circuit enables the bandgap reference circuit to operate normally and generate a bandgap reference voltage output; the high-temperature region curvature compensation circuit compensates the bandgap reference voltage generated by the first-order bandgap reference circuit to obtain a bandgap reference voltage with a low temperature drift coefficient.

[0005] Furthermore, the first-order bandgap reference circuit includes: a PMOS tube M1, a PMOS tube M2, a PMOS tube M3, a PMOS tube M4, a PMOS tube M5, a PMOS tube M6, a PMOS tube M7, a resistor R1, a resistor R2, a resistor R3, a resistor R4, a PNP transistor Q1, a PNP transistor Q2, an amplifier OP1 and an amplifier OP2, wherein the source of the PMOS tube M1 is connected to the source of the PMOS tube M2, the source of the PMOS tube M3, the source of the PMOS tube M4, the source of the PMOS tube M The source of the PMOS transistor M5, the source of the PMOS transistor M6, the source of the PMOS transistor M7 and the external power supply VDD are connected. The drain of the PMOS transistor M1 is connected to the positive input terminal of the amplifier OP1 and one end of the resistor R1 respectively. The other end of the resistor R1 is connected to the collector of the PNP transistor Q1, the base of the PNP transistor Q1, the collector of the PNP transistor Q2, the base of the PNP transistor Q2, one end of the resistor R4 and the external ground GND respectively. The gate of the PMOS transistor M1 is connected to the gate of the PMOS transistor M5, the gate of the PMOS transistor M6 and the gate of the PMOS transistor M7 respectively. The gate of the MOS tube M7, the drain of the NMOS tube M15 and the output end of the amplifier OP1 are connected, the drain of the PMOS tube M2 is connected to the inverting input end of the amplifier OP1, the inverting input end of the amplifier OP2 and the emitter of the PNP transistor Q1, and the gate of the PMOS tube M2 is connected to the gate of the PMOS tube M3, the gate of the PMOS tube M4, the gate of the PMOS tube M6, the gate of the PMOS tube M8, the gate of the PMOS tube M9, the drain of the NMOS tube M16 and the input end of the amplifier OP2. The output terminal of the circuit is connected to the output terminal of the circuit, the drain of the PMOS tube M3 is respectively connected to the positive input terminal of the amplifier OP2 and one end of the resistor R2, the other end of the resistor R2 is connected to the emitter of the PNP transistor Q2, the drain of the PMOS tube M4 is respectively connected to the drain of the PMOS tube M5, the drain of the PMOS tube M14, one end of the resistor R3 and the circuit output terminal VREF, the other end of the resistor R3 is respectively connected to the other end of the resistor R4, the drain of the PMOS tube M6, the drain of the PMOS tube M7 and the gate of the NMOS tube M19.

[0006] Furthermore, the high temperature area curvature compensation circuit includes: a PMOS tube M8, a PMOS tube M9, an NMOS tube M10, a PMOS tube M11, an NMOS tube M12, an NMOS tube M13, a PMOS tube M14, and a resistor R5, wherein the source of the PMOS tube M8 is respectively connected to the source of the PMOS tube M9, the source of the PMOS tube M11, the source of the PMOS tube M14 and the external power supply VDD, and the drain of the PMOS tube M8 is respectively connected to the gate of the NMOS tube M12 and one end of the resistor R5. The other end of the resistor R5 is respectively connected to the source of the NMOS transistor M10, the source of the NMOS transistor M13 and the external ground line GND. The drain of the PMOS transistor M9 is respectively connected to the drain of the NMOS transistor M10, the gate of the NMOS transistor M10 and the gate of the NMOS transistor M13. The drain of the PMOS transistor M11 is respectively connected to the gate of the PMOS transistor M11, the drain of the NMOS transistor M12 and the gate of the PMOS transistor M14. The source of the NMOS transistor M12 is connected to the drain of the NMOS transistor M13.

[0007] Furthermore, the startup circuit includes: an NMOS transistor M15, an NMOS transistor M16, a PMOS transistor M17, a PMOS transistor M18 and an NMOS transistor M19, wherein the source of the PMOS transistor M17 is connected to the external ground line VDD, the gate of the PMOS transistor M17 is respectively connected to the drain of the PMOS transistor M17 and the source of the PMOS transistor M18, the gate of the PMOS transistor M18 is respectively connected to the drain of the PMOS transistor M18, the gate of the NMOS transistor M16, the gate of the NMOS transistor M15 and the drain of the NMOS transistor M19, and the source of the NMOS transistor M15 is respectively connected to the source of the NMOS transistor M16, the source of the NMOS transistor M19 and the external ground line GND.

[0008] Furthermore, in the first-order bandgap reference circuit, the PMOS transistor M2 and the PMOS transistor M3 have the same channel width-to-length ratio, the emitter area of ​​the PNP transistor Q2 is N times that of the PNP transistor Q1, and the low-frequency gain A of the amplifier OP1 and the amplifier OP2 is d There is A d >>1. PMOS transistors M1 and M5 have the same channel width-to-length ratio. The channel width-to-length ratio of PMOS transistor M7 is α times that of PMOS transistor M1. PMOS transistors M3 and M4 have the same channel width-to-length ratio. The channel width-to-length ratio of PMOS transistor M6 is β times that of PMOS transistor M2. Resistors R1, R2, R3, and R4 are made of the same material. The voltage V generated by the current in PMOS transistors M4, M5, M6, and M7 across resistors R3 and R4 is REF1 have Where R1 is the resistance of resistor R1, R2 is the resistance of resistor R2, R3 is the resistance of resistor R3, R4 is the resistance of resistor R4, V EB1 is the emitter-base voltage of the PNP transistor Q1, V T is the thermal voltage with a positive temperature coefficient, N is the ratio of the emitter area of ​​PNP transistor Q2 to that of PNP transistor Q1, α is the multiple of the channel width-to-length ratio of PMOS transistor M7 to that of PMOS transistor M1, and β is the multiple of the channel width-to-length ratio of PMOS transistor M6 to that of PMOS transistor M2. The emitter-base voltage V EB1 It has a negative temperature coefficient. Therefore, by optimizing the parameters of the corresponding MOS tubes and resistors, the voltage V at the reference temperature T0 is REF1 have Where T is the absolute temperature.

[0009] Furthermore, in the high-temperature region curvature compensation circuit, the channel width-to-length ratio of the PMOS transistor M8 is K1 times that of the PMOS transistor M3. The current I8 of the PMOS transistor M8 and the current I3 of the PMOS transistor M3 are equal to I8 = K1I3. Therefore, the gate voltage of the NMOS transistor M12 increases with increasing temperature. As the temperature increases, the NMOS transistor M12 causes the working area of ​​the NMOS transistor M13 to gradually transition from the deep triode region and the triode region to the saturation region. The PMOS transistor M9 is identical to the PMOS transistor M2. The channel width-to-length ratio of the PMOS transistor M9 is K2 times that of the PMOS transistor M3. The NMOS transistors M10 and M13 have the same channel width-to-length ratio. By optimizing the parameters of the MOS transistors, the current I of the PMOS transistor M11 is reduced. 11 for where μ n is the electron mobility, C ox is the gate oxide capacitance per unit area, (W / L) 10 is the channel width-to-length ratio of the NMOS transistor M10, (W / L) 13 is the channel width-to-length ratio of the NMOS tube M13, V D13 is the drain voltage of NMOS tube M13, V T is the thermovoltage with a positive temperature coefficient, K2 is the ratio of the channel width to length ratio of the PMOS tube M9 and the PMOS tube M3, N is the ratio of the emitter area of ​​the PNP transistor Q2 and the PNP transistor Q1, T is the absolute temperature, T r1 、T r2 With T0 as the reference temperature, and T r2 >T r1 >T0. The channel width-to-length ratio of the PMOS tube M14 is K3 times that of the PMOS tube M11, and the output voltage V REF V REF =VREF1 +(R3+R4)K3I 11 , where V REF1 is the voltage generated by the current of the PMOS tube M4, PMOS tube M5, PMOS tube M6 and PMOS tube M7 on the resistor R3 and the resistor R4, R3 is the resistance value of the resistor R3, R4 is the resistance value of the resistor R4, I 11 is the current of the PMOS tube M11, and K3 is the ratio of the channel width-to-length ratio of the PMOS tube M14 to the channel width-to-length ratio of the PMOS tube M11. Factor (R3+R4)K3I 11 Temperature high-order nonlinearity can be effectively compensated by optimizing circuit parameters. REF1 The temperature nonlinearity and thus the low temperature drift coefficient of the bandgap reference voltage are improved.

[0010] The advantages and beneficial effects of the present invention are as follows:

[0011] The present invention provides a high-order curvature compensation bandgap reference circuit. The present invention adopts a technology in which the voltages generated by the current of a PMOS transistor M4 across resistors R3 and R4 and the voltage generated by the current of a PMOS transistor M6 across resistor R4 are both positive temperature coefficient voltages. The present invention adopts a technology in which the voltages generated by the current of a PMOS transistor M5 across resistors R3 and R4 and the voltage generated by the current of a PMOS transistor M7 across resistor R4 are both negative temperature coefficient voltages. The positive temperature coefficient voltage and the negative temperature coefficient voltage are weightedly summed to generate a first-order bandgap reference voltage. The present invention utilizes a technology in which the gate voltage of an NMOS transistor M12 in a high-temperature region curvature compensation circuit increases with increasing temperature to control the operation of the NMOS transistor M13 and causes the operating region of the NMOS transistor M13 to gradually transition from a deep triode region and a triode region to a saturation region with increasing temperature. The current of the PMOS transistor M14 is high-order temperature nonlinear. The first-order bandgap reference voltage is then temperature compensated, thereby obtaining a high-order temperature-compensated bandgap base voltage. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 This is a schematic diagram of a conventional first-order bandgap reference circuit according to a preferred embodiment of the present invention;

[0013] Figure 2 A schematic diagram of a high-order curvature compensation bandgap reference circuit is provided for a preferred embodiment of the present invention;

[0014] Figure 3 The present invention provides a simulation diagram of the output voltage temperature characteristics of a high-order curvature compensated bandgap reference circuit according to a preferred embodiment of the present invention. DETAILED DESCRIPTION

[0015] The following will describe the technical solutions in the embodiments of the present invention in detail with reference to the accompanying drawings. The described embodiments are only a part of the embodiments of the present invention.

[0016] The technical solution of the present invention to solve the above technical problems is:

[0017] In the embodiments of the present application, a technique is employed in which the voltages generated by the current of the PMOS transistor M4 across the resistors R3 and R4 and the voltage generated by the current of the PMOS transistor M6 across the resistor R4 are both positive temperature coefficient voltages. A technique is employed in which the voltages generated by the current of the PMOS transistor M5 across the resistors R3 and R4 and the voltage generated by the current of the PMOS transistor M7 across the resistor R4 are both negative temperature coefficient voltages. A first-order bandgap reference voltage is generated by weighted summing of the positive temperature coefficient voltage and the negative temperature coefficient voltage. The gate voltage of the NMOS transistor M12 in the high-temperature region curvature compensation circuit increases with increasing temperature to control the operation of the NMOS transistor M13 and gradually transition the operating region of the NMOS transistor M13 from the deep triode region and the triode region to the saturation region with increasing temperature. This technique causes the current of the PMOS transistor M14 to exhibit high-order temperature nonlinearity, thereby performing temperature compensation on the first-order bandgap reference voltage, thereby obtaining a high-order temperature-compensated bandgap base voltage.

[0018] In order to better understand the above technical solution, the above technical solution will be described in detail below with reference to the accompanying drawings and specific implementation methods.

[0019] Example

[0020] A high-order curvature-compensated bandgap reference circuit, such as Figure 2 As shown, it includes a first-order bandgap reference circuit 1, a high-temperature region curvature compensation circuit 2 and a startup circuit 3;

[0021] Among them, the signal output end of the first-order bandgap reference circuit 1 is respectively connected to the signal input end of the high-temperature area curvature compensation circuit 2 and the starting circuit 3, the high-temperature area curvature compensation circuit 2 is connected to the electrical signal input end of the first-order bandgap reference circuit 1, and the signal output end of the starting circuit 3 is connected to the starting signal input end of the first-order bandgap reference circuit 1. The first-order bandgap reference circuit 1 generates a bandgap reference voltage; the starting circuit 3 enables the bandgap reference circuit to work normally and generate a bandgap reference voltage output, and the high-temperature area curvature compensation circuit compensates the bandgap reference voltage generated by the first-order bandgap reference circuit 1 to obtain a bandgap reference voltage with a low temperature drift coefficient.

[0022] The startup circuit 3 only works when the bandgap reference circuit is powered on. When the bandgap reference circuit is started up, the startup circuit stops working, thereby avoiding the influence of the startup circuit on the subsequent circuits.

[0023] As a preferred technical solution, Figure 2 As shown, the first-order bandgap reference circuit 1 includes: a PMOS transistor M1, a PMOS transistor M2, a PMOS transistor M3, a PMOS transistor M4, a PMOS transistor M5, a PMOS transistor M6, a PMOS transistor M7, a resistor R1, a resistor R2, a resistor R3, a resistor R4, a PNP transistor Q1, a PNP transistor Q2, an amplifier OP1 and an amplifier OP2, wherein the source of the PMOS transistor M1 is connected to the source of the PMOS transistor M2, the source of the PMOS transistor M3, the source of the PMOS transistor M4, the source of the PMOS transistor M1 and the source of the PMOS transistor M2. The source of the PMOS transistor M5, the source of the PMOS transistor M6, the source of the PMOS transistor M7 and the external power supply VDD are connected. The drain of the PMOS transistor M1 is connected to the positive input terminal of the amplifier OP1 and one end of the resistor R1 respectively. The other end of the resistor R1 is connected to the collector of the PNP transistor Q1, the base of the PNP transistor Q1, the collector of the PNP transistor Q2, the base of the PNP transistor Q2, one end of the resistor R4 and the external ground GND respectively. The gate of the PMOS transistor M1 is connected to the gate of the PMOS transistor M5, the gate of the PMOS transistor M6 and the gate of the PMOS transistor M7 respectively. The gate of the MOS tube M7, the drain of the NMOS tube M15 and the output end of the amplifier OP1 are connected, the drain of the PMOS tube M2 is connected to the inverting input end of the amplifier OP1, the inverting input end of the amplifier OP2 and the emitter of the PNP transistor Q1, and the gate of the PMOS tube M2 is connected to the gate of the PMOS tube M3, the gate of the PMOS tube M4, the gate of the PMOS tube M6, the gate of the PMOS tube M8, the gate of the PMOS tube M9, the drain of the NMOS tube M16 and the input end of the amplifier OP2. The output terminal of the circuit is connected to the output terminal of the circuit, the drain of the PMOS tube M3 is respectively connected to the positive input terminal of the amplifier OP2 and one end of the resistor R2, the other end of the resistor R2 is connected to the emitter of the PNP transistor Q2, the drain of the PMOS tube M4 is respectively connected to the drain of the PMOS tube M5, the drain of the PMOS tube M14, one end of the resistor R3 and the circuit output terminal VREF, the other end of the resistor R3 is respectively connected to the other end of the resistor R4, the drain of the PMOS tube M6, the drain of the PMOS tube M7 and the gate of the NMOS tube M19.

[0024] The high temperature area curvature compensation circuit 2 includes: a PMOS transistor M8, a PMOS transistor M9, an NMOS transistor M10, a PMOS transistor M11, an NMOS transistor M12, an NMOS transistor M13, a PMOS transistor M14, and a resistor R5, wherein the source of the PMOS transistor M8 is respectively connected to the source of the PMOS transistor M9, the source of the PMOS transistor M11, the source of the PMOS transistor M14, and the external power supply VDD, and the drain of the PMOS transistor M8 is respectively connected to the gate of the NMOS transistor M12 and one end of the resistor R5. The other end of the resistor R5 is respectively connected to the source of the NMOS transistor M10, the source of the NMOS transistor M13, and the external ground line GND. The drain of the PMOS transistor M9 is respectively connected to the drain of the NMOS transistor M10, the gate of the NMOS transistor M10, and the gate of the NMOS transistor M13. The drain of the PMOS transistor M11 is respectively connected to the gate of the PMOS transistor M11, the drain of the NMOS transistor M12, and the gate of the PMOS transistor M14. The source of the NMOS transistor M12 is connected to the drain of the NMOS transistor M13.

[0025] The startup circuit 3 includes: an NMOS transistor M15, an NMOS transistor M16, a PMOS transistor M17, a PMOS transistor M18 and an NMOS transistor M19, wherein the source of the PMOS transistor M17 is connected to the external ground line VDD, the gate of the PMOS transistor M17 is respectively connected to the drain of the PMOS transistor M17 and the source of the PMOS transistor M18, the gate of the PMOS transistor M18 is respectively connected to the drain of the PMOS transistor M18, the gate of the NMOS transistor M16, the gate of the NMOS transistor M15 and the drain of the NMOS transistor M19, and the source of the NMOS transistor M15 is respectively connected to the source of the NMOS transistor M16, the source of the NMOS transistor M19 and the external ground line GND.

[0026] The amplifier OP1 and the amplifier OP2 in the high-order curvature compensation bandgap reference circuit are prior art.

[0027] In the first-order bandgap reference circuit 1, the PMOS transistor M2 and the PMOS transistor M3 have the same channel width-to-length ratio, the emitter area of ​​the PNP transistor Q2 is N times that of the PNP transistor Q1, and the low-frequency gain A of the amplifier OP1 and the amplifier OP2 is d There is A d >>1, then the current I1 of the PMOS tube M1 and the current I3 of the PMOS tube M3 are

[0028]

[0029] Where R1 is the resistance of resistor R1, R2 is the resistance of resistor R2, V EB1 is the emitter-base voltage of the PNP transistor Q1, V Tis a thermovoltage with a positive temperature coefficient, N is the ratio of the emitter areas of PNP transistor Q2 to PNP transistor Q1. PMOS transistors M1 and M5 have the same channel width-to-length ratio, the channel width-to-length ratio of PMOS transistor M7 is α times that of PMOS transistor M1, PMOS transistors M3 and M4 have the same channel width-to-length ratio, and the channel width-to-length ratio of PMOS transistor M6 is β times that of PMOS transistor M2. Resistors R1, R2, R3, and R4 are made of the same material. The voltage V generated by the current in PMOS transistors M4, M5, M6, and M7 across resistors R3 and R4 is: REF1 have

[0030]

[0031] Where R1 is the resistance of resistor R1, R2 is the resistance of resistor R2, R3 is the resistance of resistor R3, R4 is the resistance of resistor R4, V EB1 is the emitter-base voltage of the PNP transistor Q1, V T is the thermal voltage with a positive temperature coefficient, N is the ratio of the emitter area of ​​PNP transistor Q2 to that of PNP transistor Q1, α is the multiple of the channel width-to-length ratio of PMOS transistor M7 to that of PMOS transistor M1, and β is the multiple of the channel width-to-length ratio of PMOS transistor M6 to that of PMOS transistor M2. Among them, the emitter-base voltage V EB1 It has a negative temperature coefficient. Therefore, by optimizing the parameters of the corresponding MOS tubes and resistors, the voltage V at the reference temperature T0 is REF1 have Where T is the absolute temperature.

[0032] In the high temperature region curvature compensation circuit 2, the channel width-to-length ratio of the PMOS tube M8 is K1 times that of the PMOS tube M3, and the gate voltage V G12 for

[0033]

[0034] Where, R2 is the resistance of resistor R2, R5 is the resistance of resistor R5, K1 is the multiple of the channel width-to-length ratio of PMOS tube M8 to PMOS tube M3, V T is the thermal voltage with a positive temperature coefficient, N is the ratio of the emitter area of ​​the PNP transistor Q2 to that of the PNP transistor Q1. The gate voltage V G12As the temperature increases, the NMOS tube M12 causes the NMOS tube M13's working area to gradually transition from the deep triode area and triode area to the saturation area. The PMOS tube M9 is exactly the same as the PMOS tube and the PMOS tube M2. The channel width-to-length ratio of the PMOS tube M9 is K2 times that of the PMOS tube M3. The NMOS tube M10 and the NMOS tube M13 have the same channel width-to-length ratio. By optimizing the parameters of the MOS tube, the current I 11 for

[0035]

[0036] where μ n is the electron mobility, C ox is the gate oxide capacitance per unit area, (W / L) 10 is the channel width-to-length ratio of the NMOS transistor M10, (W / L) 13 is the channel width-to-length ratio of the NMOS tube M13, V D13 is the drain voltage of NMOS tube M13, V T is the thermovoltage with a positive temperature coefficient, K2 is the ratio of the channel width to length ratio of the PMOS tube M9 and the PMOS tube M3, N is the ratio of the emitter area of ​​the PNP transistor Q2 and the PNP transistor Q1, T is the absolute temperature, T r1 、T r2 With T0 as the reference temperature, and T r2 >T r1 >T0. The channel width-to-length ratio of the PMOS tube M14 is K3 times that of the PMOS tube M11, and the output voltage V REF for

[0037] V REF =V REF1 +(R3+R4)K3I 11 (6)

[0038] Where V REF1 is the voltage generated by the current of the PMOS tube M4, PMOS tube M5, PMOS tube M6 and PMOS tube M7 on the resistor R3 and the resistor R4, R3 is the resistance value of the resistor R3, R4 is the resistance value of the resistor R4, I 11 is the current of the PMOS tube M11, K3 is the ratio of the channel width-to-length ratio of the PMOS tube M14 to the channel width-to-length ratio of the PMOS tube M11, and the factor (R3+R4)K3I 11 Temperature high-order nonlinearity can be effectively compensated by optimizing circuit parameters. REF1 The temperature nonlinearity and thus the low temperature drift coefficient of the bandgap reference voltage are improved.

[0039] Figure 3 The output voltage V of a high-order curvature compensation bandgap reference circuit of the present invention is REF The temperature characteristic simulation curve of the bandgap reference circuit is shown in Figure 1, where the horizontal axis is the temperature T and the vertical axis is the output voltage of the bandgap reference. The simulation results show that in the temperature range of -40℃ to 125℃, the output voltage V REF The temperature coefficient is only 6.83ppm / ℃.

[0040] In the above-mentioned embodiment of the present application, a high-order curvature compensation bandgap reference circuit includes a first-order bandgap reference circuit, a high-temperature region curvature compensation circuit, and a startup circuit. The present embodiment utilizes a technique in which the voltages generated by the current of the PMOS transistor M4 across the resistors R3 and R4, and the voltage generated by the current of the PMOS transistor M6 across the resistor R4, are both positive temperature coefficient voltages; utilizes a technique in which the voltages generated by the current of the PMOS transistor M5 across the resistors R3 and R4, and the voltage generated by the current of the PMOS transistor M7 across the resistor R4, are both negative temperature coefficient voltages; a first-order bandgap reference voltage is generated by weighted summing of the positive temperature coefficient voltages and the negative temperature coefficient voltages; and utilizes a technique in which the gate voltage of the NMOS transistor M12 in the high-temperature region curvature compensation circuit increases with increasing temperature to control the operation of the NMOS transistor M13, and the operating region of the NMOS transistor M13 gradually transitions from a deep triode region and a triode region to a saturation region as the temperature increases, thereby making the current of the PMOS transistor M14 high-order temperature nonlinear, thereby temperature-compensating the first-order bandgap reference voltage, thereby obtaining a high-order temperature-compensated bandgap base voltage.

[0041] The above embodiments should be understood as merely illustrating the present invention and not as limiting the scope of protection of the present invention. After reading the contents of the present invention, technicians may make various changes or modifications to the present invention, and these equivalent changes and modifications also fall within the scope defined by the claims of the present invention.

Claims

1. A high-order curvature-compensated bandgap reference circuit, characterized in that: include: A first-order bandgap reference circuit (1), a high-temperature region curvature compensation circuit (2) and a start-up circuit (3), wherein the signal output end of the first-order bandgap reference circuit (1) is respectively connected to the signal input end of the high-temperature region curvature compensation circuit (2) and the start-up circuit (3), the high-temperature region curvature compensation circuit (2) is connected to the electrical signal input end of the first-order bandgap reference circuit (1), the signal output end of the start-up circuit (3) is connected to the start-up signal input end of the first-order bandgap reference circuit (1), and the first-order bandgap reference circuit (1) generates a bandgap reference reference voltage. voltage; the startup circuit (3) enables the bandgap reference circuit to operate normally and generate a bandgap reference voltage output; the high-temperature region curvature compensation circuit (2) compensates the bandgap reference voltage generated by the first-order bandgap reference circuit (1) to obtain a bandgap reference voltage with a low temperature drift coefficient; the high-temperature region curvature compensation circuit (2) includes: a PMOS tube M8, a PMOS tube M9, an NMOS tube M10, a PMOS tube M11, an NMOS tube M12, an NMOS tube M13, a PMOS tube M14, and a resistor R5, wherein the PMOS tube The source of M8 is connected to the source of PMOS tube M9, the source of PMOS tube M11, the source of PMOS tube M14 and the external power supply VDD respectively. The drain of PMOS tube M8 is connected to the gate of NMOS tube M12 and one end of resistor R5 respectively. The other end of resistor R5 is connected to the source of NMOS tube M10, the source of NMOS tube M13 and the external ground GND respectively. The drain of PMOS tube M9 is connected to the drain of NMOS tube M10, the gate of NMOS tube M10 and the gate of NMOS tube M13 respectively. The drain of the MOS tube M11 is respectively connected to the gate of the PMOS tube M11, the drain of the NMOS tube M12 and the gate of the PMOS tube M14, and the source of the NMOS tube M12 is connected to the drain of the NMOS tube M13; in the high temperature region curvature compensation circuit (2), the gate voltage of the NMOS tube M12 increases with the increase of temperature, and then as the temperature increases, the NMOS tube M12 causes the working area of ​​the NMOS tube M13 to gradually transition from the deep triode region and the triode region to the saturation region, so that the current of the PMOS tube M11 is temperature high-order nonlinear.

2. The high-order curvature-compensated bandgap reference circuit according to claim 1, wherein: The first-order bandgap reference circuit (1) comprises: a PMOS tube M1, a PMOS tube M2, a PMOS tube M3, a PMOS tube M4, a PMOS tube M5, a PMOS tube M6, a PMOS tube M7, a resistor R1, a resistor R2, a resistor R3, a resistor R4, a PNP transistor Q1, a PNP transistor Q2, an amplifier OP1 and an amplifier OP2, wherein the source of the PMOS tube M1 is connected to the source of the PMOS tube M2, the source of the PMOS tube M3, the source of the PMOS tube M4, the PMOS tube M5 and the PMOS tube M6 respectively. The source of the MOS tube M5, the source of the PMOS tube M6, the source of the PMOS tube M7 and the external power supply VDD are connected. The drain of the PMOS tube M1 is connected to the positive input terminal of the amplifier OP1 and one end of the resistor R1 respectively. The other end of the resistor R1 is connected to the collector of the PNP transistor Q1, the base of the PNP transistor Q1, the collector of the PNP transistor Q2, the base of the PNP transistor Q2, one end of the resistor R4 and the external ground GND respectively. The gate of the PMOS tube M1 is connected to the P The gate of the MOS tube M5, the gate of the PMOS tube M7 and the output end of the amplifier OP1 are connected, the drain of the PMOS tube M2 is respectively connected to the inverting input end of the amplifier OP1, the inverting input end of the amplifier OP2 and the emitter of the PNP transistor Q1, the gate of the PMOS tube M2 is respectively connected to the gate of the PMOS tube M3, the gate of the PMOS tube M4, the gate of the PMOS tube M6, the gate of the PMOS tube M8, the gate of the PMOS tube M9 and the output end of the amplifier OP2, The drain of the MOS transistor M3 is respectively connected to the positive input terminal of the amplifier OP2 and one end of the resistor R2. The other end of the resistor R2 is connected to the emitter of the PNP transistor Q2. The drain of the PMOS transistor M4 is respectively connected to the drain of the PMOS transistor M5, the drain of the PMOS transistor M14, one end of the resistor R3, and the circuit output terminal VREF. The other end of the resistor R3 is respectively connected to the other end of the resistor R4, the drain of the PMOS transistor M6, the drain of the PMOS transistor M7, and the gate of the NMOS transistor M19.

3. The high-order curvature-compensated bandgap reference circuit according to claim 1, wherein: The startup circuit (3) comprises: an NMOS transistor M15, an NMOS transistor M16, a PMOS transistor M17, a PMOS transistor M18 and an NMOS transistor M19, wherein the source of the PMOS transistor M17 is connected to an external power supply VDD, the gate of the PMOS transistor M17 is respectively connected to the drain of the PMOS transistor M17 and the source of the PMOS transistor M18, the gate of the PMOS transistor M18 is respectively connected to the drain of the PMOS transistor M18, the gate of the NMOS transistor M16, the gate of the NMOS transistor M15 and the drain of the NMOS transistor M19, the drain of the NMOS transistor M15 is connected to the gate of the PMOS transistor M7, the drain of the NMOS transistor M16 is connected to the output end of the amplifier OP2, and the source of the NMOS transistor M15 is respectively connected to the source of the NMOS transistor M16, the source of the NMOS transistor M19 and the external ground line GND.

4. The high-order curvature-compensated bandgap reference circuit according to claim 2, wherein: In the first-order bandgap reference circuit (1), the PMOS transistor M2 and the PMOS transistor M3 have the same channel width-to-length ratio, the emitter area of ​​the PNP transistor Q2 is N times that of the PNP transistor Q1, and the low-frequency gain A of the amplifier OP1 and the amplifier OP2 is d There is A d >>1. PMOS transistors M1 and M5 have the same channel width-to-length ratio. The channel width-to-length ratio of PMOS transistor M7 is α times that of PMOS transistor M1. PMOS transistors M3 and M4 have the same channel width-to-length ratio. The channel width-to-length ratio of PMOS transistor M6 is β times that of PMOS transistor M2. Resistors R1, R2, R3, and R4 are made of the same material. The voltage V generated by the current in PMOS transistors M4, M5, M6, and M7 across resistors R3 and R4 is REF1 have Where R1 is the resistance of resistor R1, R2 is the resistance of resistor R2, R3 is the resistance of resistor R3, R4 is the resistance of resistor R4, V EB1 is the emitter-base voltage of the PNP transistor Q1, V T is the thermal voltage with a positive temperature coefficient, N is the ratio of the emitter area of ​​PNP transistor Q2 to that of PNP transistor Q1, α is the channel width-to-length ratio of PMOS transistor M7, which is α times that of PMOS transistor M1, and β is the channel width-to-length ratio of PMOS transistor M6, which is β times that of PMOS transistor M2; the emitter-base voltage V EB1 It has a negative temperature coefficient. Therefore, by optimizing the parameters of the corresponding MOS tube and resistor, the voltage V at the reference temperature T0 is REF1 have Where T is the absolute temperature.

5. The high-order curvature-compensated bandgap reference circuit according to claim 1, wherein: In the high temperature region curvature compensation circuit (2), the channel width-to-length ratio of the PMOS tube M8 is K1 times that of the PMOS tube M3, and the current I8 of the PMOS tube M8 and the current I3 of the PMOS tube M3 are I8=K1I3; the PMOS tube M9 is exactly the same as the PMOS tube M2, and the channel width-to-length ratio of the PMOS tube M9 is K2 times that of the PMOS tube M3; the NMOS tube M10 and the NMOS tube M13 have the same channel width-to-length ratio. By optimizing the parameters of the MOS tubes, the current I 11 for where μ n is the electron mobility, C ox is the gate oxide capacitance per unit area, (W / L) 10 is the channel width-to-length ratio of the NMOS transistor M10, (W / L) 13 is the channel width-to-length ratio of the NMOS tube M13, V T is the thermal voltage with a positive temperature coefficient, K2 is the ratio of the channel width to length ratio of the PMOS tube M9 and the PMOS tube M3, N is the ratio of the emitter area of ​​the PNP transistor Q2 and the PNP transistor Q1, V D13 is the drain voltage of NMOS tube M13, R2 is the resistance value of resistor R2, T is the absolute temperature, T r1 、T r2 With T0 as the reference temperature, and T r2 >T r1 >T0.

6. A high-order curvature-compensated bandgap reference circuit according to any one of claims 4-5, characterized in that: The channel width-to-length ratio of the PMOS tube M14 is K3 times that of the PMOS tube M11. Then the output voltage V REF V REF =V REF1 +(R3+R4)K3I 11 Where V REF1 is the voltage generated by the current of the PMOS tube M4, PMOS tube M5, PMOS tube M6 and PMOS tube M7 on the resistor R3 and the resistor R4, R3 is the resistance value of the resistor R3, R4 is the resistance value of the resistor R4, I 11 is the current of the PMOS tube M11, K3 is the ratio of the channel width-to-length ratio of the PMOS tube M14 to the channel width-to-length ratio of the PMOS tube M11; the factor (R3+R4)K3I 11 Temperature high-order nonlinearity can be effectively compensated by optimizing circuit parameters. REF1 The temperature nonlinearity is reduced, thereby generating a bandgap reference voltage with a low temperature drift coefficient.

Images