Semiconductor device

Abstract

Provided is a semiconductor device including: a plurality of transistor regions; a gate pad provided over a semiconductor substrate; a built-in resistance part electrically connected to the gate pad; a plurality of gate wiring parts electrically connected to the built-in resistance part and provided in accordance with the plurality of transistor regions; and a plurality of wiring resistance parts provided in accordance with the plurality of gate wiring parts. The plurality of gate wiring parts may include a gate metal layer provided over the semiconductor substrate and a gate runner provided under the gate metal layer.

Description

Semiconductor Devices

[0001] The present invention relates to a semiconductor device.

[0002] Patent Document 1 describes a semiconductor device in which "the resistance value of an internal resistor distant from the gate pad 12 is higher than the resistance value of an internal resistor close to the gate pad 12." [Prior art documents] [Patent documents] [Patent document 1] JP 2010-98250 A [Patent document 2] Japanese Patent No. 6874443 [Patent document 3] Japanese Patent No. 6187697 [Patent document 4] Japanese Patent No. 5493840 General disclosure

[0003] (Problem to be Solved) It is desirable to suppress oscillation between semiconductor chips connected in parallel and oscillation within a single semiconductor chip. (Means for Solving the Problem)

[0004] A first aspect of the present invention provides a semiconductor device comprising: a plurality of transistor regions; gate trench portions provided in the plurality of transistor regions; a gate pad provided above a semiconductor substrate; a plurality of gate wiring portions electrically connected between the gate pad and the gate trench portion and provided corresponding to any one of the plurality of transistor regions; and a plurality of wiring resistance portions provided corresponding to the plurality of gate wiring portions.

[0005] The semiconductor device may further include a built-in resistor portion having one end electrically connected to the gate pad and the other end electrically connected to the plurality of gate wiring portions.

[0006] In any of the above semiconductor devices, the plurality of gate wiring portions may include a gate metal layer provided above the semiconductor substrate, and a gate runner provided below the gate metal layer.

[0007] Any of the above semiconductor devices may further include a contact portion provided between the gate metal layer and the gate runner, connecting the gate metal layer and the gate runner.

[0008] In any of the above semiconductor devices, the gate pad may be provided closer to the outer periphery of the semiconductor substrate than the plurality of transistor regions when viewed from above.

[0009] In any of the above semiconductor devices, each of the plurality of wiring resistance portions may be connected to each of the plurality of transistor regions.

[0010] In any of the above semiconductor devices, two or more of the plurality of wiring resistance sections may be connected to one of the plurality of transistor regions.

[0011] In any of the above semiconductor devices, the gate pad may be provided between the plurality of transistor regions in a top view.

[0012] In any of the above semiconductor devices, the built-in resistor section may include a first built-in resistor and a second built-in resistor different from the first built-in resistor, and the plurality of wiring resistor sections may include one or more first wiring resistors connected to the first built-in resistor, and one or more second wiring resistors connected to the second built-in resistor and different from the first wiring resistor.

[0013] In any of the above semiconductor devices, the plurality of gate wiring portions may be spaced apart from each other in a top view.

[0014] In any of the semiconductor devices described above, the plurality of wiring resistance portions may be provided in any of the plurality of gate wiring portions, and a cross-sectional area of ​​the wiring resistance portion perpendicular to an extension direction may be smaller than a cross-sectional area of ​​the gate wiring portion perpendicular to the extension direction.

[0015] In any of the above semiconductor devices, each of the plurality of wiring resistance portions may be disposed closer to the gate pad than each of the plurality of transistor regions.

[0016] In any of the above semiconductor devices, the plurality of gate wiring portions may be made of polysilicon.

[0017] In any of the above semiconductor devices, the built-in resistor may be made of polysilicon.

[0018] In any of the above semiconductor devices, each of the plurality of wiring resistance portions may be formed with a single layer structure of polysilicon.

[0019] Any of the above semiconductor devices may further include a first resistance measurement pad for measuring the resistance of the built-in resistor portion.

[0020] Any of the above semiconductor devices may further include a second resistance measurement pad for measuring the resistance of the wiring resistance portion.

[0021] Any of the above semiconductor devices may further include an emitter electrode provided above the semiconductor substrate. The emitter electrode may have a plurality of emitter electrode portions spaced apart from one another. The plurality of emitter electrode portions may be provided corresponding to the plurality of wiring resistance portions, respectively.

[0022] Any of the above semiconductor devices may further include an emitter electrode provided above the semiconductor substrate. The emitter electrode may have a plurality of emitter electrode portions spaced apart from one another. One of the plurality of emitter electrode portions may be provided corresponding to two or more of the plurality of wiring resistor portions.

[0023] Any of the above semiconductor devices may further include a single emitter electrode provided above the semiconductor substrate and shared by the plurality of wiring resistance portions.

[0024] In any of the above semiconductor devices, a combined resistance value of the plurality of wiring resistance sections may be 10% to 80% of a combined resistance of the built-in resistance section and the plurality of wiring resistance sections.

[0025] In any of the above semiconductor devices, the plurality of gate wiring sections may include a first gate wiring and a second gate wiring that is longer than the first gate wiring, and a resistance value of the wiring resistance section connected to the first gate wiring may be greater than a resistance value of the wiring resistance section connected to the second gate wiring.

[0026] In any of the above semiconductor devices, the plurality of transistor regions may include a first transistor region and a second transistor region having approximately the same area as the first transistor region, and a resistance value of a wiring resistor provided in a gate wiring portion connected to a gate conductive portion of the first transistor region may be approximately equal to a resistance value of a wiring resistor provided in a gate wiring portion connected to a gate conductive portion of the second transistor region.

[0027] In any of the above semiconductor devices, the plurality of transistor regions may include a first transistor region and a second transistor region having an area larger than that of the first transistor region, and a resistance value of a wiring resistor provided in a gate wiring portion connected to a gate conductive portion of the first transistor region may be greater than a resistance value of a wiring resistor provided in a gate wiring portion connected to a gate conductive portion of the second transistor region.

[0028] In any of the above semiconductor devices, the resistance value of each of the plurality of wiring resistance sections may be 3Ω or more and 30Ω or less.

[0029] In any of the above semiconductor devices, the resistance value of the gate trench portion may be 6 kΩ or less in any of the plurality of transistor regions.

[0030] In any of the above semiconductor devices, the error in the value of the CR time constant, which is the product of the capacitance of the transistor region and the resistance value of the wiring resistor section provided corresponding to the transistor region, may be within 20% in each of the plurality of transistor regions.

[0031] In any of the above semiconductor devices, the plurality of gate wiring portions may be provided between two adjacent transistor regions among the plurality of transistor regions and may include a gate wiring portion connected to one of the two adjacent transistor regions.In any of the above semiconductor devices, the plurality of gate wiring portions may include a gate wiring portion connected to the other of the two adjacent transistor regions.

[0032] The above summary of the invention does not list all of the features of the present invention, and subcombinations of these features may also be inventions.

[0033] 1 is a diagram showing an example of the top surface of the semiconductor device 100. FIG. 2 is a diagram showing an example of the top surface of the semiconductor device 100. FIG. 3 is a diagram showing an example of an aa' cross section of the semiconductor device 100. FIG. 4 is a diagram showing an example of the top surface of the semiconductor device 100. FIG. 5 is a diagram showing an example of an enlarged view of the top surface of the semiconductor device 100. FIG. 6 is a diagram showing an example of a bb' cross section of the semiconductor device 100. FIG. 7 is a diagram showing an example of a cc' cross section of the semiconductor device 100. FIG. 8 is a diagram showing an example of the top surface of the resistance measurement pad of the present example. FIG. 9 is a diagram showing a modified example of the top surface of the semiconductor device 100. FIG. 10 is a diagram showing a modified example of the top surface of the semiconductor device 100. FIG. 11 is a diagram showing an example of a dd' cross section of the semiconductor device 100.

[0034] The present invention will be described below through embodiments of the invention, but the following embodiments do not limit the scope of the invention as claimed. Furthermore, not all of the combinations of features described in the embodiments are necessarily essential to the solution of the invention.

[0035] In this specification, one side in a direction parallel to the depth direction of a semiconductor substrate is referred to as "upper" and the other side as "lower." Of the two main surfaces of a substrate, layer, or other member, one surface is referred to as the upper surface and the other surface is referred to as the lower surface. The directions of "upper" and "lower" are not limited to the direction of gravity or the directions when the semiconductor device is mounted.

[0036] In this specification, technical matters may be explained using orthogonal coordinate axes of the X-axis, Y-axis, and Z-axis. The orthogonal coordinate axes merely identify the relative positions of components and do not limit a specific direction. For example, the Z-axis does not limit the height direction relative to the ground. Note that the +Z-axis direction and the -Z-axis direction are opposite directions. When the Z-axis direction is described without specifying positive or negative, it means a direction parallel to the +Z-axis and -Z-axis.

[0037] In this specification, orthogonal axes parallel to the upper and lower surfaces of the semiconductor substrate are referred to as the X-axis and Y-axis. Furthermore, an axis perpendicular to the upper and lower surfaces of the semiconductor substrate is referred to as the Z-axis. In this specification, the direction of the Z-axis may be referred to as the depth direction. Furthermore, in this specification, the direction parallel to the upper and lower surfaces of the semiconductor substrate, including the X-axis and Y-axis, may be referred to as the horizontal direction.

[0038] In this specification, when P+ type or N+ type is used, it means that the doping concentration is higher than that of P type or N type, and when P- type or N- type is used, it means that the doping concentration is lower than that of P type or N type.

[0039] 1A shows an example of the top surface of the semiconductor device 100. In this example, only some components of the semiconductor device 100 are shown, and some components are omitted. The semiconductor device 100 may be an example of a single semiconductor chip, or may be an example of a semiconductor module including multiple semiconductor chips.

[0040] The semiconductor substrate 10 has edges 102 in a top view. The semiconductor substrate 10 of this example has two pairs of edges 102 facing each other in a top view. In this example, the X-axis and the Y-axis are parallel to one of the edges 102. The semiconductor substrate 10 is silicon. The semiconductor substrate 10 may be a wide bandgap semiconductor such as gallium nitride or silicon carbide.

[0041] The semiconductor substrate 10 is provided with a plurality of transistor regions 120. The transistor regions 120 are regions through which a main current flows in the depth direction between a front surface 21 and a back surface 23 of the semiconductor substrate 10 when the semiconductor device 100 is in operation. The front surface 21 and the back surface 23 will be described later. An emitter electrode is provided above the transistor region 120, but is not shown in the figure.

[0042] The transistor region 120 is provided with at least one of a transistor section 70 including a transistor element such as an IGBT and a diode section 80 including a diode element such as a free wheel diode (FWD). In the example of FIG. 1A , the transistor sections 70 and the diode sections 80 are alternately arranged along a predetermined arrangement direction (the X-axis direction in this example) on the front surface 21 of the semiconductor substrate 10. In another example, the transistor region 120 may be provided with only one of the transistor section 70 and the diode section 80.

[0043] In this example, the region where the transistor section 70 is disposed is marked with the symbol "I," and the region where the diode section 80 is disposed is marked with the symbol "F." The transistor section 70 and the diode section 80 may each have a longitudinal direction in the extension direction. That is, the length of the transistor section 70 in the Y-axis direction is greater than the width in the X-axis direction. Similarly, the length of the diode section 80 in the Y-axis direction is greater than the width in the X-axis direction. The extension direction of the transistor section 70 and the diode section 80 may be the same as the longitudinal direction of each trench section.

[0044] The transistor section 70 is a region obtained by projecting a collector region 22 provided on the back surface side of the semiconductor substrate 10 onto the upper surface of the semiconductor substrate 10. The collector region 22 will be described later. The transistor section 70 includes a transistor such as an IGBT. In this example, the transistor section 70 is an IGBT. However, the transistor section 70 may be another transistor such as a MOSFET.

[0045] The diode section 80 is a region obtained by projecting a cathode region 82 provided on the rear surface 23 side of the semiconductor substrate 10 onto the upper surface of the semiconductor substrate 10. The cathode region 82 will be described later. A P+ type collector region 22 may be provided in the region of the rear surface 23 of the semiconductor substrate 10 other than the cathode region 82.

[0046] The semiconductor device 100 may have one or more pads above the semiconductor substrate 10. The semiconductor device 100 of this example has a gate pad 50. The semiconductor device 100 may also have pads such as an anode pad and a cathode pad. In this example, each pad is located near an edge 102. The vicinity of the edge 102 refers to the region between the edge 102 and the transistor region 120 in a top view. When the semiconductor device 100 is mounted, each pad may be connected to an external circuit via wiring such as a wire. Furthermore, the location of each pad does not have to be near the edge 102.

[0047] A gate potential is applied to the gate pad 50. The gate pad 50 is electrically connected to gate conductive portions of the gate trench portions of the transistor region 120 via a plurality of gate wiring portions 48. In FIG. 1A, the gate wiring portions 48 are hatched with diagonal lines.

[0048] The gate wiring section 48 may be configured by appropriately combining either or both of a gate metal layer 47 and a gate runner 46, which will be described later. The configuration and arrangement of the gate wiring section 48 and the transistor region 120 will be described later.

[0049] The edge termination structure 140 is provided on the front surface 21 of the semiconductor substrate 10. In a top view, the edge termination structure 140 is provided between the transistor region 120 and the edge 102. In this example, the edge termination structure 140 is disposed between the gate wiring portion 48 and the edge 102. The edge termination structure 140 relieves electric field concentration on the front surface 21 side of the semiconductor substrate 10. The edge termination structure 140 may include at least one of a guard ring, a field plate, and a resurf, which are provided in an annular shape surrounding the transistor region 120.

[0050] Fig. 1B is a diagram showing an example of the top surface of the semiconductor device 100. Fig. 1B is an enlarged view of the region indicated by A in Fig. 1A. Fig. 1B shows the vicinity of the negative end in the Y-axis direction of one of the plurality of transistor regions 120. The semiconductor device 100 includes a semiconductor substrate 10 having a transistor section 70 including a transistor element such as an IGBT, and a diode section 80 including a diode element such as a free wheel diode (FWD).

[0051] The semiconductor device 100 of this example includes a gate trench portion 40, a dummy trench portion 30, a well region 130, an emitter region 12, a base region 14, and a contact region 15, which are provided inside the front surface side of a semiconductor substrate 10. The gate trench portion 40 and the dummy trench portion 30 are each an example of a trench portion.

[0052] The semiconductor device 100 of this example also includes a gate metal layer 47 and an emitter electrode 52 provided above the front surface of the semiconductor substrate 10. The emitter electrode 52 is an example of a front surface electrode. The gate metal layer 47 and the emitter electrode 52 are electrically insulated from each other.

[0053] An interlayer insulating film is provided between the emitter electrode 52 and the gate metal layer 47 and the front surface of the semiconductor substrate 10, but is not shown in FIG. 1B. In this example, contact holes 49, 54, and 56 are provided through the interlayer insulating film. In FIG. 1B, each contact hole is hatched with diagonal lines.

[0054] The emitter electrode 52 is provided above the gate trench portion 40, the dummy trench portion 30, the well region 130, the emitter region 12, the base region 14, and the contact region 15. The emitter electrode 52 is electrically connected to the emitter region 12, the base region 14, and the contact region 15 on the front surface of the semiconductor substrate 10 via contact holes 54.

[0055] The emitter electrode 52 is connected to a dummy conductive portion in the dummy trench portion 30 by a contact hole 56. A connection portion 25 made of a conductive material such as polysilicon doped with impurities may be provided between the emitter electrode 52 and the dummy conductive portion. The connection portion 25 is provided on the front surface of the semiconductor substrate 10 via an insulating film such as an interlayer insulating film and a dummy insulating film in the dummy trench portion 30.

[0056] The gate runner 46 is connected to the gate conductive portion in the gate trench portion 40 on the front surface of the semiconductor substrate 10 by a contact hole 55. The gate runner 46 is electrically connected to the gate metal layer 47 through a contact hole 49. The gate runner 46 is not electrically connected to the dummy conductive portion in the dummy trench portion 30 or the emitter electrode 52.

[0057] The gate runner 46 and the emitter electrode 52 are electrically isolated by an insulator such as an interlayer insulating film and an oxide film. The gate runner 46 in this example is provided from below the contact hole 49 to the tip end (the end in the Y-axis direction) of the gate trench portion 40. The gate conductive portion is exposed on the front surface of the semiconductor substrate 10 at the tip end of the gate trench portion 40 and is connected to the gate runner 46.

[0058] The emitter electrode 52 is made of a conductive material containing metal, such as aluminum or an aluminum-silicon alloy. The emitter electrode 52 may have a barrier metal made of titanium, a titanium compound, or the like below the region made of aluminum or the like.

[0059] The emitter electrode 52 may have a plug formed of tungsten or the like in the contact hole. The plug may have a barrier metal on the side in contact with the semiconductor substrate 10, with tungsten buried so as to be in contact with the barrier metal, and may be formed of aluminum or the like on the tungsten.

[0060] The well region 130 extends outside the gate runner 46, overlapping with the peripheral region, and is provided in a ring shape in top view. The well region 130 also extends to the transistor region 120 inside the gate runner 46 by a predetermined width, and is provided in a ring shape in top view. In this example, the well region 130 is provided in a range that is farther toward the gate runner 46 than the end of the contact hole 54 in the Y-axis direction. The well region 130 is a region of the second conductivity type that has a doping concentration higher than that of the base region 14. The doping concentration of the well region 130 may be the same as or lower than the doping concentration of the contact region 15. The gate runner 46 is electrically insulated from the well region 130.

[0061] In this example, the base region 14 is P- type, and the well region 130 is P+ type. The well region 130 is formed from the front surface of the semiconductor substrate to a position deeper than the lower end of the base region 14. The base region 14 is provided in contact with the well region 130 in the transistor section 70 and the diode section 80. The well region 130 is electrically connected to the emitter electrode 52.

[0062] Each of the transistor section 70 and the diode section 80 has a plurality of trench sections arranged in the arrangement direction. In the transistor section 70 of this example, one or more gate trench sections 40 and one or more dummy trench sections 30 are alternately provided along the arrangement direction. In the diode section 80 of this example, a plurality of dummy trench sections 30 are provided along the arrangement direction.

[0063] In this example, the arrangement direction of the trench portions is the X-axis direction, and the extension direction perpendicular to the arrangement direction is the Y-axis direction. The gate trench portion 40 in this example may have two extension portions 41 (parts of the trench that are linear along the extension direction) extending along the extension direction, and a connection portion 43 connecting the two extension portions 41.

[0064] At least a part of the connection portion 43 may be curved in top view. The connection portion 43 connects the ends of the two extension portions 41 in the Y-axis direction to the gate runner 46, thereby functioning as a gate electrode to the gate trench portion 40. On the other hand, by making the connection portion 43 curved, electric field concentration at the ends can be alleviated more effectively than if the connection portion 43 were completed at the extension portion 41.

[0065] In the transistor section 70, the dummy trench section 30 is provided between the respective extension portions 41 of the gate trench section 40. In the example of FIG. 1B , one dummy trench section 30 is provided between the respective extension portions 41, but two or more dummy trench sections 30 may be provided.

[0066] Furthermore, the dummy trench portion 30 may not be provided between the extension portions 41, and the gate trench portion 40 may be provided instead. With such a structure, the electron current from the emitter region 12 can be increased, thereby reducing the on-voltage.

[0067] The dummy trench portion 30 may have a linear shape extending in the extension direction, and may have an extension portion 31 and a connection portion 33, similar to the gate trench portion 40. The semiconductor device 100 shown in FIG. 1B includes a U-shaped dummy trench portion 30 having the connection portion 33, and a linear dummy trench portion 30 without the connection portion 33. The semiconductor device 100 may be configured to include only the dummy trench portion 30 having the connection portion 33.

[0068] The diffusion depth of the well region 130 may be deeper than the depths of the gate trench portion 40 and the dummy trench portion 30. The Y-axis direction ends of the gate trench portion 40 and the dummy trench portion 30 are provided in the well region 130 when viewed from above. In other words, at the Y-axis direction ends of each trench portion, the bottom portion of each trench portion in the depth direction (positive side in the Z-axis direction) is covered by the well region 130. This makes it possible to alleviate electric field concentration at the bottom portion of each trench portion.

[0069] A mesa portion is provided between each trench portion in the arrangement direction. The mesa portion refers to a region sandwiched between the trench portions inside the semiconductor substrate 10. As an example, the depth position of the mesa portion is from the front surface of the semiconductor substrate to the bottom end of the trench portion.

[0070] The mesa portion in this example is sandwiched between adjacent trench portions in the X-axis direction, and is provided on the front surface of the semiconductor substrate 10 so as to extend in the extension direction (Y-axis direction) along the trenches.

[0071] Each mesa portion is provided with a base region 14. In each mesa portion, at least one of a first conductivity type emitter region 12 and a second conductivity type contact region 15 may be provided in a region sandwiched between the base regions 14 in a top view. In this example, the emitter region 12 is N+ type, and the contact region 15 is P+ type. The emitter region 12 and the contact region 15 may be provided between the base region 14 and the front surface of the semiconductor substrate 10 in the depth direction. Examples of dopants for the emitter region 12 include arsenic (As), phosphorus (P), and antimony (Sb).

[0072] The mesa portion of the transistor section 70 has an emitter region 12 exposed on the front surface of the semiconductor substrate 10. The emitter region 12 is provided in contact with the gate trench portion 40. The mesa portion in contact with the gate trench portion 40 has a contact region 15 exposed on the front surface of the semiconductor substrate 10.

[0073] The contact regions 15 and the emitter regions 12 in the mesa portion are each provided from one trench portion to the other trench portion in the X-axis direction. As an example, the contact regions 15 and the emitter regions 12 in the mesa portion are alternately arranged along the extension direction of the trench portion (the Y-axis direction).

[0074] In another example, the contact region 15 and the emitter region 12 of the mesa portion may be provided in a stripe shape along the extension direction of the trench portion (Y-axis direction). For example, the emitter region 12 is provided in a region in contact with the trench portion, and the contact region 15 is provided in a region sandwiched between the emitter regions 12.

[0075] The mesa portion of the diode portion 80 does not have an emitter region 12. A base region 14 may be provided on the upper surface of the mesa portion of the diode portion 80. The base region 14 may be disposed over the entire mesa portion of the diode portion 80. The base region 14 of the diode portion 80 operates as an anode.

[0076] A contact hole 54 is provided above each mesa portion. The contact holes 54 are arranged in regions sandwiched between the base regions 14 in the extension direction (Y-axis direction). In this example, the contact holes 54 are provided above the contact region 15, the base region 14, and the emitter region 12. The contact holes 54 may be arranged in the center in the arrangement direction (X-axis direction) of the mesa portions.

[0077] In the diode section 80, an N+ type cathode region 82 is provided in a region adjacent to the rear surface of the semiconductor substrate. A P+ type collector region 22 may be provided in a region of the rear surface of the semiconductor substrate where the cathode region 82 is not provided. In Figure 1B, the boundary between the cathode region 82 and the collector region 22 is indicated by a dotted line.

[0078] The boundary between the collector region 22 and the cathode region 82 is the boundary between the transistor section 70 and the diode section 80. That is, in this example, the transistor section 70 is a region obtained by projecting the collector region 22 provided on the back surface side of the semiconductor substrate 10 onto the upper surface of the semiconductor substrate 10. The diode section 80 is a region obtained by projecting the cathode region 82 provided on the back surface of the semiconductor substrate 10 onto the upper surface of the semiconductor substrate 10.

[0079] 1C shows an example of the aa' cross section in FIG. 1B. The aa' cross section is an XZ plane passing through the emitter region 12 in the transistor section 70. In the aa' cross section, the semiconductor device 100 of this example has a semiconductor substrate 10 including the emitter region 12, the base region 14, the accumulation region 16, the drift region 18, the buffer region 20, the collector region 22, and the cathode region 82, an interlayer insulating film 38, an emitter electrode 52, and a collector electrode 24. The collector electrode 24 is an example of a back-side metal layer provided in contact with the back surface 23 of the semiconductor substrate 10.

[0080] The drift region 18 is a region of a first conductivity type provided in the semiconductor substrate 10. In this example, the drift region 18 is, for example, an N-type. The drift region 18 may be a region remaining in the semiconductor substrate 10 without other doped regions being formed therein. That is, the doping concentration of the drift region 18 may be the same as the doping concentration of the semiconductor substrate 10.

[0081] The accumulation region 16 is a region of a first conductivity type provided below the base region 14 in the semiconductor substrate 10. The doping concentration of the accumulation region 16 is higher than the doping concentration of the drift region 18. In this example, the accumulation region 16 is, for example, an N+ type.

[0082] The accumulation region 16 may be provided in the transistor section 70, but not in the diode section 80. The accumulation region 16 may be provided in both the transistor section 70 and the diode section 80. By providing the accumulation region 16, the carrier injection enhancement effect (IE effect) can be enhanced, and the on-voltage of the transistor section 70 can be reduced.

[0083] A buffer region 20 of the first conductivity type may be provided below the drift region 18. In this example, the buffer region 20 is N-type. The doping concentration of the buffer region 20 is higher than the doping concentration of the drift region 18. The buffer region 20 may function as a field stop layer that prevents a depletion layer extending from the lower surface side of the base region 14 from reaching the collector region 22 and the cathode region 82.

[0084] In the transistor section 70, a collector region 22 is provided below the buffer region 20. The collector region 22 may be provided in contact with the cathode region 82 on the back surface 23.

[0085] In the diode section 80, a cathode region 82 is provided below the buffer region 20. The cathode region 82 may be provided at the same depth as the collector region 22 of the transistor section 70. The diode section 80 may function as a freewheeling diode (FWD) that conducts a freewheeling current in the reverse direction when the transistor section 70 is turned off.

[0086] The collector electrode 24 is formed on the rear surface 23 of the semiconductor substrate 10. The collector electrode 24 is formed of a conductive material such as a metal. The collector electrode 24 may be formed of the same conductive material as the emitter electrode 52, or may be formed of a different conductive material.

[0087] The gate trench portion 40 has a gate trench formed on the front surface 21, a gate insulating film 42, and a gate conductive portion 44. The gate insulating film 42 is formed to cover the inner wall of the gate trench. The gate insulating film 42 may be formed by oxidizing or nitriding the semiconductor on the inner wall of the gate trench. The gate conductive portion 44 is formed inside the gate trench, further inward than the gate insulating film 42. The gate insulating film 42 insulates the gate conductive portion 44 from the semiconductor substrate 10. The gate conductive portion 44 is made of a conductive material such as polysilicon. The gate trench portion 40 is covered on the front surface 21 with an interlayer insulating film 38.

[0088] The gate conductive portion 44 includes a region facing the adjacent base region 14 across the gate insulating film 42 in the depth direction of the semiconductor substrate 10. When a predetermined voltage is applied to the gate conductive portion 44, a channel is formed by an electron inversion layer in the surface layer of the interface of the base region 14 that contacts the gate trench.

[0089] The dummy trench portion 30 may have the same structure as the gate trench portion 40. The dummy trench portion 30 has a dummy trench, a dummy insulating film 32, and a dummy conductive portion 34 formed on the front surface 21 side. The dummy insulating film 32 is formed to cover the inner wall of the dummy trench. The dummy conductive portion 34 is formed inside the dummy trench and further inward than the dummy insulating film 32. The dummy insulating film 32 insulates the dummy conductive portion 34 from the semiconductor substrate 10. The dummy trench portion 30 is covered on the front surface 21 with an interlayer insulating film 38.

[0090] The interlayer insulating film 38 is provided on the front surface 21. An emitter electrode 52 is provided above the interlayer insulating film 38. One or more trench contact portions may be provided in the interlayer insulating film 38 to electrically connect the emitter electrode 52 to the semiconductor substrate 10. Similarly, the contact holes 49, 55, and 56 may also have trench contact portions provided so as to penetrate the interlayer insulating film 38.

[0091] 2A is a diagram showing an example of the top surface of the semiconductor device 100. The semiconductor device 100 of this example includes a gate wiring portion 48, a gate pad 50, a wiring resistance portion 62, a transistor region 120, an emitter electrode portion 152, a first resistance measurement pad 141, and a second resistance measurement pad 142. The semiconductor device 100 may include a built-in resistor portion 61. FIG. 2A shows an example in which a plurality of gate wiring portions 48, transistor regions 120, emitter electrode portions 152, wiring resistance portions 62, and second resistance measurement pads 142 are provided, and the built-in resistor portion 61 is included.

[0092] In this specification, one gate wiring portion 48 refers to a wiring portion between the gate pad 50 and the gate trench portion 40, which is electrically connected between the gate pad 50 and the gate conductive portion 44 of the gate trench portion 40. One or more gate wiring portions 48 may extend from one gate pad 50. The gate wiring portion 48 may have branches, and the branched portions may be reconnected. In this example, the multiple gate wiring portions 48 are provided corresponding to each of the multiple transistor regions 120, and include a gate metal layer 47 provided above the semiconductor substrate 10 and a gate runner 46 provided below the gate metal layer 47.

[0093] 2A , the gate metal layer 47 is indicated by a solid line, and the gate runner 46 is indicated by a dotted line. In a top view, the lateral width of the gate runner 46 may be wider than the lateral width of the gate metal layer 47. The gate runner 46 and the gate metal layer 47 may at least partially overlap each other in a top view.

[0094] The gate metal layer 47 is made of a conductive metal material. In one example, the gate metal layer 47 is made of tungsten (W). The gate metal layer 47 may be made of the same material as the emitter electrode 52 and the collector electrode 24, or may be made of a different material. By making the gate metal layer 47 of a metal material, it is possible to reduce delays when a gate voltage is applied.

[0095] The gate runner 46 is made of a conductive material. In one example, the gate runner 46 is made of polysilicon. The gate runner 46 may be made of a metal material. The gate runner 46 may be provided below the gate metal layer 47 and above the front surface 21 of the semiconductor substrate 10. An interlayer insulating film 38 may be provided between the gate runner 46 and the gate metal layer 47.

[0096] The gate wiring portion 48 may be composed of only either the gate metal layer 47 or the gate runner 46. In one example, the gate wiring portion 48 is composed of only the gate runner 46. The gate wiring portion 48 may be composed of polysilicon.

[0097] The built-in resistor 61 has one end electrically connected to the gate pad 50 and the other end electrically connected to the plurality of gate wiring portions 48. The built-in resistor 61 may be provided between the gate pad 50 and the transistor region 120. The built-in resistor 61 in this example is formed simultaneously with the formation of the gate runner 46. That is, the built-in resistor 61 may be made of polysilicon. This allows the built-in resistor 61 to be formed at the stage of forming the gate wiring portions 48, thereby reducing the number of processes. The built-in resistor 61 may be made of a resistive film other than polysilicon.

[0098] The provision of the built-in resistor 61 makes it possible to adjust the relaxation time when switching the gate voltage on and off, thereby attenuating gate oscillation and short-circuit oscillation between the semiconductor chips when multiple semiconductor chips are connected in parallel, thereby suppressing the oscillation.

[0099] The wiring resistance portions 62 are provided between the first resistance measurement pad 141 and the transistor region 120, respectively corresponding to the gate wiring portions 48. In this example, the wiring resistance portions 62 are part of the gate wiring portion 48, and are portions where the gate metal layer 47 is not provided. That is, the wiring resistance portions 62 may be formed with a single layer structure of polysilicon. This allows the wiring resistance portions 62 to be formed at the stage of forming the gate wiring portion 48, thereby reducing the number of processes. The wiring resistance portions 62 may be separate resistance portions different from the gate wiring portion 48. In one example, the wiring resistance portions 62 are formed with a resistance film other than polysilicon.

[0100] The provision of the wiring resistance portion 62 makes it possible to adjust the relaxation time when switching the gate voltage on and off. Since the wiring resistance portion 62 is provided corresponding to the gate wiring portion 48, when a plurality of transistor regions 120 and gate wiring portions 48 are provided in parallel within a single semiconductor chip, the wiring resistance portion 62 can attenuate gate oscillation and short-circuit oscillation between the transistor regions 120 within the single semiconductor chip, thereby suppressing the oscillation.

[0101] The first resistance measurement pad 141 is provided above the semiconductor substrate 10 and is electrically connected to the gate pad 50 via the built-in resistor 61. A protective film (not shown), such as polyimide, does not need to be provided above the first resistance measurement pad 141. The first resistance measurement pad 141 is made of a conductive metal material. The material of the first resistance measurement pad 141 may be the same as or different from the material of the gate pad 50.

[0102] The first resistance measurement pad 141 is provided so as to partially overlap the built-in resistor 61 in top view, and the first resistance measurement pad 141 and the built-in resistor 61 are electrically connected via a contact hole 49. The detailed connection relationship between the first resistance measurement pad 141, the built-in resistor 61, and the gate pad 50 will be described later. The first resistance measurement pad 141 can measure the current and voltage between the first resistance measurement pad 141 and the gate pad 50, and measure the resistance of the built-in resistor 61.

[0103] The second resistance measurement pad 142 is provided above the semiconductor substrate 10 and is electrically connected to both ends of the wiring resistor portion 62. A protective film (not shown), such as a polyimide film, does not need to be provided above the second resistance measurement pad 142. The second resistance measurement pad 142 is made of a conductive metal material. The material of the second resistance measurement pad 142 may be the same as or different from the material of the first resistance measurement pad 141.

[0104] The second resistance measurement pads 142 are electrically connected to the wiring resistance portion 62 via contact holes 49. The detailed connection relationship between the second resistance measurement pads 142 and the wiring resistance portion 62 will be described later. The second resistance measurement pads 142 can measure the current and voltage between the two second resistance measurement pads 142 and measure the resistance of the wiring resistance portion 62.

[0105] The first resistance measurement pad 141 and the second resistance measurement pad 142 may be arranged so that the resistances of the built-in resistor portion 61 and the wiring resistor portion 62 can be measured together. The second resistance measurement pad 142 may measure the current and voltage between the first resistance measurement pad 141 and the second resistance measurement pad 142 to measure the resistance of the wiring resistor portion 62. As an example, when the wiring resistor portion 62 is connected to the first resistance measurement pad 141, the resistance of the built-in resistor portion 61 can be measured by measuring the current and voltage between the gate pad 50 and the first resistance measurement pad 141, and the resistance of the wiring resistor portion 62 can be measured by measuring the current and voltage between the first resistance measurement pad 141 and the second resistance measurement pad 142.

[0106] The transistor region 120 is a region through which a main current flows in the depth direction between the front surface 21 and the back surface 23 of the semiconductor substrate 10 when the semiconductor device 100 is in operation. The transistor region 120 includes a transistor section 70 and a diode section 80. In this specification, one transistor region 120 may be a region surrounded by one gate wiring section 48.

[0107] The emitter electrode portion 152 is provided above the semiconductor substrate 10 and applies a potential different from the gate potential to the transistor region 120. In this example, the emitter electrode portion 152 is electrically insulated from the gate wiring portion 48. In this specification, one emitter electrode portion 152 may refer to an emitter electrode made of one continuous metal plate.

[0108] 2A, one gate pad 50 and an internal resistor 61 electrically connected to the gate pad 50 are provided for each of the plurality of transistor regions 120. The semiconductor device 100 may be provided with one transistor region 120, one gate pad 50, and one internal resistor 61 electrically connected to the gate pad 50. The semiconductor device 100 may not be provided with the internal resistor 61. In this example, one gate pad 50 and one internal resistor 61 electrically connected to the gate pad 50 are provided for each of the three transistor regions 120-1, 120-2, and 120-3. By providing the internal resistor 61, gate oscillation and short-circuit oscillation between semiconductor chips can be suppressed.

[0109] 2A shows a semiconductor device 100 including a plurality of gate wiring portions 48 each provided corresponding to one of a plurality of transistor regions 120. The number of gate wiring portions 48 provided in the semiconductor device 100 may be the same as or different from the number of transistor regions 120. In this example, a first gate wiring 48-1, a second gate wiring 48-2, and a third gate wiring 48-3 are provided for a first transistor region 120-1, a second transistor region 120-2, and a third transistor region 120-3, respectively.

[0110] 2A shows a semiconductor device 100 including a plurality of wiring resistance portions 62 provided corresponding to the plurality of gate wiring portions 48. The number of gate wiring portions 48 and the number of wiring resistance portions 62 provided in the gate wiring portions 48 may be the same or different. One wiring resistance portion 62 may be provided for each gate wiring portion 48, or two or more wiring resistance portions 62 may be provided.

[0111] In this example, a first wiring resistor 62-1, a second wiring resistor 62-2, and a third wiring resistor 62-3 are shown corresponding to the first gate wiring 48-1, the second gate wiring 48-2, and the third gate wiring 48-3, respectively. By providing a wiring resistor section 62 for each gate wiring section 48, oscillation within the same chip, for example, oscillation between the first transistor region 120-1 and the second transistor region 120-2, can be suppressed.

[0112] Each of the multiple wiring resistance sections 62 is provided so as to be connected to each of the multiple transistor regions 120. The number of wiring resistance sections 62 and the number of transistor regions 120 may be the same or different. One wiring resistance section 62 may be provided for each transistor region 120, or two or more wiring resistance sections 62 may be provided for each transistor region 120.

[0113] In this example, the first wiring resistor 62-1, the second wiring resistor 62-2, and the third wiring resistor 62-3 are provided so as to be connected to the first transistor region 120-1, the second transistor region 120-2, and the third transistor region 120-3, respectively. By providing the wiring resistor portions 62 between the plurality of transistor regions 120, it is possible to suppress oscillation within the same chip.

[0114] Each of the multiple wiring resistance portions 62 is disposed closer to the gate pad 50 than each of the multiple transistor regions 120. For each gate wiring portion 48, the length of the gate wiring portion 48 from the first resistance measurement pad 141 to the wiring resistance portion 62 may be shorter than the length of the gate wiring portion 48 from the wiring resistance portion 62 to the transistor region 120. In this manner, the first resistance measurement pad 141 and each of the multiple second resistance measurement pads 142 are disposed near the gate pad 50, thereby improving the detection accuracy of each resistance value.

[0115] The resistance value of each of the multiple wiring resistance sections 62 may be greater than the resistance value of the built-in resistance section 61. The combined resistance value of the multiple wiring resistance sections 62 is greater than 0% and less than or equal to 100% of the combined resistance of the built-in resistance section 61 and the multiple wiring resistance sections 62. The combined resistance of the multiple wiring resistance sections 62 may be greater than 10% and less than or equal to 80% of the combined resistance of the built-in resistance section 61 and the multiple wiring resistance sections 62. By making the resistance value of each of the multiple wiring resistance sections 62 greater than the resistance value of the built-in resistance section 61, variations in the resistance values ​​of the wiring resistance sections 62 can be suppressed, and the operating characteristics of the semiconductor device 100 can be made uniform.

[0116] The resistance value of the combined resistance of the built-in resistor portion 61 and the plurality of wiring resistor portions 62 may be determined based on the rated output of the semiconductor device 100. In one example, the resistance value of the combined resistance of the built-in resistor portion 61 and the plurality of wiring resistor portions 62 is determined based on the rated output of the semiconductor device 100, and the resistance values ​​of the plurality of wiring resistor portions 62 are determined based on the resistance value of the combined resistance. This makes it possible to suppress both oscillation between chips when a plurality of semiconductor chips are connected in parallel and oscillation within the same chip, while maintaining the required rated output of the semiconductor device 100.

[0117] In top view, the gate pad 50 is provided closer to the outer periphery of the semiconductor substrate 10 than the plurality of transistor regions 120. By providing the gate pad 50 on the outer periphery of the semiconductor substrate 10, the gate wire can be wired without interfering with the main wiring.

[0118] The multiple gate wiring portions 48 are spaced apart from one another when viewed from above. That is, in this example, the first gate wiring 48-1, the second gate wiring 48-2, and the third gate wiring 48-3 are connected only at the first resistance measurement pad 141, and are not connected anywhere else. This allows the wiring resistance portion 62 to be disposed between the multiple transistor regions 120, making it possible to suppress oscillation within the same chip.

[0119] The emitter electrode 52 may have a plurality of emitter electrode portions 152 that are spaced apart from one another. The emitter electrode 52 in this example has a first emitter electrode portion 152-1, a second emitter electrode portion 152-2, and a third emitter electrode portion 152-3.

[0120] The plurality of emitter electrode sections 152 may be provided corresponding to the plurality of wiring resistance sections 62, respectively. The number of wiring resistance sections 62 and the number of emitter electrode sections 152 may be the same or different. One wiring resistance section 62 may be provided for each emitter electrode section 152, or two or more wiring resistance sections 62 may be provided for each emitter electrode section 152. In this example, a first emitter electrode section 152-1, a second emitter electrode section 152-2, and a third emitter electrode section 152-3 are provided corresponding to the first wiring resistance 62-1, the second wiring resistance 62-2, and the third wiring resistance 62-3, respectively.

[0121] The multiple transistor regions 120 may include two or more transistor regions having approximately the same area. In this example, the transistor region includes a first transistor region 120-1 and a second transistor region 120-2 having approximately the same area. In this specification, the transistor regions 120 having approximately the same area may mean that the difference in area between the two transistor regions 120 is within 10%. By making the areas of the multiple transistor regions 120 approximately the same, the difference in active area between the transistor regions 120 is reduced, current concentration when the semiconductor device 100 is turned off is alleviated, and latch-up resistance is improved.

[0122] The lengths of the multiple gate wiring portions 48 may be different for each gate wiring portion 48, or may be the same for each gate wiring portion 48. The lengths of the gate wiring portions 48 may be adjusted as appropriate depending on the arrangement of the gate pad 50 and the transistor region 120 in the semiconductor device 100. The multiple gate wiring portions in this example include a first gate wiring 48-1 connected to the first transistor region 120-1, and a second gate wiring 48-2 connected to the second transistor region 120-2 and longer than the first gate wiring 48-1.

[0123] The lengths of the multiple gate wiring portions 48 may be adjusted as appropriate within a range that does not cause gate signal delay between the multiple transistor regions 120 to which each gate wiring portion 48 is connected. The lengths of the multiple gate wiring portions 48 may be adjusted so that the gate resistance value is equal to or less than a predetermined value in any of the multiple transistor regions 120. The resistance value between both ends of the gate trench portion 40 connected to the gate wiring portion 48 in each transistor region 120 may be equal to or less than 6 kΩ per gate trench portion 40 in any of the regions.

[0124] The resistance values ​​of the multiple wiring resistance portions 62 may be different for each wiring resistance portion 62 or may be the same for each wiring resistance portion 62. The resistance value of each of the multiple wiring resistance portions 62 may be 3 Ω or more and 30 Ω or less. The resistance value of the wiring resistance portion 62 may be changed in accordance with the capacitance of the transistor region 120 to which each wiring resistance portion 62 is connected, may be changed in accordance with the magnitude of mutual inductance that the gate wiring portion 48 on which each wiring resistance portion 62 is arranged receives from the surrounding gate wiring portions 48, or may be changed in accordance with the resonance strength of an LC resonance circuit formed within the same chip.

[0125] The resistance value of each of the multiple wiring resistance portions 62 may be changed depending on the area of ​​the transistor region 120 to which each wiring resistance portion 62 is connected. In this example, the resistance values ​​of the wiring resistance portions 62-1 and 62-2 connected to the first transistor region 120-1 and the second transistor region 120-2, which have approximately the same area, may be approximately equal. In this specification, "the resistance values ​​of the wiring resistance portions 62 are approximately equal" may mean that the difference in resistance value between the two wiring resistance portions 62 is within 10%.

[0126] The resistance values ​​of the multiple wiring resistance portions 62 may be changed according to the length of the gate wiring portion 48 in which each wiring resistance portion 62 is provided. In this example, the resistance value of the first wiring resistance 62-1 connected to the first gate wiring portion 48-1 is greater than the resistance value of the second wiring resistance 62-2 connected to the second gate wiring portion 48-2. Generally, the longer the gate wiring portion 48 is, the greater the parasitic capacitance in that gate wiring portion 48 is. Therefore, oscillation can be suppressed even if the resistance value of the wiring resistance portion 62 in that gate wiring portion 48 is made smaller than the resistance values ​​of the wiring resistance portions 62 in the other gate wiring portions 48.

[0127] The resistance values ​​of the multiple wiring resistors 62 may be changed according to the error in the CR time constant, which is the product of the capacitance C of each of the multiple transistor regions 120 and the resistance R of each of the wiring resistors 62 provided corresponding to that transistor region 120. In this example, the error in the value of the CR time constant, which is the product of the capacitance C of the transistor region 120 and the resistance R of the wiring resistor 62 provided corresponding to that transistor region 120, is 10% or less in each of the multiple transistor regions 120. The error may be 20% or less. By keeping the error in the CR time constant at 20% or less, current non-uniformity during switching operation of the semiconductor device 100 can be eliminated.

[0128] 2B shows an example of an enlarged top view of the semiconductor device 100. Fig. 2B is an enlarged view of an area B surrounded by a two-dot chain line in Fig. 2A. The first gate wiring 48-1 may include a first gate metal layer 47-1 and a first gate runner 46-1, the second gate wiring 48-2 may include a second gate metal layer 47-2 and a second gate runner 46-2, and the third gate wiring 48-3 may include a third gate metal layer 47-3 and a third gate runner 46-3.

[0129] The plurality of gate wiring portions 48 are provided between two adjacent transistor regions 120 among the plurality of transistor regions 120, and may include a gate wiring portion 48 connected to one of the two adjacent transistor regions 120 and a gate wiring portion 48 connected to the other of the two adjacent transistor regions 120. In this example, a first gate wiring 48-1 connected to the first transistor region 120-1 and a second gate wiring 48-2 connected to the second transistor region 120-2 are provided between the first transistor region 120-1 and the second transistor region 120-2, which are two adjacent transistor regions 120.

[0130] Three or more gate wiring portions 48 may be provided between two adjacent transistor regions 120. In this example, the third gate wiring 48-3 is not provided between the first transistor region 120-1 and the second transistor region 120-2, but the third gate wiring 48-3 may be provided between the first transistor region 120-1 and the second transistor region 120-2.

[0131] Gate trench portions 40 are provided in the plurality of transistor regions 120. The gate trench portions 40 are electrically connected to gate wiring portions 48 provided corresponding to the transistor regions 120. The gate trench portions 40 are provided to extend in a predetermined extension direction (in this example, the Y-axis direction).

[0132] The gate trench portion 40 may be connected to only one gate wiring portion 48. As an example, the gate trench portion 40 included in the first transistor region 120-1 is connected to only the first gate wiring 48-1 of the multiple gate wiring portions 48. The gate trench portion 40 included in the first transistor region 120-1 and the gate trench portion 40 included in the second transistor region 120-2 may be separated from each other by the first gate wiring 48-1 and the second gate wiring 48-2.

[0133] At least some of the gate trenches 40 included in each transistor region 120 may be provided across adjacent transistor regions 120. At least some of the gate trenches 40 may be connected to multiple gate wiring portions 48. That is, in the example shown in FIG. 2B , at least some of the gate trenches 40 may extend across the trench extension direction (the Y-axis direction in this example) below the first gate wiring 48-1 and / or the second gate wiring 48-2, and may be provided across both the first transistor region 120-1 and the second transistor region 120-2.

[0134] 2C is a diagram showing an example of the bb' cross section of the semiconductor device 100. The bb' cross section is a YZ cross section passing through the gate pad 50, the first resistance measurement pad 141, the second resistance measurement pad 142-1, the built-in resistor 61, and the first wiring resistor 62-1 in the semiconductor device 100.

[0135] The built-in resistor 61 is provided above the semiconductor substrate 10, between the gate pad 50 and the first resistance measurement pad 141. The built-in resistor 61 is provided inside the interlayer insulating film 38. The built-in resistor 61 may be made of polysilicon. The built-in resistor 61 may be part of the gate runner 46.

[0136] The built-in resistor 61 is electrically connected to the gate pad 50 and the first resistance measurement pad 141 via two contact holes 49. By providing a resistor between the gate pad 50 and the plurality of gate wiring portions 48, oscillation between the chips can be suppressed when multiple semiconductor chips are connected in parallel.

[0137] The first wiring resistor 62-1 is provided above the semiconductor substrate 10, between the first resistance measurement pad 141 and the second resistance measurement pad 142-1. The wiring resistor portion 62 may be provided between the two second resistance measurement pads 142. The wiring resistor portion 62 may be provided at the same depth as the built-in resistor portion 61 in the depth direction of the semiconductor substrate 10, or may be provided at a different depth. The wiring resistor portion 62 is provided inside the interlayer insulating film 38. The wiring resistor portion 62 may be made of polysilicon. The wiring resistor portion 62 may be part of the gate runner 46.

[0138] The first wiring resistor 62-1 is electrically connected to the first resistance measurement pad 141 and the second resistance measurement pad 142-1 via two contact holes 49. The wiring resistor portion 62 may be electrically connected to the two second resistance measurement pads 142 via two contact holes 49. The wiring resistor portion 62 may be provided as part of the gate wiring portion 48. By providing the wiring resistor portion 62 in the gate wiring portion 48, oscillation within the semiconductor chip can be suppressed.

[0139] The first emitter electrode portion 152-1 is provided spaced apart from the second resistance measurement pad 142-1. The emitter electrode 52 may be provided spaced apart from each of the plurality of gate wiring portions 48. The first emitter electrode portion 152-1 may be electrically connected to the connection portion 25 inside the interlayer insulating film 38.

[0140] 2D is a diagram showing an example of a cc' cross section of the semiconductor device 100. The cc' cross section is a YZ cross section of the semiconductor device 100 that passes through the first gate wiring 48-1 and the third wiring resistor 62-3.

[0141] The first gate wiring 48-1 includes a gate metal layer 47 provided above the semiconductor substrate 10 and a gate runner 46 provided below the gate metal layer 47. The gate runner 46 may be provided inside the interlayer insulating film 38. The first gate wiring 48-1 may be composed of only one of the gate metal layer 47 or the gate runner 46.

[0142] The semiconductor device 100 of this example may have a contact portion 51 provided between the gate metal layer 47 and the gate runner 46, and electrically connecting the gate metal layer 47 and the gate runner 46. This improves the degree of freedom in wiring the gate wiring portion 48.

[0143] The cross-sectional area perpendicular to the extension direction of the wiring resistor portion 62 may be smaller than the cross-sectional area perpendicular to the extension direction of the gate wiring portion 48. In this example, in the YZ cross section shown in FIG. 2D, the cross-sectional area S ６２ is the cross-sectional area S of the first gate wiring 48-1 ４８ This makes it possible to make the resistance value of the wiring resistance portion 62 larger than the resistance value of the gate wiring portion 48, thereby suppressing oscillation within a single semiconductor chip.

[0144] Fig. 3 is an enlarged view of the resistance measurement pads of this example. Fig. 3 shows an example of the top surface of the second resistance measurement pad 142, but the top surface of the first resistance measurement pad 141 may have the same configuration. As shown in Fig. 3, the two second resistance measurement pads 142 are connected to the wiring resistance portion 62 provided below the second resistance measurement pads 142 via contact holes 49.

[0145] The wiring resistance portion 62 may be part of the gate runner 46. In this example, the wiring resistance portion 62 is a region having a width W and a length L that is provided between two contact holes 49. By changing the width W and length L of the wiring resistance portion 62, the resistance value of the wiring resistance portion 62 can be adjusted.

[0146] The width W of the wiring resistance portion 62 may be smaller than the width of the gate runner 46 in the gate wiring portion 48 in the direction perpendicular to the extension direction. The width W of the wiring resistance portion 62 may be the same as the width of the gate metal layer 47 in the gate wiring portion 48 in the direction perpendicular to the extension direction, or may be smaller than the width of the gate metal layer 47. The width W of the wiring resistance portion 62 may be smaller than the width of the second resistance measurement pad 142 in the direction perpendicular to the extension direction of the gate wiring portion 48. The width W of the wiring resistance portion 62 may be 30 μm or more and 1400 μm or less.

[0147] The length L of the wiring resistance portion 62 may be smaller than the width W of the wiring resistance portion 62. The length L of the wiring resistance portion 62 may be smaller than the width of the second resistance measurement pad 142 in the extension direction of the gate wiring portion 48. The length L of the wiring resistance portion 62 may be 20 μm or more and 800 μm or less.

[0148] An ammeter and a voltmeter (not shown) are provided between the two second resistance measurement pads 142. This makes it possible to calculate the resistance value of the wiring resistor portion 62 between the contact holes 49.

[0149] 4A is a diagram showing a modified example of the top surface of the semiconductor device 100. The modified example of FIG. 4A will be described by focusing on the differences from FIG. 2A. For simplicity, the gate wiring portion 48 is shown with a solid line, and the wiring resistor portion 62 provided in the gate wiring portion 48 is shown with a dotted line. However, the positions of these wirings in the figure are merely shown as rough outlines to avoid confusion with other wirings. The second resistance measurement pad 142 is also omitted from the illustration.

[0150] 4A, two or more of the plurality of wiring resistance portions 62 are connected to one of the plurality of transistor regions 120. As an example, a first wiring resistance 62-1 and a second wiring resistance 62-2 are connected to a first transistor region 120-1.

[0151] In this example, two first wiring resistors 62-1a and 62-1b are connected to the first transistor region 120-1, two second wiring resistors 62-2a and 62-2b are connected to the second transistor region 120-2, and two third wiring resistors 62-3a and 62-3b are connected to the third transistor region 120-3. This increases the resistance value of the gate wiring portion 48 provided for each transistor region 120, making it possible to suppress oscillation within a single semiconductor chip.

[0152] 4A , one emitter electrode portion 152 out of the plurality of emitter electrode portions 152 is provided corresponding to two or more wiring resistance portions 62 out of the plurality of wiring resistance portions 62. In this example, a first emitter electrode portion 152-1 is provided corresponding to the first wiring resistances 62-1a and 62-1b, a second emitter electrode portion 152-2 is provided corresponding to the second wiring resistances 62-2a and 62-2b, and a third emitter electrode portion 152-3 is provided corresponding to the third wiring resistances 62-3a and 62-3b.

[0153] The plurality of transistor regions 120 may have two or more transistor regions with different areas. In this example, the transistor regions include a first transistor region 120-1, a second transistor region 120-2 that is larger in area than the first transistor region 120-1, and a third transistor region 120-3 that is larger in area than the second transistor region 120-2.

[0154] The resistance value of each of the wiring resistance portions 62 of the plurality of wiring resistance portions may be changed depending on the area of ​​the transistor region 120 to which each wiring resistance portion 62 is connected. In this example, the resistance value of the first wiring resistances 62-1a and 62-1b connected to the first transistor region 120-1 is greater than the resistance value of the second wiring resistances 62-2a and 62-2b connected to the second transistor region 120-2, and the resistance value of the second wiring resistances 62-2a and 62-2b connected to the second transistor region 120-2 is greater than the resistance value of the third wiring resistances 62-3a and 62-3b connected to the third transistor region 120-3.

[0155] Generally, the larger the area of ​​a transistor region 120, the larger the parasitic capacitance in that transistor region 120, and therefore oscillation can be suppressed even if the resistance value of the wiring resistance portion 62 in that transistor region 120 is made smaller than the resistance values ​​of the wiring resistance portions 62 in other transistor regions 120. When the area of ​​a transistor region 120 is S and the resistance value of the wiring resistance portion 62 connected to that transistor region 120 is R, the resistance value R of the wiring resistance portion 62 may be adjusted so that the value of S*R becomes a predetermined value.

[0156] Fig. 4B is a diagram showing a modified example of the upper surface of the semiconductor device 100. The modified example of Fig. 4B will be described with respect to differences from Figs. 2A and 4A.

[0157] The gate pad 50 may be provided between the plurality of transistor regions 120 in top view. In this example, the gate pad 50 is provided between the plurality of transistor regions 120 and near the center of the semiconductor device 100. This improves the symmetry of the configuration of the semiconductor device 100, and enables uniform transmission of gate signals in the semiconductor device 100.

[0158] The built-in resistor section 61 may have a first built-in resistor 61-1 and a second built-in resistor 61-2 different from the first built-in resistor 61-1. The built-in resistor section 61 may have three or more built-in resistors. In this example, the built-in resistor section 61 has a first built-in resistor 61-1 connected to the gate pad 50 and a second built-in resistor 62-2 connected to the gate pad 50 and different from the first built-in resistor 61-1. The resistance values ​​of the first built-in resistor 61-1 and the second built-in resistor 62-2 may be the same or different.

[0159] The multiple wiring resistance sections 62 may include one or more first wiring resistances 62-1 connected to the first built-in resistance 61-1 and one or more second wiring resistances 62-2 connected to the second built-in resistance 61-2 and different from the first wiring resistance 62-1. In this example, the multiple wiring resistance sections include a first wiring resistance 62-1 and a second wiring resistance 62-2 connected to the first built-in resistance 61-1, and a third wiring resistance 62-3 and a fourth wiring resistance 62-4 connected to the second built-in resistance 61-2. Three or more wiring resistances may be connected to one built-in resistor. By providing multiple built-in resistance sections 61 and multiple wiring resistance sections 62, the resistance value for suppressing oscillation between semiconductor chips and the resistance value for suppressing oscillation within the semiconductor chip can be adjusted separately.

[0160] The emitter electrode portion 152 may be provided corresponding to a plurality of different transistor regions 120. The emitter electrode portion 152 may be provided corresponding to a plurality of different transistor regions 120 connected to one internal resistor. In this example, the first emitter electrode portion 152-1 is provided corresponding to the first transistor region 120-1 and the second transistor region 120-2 connected to the first internal resistor 61-1, and the second emitter electrode portion 152-2 is provided corresponding to the third transistor region 120-3 and the fourth transistor region 120-4 connected to the second internal resistor 61-2.

[0161] In this example, the emitter electrode portion 152 is provided so as not to overlap the gate wiring portion 48 in a top view. The emitter electrode portion 152 may be provided so as to overlap the gate wiring portion 48 in a top view. In this case, the gate metal layer 47 is not provided in the overlapping portion. In other words, the emitter electrode portion 152 and the gate wiring portion 48 are not electrically connected. The gate runner 46 may be provided in the portion where the gate metal layer 47 is not provided.

[0162] A plurality of first resistance measurement pads 141 may be provided. The first resistance measurement pads 141 may be provided corresponding to the plurality of built-in resistors included in the built-in resistor section 61. One first resistance measurement pad 141 may measure the resistance values ​​of a plurality of built-in resistors. In this example, a first resistance measurement pad 141-1 is provided corresponding to the first built-in resistor 61-1, and a first resistance measurement pad 141-2 is provided corresponding to the second built-in resistor 61-2.

[0163] Fig. 5A is a diagram showing a modified example of the top surface of semiconductor device 100. The modified example of Fig. 5A will be described with respect to differences from Figs. 2A, 4A, and 4B.

[0164] The emitter electrode 52 may be provided in common to the plurality of wiring resistance portions 62 above the semiconductor substrate 10. The emitter electrode 52 may be provided in common to the plurality of gate wiring portions 48 above the semiconductor substrate 10, or may be provided in common to the plurality of transistor regions 120. In this example, one emitter electrode 52 is provided in common to the plurality of wiring resistance portions 62-1, 62-2, 62-3, 62-4, 62-5, and 62-6.

[0165] 5A differs from the embodiment of FIG. 2A in that the emitter electrode portions 152 indicated by the two-dot chain lines are connected by a connection region 153. In this example, the first emitter electrode portion 152-1 provided corresponding to the first transistor region 120-1 and the fourth transistor region 120-4, the second emitter electrode portion 152-2 provided corresponding to the second transistor region 120-2 and the fifth transistor region 120-5, and the third emitter electrode portion 152-3 provided corresponding to the third transistor region 120-3 and the sixth transistor region 120-6 are each connected by the connection region 153. Connecting the emitter electrode portions 152 by the connection region 153 to form a single emitter electrode 52 can improve the operational stability of the semiconductor device 100.

[0166] 5B is a diagram showing an example of a dd' cross section of the semiconductor device 100 in FIG. 5A. The dd' cross section is an XZ cross section passing through the gate wiring portion 48 and the emitter electrode 52.

[0167] The gate wiring portion 48 is provided spaced apart from the emitter electrode 52. The gate runner 46 of the gate wiring portion 48 is connected to the gate metal layer 47 via the contact portion 51. The contact portion 51 is not provided below the emitter electrode 52. In other words, the gate runner 46 is not electrically connected to the emitter electrode 52. This allows the gate wiring portion 48 and the emitter electrode 52 to be electrically insulated from each other.

[0168] The gate runner 46 does not necessarily have to be provided below the emitter electrode 52. In this example, the gate runner 46 is provided below the emitter electrode 52. This allows the gate wiring portion 48 to be connected by the gate runner 46 even when the gate metal layer 47 is separated by the emitter electrode 52 above the semiconductor substrate 10.

[0169] The emitter electrode 52 in the connection region 153 has a predetermined width D in a direction perpendicular to the connection direction of the emitter electrode portion 152. The width D may be greater than the width between the emitter electrode 52 and the gate metal layer 47. The width D may be 0 μm or more and may be less than or equal to the width of the emitter electrode portion 152. The width D may be 1000 μm or less.

[0170] Although the present invention has been described above using embodiments, the technical scope of the present invention is not limited to the scope described in the above embodiments. It will be apparent to those skilled in the art that various modifications and improvements can be made to the above embodiments. It is clear from the claims that such modifications and improvements can also be included within the technical scope of the present invention.

[0171] It should be noted that the order of execution of each process, such as operations, procedures, steps, and stages, in the devices, systems, programs, and methods shown in the claims, specifications, and drawings is not specifically stated as "before," "prior to," etc., and that the processes can be performed in any order unless the output of a previous process is used in a subsequent process. Even if the operational flow in the claims, specifications, and drawings is described using "first," "next," etc. for convenience, this does not mean that the processes must be performed in this order.

[0172] DESCRIPTION OF SYMBOLS 10: Semiconductor substrate, 12: Emitter region, 14: Base region, 15: Contact region, 16: Accumulation region, 18: Drift region, 20: Buffer region, 21: Front surface, 22: Collector region, 23: Back surface, 24: Collector electrode, 25: Connection portion, 30: Dummy trench portion, 31: Extension portion, 32: Dummy insulating film, 33: Connection portion, 34: Dummy conductive portion, 38: Interlayer insulating film, 40: Gate trench portion, 41: Extension portion, 42: Gate insulating film, 43: Connection portion, 44: Gate conductive portion, 46: Gate runner, 47: Gate metal layer , 48...gate wiring portion, 49...contact hole, 50...gate pad, 51...contact portion, 52...emitter electrode, 54...contact hole, 55...contact hole, 56...contact hole, 61...built-in resistor portion, 62...wiring resistor portion, 70...transistor portion, 80...diode portion, 82...cathode region, 100...semiconductor device, 102...edge, 120...transistor region, 130...well region, 140...edge termination structure portion, 141...first resistance measurement pad, 142...second resistance measurement pad, 152...emitter electrode portion, 153...connection region

Claims

1. A semiconductor device comprising: a plurality of transistor regions; gate trench portions provided in the plurality of transistor regions; a gate pad provided above a semiconductor substrate; a plurality of gate wiring portions electrically connected between the gate pad and the gate trench portion, each of which corresponds to one of the plurality of transistor regions; and a plurality of wiring resistance portions provided corresponding to each of the plurality of gate wiring portions.

2. The semiconductor device according to claim 1, further comprising a built-in resistor portion having one end electrically connected to said gate pad and the other end electrically connected to said plurality of gate wiring portions.

3. The semiconductor device according to claim 1, wherein said plurality of gate wiring portions include a gate metal layer provided above said semiconductor substrate, and a gate runner provided below said gate metal layer.

4. The semiconductor device according to claim 3, further comprising a contact portion provided between said gate metal layer and said gate runner, said contact portion connecting said gate metal layer and said gate runner.

5. The semiconductor device according to claim 1, wherein the gate pad is provided closer to the outer periphery of the semiconductor substrate than the plurality of transistor regions when viewed from above.

6. The semiconductor device according to claim 1, wherein each of said plurality of wiring resistance portions is connected to each of said plurality of transistor regions.

7. The semiconductor device according to claim 1, wherein two or more of said plurality of wiring resistance sections are connected to one of said plurality of transistor regions.

8. The semiconductor device according to claim 2, wherein the gate pad is provided between the plurality of transistor regions when viewed from above.

9. The semiconductor device described in claim 8, wherein the built-in resistance section has a first built-in resistor and a second built-in resistor different from the first built-in resistor, and the multiple wiring resistance sections include one or more first wiring resistors connected to the first built-in resistor and one or more second wiring resistors connected to the second built-in resistor and different from the one or more first wiring resistors.

10. The semiconductor device according to claim 1, wherein the plurality of gate wiring portions are spaced apart from each other when viewed from above.

11. The semiconductor device according to claim 1, wherein the plurality of wiring resistance sections are provided in any of the plurality of gate wiring sections, and a cross-sectional area perpendicular to the extension direction of the wiring resistance section is smaller than a cross-sectional area perpendicular to the extension direction of the gate wiring section.

12. The semiconductor device according to claim 1, wherein each of said plurality of wiring resistance portions is disposed closer to said gate pad than each of said plurality of transistor regions.

13. The semiconductor device according to claim 1, wherein said plurality of gate wiring portions are made of polysilicon.

14. The semiconductor device according to claim 2, wherein the built-in resistor portion is made of polysilicon.

15. The semiconductor device according to claim 1, wherein each of said plurality of wiring resistance portions is formed of a single layer structure of polysilicon.

16. The semiconductor device according to claim 2, further comprising a first resistance measuring pad for measuring the resistance of said built-in resistor portion.

17. The semiconductor device according to claim 1, further comprising a second resistance measuring pad for measuring the resistance of said wiring resistance portion.

18. The semiconductor device according to claim 1, further comprising an emitter electrode provided above the semiconductor substrate, the emitter electrode having a plurality of emitter electrode portions spaced apart from one another, the plurality of emitter electrode portions being provided corresponding to the plurality of wiring resistance portions, respectively.

19. The semiconductor device according to claim 1, further comprising an emitter electrode provided above the semiconductor substrate, the emitter electrode having a plurality of emitter electrode portions spaced apart from one another, and one of the plurality of emitter electrode portions being provided corresponding to two or more wiring resistance portions of the plurality of wiring resistance portions.

20. The semiconductor device according to claim 1, further comprising a single emitter electrode provided above said semiconductor substrate and shared by said plurality of wiring resistance portions.

21. The semiconductor device according to claim 2, wherein a combined resistance value of said plurality of wiring resistance sections is 10% to 80% of a combined resistance of said built-in resistance section and said plurality of wiring resistance sections.

22. A semiconductor device according to any one of claims 1 to 21, wherein the plurality of gate wiring sections include a first gate wiring and a second gate wiring longer than the first gate wiring, and a resistance value of the wiring resistance section connected to the first gate wiring is greater than a resistance value of the wiring resistance section connected to the second gate wiring.

23. A semiconductor device according to any one of claims 1 to 21, wherein the plurality of transistor regions include a first transistor region and a second transistor region having approximately the same area as the first transistor region, and a resistance value of a wiring resistor provided in a gate wiring portion connected to a gate conductive portion of the first transistor region is approximately equal to a resistance value of a wiring resistor provided in a gate wiring portion connected to a gate conductive portion of the second transistor region.

24. A semiconductor device according to any one of claims 1 to 21, wherein the plurality of transistor regions include a first transistor region and a second transistor region having an area larger than that of the first transistor region, and a resistance value of a wiring resistor provided in a gate wiring portion connected to a gate conductive portion of the first transistor region is greater than a resistance value of a wiring resistor provided in a gate wiring portion connected to a gate conductive portion of the second transistor region.

25. The semiconductor device according to claim 1, wherein the resistance value of each of the plurality of wiring resistance sections is 3 Ω or more and 30 Ω or less.

26. The semiconductor device according to claim 1, wherein the resistance value of the gate trench portion is 6 kΩ or less in any of the plurality of transistor regions.

27. A semiconductor device according to any one of claims 1 to 21, wherein an error in the value of a CR time constant, which is the product of the capacitance of the transistor region and the resistance value of a wiring resistor portion provided corresponding to the transistor region, is within 20% in each of the plurality of transistor regions.

28. A semiconductor device according to any one of claims 1 to 21, wherein the plurality of gate wiring portions are provided between two adjacent transistor regions among the plurality of transistor regions, and include a gate wiring portion connected to one of the two adjacent transistor regions, and a gate wiring portion connected to the other of the two adjacent transistor regions.

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