Three-dimensional flash memory comprising asymmetrically-structured dual junction

Abstract

A three-dimensional flash memory including an asymmetrically-structured dual junction is disclosed. According to one embodiment, the three-dimensional flash memory may comprise: gate electrodes vertically spaced apart and stacked while extending horizontally on a substrate; and vertical channel structures passing through the gate electrodes and extending vertically, each of the vertical channel structures including a vertical channel pattern and a data storage pattern, and the respective tops of the vertical channel structures having a asymmetrically-structured dual junction that is doped with different types of impurities and has different areas.

Description

3D flash memory including dual junctions with an asymmetric structure

[0001] The following embodiments are technologies related to a three-dimensional flash memory including a dual junction of an asymmetrical structure, an operating method thereof, and a manufacturing method thereof.

[0002] Flash memory devices are electrically erasable programmable read-only memories (EEPROM) that control the input and output of data electrically by Fowler-Nordheimtunneling or hot electron injection, and can be commonly used in computers, digital cameras, MP3 players, game systems, memory sticks, etc.

[0003] In order to meet the high performance and low price demands of consumers, it is necessary to increase the integration density in these flash memory devices, and a three-dimensional structure in which memory cell transistors are arranged vertically to form a cell string has been proposed.

[0004] However, existing 3D flash memory has the disadvantage of being limited to a 4-bit multi-value level due to the limitation of using only a portion of the positive voltage area as a memory window.

[0005] Therefore, there is a need to propose a technology to improve the multi-faceted nature.

[0006] One embodiment proposes a three-dimensional flash memory including a dual junction doped with different types of impurities, and an operating method and a manufacturing method thereof, to implement improved multi-levelization compared to existing three-dimensional flash memories.

[0007] At this time, one embodiment proposes a three-dimensional flash memory including a dual junction implemented in an asymmetric structure, an operating method thereof, and a manufacturing method thereof.

[0008] However, the technical problems to be solved by the present invention are not limited to the above problems, and can be expanded in various ways without departing from the technical spirit and scope of the present invention.

[0009] According to one embodiment, a three-dimensional flash memory may include gate electrodes that are formed to extend horizontally on a substrate and are vertically spaced apart from each other and stacked; and vertical channel structures that extend vertically through the gate electrodes, each of the vertical channel structures including a vertical channel pattern and a data storage pattern, and a dual junction, which is an asymmetrical structure doped with different types of impurities and having different areas, is formed on an upper end of each of the vertical channel structures.

[0010] According to one aspect, the dual junction may be characterized by including an N+ doped N+ junction and a P+ doped P+ junction.

[0011] According to another aspect, the dual junction may be characterized by an asymmetric structure in which the N+ junction has a larger area than the P+ junction.

[0012] According to another aspect, the dual junction may be characterized in that, in response to a voltage applied to a selected gate electrode corresponding to a target memory cell to be the target of a program operation among the gate electrodes during a program operation, either the N+ junction or the P+ junction is selectively activated to form a channel in the vertical channel pattern.

[0013] According to another aspect, the N+ junction may be characterized by forming an N-type channel in the vertical channel pattern in response to a positive voltage applied to the selected gate electrode.

[0014] According to another aspect, the positive voltage may be applied to the selected gate electrode in an ISPP (Incremental step pulse program) manner.

[0015] According to another aspect, the P+ junction may be characterized by forming a P-type channel in the vertical channel pattern in response to a negative voltage applied to the selected gate electrode.

[0016] According to another aspect, the negative voltage may be characterized in that it is applied to the selected gate electrode in an ISPP manner.

[0017] According to another aspect, the three-dimensional flash memory may be characterized by performing the erase operation on the memory cells programmed with the negative voltage in a first step of moving the memory cells programmed with the negative voltage to a state programmed with a positive voltage, and in a second step of performing an erase operation on the memory cells programmed with the positive voltage and the moved memory cells.

[0018] According to another aspect, the dual junction may be characterized in that it activates only the N+ junction during a read operation to form an N-type channel in the vertical channel pattern.

[0019] According to another aspect, the dual junction may further include an insulating film interposed between the N+ junction and the P+ junction to insulate the N+ junction and the P+ junction from each other.

[0020] According to one embodiment, a program operation method of a three-dimensional flash memory including gate electrodes formed horizontally on a substrate and vertically spaced apart from each other and stacked; and vertical channel structures formed vertically extending through the gate electrodes, each of the vertical channel structures including a vertical channel pattern and a data storage pattern, and a dual junction having an asymmetric structure doped with different types of impurities and having different areas is formed on an upper end of each of the vertical channel structures, may include the steps of: applying a voltage to a selected gate electrode corresponding to a target memory cell to be a target of a program operation among the gate electrodes; and, in response to the voltage applied to the selected gate electrode, selectively activating either an N+ junction or a P+ junction included in the dual junction to form a channel in the vertical channel pattern, thereby performing a program operation on the target memory cell.

[0021] According to one aspect, the step of applying may include a step of applying a positive voltage to the selected gate electrode, and the step of performing the program operation may include a step of performing the program operation by forming an N-type channel in the vertical channel pattern through the N+ junction in response to the positive voltage applied to the selected gate electrode.

[0022] According to another aspect, the step of applying may include a step of applying a negative voltage to the selected gate electrode, and the step of performing the program operation may include a step of performing the program operation by forming a P-type channel in the vertical channel pattern through the P+ junction in response to the negative voltage applied to the selected gate electrode.

[0023] According to another aspect, the step of applying may be characterized as a step of applying the voltage to the selected gate electrode in an ISPP (Incremental step pulse program) manner.

[0024] According to one embodiment, an erase operation method of a three-dimensional flash memory including gate electrodes formed horizontally on a substrate and vertically spaced apart from each other and stacked; and vertical channel structures formed vertically extending through the gate electrodes, each of the vertical channel structures including a vertical channel pattern and a data storage pattern, and a dual junction, which is an asymmetrical structure doped with different types of impurities and having different areas, is formed on an upper end of each of the vertical channel structures, may include the steps of: moving memory cells programmed with a negative voltage to a state programmed with a positive voltage by forming a P-type channel in the vertical channel pattern through a P+ junction included in the dual junction; and performing an erase operation on the memory cells programmed with the positive voltage and the moved memory cells.

[0025] According to one embodiment, a read operation method of a three-dimensional flash memory including gate electrodes formed horizontally on a substrate and vertically spaced apart from each other and stacked; and vertical channel structures formed vertically extending through the gate electrodes, each of the vertical channel structures including a vertical channel pattern and a data storage pattern, and a dual junction having an asymmetric structure doped with different types of impurities and having different areas is formed on an upper end of each of the vertical channel structures, may include the steps of: applying a positive voltage to a selected gate electrode corresponding to a target memory cell to be subjected to a read operation among the gate electrodes; and performing a read operation on the target memory cell by activating only an N+ junction included in the dual junction in response to the positive voltage applied to the selected gate electrode to form an N-type channel in the vertical channel pattern.

[0026] According to one embodiment, a method for manufacturing a three-dimensional flash memory having a dual junction, which is an asymmetrical structure having different areas and doped with different types of impurities, comprises the steps of: preparing a semiconductor structure including gate electrodes that extend horizontally on a substrate and are vertically spaced apart from each other; and vertical channel structures that penetrate the gate electrodes and extend vertically, each of the vertical channel structures including a vertical channel pattern and a data storage pattern; disposing a first mask pattern on the semiconductor structure that covers less than half of an upper surface of each of the vertical channel structures; forming an N+-doped N+ junction in a remaining area of ​​more than half of an upper surface of each of the vertical channel structures that is not covered by the first mask pattern; disposing a second mask pattern on the semiconductor structure that covers a remaining area of ​​more than half of an upper surface of each of the vertical channel structures; And using the second mask pattern, it may include a step of forming a P+-doped P+ junction in an area less than half of the upper surface that is not covered by the second mask pattern in each of the vertical channel structures.

[0027] According to one aspect, the first mask pattern and the second mask pattern may be characterized in that they cover regions of different areas on the upper surface of each of the vertical channel structures so that the N+ junction in each of the vertical channel structures has an asymmetric structure in which the N+ junction has a larger area than the P+ junction.

[0028] One embodiment proposes a three-dimensional flash memory including a dual junction doped with different types of impurities, and an operating method and a manufacturing method thereof, thereby achieving a technical effect of implementing improved multi-levelization compared to existing three-dimensional flash memories.

[0029] At this time, one embodiment can propose a three-dimensional flash memory including a dual junction implemented in an asymmetric structure, an operating method thereof, and a manufacturing method thereof.

[0030] However, the effects of the present invention are not limited to the above effects, and can be expanded in various ways without departing from the technical spirit and scope of the present invention.

[0031] FIG. 1 is a simplified circuit diagram illustrating an array of three-dimensional flash memory according to one embodiment.

[0032] FIG. 2 is a plan view illustrating the structure of a three-dimensional flash memory according to one embodiment.

[0033] FIGS. 3A to 3D are cross-sectional views illustrating the structure of a three-dimensional flash memory according to one embodiment, corresponding to a cross-section taken along line A-A' of FIG. 2.

[0034] FIGS. 4A and 4B are diagrams illustrating an improved memory window of a three-dimensional flash memory according to one embodiment.

[0035] FIG. 5 is a flow chart illustrating a program operation method of a three-dimensional flash memory according to one embodiment.

[0036] FIGS. 6A and 6B are cross-sectional views illustrating the structure of a three-dimensional flash memory to explain a program operation method of a three-dimensional flash memory according to one embodiment.

[0037] FIG. 7 is a flow chart illustrating a reading operation method of a three-dimensional flash memory according to one embodiment.

[0038] FIG. 8 is a diagram illustrating a memory window to explain a read operation of a three-dimensional flash memory according to one embodiment.

[0039] FIG. 9 is a flow chart illustrating an erase operation method of a three-dimensional flash memory according to one embodiment.

[0040] FIGS. 10A and 10B are diagrams illustrating a memory window to explain an erase operation of a three-dimensional flash memory according to one embodiment.

[0041] FIG. 11 is a flow chart illustrating a method for manufacturing a three-dimensional flash memory according to one embodiment.

[0042] FIG. 12 is a perspective view schematically illustrating an electronic system including a three-dimensional flash memory according to one embodiment.

[0043] Hereinafter, embodiments of the present invention will be described in detail with reference to the attached drawings. However, the present invention is not limited or restricted by these embodiments. In addition, the same reference numerals in each drawing represent the same components.

[0044] In addition, the terminology used in this specification is a term used to appropriately express the preferred embodiments of the present invention, and this may vary depending on the intention of the viewer or operator, or the customs of the field to which the present invention belongs. Therefore, the definition of these terms should be determined based on the contents throughout this specification. For example, in this specification, the singular also includes the plural unless specifically stated in the phrase. In addition, the terms "comprises" and / or "comprising" as used herein do not exclude the presence or addition of one or more other components, steps, operations, and / or elements with respect to the mentioned components, steps, operations, and / or elements. In addition, although the terms first, second, etc. are used in this specification to describe various regions, directions, shapes, etc., these regions, directions, and shapes should not be limited by these terms. These terms are only used to distinguish a certain region, direction, or shape from another region, direction, or shape. Therefore, a part referred to as a first part in one embodiment may be referred to as a second part in another embodiment.

[0045] It should also be understood that the various embodiments of the present invention, while different, are not necessarily mutually exclusive. For example, specific shapes, structures, and characteristics described herein may be implemented in other embodiments without departing from the spirit and scope of the present invention. Furthermore, it should be understood that the location, arrangement, or configuration of individual components within each of the disclosed embodiments may be modified without departing from the spirit and scope of the present invention.

[0046] Hereinafter, with reference to the drawings, a three-dimensional flash memory that implements improved multi-leveling compared to existing three-dimensional flash memory, its operating method, and its manufacturing method are described in detail.

[0047]

[0048] FIG. 1 is a simplified circuit diagram illustrating an array of three-dimensional flash memory according to one embodiment.

[0049] Referring to FIG. 1, an array of a three-dimensional flash memory according to one embodiment may include a common source line (CSL), a plurality of bit lines (BL0, BL1, BL2), and a plurality of cell strings (CSTR) disposed between the common source line (CSL) and the bit lines (BL0, BL1, BL2).

[0050] The bit lines (BL0, BL1, BL2) can be arranged two-dimensionally while being spaced apart from each other along the first direction (D1) and extending in the second direction (D2). Here, the first direction (D1), the second direction (D2), and the third direction (D3) are each orthogonal to each other and can form a rectangular coordinate system defined by the X, Y, and Z axes.

[0051] A plurality of cell strings (CSTR) may be connected in parallel to each of the bit lines (BL0, BL1, BL2). The cell strings (CSTR) may be commonly connected to the common source line (CSL) provided between the bit lines (BL0, BL1, BL2) and one common source line (CSL). At this time, a plurality of common source lines (CSL) may be provided, and the plurality of common source lines (CSL) may be two-dimensionally arranged while extending in the first direction (D1) and being spaced apart from each other along the second direction (D2). The plurality of common source lines (CSL) may be electrically identically voltage-applied, but the present invention is not limited thereto, and each of the plurality of common source lines (CSL) may be electrically independently controlled so that different voltages may be applied.

[0052] The cell strings (CSTR) may be arranged to be spaced apart from each other along the second direction (D2) for each bit line while being formed to extend in the third direction (D3). According to an embodiment, each of the cell strings (CSTR) may be composed of a ground select transistor (GST) connected to a common source line (CSL), first and second string select transistors (SST1, SST2) connected to bit lines (BL0, BL1, BL2) and connected in series, memory cell transistors (MCT) and an erase control transistor (ECT) disposed between the ground select transistor (GST) and the first and second string select transistors (SST1, SST2) and connected in series. In addition, each of the memory cell transistors (MCT) may include a data storage element.

[0053] For example, each of the cell strings (CSTR) may include first and second string select transistors (SST1, SST2) connected in series, and the second string select transistor (SST2) may be connected to one of the bit lines (BL0, BL1, BL2). However, the present invention is not limited thereto, and each of the cell strings (CSTR) may include one string select transistor. As another example, the ground select transistor (GST) in each of the cell strings (CSTR) may be composed of a plurality of MOS transistors connected in series, similar to the first and second string select transistors (SST1, SST2).

[0054] A cell string (CSTR) may be composed of a plurality of memory cell transistors (MCT) having different distances from common source lines (CSL). That is, the memory cell transistors (MCT) may be connected in series along a third direction (D3) between a first string select transistor (SST1) and a ground select transistor (GST). An erase control transistor (ECT) may be connected between the ground select transistor (GST) and the common source lines (CSL). Each of the cell strings (CSTR) may further include dummy cell transistors (DMC) connected between the first string select transistor (SST1) and an uppermost one of the memory cell transistors (MCT) and between the ground select transistor (GST) and a lowermost one of the memory cell transistors (MCT).

[0055] According to an embodiment, a first string select transistor (SST1) may be controlled by first string select lines (SSL1-1, SSL1-2, SSL1-3), and a second string select transistor (SST2) may be controlled by second string select lines (SSL2-1, SSL2-2, SSL2-3). The memory cell transistors (MCT) may be controlled by a plurality of word lines (WL0-WLn), and the dummy cell transistors (DMC) may be controlled by a dummy word line (DWL), respectively. The ground select transistor (GST) may be controlled by the ground select lines (GSL0, GSL1, GSL2), and the erase control transistor (ECT) may be controlled by the erase control line (ECL). A plurality of erase control transistors (ECT) may be provided. Common source lines (CSL) can be commonly connected to the sources of erase control transistors (ECT).

[0056] The gate electrodes of the memory cell transistors (MCT), which are provided at substantially the same distance from the common source lines (CSL), may be commonly connected to one of the word lines (WL0-WLn, DWL) and thus may be in an equipotential state. However, the present invention is not limited thereto, and even if the gate electrodes of the memory cell transistors (MCT) are provided at substantially the same level from the common source lines (CSL), the gate electrodes provided in different rows or columns may be independently controlled.

[0057] Ground selection lines (GSL0, GSL1, GSL2), first string selection lines (SSL1-1, SSL1-2, SSL1-3) and second string selection lines (SSL2-1, SSL2-2, SSL2-3) extend along a first direction (D1), are spaced apart from each other in a second direction (D2) and can be arranged two-dimensionally. Ground selection lines (GSL0, GSL1, GSL2), first string selection lines (SSL1-1, SSL1-2, SSL1-3) and second string selection lines (SSL2-1, SSL2-2, SSL2-3) provided at substantially the same level from common source lines (CSL) can be electrically isolated from each other. In addition, erase control transistors (ECT) of different cell strings (CSTR) can be controlled by a common erase control line (ECL). The erase control transistors (ECT) may generate gate-induced drain leakage (GIDL) during an erase operation of the memory cell array. In some embodiments, an erase voltage may be applied to the bit lines (BL0, BL1, BL2) and / or the common source lines (CSL) during an erase operation of the memory cell array, and gate-induced leakage current may be generated in the string select transistor (SST) and / or the erase control transistors (ECT).

[0058] The string selection line (SSL) described above may be represented as an upper selection line (USL), and the ground selection line (GSL) may be represented as a lower selection line.

[0059]

[0060] FIG. 2 is a plan view illustrating a structure of a three-dimensional flash memory according to one embodiment, FIGS. 3a to 3d are cross-sectional views illustrating a structure of a three-dimensional flash memory according to one embodiment, corresponding to a cross-section taken along line A-A' of FIG. 2, and FIGS. 4a to 4b are drawings for explaining an improved memory window of a three-dimensional flash memory according to one embodiment.

[0061] Referring to the drawings, the substrate (SUB) may be a semiconductor substrate such as a silicon substrate, a silicon-germanium substrate, a germanium substrate, or a single-crystal epitaxial layer grown on a monocrystalline silicon substrate. The substrate (SUB) may be doped with a first conductive type impurity (e.g., P- impurity).

[0062] Stacked structures (ST) may be arranged on a substrate (SUB). The stacked structures (ST) may be two-dimensionally arranged along a second direction (D2) while extending in a first direction (D1). In addition, the stacked structures (ST) may be spaced apart from each other in the second direction (D2).

[0063] Each of the stacked structures (ST) may include gate electrodes (EL1, EL2, EL3) and interlayer insulating films (ILD) alternately stacked in a vertical direction (e.g., a third direction (D3)) perpendicular to the upper surface of the substrate (SUB). The stacked structures (ST) may have a substantially flat upper surface. That is, the upper surfaces of the stacked structures (ST) may be parallel to the upper surface of the substrate (SUB). Hereinafter, the vertical direction means the third direction (D3) or the opposite direction of the third direction (D3).

[0064] Referring back to FIG. 1, each of the gate electrodes (EL1, EL2, EL3) may be one of the erase control line (ECL), ground select lines (GSL0, GSL1, GSL2), word lines (WL0-WLn, DWL), first string select lines (SSL1-1, SSL1-2, SSL1-3), and second string select lines (SSL2-1, SSL2-2, SSL2-3) sequentially stacked on the substrate (SUB).

[0065] Each of the gate electrodes (EL1, EL2, EL3) may be formed to extend in the first direction (D1) and have substantially the same thickness in the third direction (D3). Hereinafter, the thickness means the thickness in the third direction (D3). Each of the gate electrodes (EL1, EL2, EL3) may be formed of a conductive material. For example, each of the gate electrodes (EL1, EL2, EL3) may include at least one selected from a doped semiconductor (e.g., doped silicon, etc.), a metal (e.g., tungsten (W), copper (Cu), aluminum (Al), titanium (Ti), tantalum (Ta), molybdenum (Mo), ruthenium (Ru), gold (Au), etc.), or a conductive metal nitride (e.g., titanium nitride, tantalum nitride, etc.). Each of the gate electrodes (EL1, EL2, EL3) may include at least one of all metal materials that can be formed by ALD in addition to the described metal materials.

[0066] More specifically, the gate electrodes (EL1, EL2, EL3) may include a first gate electrode (EL1) at the bottom, a third gate electrode (EL3) at the top, and a plurality of second gate electrodes (EL2) between the first gate electrode (EL1) and the third gate electrode (EL3). Although the first gate electrode (EL1) and the third gate electrode (EL3) are each illustrated and described as a single number, this is exemplary and is not limited thereto, and the first gate electrode (EL1) and the third gate electrode (EL3) may be provided in multiple numbers as needed. The first gate electrode (EL1) may correspond to any one of the ground selection lines (GSL0, GSL1, GLS2) illustrated in FIG. 1. The second gate electrode (EL2) may correspond to any one of the word lines (WL0-WLn, DWL) illustrated in FIG. 1. The third gate electrode (EL3) may correspond to any one of the first string selection lines (SSL1-1, SSL1-2, SSL1-3) or any one of the second string selection lines (SSL2-1, SSL2-2, SSL2-3) illustrated in FIG. 1.

[0067] Although not shown, each end of the stacked structures (ST) may have a stepwise structure along the first direction (D1). More specifically, the gate electrodes (EL1, EL2, EL3) of the stacked structures (ST) may have a length in the first direction (D1) that decreases as they move away from the substrate (SUB). The third gate electrode (EL3) may have the shortest length in the first direction (D1) and the longest distance from the substrate (SUB) in the third direction (D3). The first gate electrode (EL1) may have the longest length in the first direction (D1) and the shortest distance from the substrate (SUB) in the third direction (D3). By means of the step structure, each of the stacked structures (ST) can have a thickness that decreases as it moves away from the outermost one of the vertical channel structures (VS) described below, and the side walls of the gate electrodes (EL1, EL2, EL3) can be spaced apart at a constant interval along the first direction (D1) in a plan view.

[0068] Each of the interlayer insulating films (ILDs) may have a different thickness. For example, the lowermost and uppermost interlayer insulating films (ILDs) may have a smaller thickness than the other interlayer insulating films (ILDs). However, this is merely an example and is not limiting, and the thickness of each of the interlayer insulating films (ILDs) may be different depending on the characteristics of the semiconductor device, or may be set to be the same for all. The interlayer insulating films (ILDs) may be formed of an insulating material for insulation between the gate electrodes (EL1, EL2, EL3). For example, the interlayer insulating films (ILDs) may be formed of silicon oxide.

[0069] A plurality of channel holes (CH) penetrating through a portion of the stacked structures (ST) and the substrate (SUB) may be provided. Vertical channel structures (VS) may be provided within the channel holes (CH). The vertical channel structures (VS) may be a plurality of cell strings (CSTR) as illustrated in FIG. 1, and may be formed to extend in a third direction (D3) while being connected to the substrate (SUB). The connection of the vertical channel structures (VS) to the substrate (SUB) may be achieved by a lower surface of each of the vertical channel structures (VS) being in contact with an upper surface of the substrate (SUB), but is not limited thereto and may also be achieved by being embedded in the substrate (SUB). When a portion of each of the vertical channel structures (VS) is embedded in the substrate (SUB), the lower surfaces of the vertical channel structures (VS) may be located at a level lower than the upper surface of the substrate (SUB).

[0070] Rows of vertical channel structures (VS) penetrating one of the stacked structures (ST) may be provided in multiple numbers. For example, as illustrated in FIG. 2, rows of three vertical channel structures (VS) may penetrating one of the stacked structures (ST). However, the invention is not limited thereto, and rows of four or more vertical channel structures (VS) may penetrating one of the stacked structures (ST), or rows of one or more but not more than two vertical channel structures (VS) may penetrating one of the stacked structures (ST). In a pair of adjacent rows, the vertical channel structures (VS) corresponding to one row may be shifted in a first direction (D1) from the vertical channel structures (VS) corresponding to the other adjacent row. In a plan view, the vertical channel structures (VS) may be arranged in a zigzag shape along the first direction (D1). However, without being limited or restricted thereto, the vertical channel structures (VS) may also form an array arranged side by side in rows and columns.

[0071] Each of the vertical channel structures (VS) may be formed to extend from the substrate (SUB) in a third direction (D3). In the drawing, each of the vertical channel structures (VS) is illustrated as having a columnar shape with the same width at the top and bottom, but is not limited thereto and may have a shape in which the width in the first direction (D1) and the second direction (D2) increases as it goes in the third direction (D3). The upper surface of each of the vertical channel structures (VS) may have a circular shape, an oval shape, a square shape, or a bar shape.

[0072] Each of the vertical channel structures (VS) may include a data storage pattern (DSP), a vertical channel pattern (VCP), a vertical burial pattern (VFP), and a dual junction (DJ). In each of the vertical channel structures (VS), the data storage pattern (DSP) may have a pipe shape or a macaroni shape with an open bottom, and the vertical channel pattern (VCP) may have a pipe shape or a macaroni shape with a closed bottom. The vertical burial pattern (VFP) may fill a space surrounded by the vertical channel pattern (VCP) and the dual junction (DJ).

[0073] The data storage pattern (DSP) may cover the inner sidewall of each of the channel holes (CH), surround the outer sidewall of the vertical channel pattern (VCP) inwardly, and contact the sidewalls of the gate electrodes (EL1, EL2, EL3) inwardly. Accordingly, the regions corresponding to the second gate electrodes (EL2) of the data storage pattern (DSP) may, together with the regions corresponding to the second gate electrodes (EL2) of the vertical channel pattern (VCP), form memory cells in which a memory operation (program operation, read operation, or erase operation) is performed by a voltage applied through the second gate electrodes (EL2). The memory cells correspond to the memory cell transistors (MCT) illustrated in FIG. 1. To this end, the data storage pattern (DSP) may be a data storage element that represents a data value by trapping charges by a voltage applied through the second gate electrodes (EL2) or maintaining a state of charges (e.g., a polarization state of charges).

[0074] For example, a data storage pattern (DSP) can represent binary data values ​​or multi-valued data values ​​by the polarization state of charge by forming a ferroelectric material. The ferroelectric material has an orthorhombic crystal structure of HfO. x , HfO doped with at least one of Al, Zr or Si x , PZT(Pb(Zr, Ti)O3), PTO(PbTiO3), SBT(SrBi2Ti2O3), BLT(Bi(La, Ti)O3), PLZT(Pb(La, Zr)TiO3), BST(Bi(Sr, Ti)O3), barium titanate (BaTiO3), P(VDF-TrFE), PVDF, AlO x , ZnO x , TiO x , TaO x or InO x May include at least one of:

[0075] As another example, the data storage pattern (DSP) is formed of ONO (Tunneling Oxide-Charge trap Nitride-Blocking Oxide), and thus can represent binary data values ​​or multi-valued data values ​​by trapping charges in a charge trap nitride layer.

[0076] Although the drawing illustrates that the data storage pattern (DSP) is formed to extend in a vertical direction (e.g., a third direction (D3)), it is not limited thereto and may have a structure in which it is segmented into multiple pieces that are spaced apart only in areas corresponding to the second gate electrodes (EL2) on the outer wall of the vertical channel pattern (VCP) and the inner wall of each of the channel holes (CH).

[0077] A vertical channel pattern (VCP) may cover an inner side wall of a data storage pattern (DSP) and may extend in a vertical direction (e.g., a third direction (D3)). The vertical channel pattern (VCP) may include a first portion (VCP1) and a second portion (VCP2) on the first portion (VCP1).

[0078] A first portion (VCP1) of the vertical channel pattern (VCP) may be provided at a lower portion of each of the channel holes (CH) and may be in contact with the substrate (SUB). The first portion (VCP1) of the vertical channel pattern (VCP) may be used to block, suppress, or minimize leakage current in each of the vertical channel structures (VS) and / or as an epitaxial pattern. The thickness of the first portion (VCP1) of the vertical channel pattern (VCP) may be, for example, greater than the thickness of the first gate electrode (EL1). A side wall of the first portion (VCP1) of the vertical channel pattern (VCP) may be surrounded by a data storage pattern (DSP). An upper surface of the first portion (VCP1) of the vertical channel pattern (VCP) may be located at a higher level than an upper surface of the first gate electrode (EL1). More specifically, the upper surface of the first part (VCP1) of the vertical channel pattern (VCP) may be located between the upper surface of the first gate electrode (EL1) and the lower surface of the lowest one of the second gate electrodes (EL2). The lower surface of the first part (VCP1) of the vertical channel pattern (VCP) may be located at a level lower than the upper surface of the substrate (SUB) (i.e., the lower surface of the lowest one of the interlayer insulating films (ILD). A part of the first part (VCP1) of the vertical channel pattern (VCP) may overlap with the first gate electrode (EL1) in the horizontal direction. Hereinafter, the horizontal direction means any direction extending on a plane parallel to the first direction (D1) and the second direction (D2).

[0079] A second portion (VCP2) of the vertical channel pattern (VCP) may extend in a third direction (D3) from an upper surface of the first portion (VCP1). The second portion (VCP2) of the vertical channel pattern (VCP) may be provided between the data storage pattern (DSP) and the vertical buried pattern (VFP), and may correspond to the second gate electrodes (EL2). Accordingly, the second portion (VCP2) of the vertical channel pattern (VCP) may form memory cells together with regions corresponding to the second gate electrodes (EL2) of the data storage pattern (DSP), as described above.

[0080] The upper surface of the second part (VCP2) of the vertical channel pattern (VCP) may be substantially coplanar with the upper surface of the vertical buried pattern (VFP). The upper surface of the second part (VCP2) of the vertical channel pattern (VCP) may be located at a level higher than the upper surface of the uppermost one of the second gate electrodes (EL2). More specifically, the upper surface of the second part (VCP2) of the vertical channel pattern (VCP) may be located between the upper surface and the lower surface of the third gate electrode (EL3).

[0081] A vertical channel pattern (VCP) is a component that transfers charges or holes to a data storage pattern (DSP), and may be formed of single-crystalline silicon or polysilicon to form or boost a channel by an applied voltage. However, without being limited thereto, the vertical channel pattern (VCP) may be formed of an oxide semiconductor material capable of blocking, suppressing, or minimizing leakage current. For example, the vertical channel pattern (VCP) may be formed of an oxide semiconductor material or a group 4 semiconductor material including at least one of In, Zn, or Ga having excellent leakage current characteristics. The vertical channel pattern (VCP) may be formed of, for example, a ZnOx series material including AZO, ZTO, IZO, ITO, IGZO, or Ag-ZnO. Therefore, the vertical channel pattern (VCP) can block, suppress, or minimize leakage current to the gate electrodes (EL1, EL2, EL3) or the substrate (SUB), and can improve transistor characteristics (e.g., threshold voltage distribution and speed of program / read operation) of at least one of the gate electrodes (EL1, EL2, EL3), thereby improving electrical characteristics of the three-dimensional flash memory.

[0082] In particular, the vertical channel pattern (VCP) can be formed of single-crystalline silicon or polysilicon, as well as a low-concentration p-doped material or a low-concentration n-doped material, for the channel forming operation of the dual junction (DJ) described below.

[0083] Although the vertical channel pattern (VCP) has been described as having a structure including a first portion (VCP1) and a second portion (VCP2), it is not limited thereto and may have a structure in which the first portion (VCP1) is excluded. For example, the vertical channel pattern (VCP) may be provided between a vertically filled pattern (VFP) formed to extend to a substrate (SUB) and a data storage pattern (DSP) and may be formed to extend to the substrate (SUB) so as to contact the substrate (SUB). In this case, a lower surface of the vertical channel pattern (VCP) may be positioned at a level lower than an uppermost surface of the substrate (SUB) (a lower surface of the lowest of the interlayer insulating films (ILDs)), and an upper surface of the vertical channel pattern (VCP) may be substantially coplanar with an upper surface of the vertically filled pattern (VFP).

[0084] The vertical buried pattern (VFP) may be surrounded by a second portion (VCP2) of a vertical channel pattern (VCP). An upper surface of the vertical buried pattern (VFP) may be in contact with a dual junction (DJ), and a lower surface of the vertical buried pattern (VFP) may be in contact with a first portion (VCP1) of the vertical channel pattern (VCP). The vertical buried pattern (VFP) may be spaced apart from the substrate (SUB) in a third direction (D3). In other words, the vertical buried pattern (VFP) may be electrically floated from the substrate (SUB).

[0085] The vertical buried pattern (VFP) can be formed of a material that helps the diffusion of charges or holes in the vertical channel pattern (VCP). More specifically, the vertical buried pattern (VFP) can be formed of a material with excellent charge or hole mobility. For example, the vertical buried pattern (VFP) can be formed of a semiconductor material doped with impurities, an intrinsic semiconductor material that is not doped with impurities, or a polycrystalline semiconductor material. For a more specific example, the vertical buried pattern (VFP) can be formed of polysilicon doped with the same first conductivity type impurities as the substrate (SUB) (e.g., P- impurities). That is, the vertical buried pattern (VFP) can improve the electrical characteristics of the 3D flash memory, thereby increasing the speed of the memory operation.

[0086] Although the vertical channel structures (VS) are described as including a vertically embedded pattern (VFP), the present invention is not limited thereto and the vertically embedded pattern (VFP) may be omitted.

[0087] Additionally, each of the vertical channel structures (VS) may not only have a structure in which the vertical buried pattern (VFP) is omitted, but may also have a structure including a back gate (BG; not shown). In this case, the back gate (BG) may be in contact with the vertical channel pattern (VCP) while being at least partially surrounded by the vertical channel pattern (VCP), and may be a component that applies a voltage to the vertical channel pattern (VCP) for memory operation.

[0088] Referring back to FIG. 1, the vertical channel structures (VS) may correspond to channels of an erase control transistor (ECT), first and second string select transistors (SST1, SST2), a ground select transistor (GST), and memory cell transistors (MCT).

[0089] As illustrated in FIGS. 3A to 3D, a dual junction (DJ) may be provided on the upper surface of the vertical channel pattern (VCP). That is, the dual junction (DJ) may be positioned at the upper end of each of the vertical channel structures (VS) and connected to the upper portion of the vertical channel pattern (VCP), thereby functioning as a drain junction.

[0090] A dual junction (DJ) can have a dual structure doped with different types of impurities. For example, a dual junction (DJ) can have a dual structure including an N+-doped N+ junction and a P+-doped P+ junction.

[0091] Accordingly, the dual junction (DJ) can use the memory windows of PGM1 to PGM8 by forming a P-type channel in the vertical channel pattern (VCP) by activating the P+ junction in response to a negative program voltage being applied during a program operation as illustrated in FIG. 4a, and can use the memory windows of PGM9 to PGM32 by forming an N-type channel in the vertical channel pattern (VCP) by activating the N+ junction in response to a positive program voltage being applied.

[0092] The reason why the memory window used by the N+ junction is wider than the memory window used by the P+ junction is because the dual junction (DJ) is an asymmetric structure in which the N+ junction has a larger area than the P+ junction, as described later.

[0093] Therefore, a three-dimensional flash memory including a dual junction (DJ) can implement multi-leveling of 5 bits or more, which is an improvement over the 4-bit multi-leveling of a conventional three-dimensional NAND flash memory as illustrated in FIG. 4b.

[0094] That is, the three-dimensional flash memory can perform a program operation of recording multi-valued data according to the adjusted positive program voltage value and the adjusted negative program voltage value by adjusting the value of the program voltage applied to the selected gate electrode (Sel EL) within a negative voltage range or a positive voltage range.

[0095] In particular, the dual junction (DJ) may have an asymmetric structure with different areas while being doped with different types of impurities. More specifically, the dual junction (DJ) may have an asymmetric structure including an N+-doped N+ junction and a P+-doped P+ junction, wherein the N+ junction has a larger area than the P+ junction.

[0096] Hereinafter, the asymmetric structure in which the N+ junction has a larger area than the P+ junction means that the N+ junction occupies more than half of the upper surface area based on the upper surface center of the vertical channel structure (VS), thereby having a wider contact area (larger contact area compared to the P+ junction) with respect to the vertical channel pattern (VCP), and the P+ junction occupies less than half of the upper surface area based on the upper surface center of the vertical channel structure (VS), thereby having a narrower contact area (narrower contact area compared to the N+ junction) with respect to the vertical channel pattern (VCP).

[0097] The asymmetric structure of the dual junction (DJ) in which the contact area of ​​the N+ junction to the vertical channel pattern (VCP) is larger than the contact area of ​​the P+ junction to the vertical channel pattern (VCP) is intended to uniformly form an N-type channel and a P-type channel in the vertical channel pattern (VCP) according to the voltage applied through the gate electrodes (EL1, EL2, EL3) by considering the electrical characteristics of each of the N+ junction and the P+ junction (to ensure that the operation of forming an N-type channel and the operation of forming a P-type channel are symmetrical).

[0098] For example, an asymmetrical dual junction (DJ) structure in which the contact area of ​​the N+ junction to the vertical channel pattern (VCP) is larger than the contact area of ​​the P+ junction to the vertical channel pattern (VCP) can be implemented so that the speed of the operation of forming an N-type channel in the vertical channel pattern (VCP) in response to a positive voltage applied to the selected gate electrode (Sel EL) and the speed of the operation of forming a P-type channel in the vertical channel pattern (VCP) in response to a negative voltage applied to the selected gate electrode (Sel EL) are uniform.

[0099] Therefore, the detailed values ​​for the areas of each of the N+ junction and the P+ junction in the dual junction (DJ) of the asymmetric structure can be adjusted and determined to satisfy the described conditions (conditions in which the operation of forming an N-type channel and the operation of forming a P-type channel in a vertical channel pattern (VCP) are uniformly performed).

[0100] In addition, the asymmetric structure of the dual junction (DJ) in which the contact area of ​​the N+ junction to the vertical channel pattern (VCP) is larger than that of the P+ junction to the vertical channel pattern (VCP) is because only the N+ junction is activated during the read operation, rather than using the P+ junction, to form an N-type channel in the vertical channel pattern (VCP).

[0101] A dual junction (DJ) having an asymmetric structure can selectively activate either an N+ junction or a P+ junction in response to a voltage applied to a selected gate electrode (Sel EL) corresponding to a target memory cell to be the target of a memory operation among the gate electrodes (EL1, EL2, EL3) (more specifically, the second gate electrodes (EL2)) during a memory operation, thereby forming a channel in a vertical channel pattern (VCP).

[0102] For example, the N+ junction is connected to a positive program voltage (+V) applied to the selected gate electrode (Sel EL). pgm) can be used to perform a program operation by forming an N-type channel in a vertical channel pattern (VCP). That is, the N-type channel can be formed to extend in the vertical direction so as to be connected to the N+ junction. In this case, a positive program voltage (+V) applied to the selected gate electrode (Sel EL) pgm ) can be applied to the selected gate electrode (Sel EL) using the ISPP (Incremental step pulse program) method.

[0103] As another example, the P+ junction is connected to a negative program voltage (-V) applied to the selected gate electrode (Sel EL). pgm ) can perform a program operation by forming a P-type channel in the vertical channel pattern (VCP). Similarly, the P-type channel can be formed to extend vertically to connect to the P+ junction, and a negative program voltage (-V) applied to the selected gate electrode (Sel EL) pgm ) can also be applied to the selected gate electrode (Sel EL) using the ISPP (Incremental step pulse program) method.

[0104] As another example, the N+ junction receives a positive read voltage (+V) applied to the selected gate electrode (Sel EL). read ) can be used to perform a read operation by forming an N-type channel in a vertical channel pattern (VCP). In this case as well, the N-type channel can be formed to extend vertically to connect to the N+ junction. However, a positive read voltage (+V) applied to the selected gate electrode (Sel EL) read ) can be applied to the selected gate electrode (Sel EL) in a manner that the voltage is maintained at a constant value without increasing or decreasing the voltage, rather than in the ISPP (Incremental step pulse program) manner.

[0105] As described, since the dual junction (DJ) is implemented as an asymmetric structure in which the N+ junction has a larger area than the P+ junction, the memory window used by the N+ junction is wider than the memory window used by the P+ junction, so the 3D flash memory including the dual junction (DJ) can operate at a negative program voltage (-V pgm ) programmed memory cells with a positive program voltage (+V pgm ) and a first step to move to a programmed state with a positive program voltage (+V pgm ) to perform an erase operation on the memory cells programmed and moved memory cells using a negative program voltage (-V pgm ) can perform an erase operation on memory cells programmed with the dual junction (DJ). That is, a three-dimensional flash memory including a dual junction (DJ) can perform an erase operation consisting of two steps.

[0106] The upper surface of the dual junction (DJ) can be substantially coplanar with the upper surface of each of the stacked structures (ST) (i.e., the upper surface of the uppermost one of the interlayer insulating films (ILDs). The lower surface of the dual junction (DJ) can be located at a level lower than the upper surface of the third gate electrode (EL3). More specifically, the lower surface of the dual junction (DJ) can be located between the upper and lower surfaces of the third gate electrode (EL3). That is, at least a portion of the dual junction (DJ) can overlap the third gate electrode (EL3) in a horizontal direction.

[0107] A contact plug (CPG) connected to a bit line plug (BLPG) may be placed on the upper side of the dual junction (DJ). That is, the dual junction (DJ) may be connected to the bit line plug (BLPG) through the contact plug (CPG).

[0108] The reason why the dual junction (DJ) is connected to the bit line plug (BLPG) through the contact plug (CPG) is because the cross-sectional area of ​​the bit line plug (BLPG) is not large enough to apply voltage to each of the N+ junction and the P+ junction of the dual junction (DJ) (not large enough to provide current to each of the N+ junction and the P+ junction of the dual junction (DJ)). Therefore, the contact plug (CPG) may be configured with a sufficient area to apply voltage to each of the N+ junction and the P+ junction of the dual junction (DJ) (sufficient area to provide current to each of the N+ junction and the P+ junction of the dual junction (DJ)).

[0109] In addition, the dual junction (DJ) is connected to the bit line plug (BLPG) through the contact plug (CPG) to reduce the contact resistance between the dual junction (DJ) and the bit line plug (BLPG). Accordingly, the contact plug (CPG) may be formed of a material that can reduce the contact resistance between the dual junction (DJ) and the bit line plug (BLPG). For example, the contact plug (CPG) may be formed of a semiconductor or conductive material doped with impurities. For example, the contact plug (CPG) may be formed of a semiconductor material doped with impurities different from those of the substrate (SUB) or the vertical buried pattern (VFP) (more precisely, impurities of a second conductive type (e.g., N-) different from those of the first conductive type (e.g., P-).

[0110] Above, the dual junction (DJ) has been described as being connected to the bit line plug (BLPG) through the contact plug (CPG), but this is not limited or restricted thereto, and the contact plug (CPG) may be omitted. In this case, the bit line plug (BLPG) is configured with a sufficient area capable of applying voltage to each of the N+ junction and the P+ junction of the dual junction (DJ) (a sufficient area capable of providing current to each of the N+ junction and the P+ junction of the dual junction (DJ)), so that voltage can be directly applied to or current can be provided to the dual junction (DJ).

[0111] As illustrated in FIG. 3A, a source region (SR) may be formed below the bottom surface of the vertical channel pattern (VCP). The source region (SR) of each of the vertical channel structures (VS) may be connected to each other through separate wiring (not illustrated) within the substrate (SUB), thereby corresponding to the common source line (CSL) of FIG. 1. However, without being limited thereto, the source region (SR) of each of the vertical channel structures (VS) may have a structure in which they are not connected to each other so that each of the vertical channel structures (VS) operates independently.

[0112] In addition, the dual junction (DJ) may also be provided below the bottom of the vertical channel pattern (VCP) as illustrated in FIG. 3B. That is, the dual junction (DJ) may be positioned at the bottom of each of the vertical channel structures (VS) and connected to the bottom of the vertical channel pattern (VCP), thereby operating as a source junction. Since the dual junction (DJ) operating as a source junction also has the same structure as the dual junction (DJ) operating as the drain junction described above, a detailed description thereof will be omitted. A source region (SR) may be formed below the dual junction (DJ) operating as a source junction in each of the vertical channel structures (VS). The source regions (SR) of each of the vertical channel structures (VS) may be connected to each other through separate wiring (not illustrated) in the substrate (SUB), thereby corresponding to the common source line (CSL) of FIG. 1. However, without being limited or restricted thereto, the source region (SR) of each of the vertical channel structures (VS) may have a structure that is not connected to each other so that the vertical channel structures (VS) operate independently.

[0113] In addition, if a dual junction (DJ) is positioned at the bottom of each of the vertical channel structures (VS), the source region (SR) may be omitted. In this case, the dual junctions (DJ) operating as source junctions in each of the vertical channel structures (VS) may be connected to each other through separate wiring (not shown) in the substrate (SUB), thereby corresponding to the common source line (CSL) of FIG. 1. However, without being limited thereto, the dual junctions (DJ) operating as source junctions in each of the vertical channel structures (VS) may have a structure in which they are not connected to each other so as to operate independently for each of the vertical channel structures (VS).

[0114] Additionally, when the dual junction (DJ) is positioned only at the top of each of the vertical channel structures, each of the vertical channel structures (VS) may have a source free structure in which the source region (SR) is omitted below the bottom of the vertical channel pattern (VCP), as illustrated in FIG. 3c.

[0115] Although the above dual junction (DJ) has been described as a structure including only an N+ junction and a P+ junction, it is not limited thereto and may also be a structure including an insulator interposed between the N+ junction and the P+ junction and insulating the N+ junction and the P+ junction from each other, as illustrated in FIG. 3d.

[0116] Although not depicted in a separate drawing, the dual junction (DJ) positioned underneath the vertical channel pattern (VCP) can also be implemented with a structure that further includes an insulator.

[0117] In addition, although not shown in the drawing, a separation trench (TR) extending in a first direction (D1) may be provided between adjacent stacked structures (ST). A common source region (CSR) may be provided within a substrate (SUB) exposed by the separation trench (TR). The common source region (CSR) may extend in the first direction (D1) within the substrate (SUB). The common source region (CSR) may be formed of a semiconductor material doped with an impurity of a second conductivity type (e.g., an impurity of N+). The common source region (CSR) may correspond to a common source line (CSL) of FIG. 1.

[0118] A common source plug (CSP) may be provided within a separation trench (TR). The common source plug (CSP) may be connected to a common source region (CSR). A top surface of the common source plug (CSP) may be substantially coplanar with a top surface of each of the stacked structures (ST) (i.e., a top surface of an uppermost one of the interlayer dielectrics (ILDs). The common source plug (CSP) may have a plate shape extending in a first direction (D1) and a third direction (D3). In this case, the common source plug (CSP) may have a shape in which a width in a second direction (D2) increases as it goes in the third direction (D3).

[0119] Insulating spacers (SP) may be interposed between the common source plug (CSP) and the stacked structures (ST). The insulating spacers (SP) may be provided so as to face each other between adjacent stacked structures (ST). For example, the insulating spacers (SP) may be formed of silicon oxide, silicon nitride, silicon oxynitride, or a low-k material having a low dielectric constant.

[0120] A capping insulating film (CAP) may be provided on the stacked structures (ST), the vertical channel structures (VS), and the common source plug (CSP). The capping insulating film (CAP) may cover an upper surface of an uppermost one of the interlayer insulating films (ILD), an upper surface of the dual junction (DJ), and an upper surface of the common source plug (CSP). The capping insulating film (CAP) may be formed of an insulating material different from that of the interlayer insulating films (ILD). A contact plug (CPG) and a bit line contact plug (BLPG) may be provided inside the capping insulating film (CAP). The bit line contact plug (BLPG) may have a shape in which a width in the first direction (D1) and the second direction (D2) increases as it goes in the third direction (D3).

[0121] A bit line (BL) may be provided on a capping insulating film (CAP) and a bit line contact plug (BLPG). The bit line (BL) corresponds to any one of a plurality of bit lines (BL0, BL1, BL2) illustrated in FIG. 1, and may be formed by extending along a second direction (D2) using a conductive material. The conductive material forming the bit line (BL) may be the same material as the conductive material forming each of the aforementioned gate electrodes (EL1, EL2, EL3).

[0122] A bit line (BL) may be electrically connected to vertical channel structures (VS) via a bit line contact plug (BLPG). Here, the connection of the bit line (BL) to the vertical channel structures (VS) may mean that the bit line (BL) is connected to a vertical channel pattern (VCP) via a dual junction (DJ) included in the vertical channel structures (VS).

[0123] As described above, as the rows of three vertical channel structures (VS) penetrate within the stacked structures (ST), the three vertical channel structures (VS) positioned in the same row may have their respective bit line contact plugs (BLPG) misaligned to each other so as to be connected to respective bit lines (BL0, BL1, BL2) positioned on the same plane. For example, as illustrated in FIG. 2, the first vertical channel structure (VS1) may include a bit line contact plug (BLPG) that is biased in a first direction (D1) on the plane so as to be connected to the bit line (BL0), the second vertical channel structure (VS2) may include a bit line contact plug (BLPG) that is positioned at the center on the plane so as to be connected to the bit line (BL1), and the third vertical channel structure (VS3) may include a bit line contact plug (BLPG) that is biased in a direction opposite to the first direction (D1) on the plane so as to be connected to the bit line (BL2).

[0124] The three-dimensional flash memory according to one embodiment is not limited or restricted to the described structure, and may be implemented in various structures, assuming that it includes a vertical channel pattern (VCP), a dual junction (DJ), a data storage pattern (DSP), gate electrodes (EL1, EL2, EL3), and a bit line (BL), according to an implementation example.

[0125] The operating method and manufacturing method for a three-dimensional flash memory having a structure including a dual junction (DJ) as described above are described below.

[0126]

[0127] FIG. 5 is a flow chart illustrating a program operation method of a three-dimensional flash memory according to one embodiment, and FIGS. 6a and 6b are cross-sectional views illustrating the structure of a three-dimensional flash memory to explain the program operation method of a three-dimensional flash memory according to one embodiment.

[0128] The program operation method described below is assumed to be performed by a three-dimensional flash memory having the structure described above with reference to FIGS. 1 to 4a.

[0129] Referring to FIG. 5, in step (S510), the three-dimensional flash memory can apply a voltage to a selected gate electrode (Sel EL) corresponding to a target memory cell that is the target of a program operation among the gate electrodes (EL1, EL2, EL3) (more precisely, the second gate electrode (EL2)).

[0130] Here, the 3D flash memory can apply a voltage for program operation, whether positive or negative, to the selected gate electrode (Sel EL) using the ISPP (Incremental step pulse program) method.

[0131] Accordingly, in step (S520), the 3D flash memory can perform a program operation on a target memory cell by selectively activating either the N+ junction or the P+ junction included in the dual junction (DJ) in response to a voltage applied to the selected gate electrode (Sel EL) to form a channel in the vertical channel pattern (VCP).

[0132] For example, a 3D flash memory is configured to apply a positive program voltage (+V) to the gate electrode (Sel EL) selected in step (S510) as illustrated in FIG. 6a. pgm ), a program operation can be performed by forming an N-type channel in a vertical channel pattern (VCP) through an N+ junction of a dual junction (DJ) in step (S520) (forming an N-type channel extending in the vertical direction so that it is connected to the N+ junction).

[0133] For another example, a 3D flash memory is configured to apply a negative program voltage (-V) to the gate electrode (Sel EL) selected in step (S520) as shown in FIG. 6b. pgm ), a recording operation can be performed by forming a P-type channel in a vertical channel pattern (VCP) through the P+ junction of the dual junction (DJ) in step (S520) (forming the P-type channel extend in the vertical direction so as to be connected to the P+ junction).

[0134] At this time, the 3D flash memory can implement multi-valued operation by adjusting the value of the voltage applied to the selected gate electrode (Sel EL) to various multiple values. In particular, since the 3D flash memory can select the value of the voltage applied to the selected gate electrode (Sel EL) not only within the positive range but also within the negative range, it can implement multi-valued operation of 5 or more bits as illustrated in FIG. 4a, which is more improved than the 4-bit multi-valued operation of the existing 3D NAND flash memory as illustrated in FIG. 4b. That is, the 3D flash memory can perform a program operation of a multi-valued value according to the adjusted positive voltage value and the adjusted negative voltage value by adjusting the values ​​of the positive voltage and the negative voltage applied to the selected gate electrode (Sel EL).

[0135] In addition, in step (S520), the three-dimensional flash memory can perform a memory operation by forming a channel in the vertical channel pattern (VCP) using a dual junction (DJ) formed at the bottom of each of the vertical channel structures (VS). Since using the dual junction (DJ) formed at the bottom of each of the vertical channel structures (VS) is accomplished through the same process as using the dual junction (DJ) formed at the top of each of the vertical channel structures (VS), a detailed description thereof will be omitted.

[0136] At this time, since the dual junction (DJ) is implemented with an asymmetric structure in which the N+ junction has a larger area than the P+ junction, the operation of forming an N-type channel in the vertical channel pattern (VCP) and the operation of forming a P-type channel can be uniformly performed in consideration of the electrical characteristics of each of the N+ junction and the P+ junction. For example, the dual junction (DJ) can be implemented with an asymmetric structure in which the contact area of ​​the N+ junction to the vertical channel pattern (VCP) is larger than the contact area of ​​the P+ junction to the vertical channel pattern (VCP) so that the speed of the operation of forming an N-type channel in the vertical channel pattern (VCP) in response to a positive voltage applied to the selected gate electrode (Sel EL) and the speed of the operation of forming a P-type channel in the vertical channel pattern (VCP) in response to a negative voltage applied to the selected gate electrode (Sel EL) are uniform.

[0137]

[0138] FIG. 7 is a flow chart illustrating a reading operation method of a three-dimensional flash memory according to one embodiment, and FIG. 8 is a diagram illustrating a memory window to explain a reading operation of a three-dimensional flash memory according to one embodiment.

[0139] The reading operation method described below is assumed to be performed by a three-dimensional flash memory having the structure described above with reference to FIGS. 1 to 4a.

[0140] Referring to FIG. 7, in step (S710), the three-dimensional flash memory can apply a positive voltage to a selected gate electrode (Sel EL) corresponding to a target memory cell that is the target of a read operation among the gate electrodes (EL1, EL2, EL3) (more precisely, the second gate electrode (EL2)).

[0141] For example, 3D flash memory uses a positive read voltage (+V) applied to a gate electrode (Sel EL) selected in a way that the voltage remains at a constant value without increasing or decreasing the voltage, rather than an ISPP (Incremental step pulse program) method.read ) can be authorized.

[0142] Accordingly, in step (S720), the 3D flash memory can perform a read operation on the target memory cell by activating only the N+ junction included in the dual junction (DJ) in response to a positive voltage applied to the selected gate electrode (Sel EL) to form an N-type channel in the vertical channel pattern (VCP).

[0143] As described, since the dual junction (DJ) is implemented in an asymmetric structure in which the N+ junction has a larger area than the P+ junction, the memory window used by the N+ junction is wider than the memory window used by the P+ junction, so the 3D flash memory requires a positive read voltage (+V) applied to the selected gate electrode (Sel EL) during a read operation. read ) and the gate electrodes (EL1, EL2, EL3) (more precisely, the second gate electrode (EL2)) are applied to the remaining unselected gate electrodes (Unsel EL) except for the selected gate electrode (Sel EL). pass ) is as shown in Fig. 8.

[0144]

[0145] FIG. 9 is a flow chart illustrating an erase operation method of a three-dimensional flash memory according to one embodiment, and FIGS. 10a and 10b are diagrams illustrating a memory window to explain an erase operation of a three-dimensional flash memory according to one embodiment.

[0146] The erase operation method described below is assumed to be performed by a three-dimensional flash memory having the structure described above with reference to FIGS. 1 to 4a.

[0147] Referring to FIG. 9, in step (S910), the three-dimensional flash memory can move memory cells programmed with a negative voltage to a state programmed with a positive voltage as illustrated in FIG. 10a, as a P-type channel is formed in the vertical channel pattern (VCP) through the P+ junction.

[0148] Here, the 3D flash memory can move memory cells programmed with negative voltage in blocks.

[0149] Accordingly, in step (S920), the 3D flash memory can perform an erase operation on memory cells programmed with a positive voltage and moved memory cells, as illustrated in FIG. 10b.

[0150] More specifically, the 3D flash memory can perform an erase operation in batches on memory cells moved in step (S910) together with memory cells programmed with a positive voltage in advance (memory cells programmed with PGM9 to PGM32).

[0151] Likewise, the erasure operation can be performed on a block-by-block basis.

[0152] In this way, negative program voltage (-V pgm ) and memory cells programmed with a positive program voltage (+V pgm ) is performed in batches through steps (S910 to S920) for memory cells programmed with a negative program voltage (-V pgm ) and memory cells programmed with a positive program voltage (+V pgm ) can improve erase operation power and speed compared to when erase operations are performed individually for each memory cell programmed with the same address.

[0153]

[0154] FIG. 11 is a flow chart illustrating a method for manufacturing a three-dimensional flash memory according to one embodiment.

[0155] The manufacturing method described below is for manufacturing a three-dimensional flash memory having the structure described above with reference to FIGS. 1 to 4, and is assumed to be performed by an automated and mechanized manufacturing system.

[0156] Referring to FIG. 11, in step S1110, the manufacturing system can prepare a semiconductor structure (SEMI-STR). Here, the semiconductor structure (SEM-STR) may include gate electrodes (EL1, EL2, EL3) that are formed to extend horizontally on a substrate (SUB) and are spaced apart vertically and stacked; and vertical channel structures (VS) that extend vertically and penetrate the gate electrodes (EL1, EL2, EL3). That is, the semiconductor structure (SEMI-STR) may include the stacked structures (ST) and vertical channel structures (VS) of the structure described above with reference to FIGS. 1 to 4. However, a dual junction (DJ) is not formed in the vertical channel structures (VS).

[0157] Here, the manufacturing system can prepare a semiconductor structure (SEMI-STR) in which a source region is formed at the bottom of each of the vertical channel structures (VS). Alternatively, the manufacturing system can prepare a semiconductor structure having a source-free structure in which the source region is omitted at the bottom of each of the vertical channel structures (VS).

[0158] As described above, when a dual junction is formed at the bottom of each of the vertical channel structures (VS), in step (S1110), the manufacturing system can prepare a semiconductor structure (SEMI-STR) in which a dual junction is formed at the bottom of each of the vertical channel structures (VS).

[0159] In step (S1120), the manufacturing system can place a first mask pattern (MASK 1) that covers less than half of the upper surface area of ​​each of the vertical channel structures (VS) on the semiconductor structure (SEMI-STR).

[0160] In step (S1130), the manufacturing system can form an N+-doped N+ junction in a remaining area of ​​more than half of the upper surface of each of the vertical channel structures (VS) that is not covered by the first mask pattern (MASK 1) using the first mask pattern (MASK 1).

[0161] In step (S1140), the manufacturing system can place a second mask pattern (MASK 2) that covers more than half of the remaining area of ​​the upper surface of each of the vertical channel structures (VS) on the semiconductor structure (SEMI-STR).

[0162] In step (S1150), the manufacturing system can form a P+-doped P+ junction in an area less than half of the upper surface of each of the vertical channel structures (VS) that is not covered by the second mask pattern (MASK 2) using the second mask pattern (MASK 2).

[0163] Here, the first mask pattern (MASK 1) and the second mask pattern (MASK 2) can be configured and arranged to cover regions of different areas on the upper surface of each of the vertical channel structures (VS) in order to implement an asymmetric structure in which the N+ junction has a larger area than the P+ junction in each of the vertical channel structures (VS).

[0164] In this way, through steps (S1110 to S1150), an asymmetrical dual junction (DJ) including an N+ junction and a P+ junction can be formed in each of the vertical channel structures (VS).

[0165] Although the manufacturing method in which a P+ junction is formed after an N+ junction is formed has been described, the method is not limited thereto and the N+ junction may be formed after the P+ junction is formed. In this case, the P+ junction may be formed before the N+ junction by performing steps (S1120 to S1130) after steps (S1140 to S1150).

[0166]

[0167] FIG. 12 is a perspective view schematically illustrating an electronic system including a three-dimensional flash memory according to one embodiment.

[0168] Referring to FIG. 12, an electronic system (1200) including a three-dimensional flash memory according to embodiments may include a main substrate (1201), a controller (1202) mounted on the main substrate (1201), one or more semiconductor packages (1203), and a DRAM (1204).

[0169] The semiconductor package (1203) and DRAM (1204) can be interconnected with the controller (1202) by wiring patterns (1205) provided on the main substrate (1201).

[0170] The main board (1201) may include a connector (1206) having a plurality of pins that are coupled to an external host. The number and arrangement of the plurality of pins in the connector (1206) may vary depending on the communication interface between the electronic system (1200) and the external host.

[0171] The electronic system (1200) may communicate with an external host according to any one of interfaces, such as, for example, Universal Serial Bus (USB), Peripheral Component Interconnect Express (PCI Express), Serial Advanced Technology Attachment (SATA), and M-Phy for Universal Flash Storage (UFS). The electronic system (1200) may operate by power supplied from an external host, for example, through a connector (1206). The electronic system (1200) may further include a Power Management Integrated Circuit (PMIC) that distributes power supplied from the external host to a controller (1202) and a semiconductor package (1203).

[0172] The controller (1202) can write data to the semiconductor package (1203) or read data from the semiconductor package (1203), and can improve the operating speed of the electronic system (1200).

[0173] The DRAM (1204) may be a buffer memory to mitigate the speed difference between the semiconductor package (1203), which is a data storage space, and an external host. The DRAM (1204) included in the electronic system (1200) may also function as a type of cache memory, and may provide a space for temporarily storing data in a control operation for the semiconductor package (1203). When the electronic system (1200) includes the DRAM (1204), the controller (1202) may further include a DRAM controller for controlling the DRAM (1204) in addition to the NAND controller for controlling the semiconductor package (1203).

[0174] A semiconductor package (1203) may include first and second semiconductor packages (1203a, 1203b) that are spaced apart from each other. The first and second semiconductor packages (1203a, 1203b) may each be a semiconductor package including a plurality of semiconductor chips (1220). Each of the first and second semiconductor packages (1203a, 1203b) may include a package substrate (1210), semiconductor chips (1220) on the package substrate (1210), adhesive layers (1230) disposed on a lower surface of each of the semiconductor chips (1220), connection structures (1240) that electrically connect the semiconductor chips (1220) and the package substrate (1210), and a molding layer (1250) that covers the semiconductor chips (1220) and the connection structures (1240) on the package substrate (1210).

[0175] The package substrate (1210) may be a printed circuit board including package upper pads (1211). Each of the semiconductor chips (1220) may include input / output pads (1221). Each of the semiconductor chips (1220) may include the three-dimensional flash memory described above with reference to FIGS. 1 to 6B. More specifically, each of the semiconductor chips (1220) may include gate stack structures (1222) and memory channel structures (1223). The gate stack structures (1222) may correspond to the stack structures (ST) described above, and the memory channel structures (1223) may correspond to the vertical channel structures (VS) described above.

[0176] The connection structures (1240) may be, for example, bonding wires that electrically connect the input / output pads (1221) and the package upper pads (1211). Accordingly, in each of the first and second semiconductor packages (1203a, 1203b), the semiconductor chips (1220) may be electrically connected to each other in a bonding wire manner, and may be electrically connected to the package upper pads (1211) of the package substrate (1210). According to embodiments, in each of the first and second semiconductor packages (1203a, 1203b), the semiconductor chips (1220) may be electrically connected to each other by a through silicon via instead of the bonding wire-type connection structures (1240).

[0177] Unlike the illustration, the controller (1202) and the semiconductor chips (1220) may be included in a single package. The controller (1202) and the semiconductor chips (1220) may be mounted on a separate interposer substrate different from the main substrate (1201), and the controller (1202) and the semiconductor chips (1220) may be connected to each other by wiring provided on the interposer substrate.

[0178]

[0179] Although the embodiments described above have been described by way of limited examples and drawings, those skilled in the art will appreciate that various modifications and variations can be made based on the above teachings. For example, appropriate results can still be achieved even if the described techniques are performed in a different order than described, and / or components of the described systems, structures, devices, circuits, etc. are combined or combined in a different manner than described, or are replaced or substituted with other components or equivalents.

[0180] Therefore, other implementations, other embodiments, and equivalents to the claims also fall within the scope of the claims described below.

Claims

1. Gate electrodes that are formed horizontally on the substrate and are spaced apart vertically and stacked; and Vertical channel structures formed to extend in the vertical direction while penetrating the gate electrodes, each of the vertical channel structures including a vertical channel pattern and a data storage pattern, and a dual junction, which is an asymmetrical structure having different areas and doped with different types of impurities, is formed on the top of each of the vertical channel structures. 3D flash memory containing .

2. In paragraph 1, The above dual junction is, A three-dimensional flash memory characterized by including an N+ doped N+ junction and a P+ doped P+ junction.

3. In paragraph 2, The above dual junction is, A three-dimensional flash memory characterized in that the N+ junction has an asymmetric structure having a larger area than the P+ junction.

4. In paragraph 2, The above dual junction is, A three-dimensional flash memory characterized in that, in response to a voltage applied to a selected gate electrode corresponding to a target memory cell to be the target of a program operation among the gate electrodes during a program operation, either the N+ junction or the P+ junction is selectively activated to form a channel in the vertical channel pattern.

5. In paragraph 4, The above N+ junction is, A three-dimensional flash memory characterized in that an N-type channel is formed in the vertical channel pattern in response to a positive voltage applied to the selected gate electrode.

6. In paragraph 5, The above positive voltage is, A three-dimensional flash memory characterized in that the ISPP (Incremental step pulse program) method is applied to the selected gate electrode.

7. In paragraph 4, The above P+ junction is, A three-dimensional flash memory characterized in that a P-type channel is formed in the vertical channel pattern in response to a negative voltage applied to the selected gate electrode.

8. In paragraph 7, The above negative voltage is, A three-dimensional flash memory characterized in that the ISPP method is applied to the selected gate electrode.

9. In paragraph 7, The above three-dimensional flash memory, A three-dimensional flash memory characterized in that the first step is to move memory cells programmed with the negative voltage to a state programmed with a positive voltage, and the second step is to perform an erase operation on the memory cells programmed with the positive voltage and the moved memory cells, thereby performing the erase operation on the memory cells programmed with the negative voltage.

10. In paragraph 2, The above dual junction is, A three-dimensional flash memory characterized in that only the N+ junction is activated during a read operation to form an N-type channel in the vertical channel pattern.

11. In paragraph 2, The above dual junction is, A three-dimensional flash memory further comprising an insulating film interposed between the N+ junction and the P+ junction to insulate the N+ junction and the P+ junction from each other.

12. A method for program operation of a three-dimensional flash memory, comprising: gate electrodes formed horizontally on a substrate and spaced apart from each other in a vertical direction; and vertical channel structures formed vertically extending through the gate electrodes, each of the vertical channel structures including a vertical channel pattern and a data storage pattern, and a dual junction, which is an asymmetrical structure having different areas and doped with different types of impurities, is formed on the top of each of the vertical channel structures. A step of applying a voltage to a selected gate electrode corresponding to a target memory cell to be the target of a program operation among the gate electrodes; and A step of performing a program operation on the target memory cell by selectively activating either the N+ junction or the P+ junction included in the dual junction in response to a voltage applied to the selected gate electrode to form a channel in the vertical channel pattern. A method for operating a program of a three-dimensional flash memory including:

13. A method for erasing a three-dimensional flash memory, comprising: gate electrodes formed horizontally on a substrate and vertically spaced apart from each other; and vertical channel structures formed vertically extending through the gate electrodes, each of the vertical channel structures including a vertical channel pattern and a data storage pattern, and a dual junction, which is an asymmetrical structure having different areas and doped with different types of impurities, is formed on the top of each of the vertical channel structures. A step of moving memory cells programmed with a negative voltage to a state programmed with a positive voltage by forming a P-type channel in the vertical channel pattern through a P+ junction included in the dual junction; and A step of performing an erase operation on the memory cells programmed with the positive voltage and the moved memory cells. A method for erasing a three-dimensional flash memory including:

14. A method for reading a three-dimensional flash memory, comprising: gate electrodes formed horizontally on a substrate and spaced apart from each other in a vertical direction; and vertical channel structures formed vertically extending through the gate electrodes, each of the vertical channel structures including a vertical channel pattern and a data storage pattern, and a dual junction, which is an asymmetrical structure having different areas and doped with different types of impurities, is formed on the top of each of the vertical channel structures. A step of applying a positive voltage to a selected gate electrode corresponding to a target memory cell to be subjected to a read operation among the gate electrodes; and A step of performing a read operation on the target memory cell by activating only the N+ junction included in the dual junction in response to a positive voltage applied to the selected gate electrode to form an N-type channel in the vertical channel pattern. A method for reading a three-dimensional flash memory including:

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