Pixel driving circuit and driving method therefor, and display device

Abstract

Provided are a pixel driving circuit and a driving method therefor, and a display device, relating to the technical field of display. In the pixel driving circuit, a transistor, a capacitor and a timing signal are provided, capable of separating an anode of a light-emitting device (EL) and a source electrode of a driving transistor (MD), such that, before a light emission stage, the light-emitting device (EL) does not affect a change in potential of the source electrode of the driving transistor (MD). In addition, a capacitance value is configured to achieve accurate adjustment of a driving current, thereby enriching gray scale display. In addition, the pixel driving circuit can utilize gate driving signals provided by different rows of gate lines, such that the number of required external signal lines is relatively low, thereby significantly reducing the types and the number of external shift registers to which the pixel driving circuit is connected, and facilitating preparation of a narrow-bezel display device.

Description

Pixel driving circuit and driving method thereof, and display device Technical Field

[0001] The present application relates to the field of display technology, and in particular to a pixel driving circuit and a driving method thereof, and a display device. Background Art

[0002] With the continuous development of the display industry, research on display pixel driving circuits has gradually become an important hotspot.

[0003] Light-emitting diodes (LEDs) are an important type of display device. However, as they are current-driven devices, their brightness and duration are affected by the current magnitude and driving time. In practical applications, negative factors such as coupling capacitance in the pixel drive circuit, leakage in each transistor, threshold voltage (Vth) shift of transistors due to non-uniform transistor manufacturing processes within the display panel, threshold voltage drift caused by long-term unidirectional voltage bias of the LED, and IR drop caused by wire resistance in the circuit all affect the stability of the pixel drive circuit, resulting in uneven brightness of the LED and reduced display quality.

[0004] Summary of the Invention

[0005] The embodiments of this application adopt the following technical solutions:

[0006] In a first aspect, an embodiment of the present application provides a pixel driving circuit, wherein the pixel driving circuit in the nth row includes:

[0007] a reset subcircuit electrically connected to the first reset signal line, the first scan signal line, the first node, the second reset signal line, the second scan signal line, and the second node, and configured to reset the voltage of the first node under the control of the first scan signal, and further configured to reset the voltage of the second node under the control of the second scan signal;

[0008] a data writing sub-circuit, electrically connected to the data line, the third scanning signal line and the second node, and configured to write a data signal transmitted by the data line into the second node;

[0009] a driving transistor, wherein a gate of the driving transistor is electrically connected to the second node, a first electrode of the driving transistor is electrically connected to the third node, a second electrode of the driving transistor is electrically connected to the first node, and the driving transistor is configured to generate a driving current under control of a voltage at the second node;

[0010] a first light-emitting control subcircuit electrically connected to the first light-emitting control signal line, the first power line, and the third node, and configured to transmit a first power signal to the driving transistor under the control of the first light-emitting control signal; and a second light-emitting control subcircuit electrically connected to the second light-emitting control signal line, the first node, and the anode of the light-emitting device, respectively, and configured to transmit a driving current to the anode under the control of the second light-emitting control signal.

[0011] a storage sub-circuit, electrically connected to the first node, the second node, and the first power line, and configured to store the voltage of the second node and adjust the voltage of the first node;

[0012] a reset subcircuit, electrically connected to the anode, the fourth scan signal line, and the second power line, and configured to reset the anode under the control of the fourth scan signal;

[0013] Wherein, n is a positive integer, and the first scanning signal line, the third scanning signal line, and the fourth scanning signal line are gate lines in different rows.

[0014] In at least one embodiment of the present application, the pulse widths of the scan signals loaded on the first scan signal, the third scan signal, and the fourth scan signal are the same.

[0015] In at least one embodiment of the present application, the first scanning signal line is the gate line in the n-4th row, the third scanning signal line is the gate line in the nth row, and the fourth scanning signal line is the gate line in the n+2th row;

[0016] The gate lines in the nth row are electrically connected to the pixel driving circuits in the nth row, and the second scanning signal lines in the nth row are electrically connected to the pixel driving circuits in the nth row, where n is greater than 4.

[0017] In at least one embodiment of the present application, the pixel driving circuit in the mth row is a dummy pixel driving circuit, m is a positive integer, m is greater than or equal to 1 and less than or equal to 4, and is equal to n+1 or n+2; the pixel driving circuit in the mth row is electrically connected to the shift register in the mth row.

[0018] In at least one embodiment of the present application, the first reset signal line includes a reference signal line, the second reset signal line includes an initialization signal line, and the absolute value of the difference between the voltage of the reference signal transmitted by the reference signal line and the voltage of the initialization signal transmitted by the initialization signal line is greater than the threshold voltage of the driving transistor.

[0019] In at least one embodiment of the present application, the first reset signal line includes the first power line, and the second reset signal line includes the second power line.

[0020] In at least one embodiment of the present application, the data writing sub-circuit includes a first transistor, the gate of the first transistor is electrically connected to the third scanning signal line, the first electrode of the first transistor is electrically connected to the data line, and the second electrode of the first transistor is electrically connected to the gate of the driving transistor through the second node.

[0021] In at least one embodiment of the present application, a switch transistor is further connected in series between the data line and the first transistor, and the switch transistor is configured to write the data signal into the data line before the first transistor is turned on.

[0022] In at least one embodiment of the present application, the data writing sub-circuit includes a first transistor and a seventh transistor, the gate of the first transistor is electrically connected to the third scanning signal line, the first electrode of the first transistor is electrically connected to the data line, and the second electrode of the first transistor is electrically connected to the first electrode of the seventh transistor; the gate of the seventh transistor is electrically connected to the second scanning signal line, and the second electrode of the seventh transistor is electrically connected to the gate of the driving transistor through the second node.

[0023] In at least one embodiment of the present application, the reset sub-circuit includes a second transistor and a fourth transistor;

[0024] The gate of the second transistor is electrically connected to the second scanning signal line, the first electrode of the second transistor is electrically connected to the first reset signal line, and the second electrode of the second transistor is electrically connected to the gate of the driving transistor through the second node; the gate of the fourth transistor is electrically connected to the first scanning signal line, the first electrode of the fourth transistor is electrically connected to the second reset signal line, and the second electrode of the fourth transistor is electrically connected to the first node.

[0025] In at least one embodiment of the present application, the first light emitting control subcircuit includes a third transistor;

[0026] A gate of the third transistor is electrically connected to the first light emission control signal line, a first electrode of the third transistor is electrically connected to the first power supply line, and a second electrode of the third transistor is electrically connected to the third node.

[0027] In at least one embodiment of the present application, the second light emitting control subcircuit includes a fifth transistor;

[0028] A gate of the fifth transistor is electrically connected to the second light emission control signal line, a first electrode of the fifth transistor is electrically connected to the first node, and a second electrode of the fifth transistor is electrically connected to the anode.

[0029] In at least one embodiment of the present application, the storage subcircuit includes a first capacitor and a second capacitor;

[0030] The first electrode of the first capacitor is electrically connected to the second node, and the second electrode of the first capacitor is electrically connected to the first node; the first electrode of the second capacitor is electrically connected to the first power line, and the second electrode of the second capacitor is electrically connected to the second electrode of the first capacitor through the first node.

[0031] In at least one embodiment of the present application, the reset subcircuit includes a sixth transistor;

[0032] The gate of the sixth transistor is electrically connected to the fourth scan signal line, the first electrode of the sixth transistor is electrically connected to the anode, and the second electrode of the sixth transistor is electrically connected to the second power line and the cathode of the light emitting device respectively.

[0033] In at least one embodiment of the present application, when the data writing sub-circuit includes a first transistor, the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor and the driving transistor are all N-type transistors;

[0034] When the data writing sub-circuit includes a first transistor and a seventh transistor, the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor and the driving transistor are all N-type transistors, and the seventh transistor is a P-type transistor.

[0035] In at least one embodiment of the present application, when the driving transistor is an N-type transistor, the voltage of the reference signal is greater than the voltage of the initialization signal.

[0036] In at least one embodiment of the present application, the absolute value range of the difference between the voltage of the reference signal and the voltage of the initialization signal is 2V to 4V.

[0037] In at least one embodiment of the present application, the rising edge of the pulse signal transmitted by the second scanning signal is consistent with the rising edge of the pulse signal transmitted by the first scanning signal, the falling edge of the pulse signal transmitted by the second scanning signal is consistent with the rising edge of the pulse signal transmitted by the third scanning signal, or the falling edge of the pulse signal transmitted by the second scanning signal is located after the rising edge of the pulse signal transmitted by the third scanning signal.

[0038] In at least one embodiment of the present application, a scanning time of the third scanning signal is greater than a scanning time of the second scanning signal.

[0039] In at least one embodiment of the present application, an overlapping time between the first light emitting control signal and the second scanning signal is greater than an overlapping time between the third scanning signal and the second scanning signal.

[0040] In at least one embodiment of the present application, the first light-emitting control signal includes a first pulse signal and a second pulse signal, the second light-emitting control signal includes a third pulse signal, and the second pulse signal is consistent with the third pulse signal.

[0041] In at least one embodiment of the present application, the capacitance value of the second capacitor is smaller than the capacitance value of the first capacitor.

[0042] In at least one embodiment of the present application, the first transistor, the second transistor, the fourth transistor, and the fifth transistor are all dual-gate transistors; two gates of the same transistor are electrically connected together;

[0043] Alternatively, the first transistor, the second transistor, the fourth transistor and the fifth transistor are all metal oxide transistors.

[0044] In at least one embodiment of the present application, the driving transistor is a dual-gate transistor, and one gate of the driving transistor is electrically connected to the second node, and the other gate of the driving transistor is electrically connected to a signal input terminal with a constant voltage, and the constant voltage is less than the threshold voltage of the driving transistor.

[0045] In at least one embodiment of the present application, the light-emitting device includes an organic light-emitting diode, a micro light-emitting diode, or a sub-millimeter light-emitting diode.

[0046] In a second aspect, an embodiment of the present application provides a display device comprising a pixel driving circuit as described in any one of the first aspects.

[0047] In a third aspect, an embodiment of the present application provides a driving method for driving the pixel driving circuit according to any one of the first aspects, the method comprising:

[0048] In the first stage, a low-level first light control signal is input to the first light control signal line, a low-level second light control signal is input to the second light control signal line, a high-level first scan signal is input to the first scan signal line, a high-level second scan signal is input to the second scan signal line, a low-level third scan signal is input to the third scan signal line, and a low-level fourth scan signal is input to the fourth scan signal line;

[0049] In the second stage, a high-level first light control signal is input to the first light control signal line, a low-level second light control signal is input to the second light control signal line, a low-level first scan signal is input to the first scan signal line, a high-level second scan signal is input to the second scan signal line, a low-level third scan signal is input to the third scan signal line, and a low-level fourth scan signal is input to the fourth scan signal line;

[0050] In the third stage, a low-level first light control signal is input to the first light control signal line, a low-level second light control signal is input to the second light control signal line, a low-level first scan signal is input to the first scan signal line, a low-level second scan signal is input to the second scan signal line, a high-level third scan signal is input to the third scan signal line, and a low-level fourth scan signal is input to the fourth scan signal line;

[0051] In the fourth stage, a low-level first light control signal is input to the first light control signal line, a low-level second light control signal is input to the second light control signal line, a low-level first scan signal is input to the first scan signal line, a low-level second scan signal is input to the second scan signal line, a low-level third scan signal is input to the third scan signal line, and a high-level fourth scan signal is input to the fourth scan signal line;

[0052] In the fifth stage, a high-level first light-emitting control signal is input to the first light-emitting control signal line, a high-level second light-emitting control signal is input to the second light-emitting control signal line, a low-level first scan signal is input to the first scan signal line, a low-level second scan signal is input to the second scan signal line, a low-level third scan signal is input to the third scan signal line, and a low-level fourth scan signal is input to the fourth scan signal line.

[0053] The above description is only an overview of the technical solution of the present application. In order to more clearly understand the technical means of the present application, it can be implemented in accordance with the contents of the specification. In order to make the above and other purposes, features and advantages of the present application more obvious and easy to understand, the specific implementation methods of the present application are listed below. BRIEF DESCRIPTION OF THE DRAWINGS

[0054] In order to more clearly illustrate the technical solutions in the embodiments of the present application or related technologies, the following briefly introduces the drawings required for use in the embodiments or descriptions of the prior art. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0055] 1 and 2 are schematic structural diagrams of two pixel driving circuits provided in embodiments of the present application;

[0056] FIG3 is a timing diagram provided by an embodiment of the present application;

[0057] FIG4 is another timing diagram provided by an embodiment of the present application;

[0058] 5 to 9 are diagrams illustrating device states at different stages of the pixel driving circuit shown in FIG. 1 in the case of the timing diagram shown in FIG. 3 , provided by an embodiment of the present application;

[0059] FIG10 is a schematic structural diagram of a third pixel driving circuit provided in an embodiment of the present application;

[0060] 11 to 15 are diagrams illustrating device states at different stages of the pixel driving circuit shown in FIG. 2 in the case of the timing diagram shown in FIG. 4 , provided by an embodiment of the present application;

[0061] FIG16 is a schematic diagram of electrical connections of pixel driving circuits in different rows;

[0062] FIG17 is a schematic structural diagram of a fourth pixel driving circuit provided in an embodiment of the present application;

[0063] FIG18 is a circuit connection diagram of a display device provided in an embodiment of the present application;

[0064] FIG19 is a circuit connection diagram of another display device provided in an embodiment of the present application. Specific embodiments

[0065] The following will be combined with the drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0066] In the embodiments of the present application, words such as "first", "second", "third", and "fourth" are used to distinguish between identical or similar items with basically the same functions and effects. This is only for the purpose of clearly describing the technical solutions of the embodiments of the present application, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features.

[0067] In the embodiments of the present application, the terms "upper" and "lower" indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present application.

[0068] Throughout the specification, terms such as "one embodiment," "some embodiments," "exemplary embodiment," "example," "specific example," or "some examples" are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of the present application. Schematic representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be included in any one or more embodiments or examples in any suitable manner.

[0069] In the embodiments of the present application, “a plurality of” means two or more, and “at least one” means one or more, unless otherwise clearly defined.

[0070] The features "parallel," "perpendicular," and "identical" used in the embodiments of the present application include features such as "parallel," "perpendicular," and "identical" in the strict sense, as well as "approximately parallel," "approximately perpendicular," and "approximately identical" that include certain tolerances, taking into account the measurement and tolerances associated with the measurement of a particular quantity (e.g., limitations of the measurement system), and represent within an acceptable range of deviation for a particular value determined by a person of ordinary skill in the art. For example, "approximately" can mean within one or more standard deviations, or within 10% or 5% of the stated value.

[0071] Unless the context requires otherwise, throughout the specification and claims, the term "comprising" is to be construed in an open, inclusive sense, that is, meaning "including, but not limited to."

[0072] In the embodiments of this application, "same layer" refers to the relationship between multiple film layers formed from the same material after the same step (e.g., a one-step patterning process). "Same layer" here does not always mean that the thickness of multiple film layers is the same or the height of multiple film layers in the cross-sectional view is the same. Polygons in this specification are not strictly defined and can be approximate triangles, parallelograms, trapezoids, pentagons, or hexagons, etc., and some small deformations due to tolerances may exist.

[0073] In the embodiment of the present application, since the source and drain of the transistor are symmetrical, the source and drain can be interchanged. In the embodiment of the present application, one of the source and drain of the transistor is referred to as the first electrode, and the other of the source and drain is referred to as the second electrode.

[0074] In the embodiments of the present application, the term “electrically connected” may refer to a direct electrical connection between two components, or may refer to an electrical connection between two components via one or more other components.

[0075] This application improves upon the traditional 5T1C (five transistors, one capacitor) source-follower internal compensation pixel driver circuit. In a source-follower compensation pixel circuit, the threshold voltage (Vth) of the driver transistor is written into the source of the driver transistor through compensation, so the stability of the source potential of the driver transistor is very important. Although the traditional 5T1C pixel drive circuit can achieve compensation for the threshold voltage (Vth) of the driving transistor, it still has the following problems: 1. During the driving process, the source of the driving transistor is always directly connected to the anode of the light-emitting diode. This is affected by the unstable anode potential caused by uneven diode manufacturing process and the threshold voltage drift caused by the diode being biased by a unidirectional voltage for a long time. 2. Since the light-emitting diode itself has a capacitance, its size is comparable to the parasitic capacitance of the transistor, it is very easy to form a capacitive coupling circuit. As the potential of some scanning signals in the pixel circuit changes, it interferes with the potential of key nodes in the circuit (such as the gate and source of the driving transistor). 3. After the compensation stage, the transistors and light-emitting diodes in the circuit will inevitably leak, which will have a negative impact on the compensation effect of the threshold voltage of the driving transistor. 4. The brightness change of the light-emitting diode is greatly affected by the change of the operating current. That is, a small change in the operating current will cause a large change in the display brightness. When the pixel driving circuit in the prior art is used in a Micro LED (Micro light emitting diode) or Mini LED (Mini light emitting diode) display device, it is unable to adjust the fineness of the change in the operating current of the light-emitting diode, resulting in low adjustment accuracy of the display grayscale.

[0076] Based on this, the embodiments of the present application provide a pixel driving circuit, a driving method thereof, and a display device. The pixel driving circuit can improve the above-mentioned problems by setting transistors, capacitors, and timing signals. In addition, the pixel driving circuit can utilize gate driving signals provided by gate lines in different rows, so that the number of external signal lines required is small, which significantly reduces the types and number of shift registers external to the pixel driving circuit, and is conducive to the preparation of a narrow-frame display device.

[0077] The pixel driving circuit and its driving method, and the display device provided in the embodiments of the present application are introduced and explained below with reference to the accompanying drawings.

[0078] The display device includes a display area and a peripheral area located around the display area. The display area includes a plurality of sub-pixels. Each sub-pixel is provided with a light-emitting device and a pixel driving circuit for providing a driving signal to the light-emitting device.

[0079] An embodiment of the present application provides a pixel driving circuit, wherein, as shown in FIG1 or FIG2 , the pixel driving circuit of the nth row includes:

[0080] a reset sub-circuit 1 electrically connected to a first reset signal line (e.g., a Ref line), a first scan signal line (e.g., the n-4th gate line), a first node NS, a second reset signal line (e.g., a Vinit line), a second scan signal line (e.g., a VR line), and a second node NG, and configured to reset the voltage of the first node NS under the control of a first scan signal VG(n-4), and further configured to reset the voltage of the second node NG under the control of a second scan signal NR;

[0081] The data writing sub-circuit 2 is electrically connected to the data line Data line, the third scanning signal line (for example, the nth gate line) and the second node NG, and is configured to write the data signal VData transmitted by the data line Data line into the second node NG;

[0082] a driving transistor MD, wherein a gate of the driving transistor MD is electrically connected to the second node NG, a first electrode of the driving transistor MD is electrically connected to the third node A, a second electrode of the driving transistor MD is electrically connected to the first node NS, and the driving transistor MD is configured to generate a driving current under the control of the voltage of the second node NG;

[0083] The first light-emitting control sub-circuit 4 is electrically connected to the first light-emitting control signal line EM1, the first power line VDD, and the third node A, and is configured to transmit the first power signal VDD to the driving transistor MD under the control of the first light-emitting control signal EM1. The second light-emitting control sub-circuit 5 is electrically connected to the second light-emitting control signal line EM2, the first node NS, and the anode of the light-emitting device 8, respectively, and is configured to transmit a driving current to the anode of the light-emitting device 8 under the control of the second light-emitting control signal EM2.

[0084] The storage sub-circuit 6 is electrically connected to the first node NS, the second node NG and the first power line VDD, and is configured to store the voltage of the second node NG and adjust the voltage of the first node NS;

[0085] a reset sub-circuit 7 electrically connected to the anode of the light-emitting device 8, the fourth scan signal line (e.g., the n+2th gate line), and the second power line VDD, and configured to reset the anode of the light-emitting device 8 under the control of the fourth scan signal VG(n+2);

[0086] Wherein, n is a positive integer, and the first scanning signal line, the third scanning signal line, and the fourth scanning signal line are gate lines in different rows.

[0087] There is no limitation here on the specific circuit structures included in the above-mentioned reset sub-circuit 1, data writing sub-circuit 2, first light-emitting control sub-circuit 4, second light-emitting control sub-circuit 5, storage sub-circuit 6 and reset sub-circuit 7. As long as the corresponding functions are met, they are within the scope of protection of the pixel driving circuit provided in the embodiments of the present application.

[0088] The first node NS, the second node NG and the third node A are not actual circuit structures, but are concepts defined for the convenience of describing the circuit structure, and are hereby explained.

[0089] It should be noted that the above “nth gate line” refers to the gate line corresponding to the nth row of sub-pixels, that is, the gate line of the nth row, where one gate line connects one row of sub-pixels. Other similar descriptions have similar meanings and will not be repeated here.

[0090] In an exemplary embodiment, the light-emitting device 8 may be a light-emitting diode (LED), an organic light-emitting diode (OLED), a Micro LED (Micro light Emitting Diode) or a Mini LED (Mini light Emitting Diode, sub-millimeter light-emitting diode).

[0091] When the light-emitting device 8 is an organic light-emitting diode (OLED), the display device can be a silicon-based display device or a glass-based display device. A silicon-based display device means that the drive circuit of the display device is provided on a silicon-based substrate and the drive circuit is manufactured using a MOS process. A glass-based display device means that the drive circuit of the display device is provided on a glass-based substrate and the drive circuit is manufactured using a TFT process.

[0092] In an exemplary embodiment, the above-mentioned reset sub-circuit 1 can be used to reset the voltage of key nodes in the pixel driving circuit (for example, the first node NS electrically connected to the driving transistor MD, and the second node NG electrically connected to the gate of the driving transistor MD) before refreshing (rewriting new signals) each pixel driving circuit in a row of sub-pixels, so as to eliminate the residual signal in the previous frame of the picture and avoid the appearance of afterimages in the next frame of the display picture. When the pixel driving circuit is applied to a display device, the display effect of the display device can be improved.

[0093] In some embodiments, as shown in FIG. 1 , the data writing sub-circuit 2 is electrically connected to the data line Data line, the third scan signal line (eg, the nth gate line), and the second node NG, respectively.

[0094] In other embodiments, as shown in Figure 2, the data writing sub-circuit 2 is electrically connected to the data line Data line, the third scanning signal line (for example, the nth gate line) and the second node NG, respectively, and the data writing sub-circuit 2 is also electrically connected to the second scanning signal line (for example, the VR line).

[0095] The type of the driving transistor MD is not limited here, and transistors can be divided into N-type transistors and P-type transistors.

[0096] Exemplarily, the driving transistor MD may be an N-type transistor or a P-type transistor.

[0097] In addition, the reset sub-circuit 1 , the data writing sub-circuit 2 , the first light-emitting control sub-circuit 4 , the second light-emitting control sub-circuit 5 and the reset sub-circuit 7 also include at least one transistor respectively.

[0098] There is no limitation on the types of transistors in the reset sub-circuit 1 , the data writing sub-circuit 2 , the first light emitting control sub-circuit 4 , the second light emitting control sub-circuit 5 and the reset sub-circuit 7 .

[0099] Each transistor in the present application can be independently selected from an N-type transistor or a P-type transistor; wherein, for an N-type transistor, an operating level state is a high level state, and a non-operating level state is a low level state; for a P-type transistor, an operating level state is a low level state, and a non-operating level state is a high level state. The operating level state refers to a level state that can turn on the first and second electrodes of the transistor, and the non-operating level state refers to a level state that can turn off the first and second electrodes of the transistor.

[0100] In some examples, the driving transistor MD may include one gate, ie, the gate is electrically connected to the second node NG.

[0101] In some other examples, the driving transistor MD may include two gates, which are electrically connected together and then electrically connected to the second node NG.

[0102] In some other examples, the driving transistor MD may include two gates, which are connected to different nodes and have different potentials. For example, one gate of the driving transistor MD is electrically connected to the second node NG, and is used to control the on and off states of the driving transistor MD; the other gate of the driving transistor is electrically connected to a signal input terminal with a constant voltage, and is used to stabilize the threshold voltage of the driving transistor MD and improve the driving stability of the driving transistor MD, wherein the voltage provided by the signal input terminal with a constant voltage cannot interfere with the on and off states of the driving transistor MD, and therefore the absolute value of the constant voltage is set to be smaller than the absolute value of the threshold voltage of the driving transistor MD.

[0103] In an exemplary embodiment, the first power line VDD line is a positive power signal line, and the second power line VSS line is a negative power signal line. Both the first power line VDD line and the second power line VSS line can continuously provide signals with constant voltages. The voltage of the first power signal VDD provided by the first power line VDD line is greater than the voltage of the second power signal VSS provided by the second power line VSS line.

[0104] In some embodiments, the second power signal line VSS may be electrically connected to the ground line GND.

[0105] In an exemplary embodiment, as shown in FIG1 or FIG2 , the first light-emission control subcircuit 4 is configured to electrically connect the first power supply line VDD to the first electrode of the drive transistor MD, and the second light-emission control subcircuit 5 is configured to electrically connect the second electrode of the drive transistor MD to the anode of the light-emitting device 8, and the cathode of the light-emitting device 8 to the second power supply line VSS. When the first light-emission control subcircuit 4, the drive transistor MD, and the second light-emission control subcircuit 5 are simultaneously turned on, a path is formed between the positive power supply signal line, the drive transistor MD, the light-emitting device 8, and the negative power supply signal line, enabling the light-emitting device 8 to emit light.

[0106] In an exemplary embodiment, the first light emitting control signal EM1 transmitted in the first light emitting control signal line EM1 may be provided by an EM GOA (also referred to as an EOA), or the first light emitting control signal EM1 transmitted in the first light emitting control signal line EM1 may be provided by a driver chip.

[0107] In an exemplary embodiment, the second emission control signal EM2 transmitted in the second emission control signal line EM2 may be provided by an EOA (also referred to as EM GOA), or the second emission control signal EM2 transmitted in the second emission control signal line EM2 may be provided by a driver chip. The EOA refers to an emission control shift register on array (ECR), which is configured to provide emission control signals to pixel driver circuits of sub-pixels in display area AA to control the emission of the sub-pixels in display area AA.

[0108] As shown in FIG16 , each row of sub-pixels corresponds to a first light-emitting control signal line EM1, and each row of sub-pixels corresponds to a second light-emitting control signal line EM2; that is, sub-pixels in the same row are electrically connected to the same first light-emitting control signal line EM1, and sub-pixels in the same row are electrically connected to the same second light-emitting control signal line EM2.

[0109] In an exemplary embodiment, as shown in FIG16 , the first scanning signal line, the third scanning signal line, and the fourth scanning signal line are gate lines of different rows; that is, for the pixel driving circuit of the nth row, it is not only electrically connected to the gate line of the nth row (nth line), but can also be electrically connected to other gate lines except the gate line of the nth row, so that the gate lines of different rows provide it with scanning signals with different timings, avoiding the arrangement of other types of signal lines in areas outside the display area (the pixel driving circuit is arranged in the display area) to provide driving signals to the pixel driving circuit, thereby reducing the number of required external signal lines, significantly reducing the types and number of shift registers external to the pixel driving circuit, and facilitating the preparation of a display device with a narrow frame.

[0110] In at least one embodiment of the present application, as shown in FIG3 , the pulse widths of the scan signals loaded on the first scan signal VG(n-4), the third scan signal VG(n), and the fourth scan signal VG(n+2) are the same.

[0111] It should be noted that the pulse widths of the first scanning signal VG(n-4), the third scanning signal VG(n) and the fourth scanning signal VG(n+2) drawn in Figure 4 are only schematic illustrations. In actual applications, the pulse widths of the scanning signals loaded on the first scanning signal VG(n-4), the third scanning signal VG(n) and the fourth scanning signal VG(n+2) shown in Figure 4 are the same.

[0112] The first scanning signal VG(n-4), the third scanning signal VG(n) and the fourth scanning signal VG(n+2) are all generated by the shift register (GOA).

[0113] In at least one embodiment of the present application, as shown in FIG16 , the first scan signal line is the gate line of the n-4th row, the gate line of the n-4th row is electrically connected to the n-4th stage shift register GOA(n-4), and is used to transmit the VG(n-4) signal; the third scan signal line is the gate line of the nth row, the gate line of the nth row is electrically connected to the nth stage shift register GOA(n), and is used to transmit the VG(n) signal; the fourth scan signal line is the gate line of the n+2th row, the gate line of the n+2th row is electrically connected to the n+2th stage shift register GOA(n+2), and is used to transmit the VG(n+2) signal;

[0114] The gate line of the nth row is electrically connected to the pixel driving circuit of the nth row (in Figure 16, Pixel(n) is used to represent the sub-pixel of the nth row), and the second scanning signal line VR line of the nth row is electrically connected to the pixel driving circuit of the nth row, where n is greater than 4.

[0115] In at least one embodiment of the present application, the pixel driving circuit in the mth row is a dummy pixel driving circuit (a pixel driving circuit set in the Dummy pixel row), m is a positive integer, m is greater than or equal to 1 and less than or equal to 4, and is equal to n+1 or n+2; the pixel driving circuit in the mth row is electrically connected to the shift register in the mth row.

[0116] It should be noted that the Dummy pixel row (virtual pixel row) can transmit scanning signals but does not actually display light.

[0117] In an embodiment of the present application, for the pixel driving circuit in the nth row, when n=5, the first scanning signal line is the gate line in the 1st row, the third scanning signal line is the gate line in the 5th row, and the fourth scanning signal line is the gate line in the 7th row; in order to enable the pixel driving circuit in the 5th row to be driven normally, it is necessary to set four rows of dummy pixel driving rows and four rows of shift registers before the pixel driving circuit in this row to normally provide scanning signals to the pixel driving circuits after the 5th row. In addition, for the pixel driving circuit in the last row (i.e., the nth row) actually used for display, since the fourth scanning signal provided by the gate line in the n+2th row is required, it is necessary to set at least two rows of dummy pixel driving rows and at least two rows of shift registers after the nth row of pixels to provide scanning signals to the pixel driving circuits before the nth row.

[0118] As shown in Figure 16, each row of sub-pixels corresponds to a first light-emitting control signal line EM1, each row of sub-pixels corresponds to a second light-emitting control signal line EM2, and each row of sub-pixels corresponds to a second scanning signal line VR; that is, sub-pixels in the same row are electrically connected to the same first light-emitting control signal line EM1, sub-pixels in the same row are electrically connected to the same second light-emitting control signal line EM2, and sub-pixels in the same row are electrically connected to the same second scanning signal line VR.

[0119] In an exemplary embodiment, the VR signal can be generated and transmitted to the pixel driving circuits of each row using either a driver chip or a shift register. The EM input module inputs EM1 and EM2 signals to each row. The EM1 signal is relatively complex, so this specification uses the example of the EM1 signal being generated and provided by a driver chip IC. The EM2 signal has a relatively simple timing sequence, so it can be generated and transmitted to the pixel driving circuits of each row using either a driver chip or a shift register (EOA).

[0120] In an embodiment of the present application, the pixel driving circuit can utilize gate driving signals provided by gate lines of different rows, so that the number of external signal lines required by the pixel driving circuit is smaller, significantly reducing the types and number of shift registers external to the pixel driving circuit, which is conducive to the preparation of a narrow-frame display device.

[0121] In at least one embodiment of the present application, the first reset signal line includes a reference signal line Ref line, the second reset signal line includes an initialization signal line Vinit line, and the absolute value of the difference between the voltage Vref of the reference signal transmitted by the reference signal line Ref line and the voltage Vinit of the initialization signal transmitted by the initialization signal line Vinit line is greater than the threshold voltage (Vth) of the driving transistor.

[0122] In an embodiment of the present application, in the signal reset stage, the reset sub-circuit 1 resets the voltage of the first node NS under the control of the first scan signal VG(n-4), and resets the voltage of the second node NG under the control of the second scan signal VR. By setting the absolute value of the difference between the voltage Vref of the reference signal transmitted by the reference signal line Ref line and the voltage Vinit of the initialization signal transmitted by the initialization signal line Vinit line to be greater than the threshold voltage (Vth) of the driving transistor, it is possible to ensure that the driving transistor MD is in the on state. In combination with Figures 1 and 2, the electrodes electrically connected to the first capacitor C1 and the second capacitor C2 in the storage sub-circuit 6 can also be pre-charged to prevent the threshold compensation from being unable to be completed due to the large capacitance to be charged in the compensation stage of the pixel driving circuit, thereby improving the subsequent compensation effect on the threshold voltage of the driving transistor in the compensation stage.

[0123] In an exemplary embodiment, when the driving transistor MD is an N-type transistor, the voltage Vref of the reference signal transmitted by the reference signal line Ref line is greater than the voltage Vinit of the initialization signal transmitted by the initialization signal line Vinit line.

[0124] In an exemplary embodiment, when the driving transistor MD is a P-type transistor, the voltage Vref of the reference signal transmitted by the reference signal line Ref line is lower than the voltage Vinit of the initialization signal transmitted by the initialization signal line Vinit line.

[0125] In an exemplary embodiment, the reference signal transmitted by the reference signal line Ref line is a signal with a constant voltage, and the initialization signal transmitted by the initialization signal line Vinit line is another signal with a constant voltage.

[0126] In at least one embodiment of the present application, as shown in Figure 17, the first reset signal line includes a first power line VDD line (that is, the first electrode of the second transistor M2 is electrically connected to the first power line VDD line), and the second reset signal line includes a second power line VSS line (the first electrode of the fourth transistor M4 is electrically connected to the second power line VSS line).

[0127] In an embodiment of the present application, by setting the first reset signal line to include a first power line VDD line and the second reset signal line to include a second power line VSS line, the number of external signal lines of the pixel driving circuit can be further reduced, the circuit and wiring design in the display device can be simplified, the design space can be saved, the difficulty of the manufacturing process can be reduced, and it is conducive to application in display devices with narrow bezels.

[0128] In at least one embodiment of the present application, as shown in Figure 1, the data writing sub-circuit 2 includes a first transistor M1, the gate of the first transistor M1 is electrically connected to the third scanning signal line (the n-th row gate line), the first electrode of the first transistor M1 is electrically connected to the data line Data line, the second electrode of the first transistor M1 is electrically connected to the gate of the driving transistor MD through the second node NG, and the first transistor M1 is used to respond to the third scanning signal and transmit and write the data signal to the gate of the driving transistor MD.

[0129] In at least one embodiment of the present application, a switching transistor SW is further arranged in series between the data line Data line and the first transistor M1 of the pixel driving circuit (the black rectangle in Figure 18 or Figure 19 represents the pixel driving circuit), and the switching transistor SW is configured to write the data signal Vdata into the data line Data line before the first transistor M1 is turned on.

[0130] For example, as shown in FIG18 , in order to improve the aperture ratio, the switching transistor SW is arranged at the junction of the display area and the binding area of ​​the display device, wherein a Source driver IC is arranged in the binding area, and all data lines Data are electrically connected to the Source driver IC through the switching transistor SW. The Source driver IC is used to provide data signals to the display area of ​​the display device.

[0131] For example, as shown in FIG19 , for a column of pixel driving circuits, a switching transistor SW can be shared between the first transistors M1 of multiple pixel driving circuits and the data line Data. Taking the connection structure shown in FIG19 as an example, four pixel driving circuits can be electrically connected to the data line Data through the same switching transistor SW. Before the first transistors M1 of each of the four pixel driving circuits are turned on, the switching transistor SW can be controlled so that the data signal Vdata is pre-written to the position of the first electrode (or second electrode) of the switching transistor SW, thereby shortening the transmission path and transmission time of the data signal.

[0132] It should be noted that, here, there is no limitation on the number of switch transistors SW electrically connected to the same data line Data, and the number can be specifically designed according to the design space and the transmission time requirement of the data signal.

[0133] As shown in FIG19 , when the same data line Data is connected to a plurality of switching transistors SW, at least some of the switching transistors SW may be disposed in the display area AA, for example, in a non-opening area of ​​the display area AA.

[0134] The opening area refers to the area in the display area AA that actually displays light; the non-opening area refers to the area in the display area AA other than the opening area, which is usually used for wiring and setting circuit structures.

[0135] In an embodiment of the present application, a switching transistor SW is further provided in series between the data line Data line and the first transistor M1 of the pixel driving circuit (the black rectangle in FIG18 represents the pixel driving circuit). Therefore, before the first transistor M1 is turned on, the data signal Vdata can be written into the data line Data line in advance by turning on the switching transistor SW. After the first transistor M1 is turned on, the data signal Vdata can be quickly written into the gate of the driving transistor MD, thereby shortening the time for the data signal Vdata to be transmitted to the pixel driving circuit, improving the refresh speed and response speed of the pixel driving circuit, and improving the display effect of the display device.

[0136] In at least one embodiment of the present application, as shown in Figure 2, the data writing sub-circuit 2 includes a first transistor M1 and a seventh transistor M7, the gate of the first transistor M1 is electrically connected to the third scanning signal line (the n-th row gate line), the first electrode of the first transistor M1 is electrically connected to the data line Data line, and the second electrode of the first transistor M1 is electrically connected to the first electrode of the seventh transistor M7; the gate of the seventh transistor M7 is electrically connected to the second scanning signal line VR line, and the second electrode of the seventh transistor M7 is electrically connected to the gate of the driving transistor MD through the second node NG.

[0137] In an exemplary embodiment, the first transistor M1 and the seventh transistor M7 are of opposite types. For example, the first transistor M1 is an N-type transistor and the seventh transistor M7 is a P-type transistor. For another example, the first transistor M1 is a P-type transistor and the seventh transistor M7 is an N-type transistor. The timing diagrams provided in the embodiments of the present application and the subsequent description are all described using the example that the first transistor M1 is an N-type transistor and the seventh transistor M7 is a P-type transistor.

[0138] In an exemplary embodiment, the first transistor M1 and the seventh transistor M7 are not turned on at the same time in a partial time period, and the first transistor M1 and the seventh transistor M7 are turned on at the same time in a partial time period.

[0139] In an exemplary embodiment, the first transistor M1 can be controlled to be turned on and the seventh transistor M7 can be turned off, so that the data signal Vdata transmitted in the data line Data is written in advance to the position between the first transistor M1 and the seventh transistor M7 as shown in FIG. 2 ; when the first transistor M1 and the seventh transistor M7 are turned on at the same time, the data signal Vdata can be quickly written into the gate of the driving transistor MD through the seventh transistor M7, thereby shortening the transmission time of the data signal Vdata, improving the refresh speed and response speed of the pixel driving circuit, and improving the display effect of the display device.

[0140] In at least one embodiment of the present application, as shown in FIG1 or FIG2 , the reset sub-circuit 1 includes a second transistor M2 and a fourth transistor M4;

[0141] The gate of the second transistor M2 is electrically connected to the second scan signal line (for example, the VR line), the first electrode of the second transistor M2 is electrically connected to the first reset signal line (for example, the Ref line), and the second electrode of the second transistor M2 is electrically connected to the gate of the driving transistor MD through the second node NG; the gate of the fourth transistor M4 is electrically connected to the first scan signal line (for example, the n-4th gate line), the first electrode of the fourth transistor M4 is electrically connected to the second reset signal line (for example, the Vinit line), and the second electrode of the fourth transistor M4 is electrically connected to the first node NS.

[0142] In an exemplary embodiment, the second transistor M2 is controlled by a second scan signal VR transmitted by a second scan signal line (e.g., a VR line), and in response to the second scan signal VR, resets the voltage of a second node NG electrically connected to the gate of the driving transistor MD via a reset signal (e.g., a reference signal Vref) transmitted by a first reset signal line (e.g., a Ref line).

[0143] In an exemplary embodiment, the fourth transistor is controlled by a first scan signal (e.g., a VG(n-4) signal) transmitted by a first scan signal line (e.g., the n-4th gate line), and in response to the first scan signal, a second reset signal (e.g., a Vinit signal) transmitted by a second reset signal line (e.g., a Vinit line) resets the first node NS electrically connected to the second electrode of the driving transistor MD.

[0144] In an embodiment of the present application, before refreshing (rewriting new signals) each pixel driving circuit in a row of sub-pixels, the voltage of key nodes in the pixel driving circuit (for example, the first node NS electrically connected to the source of the driving transistor MD and the second node NG electrically connected to the gate of the driving transistor MD) can be reset through the second transistor M2 and the fourth transistor M4 to eliminate the residual signal in the previous frame of the picture and avoid the appearance of afterimages in the next frame of the display picture. When the pixel driving circuit is applied to a display device, the display effect of the display device can be improved.

[0145] In at least one embodiment of the present application, as shown in FIG1 or FIG2 , the first light emitting control subcircuit 4 includes a third transistor M3;

[0146] A gate of the third transistor M3 is electrically connected to the first light emission control signal line EM1 , a first electrode of the third transistor M3 is electrically connected to the first power line VDD , and a second electrode of the third transistor M3 is electrically connected to the third node A .

[0147] In an exemplary embodiment, the third transistor M3 is used to transmit the first power signal VDD of the first power line VDD line to the first electrode (e.g., source) of the driving transistor MD through the third node A under the control of the first light-emitting control signal EM1 transmitted by the first light-emitting control signal line EM1.

[0148] In at least one embodiment of the present application, as shown in FIG1 or FIG2 , the second light emitting control subcircuit 5 includes a fifth transistor M5 ;

[0149] A gate of the fifth transistor M5 is electrically connected to the second light emitting control signal line EM2 , a first electrode of the fifth transistor M5 is electrically connected to the first node NS, and a second electrode of the fifth transistor M5 is electrically connected to the anode of the light emitting device 8 .

[0150] In an exemplary embodiment, when the first power signal VDD transmitted by the first power line VDD is transmitted to the first electrode (for example, the source) of the driving transistor MD through the third node A, the fifth transistor M5 is used to transmit the driving current generated by the driving transistor MD to the anode of the light-emitting device 8 under the control of the second light-emitting control signal EM2 transmitted by the second light-emitting control signal line EM2.

[0151] In at least one embodiment of the present application, as shown in FIG1 or FIG2 , the storage sub-circuit 6 includes a first capacitor C1 and a second capacitor C2 ;

[0152] The first electrode of the first capacitor C1 is electrically connected to the second node NG, and the second electrode of the first capacitor C1 is electrically connected to the first node NS; the first electrode of the second capacitor C1 is electrically connected to the first power line VDD line, and the second electrode of the second capacitor C2 is electrically connected to the second electrode of the first capacitor C1 through the first node NS.

[0153] There is no limitation on the capacitance values ​​of the first capacitor C1 and the second capacitor C2 .

[0154] In some embodiments, the driving current of the driving transistor MD may be adjusted by adjusting the capacitance ratio of the first capacitor C1 to the second capacitor C2 .

[0155] In other embodiments, in order to have a smaller impact on the voltage of the gate of the driving transistor MD when the voltage value of the data signal Vdata changes greatly, thereby having a smaller impact on the driving current of the driving transistor MD (that is, the change amplitude of the driving current of the driving transistor MD is smaller), the capacitance value of the first capacitor C1 can be set to be greater than the capacitance value of the second capacitor C2.

[0156] In an embodiment of the present application, the voltage of the second node NG can be stabilized by setting the first capacitor C1, and the voltage of the first node NS can be stabilized by setting the second capacitor C2. By adjusting the size ratio of the capacitance values ​​of the first capacitor C1 and the second capacitor C2, a data signal Vdata with a large change can be brought about a driving current with a small change, thereby achieving more precise control of the driving current, achieving more precise adjustment and display of the grayscale of the display device, and improving the display effect of the display device.

[0157] In at least one embodiment of the present application, as shown in FIG1 or FIG2 , the reset subcircuit 7 includes a sixth transistor M6;

[0158] The gate of the sixth transistor M6 is electrically connected to the fourth scan signal line (for example, the n+2th gate line), the first electrode of the sixth transistor M6 is electrically connected to the anode of the light-emitting device 8, and the second electrode of the sixth transistor M6 is electrically connected to the second power line VSS line and the cathode of the light-emitting device 8 respectively.

[0159] In an exemplary embodiment, the sixth transistor M6 is used to transfer the second power signal VSS transmitted by the second power line VSS line to the anode of the light-emitting device 8 under the control of the fourth scan signal transmitted by the fourth scan signal line (for example, the n+2th gate line), thereby resetting the anode of the light-emitting device 8 through the second power line VSS line before the light-emitting device 8 emits light.

[0160] Exemplarily, the second power line VSS line may be electrically connected to the ground terminal GND.

[0161] In at least one embodiment of the present application, as shown in FIG1 , when the data writing sub-circuit 2 includes a first transistor M1 , the first transistor M1 , the second transistor M2 , the third transistor M3 , the fourth transistor M4 , the fifth transistor M5 , the sixth transistor M6 and the driving transistor MD are all N-type transistors;

[0162] As shown in FIG2 , when the data writing sub-circuit 2 includes a first transistor M1 and a seventh transistor M7, the first transistor M1, the second transistor M2, the third transistor M3, the fourth transistor M4, the fifth transistor M5, the sixth transistor M6 and the driving transistor MD are all N-type transistors, and the seventh transistor M7 is a P-type transistor.

[0163] The first transistor M1 and the seventh transistor M7 are of opposite types, are turned on at different times in some time periods, and are turned on at the same time in some time periods.

[0164] In at least one embodiment of the present application, when the driving transistor is an N-type transistor, the voltage Vref of the reference signal is greater than the voltage Vinit of the initialization signal.

[0165] In at least one embodiment of the present application, the absolute value range of the difference between the voltage Vref of the reference signal and the voltage Vinit of the initialization signal is 2V to 4V.

[0166] Exemplarily, the absolute value of the difference between the voltage Vref of the reference signal and the voltage Vinit of the initialization signal is 2.3V, 2.5V, 2.8V, 3V, 3.3V, 3.5V or 3.8V.

[0167] In an embodiment of the present application, in the signal reset stage, by setting the absolute value range of the difference between the voltage Vref of the reference signal and the voltage Vinit of the initialization signal to 2V~4V, it is possible to ensure that the driving transistor MD is in the on state. In combination with Figures 1 and 2, the electrodes electrically connected to the first capacitor C1 and the second capacitor C2 in the storage sub-circuit 6 can also be pre-charged to prevent the threshold compensation from being unable to be completed during the compensation stage of the pixel driving circuit due to the large capacitance to be charged, thereby improving the subsequent compensation effect on the threshold voltage of the driving transistor in the compensation stage.

[0168] In at least one embodiment of the present application, as shown in FIG3 and FIG4 , the rising edge of the pulse signal transmitted by the second scanning signal VR is consistent with the rising edge of the pulse signal transmitted by the first scanning signal VG(n-4);

[0169] In some embodiments, as shown in FIG3 , the falling edge of the pulse signal transmitted by the second scanning signal VR coincides with the rising edge of the pulse signal transmitted by the third scanning signal VG(n);

[0170] Alternatively, in some other embodiments, as shown in FIG. 4 , the falling edge of the pulse signal transmitted by the second scanning signal VR is located after the rising edge of the pulse signal transmitted by the third scanning signal VG(n).

[0171] In an embodiment of the present application, in combination with Figure 3 and Figure 1, when the first transistor M1, the second transistor M2, the third transistor M3, the fourth transistor M4, the fifth transistor M5, the sixth transistor M6 and the driving transistor MD are all N-type transistors, and the seventh transistor M7 is a P-type transistor, the second scanning signal VR and the third scanning signal VG(n) are not at the high level at the same time. Therefore, the second transistor M2 and the first transistor M1 are not turned on at the same time. When the third scanning signal VG(n) is at a high level, the data signal Vdata is written into the pixel driving circuit.

[0172] In an embodiment of the present application, as shown in conjunction with FIG4 and FIG2 , when the first transistor M1, the second transistor M2, the third transistor M3, the fourth transistor M4, the fifth transistor M5, the sixth transistor M6, and the driving transistor MD are all N-type transistors and the seventh transistor M7 is a P-type transistor, the third scan signal VG(n) is input in advance (at the position marked by the dashed rectangle in FIG4 ) before the second scan signal VR becomes low, causing the first transistor M1 to turn on in advance, thereby controlling the data signal Vdata to be written in advance to the node between the first transistor M1 and the seventh transistor M7. During the period when the second scan signal VR is low and the third scan signal VG(n) is high, the first transistor M1 and the seventh transistor M7 are simultaneously turned on, thereby causing the data signal Vdata to be transmitted from the first electrode of the seventh transistor M7 through the second node NG to the gate of the driving transistor MD, thereby implementing the writing of the data signal. In this way, the time it takes for the data signal Vdata to be transmitted to the pixel driving circuit is shortened, the refresh speed and response speed of the pixel driving circuit are increased, and the display effect of the display device is improved.

[0173] In at least one embodiment of the present application, as shown in FIG3 and FIG4 , the scanning time of the third scanning signal VG(n) is greater than the scanning time of the second scanning signal VR. It can be understood that the pulse width of the third scanning signal VG(n) is greater than the pulse width of the second scanning signal VR.

[0174] It should be noted that, in the timing diagrams shown in FIG3 and FIG4 , the lengths of the signal lines are merely schematic representations of different time periods and do not represent the lengths of the time periods.

[0175] In an embodiment of the present application, by setting the scanning time of the third scanning signal VG(n) to be greater than the scanning time of the second scanning signal VR, the writing time of the data signal Vdata can be greatly extended, as shown in Figure 1 or Figure 2, thereby extending the charging time of the first electrode of the first capacitor C1 (the electrode electrically connected to the second node NG), which is subsequently more conducive to the stability of the voltage of the first capacitor C1 to the second node NG (and the gate of the driving transistor MD), thereby improving the driving stability of the pixel driving circuit.

[0176] In at least one embodiment of the present application, as shown in FIG. 4 , the overlapping time between the first light emitting control signal EM1 and the second scan signal VR is greater than the overlapping time between the third scan signal VG(n) and the second scan signal VR.

[0177] In the embodiment of the present application, as shown in combination with Figures 2 and 4, when the first light-emitting control signal EM1 and the second scan signal VR are both at a high level, the second transistor M2 and the third transistor M3 are turned on. At this time, the voltage of the second node NG is the voltage of the reference signal Vref, the driving transistor MD is turned on, the voltage of the first node NS is the voltage of the initialization signal Vinit, the first power line VDD is connected to the first node NS, and the first power line VDD charges the second node NS. When the potential of the first node NS becomes Vref-Vth (where Vth is the threshold voltage of the driving TFT MD), the driving transistor MD is turned off. At this time, the potential of the first node NS is Vref-Vth. Since this process changes slowly and the potential of the second node NG is always pulled by the voltage of the reference signal Vref, the potential of the second node NG remains at Vref, thereby completing the reading of the threshold voltage Vth of the driving transistor MD.

[0178] In an embodiment of the present application, by setting the overlapping time of the first light-emitting control signal EM1 and the second scanning signal VR to be greater than the overlapping time of the third scanning signal VG(n) and the second scanning signal VR, the time for the first power line VDD line to charge the second node NS can be effectively extended, thereby more accurately reading the threshold voltage Vth of the driving transistor MD, so as to facilitate subsequent more accurate compensation of the threshold voltage Vth of the driving transistor MD.

[0179] In at least one embodiment of the present application, as shown in FIG3 or FIG4 , the first light-emitting control signal EM1 includes a first pulse signal and a second pulse signal, the second light-emitting control signal EM2 includes a third pulse signal, and the second pulse signal and the third pulse signal are consistent.

[0180] In at least one embodiment of the present application, the capacitance of the second capacitor C2 is smaller than the capacitance of the first capacitor C1 .

[0181] In the embodiment of the present application, by setting the capacitance value of the second capacitor C2 to be smaller than the capacitance value of the first capacitor C1, it is possible to achieve a small change in the driving current caused by a large change in the data signal Vdata. When using a low-resolution Source IC in the prior art, more precise control of the driving current can be achieved, and more precise adjustment and display of the grayscale displayed by the display device can be achieved, thereby improving the display effect of the display device.

[0182] In at least one embodiment of the present application, for the pixel driving circuit shown in Figure 1, the first transistor M1, the second transistor M2, the fourth transistor M4, and the fifth transistor M5 can be set to be dual-gate transistors; the two gates of the same transistor are electrically connected together; or, the first transistor M1, the second transistor M2, the fourth transistor M4, and the fifth transistor M5 can be metal oxide transistors.

[0183] In at least one embodiment of the present application, for the pixel driving circuit shown in Figure 2, the seventh transistor M7, the second transistor M2, the fourth transistor M4, and the fifth transistor M5 can be set to be dual-gate transistors; the two gates of the same transistor are electrically connected together; or, the seventh transistor M7, the second transistor M2, the fourth transistor M4, and the fifth transistor M5 can be metal oxide transistors.

[0184] In the embodiments of the present application, during the operation of the pixel circuit, leakage will inevitably occur in the transistors and light-emitting devices, thereby affecting the compensation and light-emitting effects. Therefore, the transistors around the key nodes (for example, the transistors around the NS and NG nodes) can be designed with a dual-gate design. As shown in Figure 10, the first transistor M1, the second transistor M2, the fourth transistor M4 and the fifth transistor M5 are all dual-gate transistors (or) metal oxide transistors, which can significantly reduce the leakage of the transistors around the key nodes, thereby improving the display effect of the display device.

[0185] In at least one embodiment of the present application, the driving transistor MD is a dual-gate transistor, and one gate of the driving transistor is electrically connected to the second node NG, and the other gate of the driving transistor MD is electrically connected to the signal input terminal with a constant voltage, and the constant voltage is less than the threshold voltage of the driving transistor MD.

[0186] In an embodiment of the present application, one gate of the driving transistor MD is electrically connected to the second node NG, for controlling the on and off states of the driving transistor MD; the other gate of the driving transistor is electrically connected to a signal input terminal with a constant voltage, for stabilizing the threshold voltage of the driving transistor MD and improving the driving stability of the driving transistor MD, wherein the voltage provided by the signal input terminal with a constant voltage cannot interfere with the on and off states of the driving transistor MD, and therefore the absolute value of the constant voltage is set to be smaller than the absolute value of the threshold voltage of the driving transistor MD.

[0187] In at least one embodiment of the present application, the light-emitting device 8 includes an organic light-emitting diode (OLED), a Micro LED (Micro light Emitting Diode) or a Mini LED (Mini light Emitting Diode, sub-millimeter light-emitting diode).

[0188] An embodiment of the present application provides a display device, comprising a pixel driving circuit as described in any one of the above.

[0189] The above-mentioned display device can be an organic light-emitting diode (OLED) display device, a Micro LED (Micro light Emitting Diode) display device or a Mini LED (Mini light Emitting Diode) display device.

[0190] The display device may include any device or product with a display function. For example, the display device may be a smart phone, a mobile phone, an e-book reader, a desktop computer (PC), a laptop PC, a netbook PC, a personal digital assistant (PDA), a portable multimedia player (PMP), a digital audio player, a mobile medical device, a camera, a wearable device (such as a head-mounted device, electronic clothing, an electronic bracelet, an electronic necklace, an electronic accessory, an electronic tattoo, or a smart watch), a television, etc.

[0191] The display device provided in the embodiment of the present application includes the pixel driving circuit described above. Due to the setting of transistors, capacitors and timing signals in the pixel driving circuit, the anode of the light-emitting device 8 and the second electrode (e.g., source) of the driving transistor MD can be separated. Therefore, before the light-emitting stage, the light-emitting device 8 itself (threshold voltage drift, coupling of its own capacitance in the circuit) will not affect the potential change of the source level of the driving transistor MD. At the same time, a second capacitor C2 is set to ensure the stability of the NS node potential and the compensation effect. In addition, by setting the size of the capacitance ratio of C2 and C1, the pixel driving circuit can achieve a richer grayscale display when driving Micro LED and Mini LED type light-emitting devices; finally, the pixel driving circuit can use the gate drive signals provided by the gate lines of different rows, so that the number of external signal lines required is small, which significantly reduces the types and number of shift registers external to the pixel driving circuit, which is conducive to the preparation of a narrow-frame display device.

[0192] An embodiment of the present application provides a driving method for driving a pixel driving circuit as described above. The driving method includes:

[0193] S801. In a first stage, for example, stage T1 shown in FIG. 3 or 4 , a low-level first light-emitting control signal EM1 is input to the first light-emitting control signal line, a low-level second light-emitting control signal EM2 is input to the second light-emitting control signal line, a high-level first scan signal VG(n-4) is input to the first scan signal line, a high-level second scan signal VR is input to the second scan signal line, a low-level third scan signal VG(n) is input to the third scan signal line, and a low-level fourth scan signal VG(n+2) is input to the fourth scan signal line.

[0194] S802. In the second stage, for example, stage T2 shown in FIG. 3 or 4 , a high-level first light-emitting control signal EM1 is input to the first light-emitting control signal line, a low-level second light-emitting control signal EM2 is input to the second light-emitting control signal line, a low-level first scan signal VG(n-4) is input to the first scan signal line, a high-level second scan signal VR is input to the second scan signal line, a low-level third scan signal VG(n) is input to the third scan signal line, and a low-level fourth scan signal VG(n+2) is input to the fourth scan signal line.

[0195] S803. In a third stage, for example, stage T3 shown in FIG. 3 or FIG. 4 , a low-level first light-emitting control signal EM1 is input to the first light-emitting control signal line, a low-level second light-emitting control signal EM2 is input to the second light-emitting control signal line, a low-level first scan signal VG(n-4) is input to the first scan signal line, a low-level second scan signal VR is input to the second scan signal line, a high-level third scan signal VG(n) is input to the third scan signal line, and a low-level fourth scan signal VG(n+2) is input to the fourth scan signal line.

[0196] S804. In a fourth stage, for example, stage T4 shown in FIG. 3 or FIG. 4 , a low-level first light-emitting control signal EM1 is input to the first light-emitting control signal line, a low-level second light-emitting control signal EM2 is input to the second light-emitting control signal line, a low-level first scan signal VG(n-4) is input to the first scan signal line, a low-level second scan signal VR is input to the second scan signal line, a low-level third scan signal VG(n) is input to the third scan signal line, and a high-level fourth scan signal VG(n+2) is input to the fourth scan signal line.

[0197] S805. In the fifth stage, for example, the T5 stage shown in FIG3 or FIG4, a high-level first light-emitting control signal EM1 is input to the first light-emitting control signal line, a high-level second light-emitting control signal EM2 is input to the second light-emitting control signal line, a low-level first scanning signal VG(n-4) is input to the first scanning signal line, a low-level second scanning signal VR is input to the second scanning signal line, a low-level third scanning signal VG(n) is input to the third scanning signal line, and a low-level fourth scanning signal VG(n+2) is input to the fourth scanning signal line.

[0198] The driving method of the pixel driving circuit provided in the embodiment of the present application can improve the threshold voltage drift problem of the driving transistor during the driving process of the circuit. Since the anode of the light-emitting device 8 and the second electrode (e.g., source electrode) of the driving transistor MD in the pixel driving circuit are separated (not directly electrically connected), the light-emitting device 8 itself (threshold voltage drift, coupling of its own capacitance in the circuit) will not affect the potential change of the source level of the driving transistor MD before the light-emitting stage. At the same time, a second capacitor C2 is provided to ensure the stability of the NS node potential and the compensation effect. In addition, by setting the size of the capacitance ratio of C2 and C1, the pixel driving circuit can achieve a richer grayscale display when driving Micro LED and Mini LED type light-emitting devices. Finally, the pixel driving circuit can use the gate drive signals provided by the gate lines of different rows, so that the number of external signal lines required is small, significantly reducing the types and number of shift registers external to the pixel driving circuit, which is conducive to the preparation of narrow-frame display devices.

[0199] Taking the circuit diagram shown in FIG1 as an example, and taking all transistors as N-type transistors as an example, the driving principle and driving process of the driving circuit are specifically explained; FIG3 provides the timing corresponding to the circuit diagram in FIG1; FIG5 to FIG9 respectively provide the circuit states of the circuit diagram in FIG1 at different stages of the timing shown in FIG3. In FIG5 to FIG9, the transistor cut-off is marked with “×”.

[0200] In the first stage (reset stage), for example, stage T1 shown in FIG3 , a low-level first light-emitting control signal EM1 is input to the first light-emitting control signal line, a low-level second light-emitting control signal EM2 is input to the second light-emitting control signal line, a high-level first scanning signal VG(n-4) is input to the first scanning signal line, a high-level second scanning signal VR is input to the second scanning signal line, a low-level third scanning signal VG(n) is input to the third scanning signal line, and a low-level fourth scanning signal VG(n+2) is input to the fourth scanning signal line;

[0201] At this time, in combination with Figures 3 and 5, the second transistor M2 and the fourth transistor M4 are turned on, the potential of the first node NS is Vinit, and the potential of the second node NG is Vref. Since Vref and Vinit are both high-level potentials with constant voltage, the driving transistor MD is turned on. In this way, the potential of the first node NS and the second node NG is reset. In addition, the electrodes (plates) connected to the first capacitor C1 and the second capacitor C2 are pre-charged to prevent the inability to complete the extraction and compensation of the threshold voltage in the subsequent threshold voltage extraction stage due to the large capacitance to be charged.

[0202] In the second stage (threshold voltage extraction stage), for example, stage T2 shown in FIG3 , a high-level first light-emitting control signal EM1 is input to the first light-emitting control signal line, a low-level second light-emitting control signal EM2 is input to the second light-emitting control signal line, a low-level first scanning signal VG(n-4) is input to the first scanning signal line, a high-level second scanning signal VR is input to the second scanning signal line, a low-level third scanning signal VG(n) is input to the third scanning signal line, and a low-level fourth scanning signal VG(n+2) is input to the fourth scanning signal line;

[0203] At this time, in combination with Figures 3 and 6, the second transistor M2 and the third transistor M3 are turned on, the first capacitor C1 can keep the potential of the second node NG still at Vref, the driving transistor MD remains on, and a path is formed between the first power line VDD line and the first node NS. The first power line VDD line charges the first node NS. When the potential of the first node NS becomes Vref-Vth, the driving transistor MD is turned off. Since this process changes slowly and the potential of the second node NG is always pulled by Vref, the potential of the second node NG remains at Vref. At this time, Vgs=Vref-(Vref-Vth)=Vth, thereby completing the extraction of the threshold voltage Vth of the driving transistor MD.

[0204] In the third stage (data writing and compensation stage), for example, stage T3 shown in FIG3 , a low-level first light-emitting control signal EM1 is input to the first light-emitting control signal line, a low-level second light-emitting control signal EM2 is input to the second light-emitting control signal line, a low-level first scanning signal VG(n-4) is input to the first scanning signal line, a low-level second scanning signal VR is input to the second scanning signal line, a high-level third scanning signal VG(n) is input to the third scanning signal line, and a low-level fourth scanning signal VG(n+2) is input to the fourth scanning signal line;

[0205] At this time, as shown in Figures 3 and 7 , the first transistor M1 is turned on, the potential of the second node NG is Vdata, and the driving transistor MD is turned on. Since the potential of the second node NG changes from Vref in the previous stage to Vdata, due to the coupling effect of capacitance, the potential of the first node NS changes to (Vdata-Vref)*C1 / (C1+C2)+Vref-Vth, where C1 and C2 represent the capacitance values ​​of the first capacitor and the second capacitor. In addition, since the fifth transistor M5 is turned off at this time, the potential of the first node NS is not affected by the potential of the anode of the light-emitting device 8 and the IR Rise of VSS in the second and third stages.

[0206] In the fourth stage (reset stage), for example, stage T4 shown in FIG3 , a low-level first light-emitting control signal EM1 is input to the first light-emitting control signal line, a low-level second light-emitting control signal EM2 is input to the second light-emitting control signal line, a low-level first scan signal VG(n-4) is input to the first scan signal line, a low-level second scan signal VR is input to the second scan signal line, a low-level third scan signal VG(n) is input to the third scan signal line, and a high-level fourth scan signal VG(n+2) is input to the fourth scan signal line.

[0207] At this time, as shown in FIG3 and FIG8 , the sixth transistor M6 is turned on. Furthermore, under the action of the first capacitor C1, the potential of the second node NG is maintained at Vdata, and the driving transistor MD is turned on. The potential of the second power line VSS is written to the anode of the light-emitting device 8 (labeled EM in FIG8 ) via the sixth transistor M6, thereby resetting the anode potential. This prevents uneven anode potential of the light-emitting device due to factors such as process technology from negatively impacting the operating current of the pixel during the light-emitting phase. Furthermore, since the fifth transistor M5 is turned off at this time, resetting the anode potential of the light-emitting device does not affect the potential of the first node NS, which has already been compensated, thereby ensuring the compensation effect of the threshold voltage Vth of the driving transistor.

[0208] S805. In the fifth stage, for example, the T5 stage shown in FIG3 , a high-level first light-emitting control signal EM1 is input to the first light-emitting control signal line, a high-level second light-emitting control signal EM2 is input to the second light-emitting control signal line, a low-level first scanning signal VG(n-4) is input to the first scanning signal line, a low-level second scanning signal VR is input to the second scanning signal line, a low-level third scanning signal VG(n) is input to the third scanning signal line, and a low-level fourth scanning signal VG(n+2) is input to the fourth scanning signal line.

[0209] At this time, in combination with Figures 3 and 9, the third transistor M3 and the fifth transistor M5 are turned on. Due to the action of the first capacitor C1, the potential of the second node NG is maintained at Vdata, the driving transistor MD is turned on, and a path is formed between the first power line VDD line and the second power line VSS line, and the light-emitting device 8 (EL) emits light.

[0210] Since Vg=Vdata, Vs=[C1(Vdata-Vref) / (C1+C2)+Vref-Vth]; Vgs=Vdata-[C1(Vdata-Vref) / (C1+C2)+Vref-Vth]; Ids=k(Vgs-Vth) 2 =k[C2(Vdata-Vref) / (C1+C2)] 2 ;

[0211] Among them, k is a device parameter, which is related to the carrier mobility, channel width-to-length ratio and self-capacitance of the driving transistor. It can be seen that in the light-emitting stage, the magnitude of the driving current Ids is independent of the threshold voltage Vth, the voltage of the first power signal VDD and the voltage of the second power signal VSS. Therefore, the pixel driving circuit can avoid different potential changes in different sub-pixels due to the uneven threshold voltage Vth of the driving transistor MD and the different resistance differences between the first power line VDD and the second power line VSS, thereby avoiding the problem of uneven display images in different areas of the display device and improving the display effect.

[0212] Taking the circuit diagram shown in Figure 2 as an example, taking the seventh transistor as a P-type transistor and the other transistors as N-type transistors as an example, the driving principle and driving process of the driving circuit are specifically explained; Figure 4 provides the timing corresponding to the circuit diagram in Figure 2; Figures 11 to 15 respectively provide the circuit states of the circuit diagram in Figure 2 at different stages of the timing shown in Figure 4. In Figures 11 to 15, the transistor cut-off is marked with "×".

[0213] It should be noted that in the first stage T1, the second stage T2, the fourth stage T4 and the fifth stage T5, the driving principle and driving process of the circuit diagram shown in Figure 2 are the same as the driving principle and driving process of the circuit diagram shown in Figure 1 in the previous text. Only the driving process of the third stage T3 is specifically introduced and explained below.

[0214] In the third stage (data writing and compensation stage), for example, stage T3 shown in FIG4 , a low-level first light-emitting control signal EM1 is input to the first light-emitting control signal line, a low-level second light-emitting control signal EM2 is input to the second light-emitting control signal line, a low-level first scanning signal VG(n-4) is input to the first scanning signal line, a low-level second scanning signal VR is input to the second scanning signal line, a high-level third scanning signal VG(n) is input to the third scanning signal line, and a low-level fourth scanning signal VG(n+2) is input to the fourth scanning signal line;

[0215] At this point, as shown in Figures 4 and 13 , the first transistor M1 and the seventh transistor are simultaneously turned on, the potential of the second node NG is Vdata, and the driving transistor MD is turned on. Since the potential of the second node NG changes from Vref in the previous stage to Vdata, due to capacitive coupling, the potential of the first node NS changes to (Vdata-Vref)*C1 / (C1+C2)+Vref-Vth, where C1 and C2 represent the capacitance values ​​of the first and second capacitors. Furthermore, since the fifth transistor M5 is turned off at this point, during the second and third stages, the potential of the first node NS is not affected by the potential of the anode of the light-emitting device 8 or the IR Rise of VSS.

[0216] It should be noted that, since a high-level third scan signal VG(n) is input in advance to the third scan signal line in the third stage, for example, before the T3 stage shown in FIG4 , the first transistor M1 is already turned on before the seventh transistor M7 is turned on, thereby writing the data signal Vdata transmitted by the data line Data line in advance to a position between the first transistor M1 and the seventh transistor M7. When the first transistor M1 and the seventh transistor M7 are turned on at the same time, the data signal Vdata can be quickly written into the gate of the drive transistor MD through the seventh transistor M7, thereby shortening the transmission time of the data signal Vdata, improving the refresh speed and response speed of the pixel drive circuit, and improving the display effect of the display device.

[0217] The above description is merely a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this application should be included in the scope of protection of this application. Therefore, the scope of protection of this application should be based on the scope of protection of the claims.

Claims

1. A pixel driving circuit, wherein: The pixel driving circuit in the nth row includes: a reset subcircuit, electrically connected to the first reset signal line, the first scan signal line, the first node, the second reset signal line, the second scan signal line and the second node, configured to reset the voltage of the first node under the control of the first scan signal, and also configured to reset the voltage of the second node under the control of the second scan signal; a data writing sub-circuit, electrically connected to the data line, the third scanning signal line and the second node, and configured to write the data signal transmitted by the data line into the second node; a driving transistor, wherein a gate of the driving transistor is electrically connected to the second node, a first electrode of the driving transistor is electrically connected to a third node, a second electrode of the driving transistor is electrically connected to the first node, and the driving transistor is configured to generate a driving current under the control of a voltage of the second node; a first light-emitting control subcircuit electrically connected to the first light-emitting control signal line, the first power line and the third node, and configured to transmit the first power signal to the driving transistor under the control of the first light-emitting control signal; a second light-emitting control subcircuit electrically connected to the second light-emitting control signal line, the first node and the anode of the light-emitting device, respectively, and configured to transmit the driving current to the anode under the control of the second light-emitting control signal; a storage subcircuit, electrically connected to the first node, the second node and the first power line, and configured to store the voltage of the second node and adjust the voltage of the first node; a reset subcircuit, electrically connected to the anode, the fourth scan signal line and the second power line, and configured to reset the anode under the control of the fourth scan signal; Wherein, n is a positive integer, and the first scanning signal line, the third scanning signal line, and the fourth scanning signal line are gate lines of different rows.

2. The pixel driving circuit according to claim 1, wherein: The pulse widths of the scan signals loaded on the first scan signal, the third scan signal, and the fourth scan signal are the same.

3. The pixel driving circuit according to claim 2, wherein: The first scanning signal line is the gate line in the n-4th row, the third scanning signal line is the gate line in the nth row, and the fourth scanning signal line is the gate line in the n+2th row; The gate lines in the nth row are electrically connected to the pixel driving circuits in the nth row, and the second scanning signal lines in the nth row are electrically connected to the pixel driving circuits in the nth row, where n is greater than 4.

4. The pixel driving circuit according to claim 3, wherein: The pixel driving circuit in the mth row is a dummy pixel driving circuit, where m is a positive integer, which is greater than or equal to 1 and less than or equal to 4, and is equal to n+1 or n+2; The pixel driving circuit in the mth row is electrically connected to the shift register in the mth row.

5. The pixel driving circuit according to claim 1, wherein: The first reset signal line includes a reference signal line, the second reset signal line includes an initialization signal line, and an absolute value of a difference between a voltage of a reference signal transmitted by the reference signal line and a voltage of an initialization signal transmitted by the initialization signal line is greater than a threshold voltage of the driving transistor.

6. The pixel driving circuit according to claim 1, wherein: The first reset signal line includes the first power line, and the second reset signal line includes the second power line.

7. The pixel driving circuit according to claim 3, wherein: The data writing subcircuit includes a first transistor, a gate of the first transistor is electrically connected to the third scanning signal line, a first electrode of the first transistor is electrically connected to the data line, and a second electrode of the first transistor is electrically connected to the gate of the driving transistor through the second node.

8. The pixel driving circuit according to claim 7, wherein: A switch transistor is further connected in series between the data line and the first transistor, and the switch transistor is configured to write the data signal into the data line before the first transistor is turned on.

9. The pixel driving circuit according to claim 3, wherein: The data writing subcircuit includes a first transistor and a seventh transistor, the gate of the first transistor is electrically connected to the third scanning signal line, the first electrode of the first transistor is electrically connected to the data line, and the second electrode of the first transistor is electrically connected to the first electrode of the seventh transistor; the gate of the seventh transistor is electrically connected to the second scanning signal line, and the second electrode of the seventh transistor is electrically connected to the gate of the driving transistor through the second node.

10. The pixel driving circuit according to claim 8 or 9, wherein: The reset subcircuit includes a second transistor and a fourth transistor; The gate of the second transistor is electrically connected to the second scan signal line, the first electrode of the second transistor is electrically connected to the first reset signal line, and the second electrode of the second transistor is electrically connected to the first reset signal line. The second node is electrically connected to the gate of the driving transistor; the gate of the fourth transistor is electrically connected to the first scanning signal line, the first electrode of the fourth transistor is electrically connected to the second reset signal line, and the second electrode of the fourth transistor is electrically connected to the first node.

11. The pixel driving circuit according to claim 10, wherein: The first light emission control subcircuit includes a third transistor; A gate of the third transistor is electrically connected to the first light emission control signal line, a first electrode of the third transistor is electrically connected to the first power supply line, and a second electrode of the third transistor is electrically connected to the third node.

12. The pixel driving circuit according to claim 11, wherein: The second light emitting control subcircuit includes a fifth transistor; A gate of the fifth transistor is electrically connected to the second light emission control signal line, a first electrode of the fifth transistor is electrically connected to the first node, and a second electrode of the fifth transistor is electrically connected to the anode.

13. The pixel driving circuit according to claim 12, wherein: The storage subcircuit includes a first capacitor and a second capacitor; A first electrode of the first capacitor is electrically connected to the second node, and a second electrode of the first capacitor is electrically connected to the first node; A first electrode of the second capacitor is electrically connected to the first power line, and a second electrode of the second capacitor is electrically connected to the second electrode of the first capacitor via the first node.

14. The pixel driving circuit according to claim 13, wherein: The reset subcircuit includes a sixth transistor; The gate of the sixth transistor is electrically connected to the fourth scan signal line, the first electrode of the sixth transistor is electrically connected to the anode, and the second electrode of the sixth transistor is electrically connected to the second power line and the cathode of the light emitting device respectively.

15. The pixel driving circuit according to claim 14, wherein: In the case where the data writing sub-circuit includes a first transistor, the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor and the driving transistor are all N-type transistors; In the case where the data writing sub-circuit includes the first transistor and the seventh transistor, The first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor and the driving transistor are all N-type transistors, and the seventh transistor is a P-type transistor.

16. The pixel driving circuit according to claim 5, wherein: In the case where the driving transistor is an N-type transistor, the voltage of the reference signal is greater than the voltage of the initialization signal.

17. The pixel driving circuit according to claim 16, wherein: The absolute value range of the difference between the voltage of the reference signal and the voltage of the initialization signal is 2V to 4V.

18. The pixel driving circuit according to claim 2, wherein: The rising edge of the pulse signal transmitted by the second scanning signal is consistent with the rising edge of the pulse signal transmitted by the first scanning signal, the falling edge of the pulse signal transmitted by the second scanning signal is consistent with the rising edge of the pulse signal transmitted by the third scanning signal, or the falling edge of the pulse signal transmitted by the second scanning signal is located after the rising edge of the pulse signal transmitted by the third scanning signal.

19. The pixel driving circuit according to claim 18, wherein: A scanning time of the third scanning signal is greater than a scanning time of the second scanning signal.

20. The pixel driving circuit according to claim 18, wherein: An overlapping time between the first light emitting control signal and the second scanning signal is greater than an overlapping time between the third scanning signal and the second scanning signal.

21. The pixel driving circuit according to claim 1, wherein: The first light-emitting control signal includes a first pulse signal and a second pulse signal, the second light-emitting control signal includes a third pulse signal, and the second pulse signal is consistent with the third pulse signal.

22. The pixel driving circuit according to claim 13, wherein: The capacitance value of the second capacitor is smaller than the capacitance value of the first capacitor.

23. The pixel driving circuit according to claim 14, wherein: The first transistor, the second transistor, the fourth transistor and the fifth transistor are all dual-gate transistors; two gates of the same transistor are electrically connected together; Alternatively, the first transistor, the second transistor, the fourth transistor and the fifth transistor are all metal oxide transistors.

24. The pixel driving circuit according to claim 1, wherein: The driving transistor is a dual-gate transistor, one gate of the driving transistor is electrically connected to the second node, and the other gate of the driving transistor is electrically connected to a signal input terminal with a constant voltage, and the constant voltage is less than a threshold voltage of the driving transistor.

25. The pixel driving circuit according to claim 1, wherein: The light emitting device includes an organic light emitting diode, a micro light emitting diode or a sub-millimeter light emitting diode.

26. A display device, wherein: Comprising the pixel driving circuit as described in any one of claims 1-25.

27. A driving method, wherein: Applied to driving a pixel driving circuit as claimed in any one of claims 1 to 25, the method comprising: In the first stage, a low-level first light control signal is input to the first light control signal line, a low-level second light control signal is input to the second light control signal line, a high-level first scan signal is input to the first scan signal line, a high-level second scan signal is input to the second scan signal line, a low-level third scan signal is input to the third scan signal line, and a low-level fourth scan signal is input to the fourth scan signal line; In the second stage, a high-level first light control signal is input to the first light control signal line, a low-level second light control signal is input to the second light control signal line, a low-level first scan signal is input to the first scan signal line, a high-level second scan signal is input to the second scan signal line, a low-level third scan signal is input to the third scan signal line, and a low-level fourth scan signal is input to the fourth scan signal line; In the third stage, a low-level first light control signal is input to the first light control signal line, a low-level second light control signal is input to the second light control signal line, a low-level first scan signal is input to the first scan signal line, a low-level second scan signal is input to the second scan signal line, a high-level third scan signal is input to the third scan signal line, and a low-level fourth scan signal is input to the fourth scan signal line; In the fourth stage, a low-level first light control signal is input to the first light control signal line, a low-level second light control signal is input to the second light control signal line, a low-level first scan signal is input to the first scan signal line, a low-level second scan signal is input to the second scan signal line, and a low-level first scan signal is input to the third scan signal line. a third scanning signal, inputting a fourth scanning signal of a high level to the fourth scanning signal line; In the fifth stage, a first light-emitting control signal of a high level is input to the first light-emitting control signal line, a second light-emitting control signal of a high level is input to the second light-emitting control signal line, a first scan signal of a low level is input to the first scan signal line, a second scan signal of a low level is input to the second scan signal line, a third scan signal of a low level is input to the third scan signal line, and a fourth scan signal of a low level is input to the fourth scan signal line.

Images