Display control method and apparatus, vehicle-mounted display system, and storage medium

Abstract

A display control method and apparatus (1201), a vehicle-mounted display system, and a storage medium. The display control method comprises: dividing a received video frame in a current frame period into m sub-frames (101), wherein the m sub-frames are in one-to-one correspondence with m display areas on a display apparatus (1202), and m is a natural number greater than 1; on the basis of a preset rule, selecting one sub-frame from among the m sub-frames as a target sub-frame (102); writing m-1 sub-frames except the target sub-frame among the m sub-frames into a cache (103); on the basis of the time sequence of each sub-frame among the m sub-frames, reading, from the cache, m-1 sub-frames between the target sub-frame in the current frame period and a target sub-frame in a previous frame period (104); generating a display frame on the basis of the target sub-frame in the current frame period and the m-1 sub-frames read from the cache (105); and sending the display frame to the display apparatus (1202) for display (106).

Description

Display control method and device, vehicle-mounted display system, and storage medium Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a display control method and device, a vehicle-mounted display system, and a storage medium. Background Art

[0002] In-vehicle display devices can display in different zones. For example, they can be divided into multiple display areas, such as instrument panel, navigation area, and entertainment area. Each video frame provided by the SOC (System on Chip) includes multiple sections corresponding to the multiple display areas. By displaying this video frame on the in-vehicle display device, the corresponding content can be displayed in each display area.

[0003] Summary of the Invention

[0004] According to a first aspect of an embodiment of the present disclosure, a display control method is provided, comprising: dividing a received video frame in a current frame period into m subframes, wherein the m subframes correspond one-to-one to m display areas on a display device, and m is a natural number greater than 1; selecting a subframe from the m subframes as a target subframe according to a preset rule; writing m-1 subframes of the m subframes except the target subframe into a cache; reading m-1 subframes between the target subframe in the current frame period and the target subframe in the previous frame period from the cache according to the timing of each subframe in the m subframes; generating a display frame according to the target subframe of the current frame period and the m-1 subframes read from the cache; and sending the display frame to the display device for display.

[0005] In some embodiments, the cache includes m-1 sub-caches, the m-1 sub-caches correspond one-to-one to the m-1 sub-frames, and writing the m-1 sub-frames into the cache includes: using the current write address to write each sub-frame in the m-1 sub-frames into the corresponding sub-caches, wherein the current write address is determined by the current frame period.

[0006] In some embodiments, reading m-1 subframes from the cache includes: reading m-1 subframes in the current frame period from the cache when the target subframe in the current frame period is the latest subframe in the current frame period.

[0007] In some embodiments, reading m-1 subframes in the current frame period from the cache includes: reading a subframe from each of the m-1 sub-caches using a current read address, wherein the current read address is the same as the current write address.

[0008] In some embodiments, generating the display frame includes: combining m-1 subframes in the current frame period and a target subframe in the current frame period to generate the display frame.

[0009] In some embodiments, reading m-1 subframes from the cache includes: when the target subframe in the current frame period is the earliest subframe in the current frame period, reading the latest m-1 subframes in the previous frame period from the cache.

[0010] In some embodiments, reading the m-1 subframes in the previous frame period from the cache includes: using a current read address to read a subframe from each of the m-1 sub-caches, wherein the current read address is the current write address minus 1.

[0011] In some embodiments, generating the display frame includes: combining the target subframe in the current frame period and the latest m-1 subframes in the previous frame period to generate the display frame.

[0012] In some embodiments, reading m-1 subframes from the cache includes: in the current frame period, if there are k subframes whose timing is earlier than the timing of the target subframe in the current frame period, reading the k subframes in the current frame period from the cache, and reading the latest mk-1 subframes in the previous frame period from the cache, where 1≤k <m-1。

[0013] In some embodiments, reading k subframes from the cache includes: using a first read address to read k subframes from k sub-caches corresponding to the k sub-frames in the m-1 sub-caches, wherein the first read address is the same as the current write address; reading mk-1 subframes from the cache includes: using a second read address to read mk-1 subframes from mk-1 sub-caches corresponding to the mk-1 sub-frames in the m-1 sub-caches, wherein the second read address is the current write address minus 1.

[0014] In some embodiments, generating the display frame includes combining the k subframes in the current frame period, the target subframe in the current frame period, and the mk-1 subframes in the previous frame period to generate the display frame.

[0015] In some embodiments, among the m subframes, the target subframe is a subframe with a maximum delay weight.

[0016] In some embodiments, among the m subframes, the target subframe is a subframe specified by a received instruction.

[0017] In some embodiments, sending the display frame to the display device includes: dividing the display frame into a first display subframe and a second display subframe; sending the first display subframe to the display device through a first display interface; and sending the second display subframe to the display device through a second display interface.

[0018] According to a second aspect of an embodiment of the present disclosure, a display control device is provided, comprising: a memory configured to store instructions; a processor coupled to the memory, the processor being configured to execute a method as described in any of the above embodiments based on the instructions stored in the memory.

[0019] According to a third aspect of an embodiment of the present disclosure, a display control device is provided, comprising: a receiving circuit configured to receive a video frame within a current frame period; a segmentation circuit configured to divide the video frame within the current frame period into m subframes, wherein the m subframes correspond one-to-one to m display areas on a display device, and m is a natural number greater than 1; a selection circuit configured to select a subframe from the m subframes as a target subframe according to a preset rule, send the target subframe from the m subframes to a rearrangement circuit, and write m-1 subframes of the m subframes except the target subframe into a cache through a write control circuit; the rearrangement circuit configured to read m-1 subframes between the target subframe in the current frame period and the target subframe in the previous frame period from the cache through a read control circuit according to the timing of each subframe in the m subframes, and generate a display frame based on the target subframe of the current frame period and the m-1 subframes read from the cache; and a sending circuit configured to send the display frame to the display device for display.

[0020] In some embodiments, the cache includes m-1 sub-caches, and the m-1 sub-caches correspond one-to-one to the m-1 sub-frames; the write control circuit is configured to use a current write address to write each sub-frame of the m-1 sub-frames into the corresponding sub-caches, wherein the current write address is determined by the current frame period.

[0021] In some embodiments, the rearrangement circuit is configured to read m-1 subframes in the current frame period from the cache through the read control circuit when the target subframe in the current frame period is the latest subframe in the current frame period.

[0022] In some embodiments, the read control circuit is configured to read a sub-frame from each of the m-1 sub-buffers using a current read address, wherein the current read address is the same as the current write address.

[0023] In some embodiments, the rearrangement circuit is configured to combine m-1 subframes in the current frame period and a target subframe in the current frame period to generate the display frame.

[0024] In some embodiments, the rearrangement circuit is configured to read the latest m-1 subframes in the previous frame period from the cache through the read control circuit when the target subframe in the current frame period is the earliest subframe in the current frame period.

[0025] In some embodiments, the read control circuit is configured to read a subframe from each of the m-1 sub-buffers using a current read address, wherein the current read address is the current write address minus 1.

[0026] In some embodiments, the rearrangement circuit is configured to combine the target subframe in the current frame period and the latest m-1 subframes in timing in the previous frame period to generate the display frame.

[0027] In some embodiments, the rearrangement circuit is configured to read the k subframes in the current frame period from the cache through the read control circuit when the timing of k subframes in the current frame period is earlier than the timing of the target subframe in the current frame period, and read the latest mk-1 subframes in the previous frame period from the cache, where 1≤k <m-1。

[0028] In some embodiments, the read control circuit is configured to use a first read address to read k subframes from k sub-caches corresponding to the k sub-frames in the m-1 sub-caches, wherein the first read address is the same as the current write address; and is also configured to use a second read address to read mk-1 subframes from mk-1 sub-caches corresponding to the mk-1 sub-frames in the m-1 sub-caches, wherein the second read address is the current write address minus 1.

[0029] In some embodiments, the rearrangement circuit is configured to combine the k subframes in the current frame period, the target subframe in the current frame period, and the mk-1 subframes in the previous frame period to generate the display frame.

[0030] According to a fourth aspect of an embodiment of the present disclosure, there is provided a vehicle-mounted display system, comprising: a display control device as described in any of the above embodiments; and a display device configured to receive a display frame sent by the display control device and present the display frame.

[0031] According to a fifth aspect of an embodiment of the present disclosure, a non-volatile computer-readable storage medium is provided, wherein the non-volatile computer-readable storage medium stores computer instructions, and when the instructions are executed by a processor, the method described in any of the above embodiments is implemented.

[0032] Other features and advantages of the present disclosure will become apparent from the following detailed description of exemplary embodiments of the present disclosure with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the present disclosure and, together with the description, serve to explain the principles of the present disclosure.

[0034] The present disclosure can be more clearly understood from the following detailed description with reference to the accompanying drawings, in which:

[0035] FIG1 is a schematic flow chart of a display control method according to an embodiment of the present disclosure;

[0036] 2A-2C are schematic diagrams of subframe timing according to some embodiments of the present disclosure;

[0037] FIG3 is a schematic diagram of subframe reading according to an embodiment of the present disclosure;

[0038] FIG4 is a schematic diagram of subframe reading according to another embodiment of the present disclosure;

[0039] FIG5 is a schematic diagram of subframe reading according to another embodiment of the present disclosure;

[0040] FIG6 is a schematic diagram of framing according to an embodiment of the present disclosure;

[0041] FIG7 is a schematic diagram of framing according to another embodiment of the present disclosure;

[0042] FIG8 is a schematic diagram of framing according to another embodiment of the present disclosure;

[0043] FIG9 is a schematic diagram of display frame splitting according to an embodiment of the present disclosure;

[0044] FIG10 is a schematic structural diagram of a display control device according to an embodiment of the present disclosure;

[0045] FIG11 is a schematic structural diagram of a display control device according to another embodiment of the present disclosure;

[0046] FIG12 is a schematic structural diagram of a vehicle-mounted display system according to an embodiment of the present disclosure.

[0047] It should be understood that the size of each part shown in the accompanying drawings is not drawn according to the actual proportional relationship. In addition, the same or similar reference numerals represent the same or similar components. DETAILED DESCRIPTION

[0048] Various exemplary embodiments of the present disclosure will now be described in detail with reference to the accompanying drawings. The description of the exemplary embodiments is merely illustrative and is in no way intended to limit the present disclosure, its application, or use. The present disclosure can be implemented in many different forms and is not limited to the embodiments described herein. These embodiments are provided to make the present disclosure thorough and complete and to fully convey the scope of the present disclosure to those skilled in the art. It should be noted that unless otherwise specifically stated, the relative arrangement of the components and steps, the composition of the materials, and the numerical values ​​set forth in these embodiments should be interpreted as being merely exemplary and not as limiting.

[0049] The terms "first," "second," and similar terms used in this disclosure do not denote any order, quantity, or importance, but are simply used to distinguish one part from another. Terms such as "include" or "comprise" mean that the elements preceding the term include the elements listed after the term, and do not exclude the possibility of also including other elements.

[0050] All terms (including technical or scientific terms) used in this disclosure have the same meaning as those understood by one of ordinary skill in the art to which this disclosure belongs, unless otherwise specifically defined. It should also be understood that terms defined in, for example, general dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology, and should not be interpreted in an idealized or highly formal sense, unless explicitly defined herein.

[0051] Technologies, methods, and equipment known to ordinary technicians in the relevant art may not be discussed in detail, but where appropriate, the technologies, methods, and equipment should be considered part of the specification.

[0052] The inventors noted that if a vehicle-mounted display device is capable of displaying in partitions, and a user performs a touch operation on a display area of ​​the vehicle-mounted display device, it is necessary to reduce the display delay of that display area. Currently, the same control method is used for the content displayed in each display area, making it impossible to effectively reduce the display delay of a specific display area.

[0053] Accordingly, the present disclosure provides a display control solution that effectively reduces the display delay of a specified display area and improves the user experience by adopting different control methods for subframes displayed in different display areas.

[0054] Figure 1 is a flow chart of a display control method according to an embodiment of the present disclosure. In some embodiments, the display control method is executed by a display control device.

[0055] In step 101 , a received video frame in a current frame period is divided into m subframes, wherein the m subframes correspond one-to-one to m display areas on a display device, and m is a natural number greater than 1.

[0056] It should be noted that in order to facilitate control of the display content of each display area on the display device, the video frame within the current frame period is divided. For example, if the display device includes three display areas, the video frame within the current frame period is divided into three sub-frames, where the first sub-frame is used for display in the first display area, the second sub-frame is used for display in the second display area, and the third sub-frame is used for display in the third display area.

[0057] To facilitate processing of the obtained m subframes, a different timing sequence is configured for each of the m subframes. For example, when a video frame is divided into three subframes, within a frame period SVT, the first subframe is configured with the first timing sequence VT1, as shown in FIG2A , the second subframe is configured with the second timing sequence VT2, as shown in FIG2B , and the third subframe is configured with the third timing sequence VT3, as shown in FIG2C .

[0058] In step 102, according to a preset rule, a subframe is selected from the m subframes as a target subframe.

[0059] In some embodiments, the target subframe among the m subframes is the subframe specified by the received instruction. For example, if a video frame is divided into three subframes and the received instruction indicates that the user has performed a touch operation on the second display area, the second subframe corresponding to the second display area is used as the target subframe. In this case, the first and third subframes are written to the cache, while the second subframe is not.

[0060] In other embodiments, the target subframe is the subframe with the largest delay weight among the m subframes. For example, if a video frame is divided into three subframes, and the second subframe has the largest predetermined delay weight, the second subframe is used as the target subframe. In this case, the first and third subframes are written to the cache, while the second subframe is not.

[0061] That is, when the user does not perform any touch operation on the vehicle-mounted display device, the target subframe can be selected according to the delay weight pre-configured for the subframe corresponding to each display area.

[0062] In step 103, m-1 subframes excluding the target subframe among the m subframes are written into a buffer.

[0063] It should be noted that, among the m subframes, only m-1 subframes except the target subframe are written into the cache, and the target subframe is not written into the cache, thereby effectively reducing the delay of the target subframe.

[0064] In some embodiments, the buffer includes m-1 sub-buffers, and the m-1 sub-buffers correspond one-to-one to the m-1 sub-frames. In this case, using the current write address WDMA -addr Write each of the m-1 subframes into the corresponding sub-buffer, where the current write address WDMA -addr Determined by the current frame period.

[0065] For example, each sub-cache adopts a ring memory structure, and the initial value of the write address is 0, that is, WDMA -addr = 0. When the rising edge of the frame synchronization signal in the current frame period is received, the write address is updated by adding 1 to the write address. At this time, the updated write address WDMA -addr =1, and so on. If the ring memory includes n storage spaces, the write address WDMA -addr =n and write address WDMA -addr =0 corresponds to the same storage space, so circular storage can be achieved through the above processing.

[0066] For example, when a video frame is divided into three subframes and the second subframe is the target subframe, the first subframe is written into the first sub-buffer and the third subframe is written into the second sub-buffer according to the current write address.

[0067] In step 104 , m−1 subframes between a target subframe in a current frame period and a target subframe in a previous frame period are read from a buffer according to the timing of each subframe in the m subframes.

[0068] In some embodiments, when the target subframe in the current frame period is the latest subframe in the current frame period, m-1 subframes in the current frame period are read from the buffer.

[0069] In this case, the current read address is the same as the current write address, i.e. RDMA -addr =WDMA -addr Using the current read address, read a sub-frame from each of the m-1 sub-buffers.

[0070] For example, as shown in Figure 3, there are three subframes in each frame period. The nth frame period includes subframes F1_n, F2_n, and F3_n, with F3_n being the target subframe. Since F3_n is the latest subframe in the nth frame period, subframes F1_n and F2_n in the nth frame period are read from the cache based on the timing trigger of F3_n. The read subframes F1_n and F2_n are represented by dark boxes.

[0071] Based on the same processing method, as shown in Figure 3, in the n-1th frame period, based on the timing trigger of the target subframe F3_n-1, subframe F1_n-1 and subframe F2_n-1 in the n-1th frame period are read from the buffer. In the n+1th frame period, based on the timing trigger of the target subframe F3_n+1, subframe F1_n+1 and subframe F2_n+1 in the n+1th frame period are read from the buffer. The read subframes F1_n+1 and F2_n+1 are represented by dark boxes.

[0072] In some embodiments, when the target subframe in the current frame period is the earliest subframe in the current frame period, the latest m-1 subframes in the previous frame period are read from the cache.

[0073] In this case, RDMA-addr=WDMA-addr-1, that is, the current read address is the current write address minus 1. Using the current read address, a sub-frame is read from each of the m-1 sub-buffers.

[0074] For example, as shown in Figure 4, there are three subframes in each frame period. The nth frame period includes subframes F1_n, F2_n, and F3_n, with subframe F1_n being the target subframe. Since subframe F1_n is the earliest subframe in the nth frame period, subframes F2_n-1 and F3_n-1 in the n-1th frame period are read from the cache based on the timing trigger of subframe F1_n. The read subframes F2_n-1 and F3_n-1 are represented by dark boxes.

[0075] Based on the same processing method, as shown in Figure 4, in the n+1th frame period, according to the timing trigger of the target subframe F1_n+1, the subframe F2_n and subframe F3_n in the nth frame period are read from the cache, and the read subframes F2_n and subframe F3_n are represented by dark boxes.

[0076] In some embodiments, in the current frame period, when there are k subframes whose timing is earlier than the timing of the target subframe in the current frame period, k subframes in the current frame period are read from the cache, and the latest mk-1 subframes in the previous frame period are read from the cache, where 1≤k <m-1。

[0077] In this case, k subframes are read from the k sub-buffers corresponding to the k sub-frames in the current frame period among the m-1 sub-buffers using a first read address, where the first read address is the same as the current write address. Furthermore, mk-1 sub-frames are read from the mk-1 sub-buffers corresponding to the mk-1 sub-frame with the latest timing in the previous frame period among the m-1 sub-buffers using a second read address, where the second read address is the current write address minus 1.

[0078] For example, as shown in Figure 5, there are three subframes in each frame period. In the nth frame period, subframe F1_n, subframe F2_n, and subframe F3_n are included, and subframe F2_n is the target subframe. Since in the nth frame period, the timing of subframe F2_n is later than the timing of subframe F1_n, and the timing of subframe F2_n is earlier than the timing of subframe F3_n, based on the timing trigger of subframe F2_n, subframe F1_n in the nth frame period is read from the cache, and subframe F3_n-1 in the n-1th frame period is read from the cache. The read subframes F1_n and F3_n-1 are represented by dark boxes.

[0079] Based on the same processing method, as shown in Figure 5, in the n+1th frame period, according to the timing trigger of the subframe F2_n+1, the subframe F1_n+1 in the n+1th frame period is read from the cache, and the subframe F3_n in the nth frame period is read from the cache. The read subframes F1_n+1 and F3_n are represented by dark boxes.

[0080] In step 105 , a display frame is generated according to the target subframe of the current frame period and the m−1 subframes read from the buffer.

[0081] In some embodiments, when the target subframe in the current frame period is the latest subframe in the current frame period, m-1 subframes in the current frame period are read from the buffer.

[0082] In this case, the m-1 sub-frames in the current frame period and the target sub-frame in the current frame period are combined to generate a display frame.

[0083] For example, as shown in FIG3 , in the nth frame period, according to the timing trigger of the target subframe F3_n, the subframe F1_n and subframe F2_n in the nth frame period are read from the cache, and the read subframe F1_n and subframe F2_n are combined with the target subframe F3_n to generate a display frame, as shown in FIG6 .

[0084] Based on the same processing method, as shown in Figure 3, in the n-1th frame period, based on the timing trigger of the target subframe F3_n-1, subframe F1_n-1 and subframe F2_n-1 in the n-1th frame period are read from the cache, and the read subframe F1_n-1 and subframe F2_n-1 are combined with the target subframe F3_n-1 to generate a display frame. In the n+1th frame period, based on the timing trigger of the target subframe F3_n+1, subframe F1_n+1 and subframe F2_n+1 in the n+1th frame period are read from the cache, and the read subframe F1_n+1 and subframe F2_n+1 are combined with the target subframe F3_n+1 to generate a display frame.

[0085] In some embodiments, when the target subframe in the current frame period is the earliest subframe in the current frame period, the latest m-1 subframes in the previous frame period are read from the cache.

[0086] In this case, the target subframe in the current frame period and the m-1 subframes that are latest in timing in the previous frame period are combined to generate a display frame.

[0087] For example, as shown in FIG4 , in the nth frame period, according to the timing trigger of the target subframe F1_n, the subframe F2_n-1 and the subframe F3_n-1 in the n-1th frame period are read from the cache, and the target subframe F1_n and the read subframe F2_n-1 and subframe F3_n-1 are combined to generate a display frame, as shown in FIG7 .

[0088] Based on the same processing method, as shown in Figure 4, in the n+1th frame period, according to the timing trigger of the target subframe F1_n+1, the subframe F2_n and subframe F3_n in the nth frame period are read from the cache, and the target subframe F1_n+1 and the read subframe F2_n and subframe F3_n are combined to generate a display frame.

[0089] In some embodiments, in the current frame period, when there are k subframes whose timing is earlier than the timing of the target subframe in the current frame period, k subframes in the current frame period are read from the cache, and the latest mk-1 subframes in the previous frame period are read from the cache, where 1≤k <m-1。

[0090] In this case, k subframes in the current frame period, the target subframe in the current frame period, and mk-1 subframes in the previous frame period are combined to generate a display frame.

[0091] For example, as shown in FIG5 , in the nth frame period, according to the timing trigger of the target subframe F2_n, the subframe F1_n in the nth frame period is read from the cache, and the subframe F3_n-1 in the n-1th frame period is read from the cache, and the read subframe F1_n, the target subframe F2_n and the read subframe F3_n-1 are combined to generate a display frame, as shown in FIG8 .

[0092] Based on the same processing method, as shown in Figure 5, in the n+1th frame period, according to the timing trigger of the target subframe F2_n+1, the subframe F1_n+1 in the n+1th frame period is read from the cache, and the subframe F3_n in the nth frame period is read from the cache, and the read subframe F1_n+1, the target subframe F2_n+1 and the read subframe F3_n are combined to generate a display frame.

[0093] In step 106, the display frame is sent to a display device for display.

[0094] In some embodiments, the display frame is divided into a first display subframe and a second display subframe. Next, the first display subframe is sent to the display device via the first display interface, and the second display subframe is sent to the display device via the second display interface.

[0095] For example, as shown in FIG9 , the display frame shown in FIG6 is divided into two display subframes, wherein the subframe F2_n is divided into two parts, the subframe F2_n-a and the subframe F2_n-b, the subframe F1_n and the subframe F2_n-a constitute the first display subframe SF1, and the subframe F2_n-b and the subframe F3_n constitute the second display subframe SF2.

[0096] For example, in the display frame shown in FIG6 , the resolution of each subframe is 3498×1040, the resolution of the display frame shown in FIG6 is 10496×1040, and the resolution of the first display subframe SF1 and the second display subframe SF2 shown in FIG9 is 5248×1040.

[0097] In some embodiments, the first display interface and the second display interface are EDP (Embedded Display Port).

[0098] In the display control method provided in the above embodiment of the present disclosure, different control methods are adopted for subframes displayed in different display areas, thereby effectively reducing the display delay of the designated display area and improving the user experience.

[0099] FIG10 is a schematic diagram of the structure of a display control device according to an embodiment of the present disclosure. As shown in FIG10 , the display control device includes a memory 1001 and a processor 1002 .

[0100] The memory 1001 is used to store instructions. The processor 1002 is coupled to the memory 1001. The processor 1002 is configured to execute the method involved in any embodiment of FIG1 based on the instructions stored in the memory.

[0101] As shown in Figure 10, the display control device further includes a communication interface 1003 for exchanging information with other devices. The display control device also includes a bus 1004 through which the processor 1002, the communication interface 1003, and the memory 1001 communicate with each other.

[0102] Memory 1001 may include high-speed RAM (Random Access Memory) or NVM (Non-Volatile Memory), for example, at least one disk storage device. Memory 1001 may also be a storage array. Memory 1001 may also be divided into blocks, and the blocks may be combined into virtual volumes according to certain rules.

[0103] In addition, the processor 1002 may be a central processing unit, or may be an ASIC (Application Specific Integrated Circuit), or may be configured to implement one or more integrated circuits of the embodiments of the present disclosure.

[0104] The present disclosure further provides a non-transitory computer-readable storage medium storing computer instructions, which, when executed by a processor, implement the method involved in any embodiment of FIG. 1 .

[0105] FIG11 is a schematic diagram of the structure of a display control device according to another embodiment of the present disclosure. As shown in FIG11 , the display control device includes a receiving circuit 1101 , a segmentation circuit 1102 , a selection circuit 1103 , a rearrangement circuit 1104 , a write control circuit 1105 , a read control circuit 1106 , a sending circuit 1107 , and a buffer 1108 .

[0106] The receiving circuit 1101 is configured to receive a video frame in a current frame period.

[0107] The segmentation circuit 1102 is configured to divide the video frame in the current frame period into m sub-frames, wherein the m sub-frames correspond one-to-one to m display areas on the display device, and m is a natural number greater than 1.

[0108] It should be noted that in order to facilitate control of the display content of each display area on the display device, the video frame within the current frame period is divided. For example, if the display device includes three display areas, the video frame within the current frame period is divided into three sub-frames, where the first sub-frame is used for display in the first display area, the second sub-frame is used for display in the second display area, and the third sub-frame is used for display in the third display area.

[0109] To facilitate processing of the obtained m subframes, a different timing sequence is configured for each of the m subframes. For example, when a video frame is divided into three subframes, within a frame period SVT, the first subframe is configured with the first timing sequence VT1, as shown in FIG2A , the second subframe is configured with the second timing sequence VT2, as shown in FIG2B , and the third subframe is configured with the third timing sequence VT3, as shown in FIG2C .

[0110] The selection circuit 1103 is configured to select a subframe as a target subframe from the m subframes according to a preset rule, send the target subframe from the m subframes to the rearrangement circuit 1104, and write m-1 subframes other than the target subframe from the m subframes into the cache 1108 through the write control circuit 1105.

[0111] It should be noted that, among the m subframes, only m-1 subframes except the target subframe are written into the cache, and the target subframe is not written into the cache, thereby effectively reducing the delay of the target subframe.

[0112] In some embodiments, the target subframe among the m subframes is the subframe specified by the received instruction. For example, if a video frame is divided into three subframes and the received instruction indicates that the user has performed a touch operation on the second display area, the second subframe corresponding to the second display area is used as the target subframe. In this case, the first and third subframes are written to the cache, while the second subframe is not.

[0113] In other embodiments, the target subframe is the subframe with the largest delay weight among the m subframes. For example, if a video frame is divided into three subframes, and the second subframe has the largest predetermined delay weight, the second subframe is used as the target subframe. In this case, the first and third subframes are written to the cache, while the second subframe is not.

[0114] That is, when the user does not perform any touch operation on the vehicle-mounted display device, the target subframe can be selected according to the delay weight pre-configured for the subframe corresponding to each display area.

[0115] In some embodiments, the buffer includes m-1 sub-buffers, and the m-1 sub-buffers correspond one-to-one to the m-1 sub-frames. In this case, using the current write address WDMA -addr Write each of the m-1 subframes into the corresponding sub-buffer, where the current write address WDMA -addr Determined by the current frame period.

[0116] The rearrangement circuit 1104 is configured to read m-1 subframes between the target subframe in the current frame period and the target subframe in the previous frame period from the cache 1108 through the read control circuit 1106 according to the timing of each subframe in the m subframes, and generate a display frame based on the target subframe in the current frame period and the m-1 subframes read from the cache.

[0117] In some embodiments, the rearrangement circuit 1104 is configured to read m-1 subframes in the current frame period from the cache 1108 through the read control circuit 1006 when the target subframe in the current frame period is the latest subframe in the current frame period.

[0118] For example, the read control circuit 1006 is configured to read a sub-frame from each of the m-1 sub-buffers using a current read address, wherein the current read address is the same as the current write address.

[0119] In this case, the rearrangement circuit 1104 combines the target subframe in the current frame period and the latest m-1 subframes in timing in the previous frame period to generate a display frame.

[0120] For example, the sub-frame reading method in this scenario is shown in FIG3 , and the generated display frame is shown in FIG6 .

[0121] In some embodiments, the rearrangement circuit 1104 is configured to read the latest m-1 subframes in the previous frame period from the cache when the target subframe in the current frame period is the earliest subframe in the current frame period.

[0122] In some embodiments, the read control circuit 1106 is configured to read a sub-frame from each of the m-1 sub-buffers using a current read address, where the current read address is equal to a current write address minus 1.

[0123] In this case, the rearrangement circuit 1104 combines the target subframe in the current frame period and the latest m-1 subframes in timing in the previous frame period to generate a display frame.

[0124] For example, the sub-frame reading method in this scenario is shown in FIG4 , and the generated display frame is shown in FIG7 .

[0125] In some embodiments, the rearrangement circuit 1104 is configured to read k subframes in the current frame period from the cache through the read control circuit 1106 when there are k subframes whose timing is earlier than the timing of the target subframe in the current frame period, and read the latest mk-1 subframes in the previous frame period from the cache, where 1≤k <m-1。

[0126] In some embodiments, the read control circuit 1106 is configured to read k subframes from k sub-buffers corresponding to k sub-frames in the m-1 sub-buffers using a first read address, where the first read address is the same as the current write address; and is also configured to read mk-1 subframes from mk-1 sub-buffers corresponding to mk-1 sub-frames in the m-1 sub-buffers using a second read address, where the second read address is the current write address minus 1.

[0127] In this case, the rearrangement circuit 1104 combines k subframes in the current frame period, the target subframe in the current frame period, and mk-1 subframes in the previous frame period to generate a display frame.

[0128] For example, the sub-frame reading method in this scenario is shown in FIG5 , and the generated display frame is shown in FIG8 .

[0129] The transmission circuit 1107 is configured to transmit the display frame to a display device for display.

[0130] In some embodiments, the transmitting circuit 1107 divides the display frame into a first display subframe and a second display subframe. Next, the first display subframe is transmitted to the display device via the first display interface, and the second display subframe is transmitted to the display device via the second display interface.

[0131] For example, as shown in FIG9 , the transmitting circuit 1107 divides the display frame shown in FIG6 into two display subframes, wherein the subframe F2_n is divided into two parts, a subframe F2_n-a and a subframe F2_n-b, the subframe F1_n and the subframe F2_n-a constitute a first display subframe, and the subframe F2_n-b and the subframe F3_n constitute a second display subframe.

[0132] For example, in the display frame shown in FIG6 , the resolution of each subframe is 3498×1040, the resolution of the display frame shown in FIG6 is 10496×1040, and the resolution of the first display subframe SF1 and the second display subframe SF2 shown in FIG9 is 5248×1040.

[0133] In some embodiments, the first display interface and the second display interface are EDPs.

[0134] FIG12 is a schematic diagram of the structure of an in-vehicle display system according to an embodiment of the present disclosure. As shown in FIG12 , the in-vehicle display system includes a display control device 1201 and a display device 1202. The display control device 1201 is the display control device described in any of the embodiments in FIG10 or FIG11 .

[0135] The display device 1202 is configured to receive and present the display frame sent by the display control device 1201. For example, the display device can be any product or component with a display function, such as a monitor, a mobile phone, a tablet computer, a television, a laptop computer, a digital photo frame, or a navigation system.

[0136] In some embodiments, the display device 1202 receives a first display subframe sent by the display control device 1201 through a first display interface, receives a second display subframe sent by the display control device 1201 through a second display interface, and splices the first display subframe and the second display subframe for display.

[0137] For example, the resolutions of the first display subframe and the second display subframe are 5248×1040, and a display frame with a resolution of 10496×1040 is obtained by splicing the first display subframe and the second display subframe.

[0138] In some embodiments, the first display interface and the second display interface are EDPs.

[0139] Thus far, the embodiments of the present disclosure have been described in detail. To avoid obscuring the concept of the present disclosure, some details known in the art have not been described. Based on the above description, those skilled in the art can fully understand how to implement the technical solutions disclosed herein.

[0140] Although some specific embodiments of the present disclosure have been described in detail through examples, those skilled in the art will understand that the above examples are for illustration only and are not intended to limit the scope of the present disclosure. Those skilled in the art will understand that the above embodiments may be modified or some technical features may be replaced with equivalents without departing from the scope and spirit of the present disclosure. The scope of the present disclosure is defined by the appended claims.

Claims

1. A display control method, comprising: Divide the received video frame in the current frame period into m subframes, wherein the m subframes correspond one-to-one to the m display areas on the display device, and m is a natural number greater than 1; According to a preset rule, selecting a subframe from the m subframes as a target subframe; Writing m-1 subframes of the m subframes except the target subframe into a cache; Reading, from the buffer, m-1 subframes located between the target subframe in the current frame period and the target subframe in the previous frame period according to the timing of each subframe in the m subframes; Generate a display frame according to the target subframe of the current frame period and the m-1 subframes read from the buffer; The display frame is sent to the display device for display.

2. The method according to claim 1, wherein: The cache includes m-1 sub-buffers, and the m-1 sub-buffers correspond one-to-one to the m-1 sub-frames. Writing m-1 subframes into the buffer involves: Each subframe in the m-1 subframes is written into a corresponding sub-buffer using a current write address, wherein the current write address is determined by the current frame period.

3. The method according to claim 2, wherein: Reading m-1 subframes from the buffer comprises: In a case where the target subframe in the current frame period is the latest subframe in the current frame period, m-1 subframes in the current frame period are read from the buffer.

4. The method according to claim 3, wherein: Reading m-1 subframes in the current frame period from the buffer comprises: A subframe is read from each of the m-1 sub-buffers using a current read address, wherein the current read address is the same as the current write address.

5. The method according to claim 3, wherein: Generating a display frame includes: The m-1 subframes in the current frame period and the target subframe in the current frame period are combined to generate the display frame.

6. The method according to claim 2, wherein: Reading m-1 subframes from the buffer comprises: When the target subframe in the current frame period is the earliest subframe in the current frame period, the latest m-1 subframes in the previous frame period are read from the cache.

7. The method according to claim 6, wherein: Reading m-1 subframes in the previous frame period from the buffer comprises: A subframe is read from each sub-buffer in the m-1 sub-buffers using a current read address, wherein the current read address is the current write address minus 1.

8. The method according to claim 6, wherein: Generating a display frame includes: The target subframe in the current frame period and the latest m-1 subframes in the previous frame period are combined to generate the display frame.

9. The method according to claim 2, wherein: Reading m-1 subframes from the buffer comprises: In the current frame period, if there are k subframes whose timing is earlier than the timing of the target subframe in the current frame period, read the k subframes in the current frame period from the cache, and read the latest mk-1 subframes in the previous frame period from the cache, where 1≤k <m-1。 10. The method according to claim 9, wherein: Reading k subframes from the buffer comprises: Using a first read address, reading k subframes from k sub-buffers corresponding to the k sub-frames in the m-1 sub-buffers, wherein the first read address is the same as the current write address; Reading mk-1 subframes from the buffer comprises: The mk-1 subframes are read from the mk-1 sub-buffers corresponding to the mk-1 sub-frames in the m-1 sub-buffers using a second read address, wherein the second read address is the current write address minus 1.

11. The method according to claim 9, wherein: Generating a display frame includes: The k subframes in the current frame period, the target subframe in the current frame period, and the mk-1 subframes in the previous frame period are combined to generate the display frame.

12. The method according to claim 1, wherein: Among the m subframes, the target subframe is a subframe having a maximum delay weight.

13. The method according to claim 1, wherein: Among the m subframes, the target subframe is a subframe designated by the received instruction.

14. The method according to any one of claims 1 to 13, wherein: Sending the display frame to the display device comprises: dividing the display frame into a first display subframe and a second display subframe; Sending the first display subframe to the display device through a first display interface; The second display subframe is sent to the display device through a second display interface.

15. A display control device, comprising: a memory configured to store instructions; A processor is coupled to the memory, and the processor is configured to execute the method according to any one of claims 1 to 14 based on instructions stored in the memory.

16. A display control device, comprising: A receiving circuit configured to receive a video frame in a current frame period; a segmentation circuit configured to divide the video frame in the current frame period into m subframes, wherein the m subframes correspond one-to-one to the m display areas on the display device, and m is a natural number greater than 1; A selection circuit is configured to select a subframe from the m subframes as a target subframe according to a preset rule, send the target subframe among the m subframes to a rearrangement circuit, and write m-1 subframes among the m subframes except the target subframe into a cache through a write control circuit; a rearrangement circuit configured to read m-1 subframes located between a target subframe in the current frame period and a target subframe in a previous frame period from the buffer through a read control circuit according to a timing of each subframe in the m subframes, and generate a display frame according to the target subframe in the current frame period and the m-1 subframes read from the buffer; The sending circuit is configured to send the display frame to the display device for display.

17. The device according to claim 16, wherein: The cache includes m-1 sub-buffers, and the m-1 sub-buffers correspond one-to-one to the m-1 sub-frames; The write control circuit is configured to write each subframe of the m-1 subframes into a corresponding sub-buffer using a current write address, wherein the current write address is determined by the current frame period.

18. The device according to claim 17, wherein: The rearrangement circuit is configured to read m-1 subframes in the current frame period from the buffer through the read control circuit when the target subframe in the current frame period is the latest subframe in the current frame period.

19. The device according to claim 18, wherein: The read control circuit is configured to read a subframe from each of the m-1 sub-buffers using a current read address, wherein the current read address is the same as the current write address.

20. The device according to claim 18, wherein The rearrangement circuit is configured to combine m-1 subframes in the current frame period and a target subframe in the current frame period to generate the display frame.

21. The device according to claim 17, wherein: The rearrangement circuit is configured to read the latest m-1 subframes in the previous frame period from the cache through the read control circuit when the target subframe in the current frame period is the earliest subframe in the current frame period.

22. The device according to claim 21, wherein The read control circuit is configured to read a subframe from each of the m-1 sub-buffers using a current read address, wherein the current read address is the current write address minus 1.

23. The device according to claim 21, wherein The rearrangement circuit is configured to place the target subframe in the current frame period and the target subframe in the previous frame period. The m-1 sub-frames that are latest in timing are combined to generate the display frame.

24. The device according to claim 17, wherein: The rearrangement circuit is configured to read the k subframes in the current frame period from the cache through the read control circuit when there are k subframes whose timing is earlier than the timing of the target subframe in the current frame period, and read the latest mk-1 subframes in the previous frame period from the cache, where 1≤k <m-1。 25. The device according to claim 24, wherein: The read control circuit is configured to use a first read address to read k subframes from k sub-caches among the m-1 sub-caches corresponding to the k sub-frames, wherein the first read address is the same as the current write address; and is also configured to use a second read address to read mk-1 subframes from mk-1 sub-caches among the m-1 sub-caches corresponding to the mk-1 sub-frames, wherein the second read address is the current write address minus 1.

26. The device according to claim 24, wherein: The rearrangement circuit is configured to combine the k subframes in the current frame period, the target subframe in the current frame period, and the mk-1 subframes in the previous frame period to generate the display frame.

27. A vehicle-mounted display system, comprising: The display control device according to any one of claims 15 to 26; and The display device is configured to receive the display frame sent by the display control device and present the display frame.

28. A computer-readable storage medium, wherein: The computer-readable storage medium stores computer instructions, and when the instructions are executed by a processor, the method according to any one of claims 1 to 14 is implemented.

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