Pixel circuit and driving method therefor, and display apparatus

Abstract

A pixel circuit (50) and a driving method therefor, and a display apparatus. The pixel circuit (50) comprises a drive circuit (100) and a data writing circuit (200), wherein the drive circuit (100) is configured to control the magnitude of a drive current flowing through a first end (100a) and a second end (100b); and a first end (200a) of the data writing circuit (200) is electrically connected to the second end (100b) of the drive circuit (100), a second end (200b) of the data writing circuit (200) is configured to receive a data signal, the data writing circuit (200) is configured to write the data signal into the second end (100b) of the drive circuit (100) in response to a data scanning signal and comprises a data writing transistor (T1) and a first compensation capacitor (Cst1), a gate electrode of the data writing transistor (T1) is configured to receive the data scanning signal, and a first electrode of the first compensation capacitor (Cst1) is electrically connected to a first electrode of the data writing transistor (T1). The pixel circuit (50) can reduce the influence of a fluctuation in the data signal and a change in the state of the data writing transistor (T1) on the voltage of the second end (100b) of a drive transistor, which is conducive to maintaining the stability of a gate-source voltage of the drive transistor, so that a light-emitting element has a stable light-emitting state.

Description

Pixel circuit, driving method thereof, and display device Technical Field

[0001] At least one embodiment of the present disclosure relates to a pixel circuit, a driving method thereof, and a display device. Background Art

[0002] With the continuous development of display technology, pixel circuits using low-temperature polycrystalline silicon-oxide (LTPO) are increasingly being used in display devices. LTPO-based pixel circuits offer high refresh rates, low leakage current, and uniform brightness across the display panel. Furthermore, internal compensation circuits are widely used due to their low requirements for driver integrated circuits (ICs), low cost, and simple control algorithms.

[0003] Summary of the Invention

[0004] At least one embodiment of the present disclosure provides a pixel circuit, a driving method thereof, and a display device.

[0005] At least one embodiment of the present disclosure provides a pixel circuit, which includes a driving circuit and a data writing circuit, wherein the driving circuit includes a control end, a first end, and a second end, and is configured to control the magnitude of the driving current flowing through the first end and the second end; the data writing circuit includes a first end and a second end, wherein the first end of the data writing circuit is electrically connected to the second end of the driving circuit, the second end of the data writing circuit is configured to receive a data signal, and the data writing circuit is configured to write the data signal to the second end of the driving circuit in response to a data scanning signal, and includes a data writing transistor and a first compensation capacitor, wherein the gate of the data writing transistor is configured to receive the data scanning signal, and the first electrode of the first compensation capacitor is electrically connected to the first electrode of the data writing transistor.

[0006] For example, according to the pixel circuit provided by at least one embodiment of the present disclosure, the second electrode of the first compensation capacitor is electrically connected to the second end of the driving circuit, and the second electrode of the data writing transistor is electrically connected to the data signal end to receive the data signal.

[0007] For example, according to the pixel circuit provided by at least one embodiment of the present disclosure, the capacitance value of the first compensation capacitor is 30 to 100 times the capacitance value of the parasitic capacitance between the gate of the data writing transistor and the first electrode of the data writing transistor.

[0008] For example, in the pixel circuit provided by at least one embodiment of the present disclosure, the capacitance value of the first compensation capacitor is 100 fF to 300 fF.

[0009] For example, according to the pixel circuit provided by at least one embodiment of the present disclosure, the second electrode of the first compensation capacitor is electrically connected to the data signal end to receive the data signal, and the second electrode of the data writing transistor is electrically connected to the second end of the driving circuit.

[0010] For example, according to the pixel circuit provided by at least one embodiment of the present disclosure, the pixel circuit also includes: a first reset circuit, the control end of the first reset circuit is configured to receive a first reset control signal, the first end of the first reset circuit is electrically connected to the first pole of the first compensation capacitor, the second end of the first reset circuit is electrically connected to the reference signal end to receive a reference signal, and the first reset circuit is configured to respond to the first reset control signal to write the reference signal to the second end of the driving circuit with the first compensation capacitor.

[0011] For example, according to the pixel circuit provided by at least one embodiment of the present disclosure, the first reset circuit includes a first reset transistor, the gate of the first reset transistor is electrically connected to the first reset control terminal to receive the first reset control signal, the first electrode of the first reset transistor is electrically connected to the first electrode of the first compensation capacitor, and the second electrode of the first reset transistor is electrically connected to the reference signal terminal to receive the reference signal; the data write transistor is multiplexed as the first reset transistor, the data scan signal is multiplexed as the first reset control signal, the second electrode of the data write transistor is also electrically connected to the reference signal terminal to receive the reference signal, and is configured to apply the reference signal to the second end of the driving circuit with the first compensation capacitor.

[0012] For example, in the pixel circuit provided according to at least one embodiment of the present disclosure, the data signal terminal is reused as the reference signal terminal and is configured to receive the data signal and the reference signal respectively in different time periods; or, the data signal terminal and the reference signal terminal are different signal terminals independent of each other.

[0013] For example, according to the pixel circuit provided by at least one embodiment of the present disclosure, the first reset circuit includes a first reset transistor, the gate of the first reset transistor is electrically connected to the first reset control terminal to receive the first reset control signal, the first electrode of the first reset transistor is electrically connected to the first electrode of the first compensation capacitor, and the second electrode of the first reset transistor is electrically connected to the reference signal terminal to receive the reference signal; the data write transistor and the first reset transistor are transistors that are independently controlled from each other, the gate of the data write transistor is electrically connected to the data control terminal, the gate of the first reset transistor is electrically connected to the first reset control terminal, the data control terminal and the first reset control terminal are different signal terminals independent of each other, and the data signal terminal and the reference signal terminal are different signal terminals independent of each other.

[0014] For example, according to the pixel circuit provided by at least one embodiment of the present disclosure, the pixel circuit also includes a light-emitting element and a second reset circuit, the light-emitting element is configured to emit light under the drive of the driving current, wherein the second end of the driving circuit is electrically connected to the first electrode of the light-emitting element, the driving circuit is configured to control the magnitude of the driving current flowing through the light-emitting element, and the second electrode of the light-emitting element is electrically connected to the first voltage end to receive a first power supply voltage; the control end of the second reset circuit is configured to receive a second reset control signal, the first end of the second reset circuit is electrically connected to the first electrode of the light-emitting element, the second end of the second reset circuit is electrically connected to the first reset signal end to receive a first reset signal, and the second reset circuit is configured to apply the first reset signal to the first electrode of the light-emitting element in response to the second reset control signal.

[0015] For example, according to the pixel circuit provided by at least one embodiment of the present disclosure, the second reset circuit includes a second reset transistor, the gate of the second reset transistor is electrically connected to the second reset control terminal to receive the second reset control signal, the first electrode of the second reset transistor is electrically connected to the first electrode of the light-emitting element, and the second electrode of the second reset transistor is electrically connected to the first reset signal terminal to receive the first reset signal; the gate of the data write transistor is electrically connected to the gate of the second reset transistor, the data write transistor and the second reset transistor share a gate, the data scan signal serves as the second reset control signal, and the type of the data transistor is the same as the type of the second reset transistor; or, the gate of the data transistor and the gate of the second reset transistor are independent of each other and not electrically connected.

[0016] For example, according to the pixel circuit provided by at least one embodiment of the present disclosure, the pixel circuit also includes: a first light-emitting control circuit and a second light-emitting control circuit, the control end of the first light-emitting control circuit is configured to receive a first light-emitting control signal, the first end of the first light-emitting control circuit is electrically connected to the first end of the driving circuit, the second end of the first light-emitting control circuit is electrically connected to the second voltage end to receive a second power supply voltage, and the first light-emitting control circuit is configured to apply the second power supply voltage to the first end of the driving circuit in response to the first light-emitting control signal; the control end of the second light-emitting control circuit is configured to receive a second light-emitting control signal, the second light-emitting control signal is different from the first light-emitting control signal, the first end of the second light-emitting control circuit is electrically connected to the second end of the driving circuit, the second end of the second light-emitting control circuit is electrically connected to the first electrode of the light-emitting element, and the second light-emitting control circuit is configured to apply the driving current to the light-emitting element in response to the second light-emitting control signal.

[0017] For example, according to the pixel circuit provided by at least one embodiment of the present disclosure, the pixel circuit also includes a direct reset circuit, the control end of the direct reset circuit is configured to receive a direct reset control signal, the first end of the direct reset circuit is electrically connected to the second end of the driving circuit, the second end of the direct reset circuit is electrically connected to the second reset signal end to receive the second reset signal, and the direct reset circuit is configured to directly apply the second reset signal to the second end of the driving circuit in response to the direct reset control signal; the direct reset circuit includes a direct reset transistor, the gate of the direct reset transistor is electrically connected to the direct reset control signal end to receive the direct reset control signal, the first electrode of the direct reset transistor is electrically connected to the second end of the driving circuit, and the second electrode of the direct reset transistor is electrically connected to the second reset signal end to receive the second reset signal.

[0018] For example, according to the pixel circuit provided by at least one embodiment of the present disclosure, the value of the first reset signal is equal to the value of the second reset signal.

[0019] For example, according to the pixel circuit provided by at least one embodiment of the present disclosure, the first light-emitting control circuit includes a first light-emitting control transistor, the gate of the first light-emitting control transistor is electrically connected to the first light-emitting control end to receive the first light-emitting control signal, the first electrode of the first light-emitting control transistor is electrically connected to the first end of the driving circuit, and the second electrode of the first light-emitting control transistor is electrically connected to the second voltage end to receive the second power supply voltage; the second light-emitting control circuit includes a second light-emitting control transistor, the gate of the second light-emitting control transistor is electrically connected to the second light-emitting control end to receive the second light-emitting control signal, the first electrode of the second light-emitting control transistor is electrically connected to the second end of the driving circuit, and the second electrode of the second light-emitting control transistor is electrically connected to the first electrode of the light-emitting element.

[0020] For example, according to the pixel circuit provided by at least one embodiment of the present disclosure, the pixel circuit also includes an auxiliary compensation circuit, the auxiliary compensation circuit includes a second compensation capacitor, the first electrode of the second compensation capacitor is electrically connected to the second end of the driving circuit, and the second electrode of the second compensation capacitor is configured to receive a first constant signal.

[0021] For example, according to the pixel circuit provided by at least one embodiment of the present disclosure, the second pole of the second compensation capacitor is electrically connected to the second voltage terminal, and the second power supply voltage serves as the first constant signal; or the second pole of the second compensation capacitor is electrically connected to the first reset signal terminal, and the first reset signal serves as the first constant signal; or the second pole of the second compensation capacitor is electrically connected to the external constant signal terminal outside the pixel circuit to receive the first constant signal from the external constant signal terminal.

[0022] For example, according to the pixel circuit provided by at least one embodiment of the present disclosure, the pixel circuit also includes an auxiliary circuit, the auxiliary circuit includes an auxiliary capacitor, the first pole of the auxiliary capacitor is electrically connected to the gate of the data writing transistor, and the second pole of the auxiliary capacitor is configured to receive a second constant signal.

[0023] For example, according to the pixel circuit provided by at least one embodiment of the present disclosure, the pixel circuit also includes a third reset circuit and a compensation control circuit, the control end of the third reset circuit is configured to receive a third reset control signal, the first end of the third reset circuit is electrically connected to the first end of the driving circuit, the second end of the third reset circuit is electrically connected to the control end of the driving circuit, and the third reset circuit is configured to allow the second power supply voltage to be applied to the control end of the driving circuit in response to the third reset control signal; the compensation control circuit includes a compensation control capacitor, the first electrode of the compensation control capacitor is electrically connected to the control end of the driving circuit, and the second electrode of the compensation control capacitor is electrically connected to the first electrode of the light-emitting element.

[0024] For example, according to the pixel circuit provided by at least one embodiment of the present disclosure, the driving circuit includes a driving transistor, the gate of the driving transistor serves as the control end of the driving circuit, the first electrode of the driving transistor serves as the first end of the driving circuit, and the second electrode of the driving transistor serves as the second end of the driving circuit; the third reset circuit includes a third reset transistor, the gate of the third reset transistor is electrically connected to the third reset control end to receive the third reset control signal, the first electrode of the third reset transistor is electrically connected to the first electrode of the driving transistor, and the second electrode of the third reset transistor is electrically connected to the gate of the driving transistor.

[0025] At least one embodiment of the present disclosure further provides a display device, which includes the pixel circuit described in any of the above embodiments.

[0026] At least one embodiment of the present disclosure also provides a driving method for a pixel circuit, which is applicable to the pixel circuit described in any of the above embodiments. The driving method includes: in the data writing and compensation stage, setting the data scanning signal to an on signal to turn on the data writing transistor, and writing the data signal into the second end of the driving circuit through the data writing transistor and the first compensation capacitor.

[0027] For example, according to the driving method of the pixel circuit provided by at least one embodiment of the present disclosure, the pixel circuit also includes a data writing circuit, the control end of the data writing circuit is configured to receive a data scanning signal, the first end of the data writing circuit is electrically connected to the second end of the driving circuit, and the second end of the data writing circuit is electrically connected to the data signal end to receive the data signal; the driving method also includes: in the data writing and compensation stage, making the data scanning signal a turn-on signal to write the data signal to the second end of the driving circuit; and when entering the light-emitting stage from the data writing and compensation stage, making the data scanning signal change from a turn-on signal to a turn-off signal to turn off the data writing transistor, wherein, in the light-emitting stage, the data scanning signal remains an off signal.

[0028] For example, according to the driving method of the pixel circuit provided by at least one embodiment of the present disclosure, in the step of writing the data signal into the second end of the driving circuit through the data writing transistor and the first compensation capacitor, the difference between the initial voltage value Vc11 of the first electrode of the first compensation capacitor before entering the data writing and compensation stage and its stable voltage value Vc12 during the data writing and compensation stage is a first change amount △Vc1, and the difference between the initial voltage value Vc13 of the second electrode of the first compensation capacitor before entering the data writing and compensation stage and its stable voltage value Vc14 during the data writing and compensation stage is a second change amount △Vc2, and the first change amount △Vc1 is equal to the second change amount △Vc2.

[0029] For example, according to the driving method of the pixel circuit provided by at least one embodiment of the present disclosure, the pixel circuit also includes an auxiliary compensation circuit, and the auxiliary compensation circuit includes a second compensation capacitor, wherein the first electrode of the second compensation capacitor is electrically connected to the second end of the driving circuit, and the second electrode of the second compensation capacitor is configured to receive a first constant signal; in the step of writing the data signal to the second end of the driving circuit through the data writing transistor and the first compensation capacitor, the first compensation capacitor and the second compensation capacitor are connected in series, and in the data writing and compensation stage, the voltage Vc3 of the second end of the driving circuit is Vc3 = (Vdata-Vref) × [C1 / (C1+C2)] + Vini1, where Vdata represents the value of the data signal, Vref represents the initial voltage value of the first electrode of the first compensation capacitor before entering the data writing and compensation stage, C1 represents the capacitance value of the first compensation capacitor, C2 represents the capacitance value of the second compensation capacitor, and Vini1 represents the initial voltage value of the second end of the driving circuit before entering the data writing and compensation stage.

[0030] For example, according to the driving method of the pixel circuit provided by at least one embodiment of the present disclosure, the pixel circuit also includes: a light-emitting element, a first reset circuit, a second reset circuit, a third reset circuit, a first light-emitting control circuit and a second light-emitting control circuit, the second end of the driving circuit is electrically connected to the first electrode of the light-emitting element, and the driving circuit is configured to control the magnitude of the driving current flowing through the light-emitting element; the control end of the first reset circuit is configured to receive a first reset control signal, the first end of the first reset circuit is electrically connected to the first electrode of the first compensation capacitor, and the second end of the first reset circuit is electrically connected to the reference signal end to receive a reference signal; the control end of the second reset circuit is configured to receive the first reset control signal. a first reset control signal, a first end of the second reset circuit is electrically connected to the first electrode of the light-emitting element, and a second end of the second reset circuit is electrically connected to the first reset signal end to receive the first reset signal; a control end of the third reset circuit is configured to receive a third reset control signal, a first end of the third reset circuit is electrically connected to the first end of the drive circuit, and a second end of the third reset circuit is electrically connected to the control end of the drive circuit; a control end of the first light-emitting control circuit is configured to receive a first light-emitting control signal, a first end of the first light-emitting control circuit is electrically connected to the first end of the drive circuit, and a second end of the first light-emitting control circuit is electrically connected to the second voltage end to receive a second power supply voltage; The control end of the second light-emitting control circuit is configured to receive a second light-emitting control signal, the first end of the second light-emitting control circuit is electrically connected to the second end of the drive circuit, and the second end of the second light-emitting control circuit is electrically connected to the first electrode of the light-emitting element; the driving method further includes: in a reset stage before the compensation stage, making the first reset control signal a turn-on signal to turn on the first reset circuit, wherein the first reset circuit applies the reference signal to the first electrode of the first compensation capacitor; making the first light-emitting control signal a turn-on signal to turn on the first light-emitting control circuit, wherein the first light-emitting control circuit applies the second power supply voltage to the first end of the drive circuit; making the third The reset control signal is a start signal to start the third reset circuit, wherein the third reset circuit applies the second power supply voltage to the control terminal of the drive circuit; the second reset control signal is set to a start signal to start the second reset circuit, wherein the second reset circuit applies the first reset signal to the first electrode of the light-emitting element; and the second light-emitting control signal is set to a start signal to start the second light-emitting control circuit; the first reset signal is applied to the second terminal of the drive circuit via the second light-emitting control circuit, and the value of the first reset signal is Vini1, so that the initial voltage value of the second terminal of the drive circuit before entering the data writing and compensation phase is Vini1;Alternatively, the pixel circuit further includes a direct reset circuit, wherein a control terminal of the direct reset circuit is configured to receive a direct reset control signal, a first terminal of the direct reset circuit is electrically connected to a second terminal of the driving circuit, and a second terminal of the direct reset circuit is electrically connected to a second reset signal terminal to receive a second reset signal. During the light-emitting phase, the driving method further includes: setting the direct reset control signal to an on signal to turn on the direct reset circuit, applying the second reset signal to the second terminal of the driving circuit, the value of the second reset signal being Vini2, so that an initial voltage value of the second terminal of the driving circuit before entering the data writing and compensation phase is Vini2.

[0031] For example, according to the driving method of the pixel circuit provided by at least one embodiment of the present disclosure, the pixel circuit also includes a compensation control circuit, and the compensation control circuit includes a compensation control capacitor, wherein the first electrode of the compensation control capacitor is electrically connected to the gate of the driving transistor, and the second electrode of the compensation control capacitor is electrically connected to the first electrode of the light-emitting element; the driving method also includes: in the data writing and compensation stage, setting the second reset control signal to a turn-on signal to turn on the second reset circuit, wherein the second reset circuit applies the first reset signal to the first electrode of the light-emitting element and the second electrode of the compensation control capacitor. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present disclosure, rather than limiting the present disclosure.

[0033] FIG1 is a schematic block diagram of a pixel circuit provided by at least one embodiment of the present disclosure.

[0034] FIG. 2A is a circuit diagram of an implementation example of the pixel circuit shown in FIG. 1 .

[0035] FIG. 2B is a schematic diagram of the pixel circuit shown in FIG. 2A in a data writing and compensation stage.

[0036] FIG. 2C is a schematic diagram of the pixel circuit shown in FIG. 2A in a light emitting stage.

[0037] FIG3 is a signal timing diagram of a driving method provided by at least one embodiment of the present disclosure.

[0038] FIG4 is a schematic block diagram of another pixel circuit provided by at least one embodiment of the present disclosure.

[0039] FIG. 5A is a circuit diagram of an implementation example of the pixel circuit shown in FIG. 4 .

[0040] FIG. 5B is a schematic diagram of the pixel circuit shown in FIG. 5A in a data writing and compensation stage.

[0041] FIG5C is a schematic diagram of the pixel circuit shown in FIG5A in a light emitting stage.

[0042] FIG6 is a signal timing diagram of another driving method provided by at least one embodiment of the present disclosure.

[0043] FIG7 is a schematic block diagram of yet another pixel circuit provided by at least one embodiment of the present disclosure.

[0044] FIG8A is a circuit diagram of an implementation example of the pixel circuit shown in FIG7 .

[0045] FIG8B is a schematic diagram of the pixel circuit shown in FIG8A in a reset phase.

[0046] FIG. 8C is a schematic diagram of the pixel circuit shown in FIG. 8A in a data writing and compensation stage.

[0047] FIG8D is a schematic diagram of the pixel circuit shown in FIG8A in a light emitting stage.

[0048] FIG9 is a signal timing diagram of another driving method provided by at least one embodiment of the present disclosure.

[0049] FIG10 is a schematic block diagram of yet another pixel circuit provided by at least one embodiment of the present disclosure.

[0050] FIG. 11A is a circuit diagram of an implementation example of the pixel circuit shown in FIG. 10 .

[0051] FIG11B is a schematic diagram of the pixel circuit shown in FIG11A in a reset phase.

[0052] FIG. 11C is a schematic diagram of the pixel circuit shown in FIG. 11A in the data writing and compensation stage.

[0053] FIG11D is a schematic diagram of the pixel circuit shown in FIG11A in a light emitting stage.

[0054] FIG12 is a signal timing diagram of another driving method provided by at least one embodiment of the present disclosure.

[0055] FIG13 is a schematic block diagram of yet another pixel circuit provided by at least one embodiment of the present disclosure.

[0056] FIG14A is a circuit diagram of an implementation example of the pixel circuit shown in FIG13 .

[0057] FIG. 14B is a schematic diagram of the pixel circuit shown in FIG. 13 in the data writing and compensation stage.

[0058] FIG14C is a schematic diagram of the pixel circuit shown in FIG13 in a light emitting stage.

[0059] FIG15 is a schematic block diagram of yet another pixel circuit provided by at least one embodiment of the present disclosure.

[0060] FIG16 is a circuit diagram of an implementation example of the pixel circuit shown in FIG15 .

[0061] FIG17 is a schematic block diagram of yet another pixel circuit provided by at least one embodiment of the present disclosure.

[0062] FIG18 is a circuit diagram of an implementation example of the pixel circuit shown in FIG17 .

[0063] FIG19 is a circuit diagram of another implementation example of the pixel circuit shown in FIG1 .

[0064] FIG20 is a schematic block diagram of a display device provided by at least one embodiment of the present disclosure. DETAILED DESCRIPTION

[0065] To make the purpose, technical solutions, and advantages of the embodiments of the present disclosure more clear, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0066] Unless otherwise defined, technical or scientific terms used in this disclosure should have the ordinary meanings understood by people with ordinary skills in the field to which this disclosure belongs. The words "first", "second" and similar terms used in this disclosure do not indicate any order, quantity or importance, but are simply used to distinguish different components. The words "include" or "comprising" and similar terms mean that the elements or objects preceding the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects.

[0067] The features "perpendicular," "parallel," and "identical" used in the embodiments of the present disclosure include the features "perpendicular," "parallel," and "identical" in the strict sense, as well as "approximately perpendicular," "approximately parallel," and "approximately identical" that include certain errors, taking into account the errors associated with the measurement of specific quantities (i.e., the limitations of the measurement system), and represent within the acceptable deviation range for the specific value determined by ordinary technicians in this field. The "center" in the embodiments of the present disclosure can include a position strictly at the geometric center and a position approximately at the center of a small area around the geometric center.

[0068] Typically, in a pixel circuit, the first electrode of the data write transistor can be electrically connected to the first electrode of the drive transistor, so that a data signal can be written to the first electrode of the drive transistor. During the driving process of the pixel circuit, when the pixel circuit enters the light-emitting phase, the data write transistor will switch from an on state to an off state. However, due to the parasitic capacitance between the gate of the data write transistor and its first electrode, the voltage of the first electrode of the data write transistor may decrease at the moment the data write transistor is turned off, thereby reducing the voltage of the first electrode of the drive transistor, and further reducing the gate-source voltage Vgs of the drive transistor during the light-emitting phase, affecting the magnitude of the drive current.

[0069] For example, when the gate-source voltages Vgs of the driving transistors of multiple sub-pixels in a display panel are reduced to varying degrees when entering the light-emitting phase, the brightness of the multiple sub-pixels will be different, which in turn affects the brightness uniformity of the entire display panel. In addition, because the pixel circuit includes multiple transistors, multiple capacitors, and multiple signal lines, the internal compensation structure of the pixel circuit is complex. For example, some signal lines may have parasitic capacitances between the first electrode of the driving transistor. When the voltage signals of these signal lines change, the voltage of the first electrode of the driving transistor may fluctuate, thereby causing crosstalk. For example, it may cause the light-emitting element to suddenly emit light, resulting in abnormal image quality of the display panel and affecting the display effect.

[0070] At the same time, some display devices may have short-term afterimages when displaying. That is, after the display device displays the same image for a period of time, when the current displayed image is switched to the next image, the original image will partially remain and appear in the next image, and then after a period of time, the afterimage will disappear. The reason for the short-term afterimage may be that the driving transistor in the pixel circuit has a hysteresis effect. The hysteresis effect is mainly caused by the threshold voltage (Vth) shift caused by the mobile ions remaining in the holes. When the display device switches the screen, the gate-source voltage Vgs of the driving transistor (the voltage difference between the gate and source of the driving transistor) may be different, so it may cause the threshold voltage of the driving transistor to shift. For example, after the display device displays the initial image for a period of time, when the display device switches to a new image, the initial image will still partially remain for several hours, thereby affecting the display. For example, in the low grayscale driving process, the gate-source voltage Vgs of the driving transistor is more likely to fluctuate due to the shift of its threshold voltage (Vth).

[0071] At least one embodiment of the present disclosure provides a pixel circuit, a driving method thereof, and a display device.

[0072] At least one embodiment of the present disclosure provides a pixel circuit including a driving circuit and a data writing circuit, the driving circuit including a control end, a first end, and a second end, and is configured to control the magnitude of the driving current flowing through the first end and the second end; the data writing circuit including a first end and a second end, the first end of the data writing circuit being electrically connected to the second end of the driving circuit, the second end of the data writing circuit being configured to receive a data signal, the data writing circuit being configured to write the data signal to the second end of the driving circuit in response to a data scanning signal, and including a data writing transistor and a first compensation capacitor, the gate of the data writing transistor being configured to receive the data scanning signal, and the first electrode of the first compensation capacitor being electrically connected to the first electrode of the data writing transistor.

[0073] The pixel circuit provided by at least one embodiment of the present disclosure electrically connects the first electrode of the first compensation capacitor to the first electrode of the data writing transistor, thereby reducing the influence of the data writing transistor on the voltage of the second end of the driving circuit when the pixel circuit switches to the light-emitting stage, so that the fluctuation of the gate-source voltage Vgs of the driving transistor in the light-emitting stage is smaller, thereby improving the uniformity of the brightness of the display panel; at the same time, it can also reduce the influence of the fluctuation of the data writing signal on the voltage of the second end of the driving circuit. Therefore, the pixel circuit provided by the embodiment of the present disclosure is of great significance for stabilizing the gate-source voltage Vgs of the driving circuit and improving the display effect of the display device.

[0074] The pixel circuit and its driving method, and the display device provided by the embodiments of the present disclosure are described below with reference to the accompanying drawings.

[0075] FIG1 is a schematic block diagram of a pixel circuit provided by at least one embodiment of the present disclosure.

[0076] As shown in Figure 1, the pixel circuit 10 includes a driving circuit 100, a data writing circuit 200 (first reset circuit 300), a light-emitting element 400, a second reset circuit 500, a first light-emitting control circuit 600, a second light-emitting control circuit 700, a third reset circuit 800 and a compensation control circuit 900.

[0077] As shown in FIG1 , the driving circuit 100 includes a control terminal 100m, a first terminal 100a, and a second terminal 100b. The first terminal 100a of the driving circuit 100 is electrically connected to a first node N1, the control terminal 100m of the driving circuit 100 is electrically connected to a second node N2, and the second terminal 100b of the driving circuit 100 is electrically connected to a third node N3. The driving circuit 100 is configured to control the magnitude of a driving current flowing through the first terminal 100a and the second terminal 100b. For example, the driving current can be used to drive the light-emitting element 400 to emit light. For example, during the light-emitting phase, the driving circuit 100 can provide a driving current to the light-emitting element 400 to drive the light-emitting element 400 to emit light, and the light can be emitted at a desired "grayscale."

[0078] As shown in FIG1 , the data write circuit 200 includes a control terminal 200m, a first terminal 200a, and a second terminal 200b. The control terminal 200m of the data write circuit 200 is configured to receive a data scan signal G1. The first terminal 200a of the data write circuit 200 is electrically connected to the second terminal 100b of the driver circuit 100. The second terminal 200b of the data write circuit 200 is electrically connected to the data signal terminal DATA to receive the data signal DATA. The data write circuit 200 includes a data write transistor T1 and a first compensation capacitor Cst1 (see FIG2A ). The gate of the data write transistor T1 is configured to receive the data scan signal G1, and the first electrode of the first compensation capacitor Cst1 is electrically connected to the first electrode of the data write transistor T1. For example, during the data write and compensation phase, the data write circuit 200 is turned on in response to the data scan signal G1. The data write transistor T1 and the first compensation capacitor Cst1 cooperate to write the data signal DATA to the second terminal 100m of the driver circuit 100.

[0079] As shown in Figure 1 , the first reset circuit 300 includes a control terminal 300m, a first terminal 300a, and a second terminal 300b. The control terminal 300m of the first reset circuit 300 is configured to receive a first reset control signal RST1. The first terminal 300a of the first reset circuit 300 is electrically connected to the second terminal 100b of the driver circuit 100. The first reset circuit 300 includes a first reset transistor T2. Here, the data transistor T1 is multiplexed as the first reset transistor T2. The first electrode of the first reset transistor T2 is electrically connected to the first electrode of the first compensation capacitor Cst1. The second terminal 300b of the first reset circuit 300 is electrically connected to the reference signal terminal REF to receive a reference signal REF. The first reset circuit 300 is configured to write the reference signal REF to the second terminal 100b of the driver circuit 100 in response to the first reset control signal RST1 and the first compensation capacitor Cst1. For example, the reference signal REF can be a reference voltage. For example, in some embodiments of the present disclosure, as shown in FIG1 , the first reset circuit 300 includes a first reset transistor T2 (see FIG2A ), and the data write transistor T1 can be reused as the first reset transistor T2 to simplify the structure of the pixel circuit. For example, in some embodiments, the data write circuit 200 and the first reset circuit 300 can also be independent of each other and controlled separately. The specific setting can be based on design requirements, and the embodiments of the present disclosure are not limited to this.

[0080] As shown in FIG1 , the light-emitting element 400 includes a first electrode 400a and a second electrode 400b, and the light-emitting element 400 is configured to emit light under the drive of a driving current. The second terminal 100b of the driving circuit 100 is electrically connected to the first electrode 400a of the light-emitting element 400, and the driving circuit 100 is configured to control the magnitude of the driving current flowing through the light-emitting element 400. For example, in one example, as shown in FIG1 , the first electrode 400a of the light-emitting element 400 is electrically connected to the fourth node N4, and the light-emitting element 400 can be electrically connected to the second terminal 100b of the driving circuit 100 via the second light-emitting control circuit 700. Embodiments of the present disclosure include but are not limited to this situation. The second electrode 400b of the light-emitting element 400 is electrically connected to the first voltage terminal VSS to receive the first power supply voltage VSS. For example, the first voltage terminal VSS can be grounded, that is, the first power supply voltage VSS can be 0V. For example, the first power supply voltage VSS can be a negative voltage. For example, the light-emitting element can be implemented as a light-emitting diode (LED), such as an organic light-emitting diode (OLED), a quantum dot light-emitting diode (QLED) or an inorganic light-emitting diode, such as a micro light-emitting diode (Micro LED) or a micro OLED. The embodiments of the present disclosure do not limit the type of the light-emitting element.

[0081] The second reset circuit 500 includes a control terminal 500m, a first terminal 500a, and a second terminal 500b. The control terminal 500m of the second reset circuit 500 is configured to receive a second reset control signal RST2. The first terminal 500a of the second reset circuit 500 is electrically connected to the first electrode 400a of the light-emitting element 400. The second terminal 500b of the second reset circuit 500 is electrically connected to the first reset signal terminal VINI1 to receive the first reset signal VINI1. The second reset circuit 500 is configured to apply the first reset signal VINI1 to the first electrode 400a of the light-emitting element 400 and the second terminal 100b of the driving circuit 100 in response to the second reset control signal RST2, thereby achieving a reset operation.

[0082] The first light-emitting control circuit 600 includes a control terminal 600m, a first terminal 600a, and a second terminal 600b. The control terminal 600m of the first light-emitting control circuit 600 is configured to receive a first light-emitting control signal EM1. The first terminal 600a of the first light-emitting control circuit 600 is electrically connected to the first terminal 100a of the driver circuit 100. The second terminal 600b of the first light-emitting control circuit 600 is electrically connected to the second voltage terminal ELVDD to receive the second power supply voltage ELVDD. The first light-emitting control circuit 600 is configured to apply the second power supply voltage ELVDD to the first terminal 100a of the driver circuit 100 in response to the first light-emitting control signal EM1. For example, during a reset phase, the first light-emitting control circuit 600 can be turned on in response to the first light-emitting control signal EM1, thereby applying the second power supply voltage ELVDD to the first terminal 100a of the driver circuit 100. For example, during the light-emitting phase, the first light-emitting control circuit 600 may also be turned on in response to the first light-emitting control signal EM1, thereby applying the second power supply voltage ELVDD to the first terminal 100a of the driver circuit 100. When the driver circuit 100 is turned on, the second power supply voltage ELVDD is written to the second terminal 100b of the driver circuit 100. The second terminal 400b of the light-emitting element 400 receives the first power supply voltage VSS, and the light-emitting element 400 emits light under the influence of the second power supply voltage ELVDD and the first power supply voltage VSS. For example, the second power supply voltage ELVDD can be a high voltage, and the first power supply voltage VSS can be a low voltage, but the embodiments of the present disclosure are not limited to this.

[0083] As shown in FIG1 , the second light-emitting control circuit 700 includes a control terminal 700m, a first terminal 700a, and a second terminal 700b. The control terminal 700m of the second light-emitting control circuit 700 is configured to receive a second light-emitting control signal EM2. The first terminal 700a of the second light-emitting control circuit 700 is electrically connected to the second terminal 100b of the driver circuit 100, and the second terminal 700b of the second light-emitting control circuit 700 is electrically connected to the first electrode 400a of the light-emitting element 400. The second light-emitting control circuit 700 is configured to apply a driving current to the light-emitting element 400 in response to the second light-emitting control signal EM2 and to allow the first reset signal VINI1 to be applied to the second terminal 100b of the driver circuit 100 via the second light-emitting control circuit 700. For example, during the light-emitting phase, the second light-emitting control circuit 700 is turned on in response to the second light-emitting control signal EM2, so that the driver circuit 100 can apply a driving current to the light-emitting element 400 via the second light-emitting control circuit 700 to cause the light-emitting element 400 to emit light. For example, during the reset phase, the second light-emitting control circuit 700 may also be turned on in response to the second light-emitting control signal EM2, thereby allowing the first reset signal VINI1 to be applied to the second terminal 100b of the driver circuit 100 in conjunction with other circuit components (e.g., the second reset circuit 500), thereby achieving a reset operation for the driver circuit 100 and the light-emitting element 400. For example, during the data writing and compensation phase, the second light-emitting control circuit 700 may be turned off in response to the second light-emitting control signal EM2, thereby preventing the light-emitting element 400 from emitting light, thereby improving the contrast of the corresponding display device. For example, the first reset signal VINI1 may be a first reset voltage.

[0084] For example, as shown in FIG1 , the second light-emitting control signal EM2 is different from the first light-emitting control signal EM1. For example, the second light-emitting control signal EM2 can be electrically connected to different signal output terminals. For example, during the reset phase and the light-emitting phase, the first light-emitting control signal EM1 and the second light-emitting control signal EM2 are both on signals. For example, during the data writing and compensation phases, the first light-emitting control signal EM1 and the second light-emitting control signal EM2 are both off signals to prevent the light-emitting element 400 from emitting light. For example, in some embodiments of the present disclosure, the first light-emitting control circuit 600 and the second light-emitting control circuit 700 can share the same control terminal to simplify the pixel circuit structure and control method, but the embodiments of the present disclosure are not limited to this.

[0085] As shown in FIG1 , the third reset circuit 800 includes a control terminal 800m, a first terminal 800a, and a second terminal 800b. The control terminal 800m of the third reset circuit 800 is configured to receive a third reset control signal RST3. The first terminal 800a of the third reset circuit 800 is electrically connected to the first terminal 100a of the driver circuit 100, and the second terminal 800b of the third reset circuit 800 is electrically connected to the control terminal 100m of the driver circuit 100. The third reset circuit 800 is configured to allow the second power supply voltage ELVDD to be applied to the control terminal 100m of the driver circuit 100 in response to the third reset control signal RST3. For example, during a reset phase, the third reset circuit 800 is turned on in response to the third reset control signal RST3, thereby allowing the second power supply voltage ELVDD to be applied to the control terminal 100m of the driver circuit 100, thereby resetting the driver circuit 100.

[0086] As shown in FIG1 , the compensation control circuit 900 includes a first terminal 900a and a second terminal 900b. The first terminal 900a of the compensation control circuit 900 is electrically connected to the control terminal 100m of the driving circuit 100, and the second terminal 900b of the compensation control circuit 900 is electrically connected to the first electrode 400a of the light-emitting element 400. For example, the compensation control circuit 900 may include a compensation control capacitor Ca (as shown in FIG2A ), wherein a first terminal of the compensation control capacitor Ca is electrically connected to the control terminal 100m of the driving circuit 100, and a second terminal of the compensation control capacitor Ca is electrically connected to the first electrode 400a of the light-emitting element 400. For example, when the light-emitting stage is entered from the data writing and compensation stage, when the voltage of the first electrode 400a of the light-emitting element 400 increases, the compensation control capacitor Ca can play a bootstrap role, thereby increasing the voltage of the control terminal 100m of the driving circuit 100, thereby facilitating the driving circuit 100 to be in the on state, thereby causing the light-emitting element 400 to emit light.

[0087] FIG2A is a circuit diagram of an implementation example of the pixel circuit shown in FIG1 ; FIG3 is a signal timing diagram of a driving method provided by at least one embodiment of the present disclosure.

[0088] For example, the pixel circuit shown in FIG1 can be implemented as the pixel circuit structure shown in FIG2A . As shown in FIG2A , the pixel circuit 101 includes: a driving transistor DT, a data writing transistor T1 (a first reset transistor T2), a second reset transistor T3, a first emission control transistor T4, a second emission control transistor T5, a third reset transistor T6, a first compensation capacitor Cst1, a compensation control capacitor Ca, and a light-emitting element OLED. For example, the data writing transistor T1 (a first reset transistor T2), the first reset transistor T2, the second reset transistor T3, the first emission control transistor T4, the second emission control transistor T5, and the third reset transistor T6 are used as switching transistors. For example, the embodiments of the present disclosure are described using an OLED as an example, but are not limited to this. For example, the light-emitting element may also be other light-emitting devices, and the embodiments of the present disclosure are not limited to this. For example, when the light-emitting element is an OLED, the light-emitting element may be of various types, such as top emission, bottom emission, etc., and may emit red light, green light, blue light, or white light, and the embodiments of the present disclosure are not limited to this.

[0089] For example, as shown in Figures 1 and 2A, the driving circuit 100 includes a driving transistor DT, a first electrode of the driving transistor DT serving as a first end 100a of the driving circuit 100, electrically connected to a first node N1; a gate of the driving transistor DT serving as a control end 100m of the driving circuit 100, electrically connected to a second node N2; and a second electrode of the driving transistor DT serving as a second end 100b of the driving circuit 100, electrically connected to a third node N3.

[0090] For example, as shown in Figures 1 and 2A, the data write circuit 200 includes a data write transistor T1 and a first compensation capacitor Cst1, the gate of the data write transistor T1 is electrically connected to the data scan signal terminal G1 to receive the data scan signal G1, the first electrode of the data write transistor T1 is electrically connected to the first electrode of the first compensation capacitor Cst1, the second electrode of the data write transistor T1 is electrically connected to the data signal terminal DATA to receive the data signal DATA, and the second electrode of the first compensation capacitor Cst1 is electrically connected to the second electrode of the driving transistor DT.

[0091] For example, as shown in Figures 1 and 2A, the first reset circuit 300 includes a first reset transistor T2, the gate of the first reset transistor T2 is electrically connected to the first reset control terminal RST1 to receive the first reset control signal RST1, the first electrode of the first reset transistor T2 is electrically connected to the first electrode of the first compensation capacitor Cst1, and the second electrode of the first reset transistor T2 is electrically connected to the reference signal terminal REF to receive the reference signal REF.

[0092] For example, as shown in Figures 1 and 2A, the data write transistor T1 is multiplexed as the first reset transistor T2, and the data scan signal G1 is multiplexed as the first reset control signal RST1. The second electrode of the data write transistor T1 is also electrically connected to the reference signal terminal REF to receive the reference signal REF, and is configured to apply the reference signal REF to the second terminal 100b of the driving circuit 100 with the first compensation capacitor Cst1. For example, in the pixel circuit 101 shown in Figure 2A, the data signal terminal DATA is multiplexed as the reference signal terminal REF, and the data signal terminal DATA is configured to receive the data signal DATA and the reference signal REF in different time periods. In this way, the data signal terminal DATA can receive different signals in different time periods according to the working requirements of the pixel circuit, thereby simplifying the structure of the pixel circuit.

[0093] For example, in some embodiments of the present disclosure, referring to FIG1 and FIG2A , the data signal terminal DATA and the reference signal terminal REF may also be independent signal terminals, and both the data signal terminal DATA and the reference signal terminal REF are electrically connected to the second electrode of the data write transistor T1. For example, during different time periods, the data signal terminal DATA may apply the data signal DATA to the second electrode of the data write transistor T1, and the reference signal terminal REF may apply the reference signal REF to the second electrode of the data write transistor T1, thereby making the control method of the pixel circuit more flexible.

[0094] For example, as shown in Figures 1 and 2A, the second reset circuit 500 includes a second reset transistor T3, the gate of the second reset transistor T3 is electrically connected to the second reset control terminal RST2 to receive the second reset control signal RST2, the first electrode of the second reset transistor T3 is electrically connected to the first electrode of the light-emitting element OLED, and the second electrode of the second reset transistor T3 is electrically connected to the first reset signal terminal VINI1 to receive the first reset signal VINI1.

[0095] For example, as shown in Figures 1 and 2A, the first light-emitting control circuit 600 includes a first light-emitting control transistor T4, the gate of which is electrically connected to the first light-emitting control terminal EM1 to receive the first light-emitting control signal EM1, the first electrode of the first light-emitting control transistor T4 is electrically connected to the first terminal 100a of the driving circuit 100 (the first electrode of the driving transistor DT), and the second electrode of the first light-emitting control transistor T4 is electrically connected to the second voltage terminal ELVDD to receive the second power supply voltage ELVDD.

[0096] For example, as shown in Figures 1 and 2A, the second light-emitting control circuit 700 includes a second light-emitting control transistor T5, a gate of the second light-emitting control transistor T5 is electrically connected to the second light-emitting control terminal EM2 to receive the second light-emitting control signal EM2, a first electrode of the second light-emitting control transistor T5 is electrically connected to the second terminal 100b of the driving circuit 100 (the second electrode of the driving transistor DT), and a second electrode of the second light-emitting control transistor T5 is electrically connected to the first electrode of the light-emitting element OLED.

[0097] For example, as shown in Figures 1 and 2A, the third reset circuit 800 includes a third reset transistor T6, the gate of the third reset transistor T6 is electrically connected to the third reset control terminal RST3 to receive the third reset control signal RST3, the first electrode of the third reset transistor T6 is electrically connected to the first electrode (first node N1) of the driving transistor DT, and the second electrode of the third reset transistor T6 is electrically connected to the gate (second node N2) of the driving transistor DT.

[0098] For example, as shown in FIG1 and FIG2A, the first electrode of the compensation control capacitor Ca is electrically connected to the gate (second node N2) of the driving transistor DT, and the second electrode of the compensation control capacitor Ca is electrically connected to the first electrode (fourth node N4) of the light emitting element OLED.

[0099] For example, as shown in Figures 1 and 2A, the light-emitting element 400 can be implemented as an organic light-emitting diode (OLED). In the embodiments described below, the light-emitting element is an OLED as an example, and the embodiments of the present disclosure include but are not limited to this. The light-emitting element can also be other types of electroluminescent devices such as inorganic light-emitting diodes, and the embodiments of the present disclosure do not limit the type of light-emitting element.

[0100] It should be noted that in the description of the embodiments of the present disclosure, the first node N1, the second node N2, the third node N3 and the fourth node N4 do not necessarily represent actual components, but represent the junction points of related circuit connections in the circuit diagram. In the description of the embodiments of the present disclosure, the symbol DATA can represent both a data signal terminal and a data signal; similarly, the symbol G1 can represent both a data scan signal terminal and a data scan signal; the symbol REF can represent both a reference signal terminal and a reference signal; the symbol RST1 can represent both a first reset control signal terminal and a first reset control signal; the symbol RST2 can represent both a second reset control signal terminal and a second reset control signal; the symbol RST3 can represent both a third reset control signal terminal and a third reset control signal; the symbol VSS can represent both a first voltage terminal and a first power supply voltage; the symbol ELVDD can represent both a second voltage terminal and a second power supply voltage; the symbol EM1 can represent both a first light-emitting control terminal and a first light-emitting control signal; the symbol EM2 can represent both a second light-emitting control terminal and a second light-emitting control signal; the symbol VINI1 can represent both a first reset signal terminal and a first reset signal; the symbol VINI2 can represent both a second reset signal terminal and a second reset signal. The following embodiments are the same and will not be repeated here.

[0101] It should be noted that the transistors used in the embodiments of the present disclosure may be thin film transistors, field effect transistors, or other switching devices with the same characteristics. The embodiments of the present disclosure are described using thin film transistors as examples. The source and drain of the transistors used here may be symmetrical in structure, so the source and drain may be structurally indistinguishable. In the embodiments of the present disclosure, in order to distinguish the two poles of the transistor other than the gate, one pole is directly described as the first pole and the other pole is directly described as the second pole.

[0102] In addition, transistors can be divided into N-type and P-type transistors according to their characteristics. When the transistor is a P-type transistor, the turn-on voltage is a low-level voltage (for example, 0V, -5V, -10V, or other suitable voltages), and the turn-off voltage is a high-level voltage (for example, 5V, 10V, or other suitable voltages); when the transistor is an N-type transistor, the turn-on voltage is a high-level voltage (for example, 5V, 10V, or other suitable voltages), and the turn-off voltage is a low-level voltage (for example, 0V, -5V, -10V, or other suitable voltages). However, the embodiments of the present disclosure do not limit the type of transistor. When the type of transistor changes, the connection relationship in the circuit can be adjusted accordingly.

[0103] The working principle of the pixel circuit 101 shown in FIG2A is described below in conjunction with the signal timing diagram shown in FIG3. As shown in FIG3, the display process of each frame of image includes three stages, namely reset stage 1, data writing and compensation stage 2, and light emitting stage 3.

[0104] It should be noted that FIG2A is a schematic diagram of the pixel circuit 101 in the reset phase; FIG2B is a schematic diagram of the pixel circuit 101 shown in FIG2A in the data writing and compensation phase; and FIG2C is a schematic diagram of the pixel circuit 101 shown in FIG2A in the light emitting phase. Furthermore, the transistors marked with dashed lines in FIG2B and FIG2C are all in the off state during the corresponding phase.

[0105] For example, in the pixel circuit 101 shown in Figure 2A, the driving transistor DT, the data writing transistor T1 (first reset transistor T2), the second reset transistor T3, the first light-emitting control transistor T4, the second light-emitting control transistor T5 and the third reset transistor T6 are all N-type transistors, that is, each transistor is turned on when a high-level signal is connected to its gate, and is turned off when a low-level signal is connected.

[0106] As shown in FIG2B and FIG3, an embodiment of the present disclosure provides a driving method, which includes: in a data writing and compensation phase, setting a data scanning signal G1 as a turn-on signal to turn on a data writing transistor T1, and writing a data signal DATA to a second terminal 100b (i.e., a second electrode of a driving transistor DT) of a driving circuit 100 via the data writing transistor T1 and a first compensation capacitor Cst1. For the pixel circuit 101, when the data writing transistor T1 is turned on, the data signal DATA is first applied to the first electrode of the first compensation capacitor Cst1, thereby causing the voltage of the second electrode of the driving transistor DT to change due to the change in the voltage of the second electrode of the first compensation capacitor Cst1, thereby causing the voltage of the second electrode of the driving transistor DT to reach a specific value. For example, when entering the light-emitting stage 3 from the data writing and compensation stage 2, the data writing transistor T1 changes from the on state to the off state. Since there is a parasitic capacitance between the gate of the data writing transistor T1 and its first electrode, and under the voltage dividing effect of the parasitic capacitance and the first compensation capacitor Cst1, the change in the voltage of the first electrode of the first compensation capacitor Cst1 can be made smaller, and then the change in the voltage of the second electrode of the first compensation capacitor Cst1 can also be made smaller, thereby reducing the influence of the data writing transistor T1 on the voltage of the second electrode of the driving transistor DT when it is turned off, which is beneficial to maintaining the stability of the driving current flowing through the driving transistor DT, so as to improve the uniformity of the brightness of the display panel.

[0107] Specifically, for example, as shown in FIG1 and FIG3, in the reset phase 1, the driving method includes: setting the first reset control signal RST1 as a start signal to start the first reset circuit 300, and the first reset circuit 300 applies the reference signal REF to the first electrode of the first compensation capacitor Cst1; and setting the first light-emitting control signal EM1 as a start signal to start the first light-emitting control circuit 600, and the first light-emitting control circuit 600 applies the second power supply voltage ELVDD to the first terminal 100a of the driving circuit 100; setting the third reset control signal RST3 as a start signal to start the third reset circuit 800, and the third reset circuit 800 applies the second power supply voltage ELVDD to the driving circuit 100. The control terminal 100m of the circuit 100; the second light-emitting control signal EM2 is set as a start signal to turn on the second light-emitting control circuit 700; and the second reset control signal RST2 is set as a start signal to turn on the second reset circuit 500. The second reset circuit 500 applies the first reset signal VINI1 to the first electrode 400a of the light-emitting element 400. The first reset signal VINI1 is applied to the second terminal 100b of the driving circuit 100 via the second light-emitting control circuit 700. The value of the first reset signal VINI1 is Vini1, so that the initial voltage value of the second terminal 100b of the driving circuit 100 before entering the data writing and compensation stage is Vini1.

[0108] Correspondingly, for example, as shown in FIG2A and FIG3 , in reset phase 1, in pixel circuit 101, since data write transistor T1 is multiplexed into first reset transistor T2, data scan signal G1 is multiplexed into first reset control signal RST1. Thus, data scan signal G1 is set to a high-level signal to turn on data write transistor T1, and reference signal REF can be applied to the first electrode of data write transistor T1, and further applied to the first electrode of first compensation capacitor Cst1. Furthermore, first emission control signal EM1 is set to a high-level signal to turn on first emission control transistor T4, and third reset control signal RST3 is set to a high-level signal to turn on third reset transistor T6. Thus, second power supply voltage ELVDD can be applied to the first electrode of drive transistor DT and then to the gate of drive transistor DT via third reset transistor T6. At the same time, the second light-emitting control signal EM2 is set to a high-level signal to turn on the second light-emitting control transistor T5, and the second reset control signal RST2 is set to a high-level signal to turn on the second reset transistor T3, so that the first reset signal VINI1 can be applied to the first electrode (the fourth node N4) of the light-emitting element OLED, and applied to the second electrode (the third node N3) of the driving transistor DT through the second light-emitting control transistor T5, so that the voltage value of the second electrode of the driving transistor DT and the voltage value of the first electrode of the light-emitting element OLED are both equal to the value Vini1 of the first reset signal VINI1.

[0109] For example, as shown in Figures 1 and 3, the driving method also includes: in the data writing and compensation stage 2, the data scanning signal G1 is set to a turn-on signal to turn on the data writing transistor T1, and the data signal DATA is written to the second end 100b of the driving circuit 100 (that is, the second electrode of the driving transistor DT) through the data writing transistor T1 and the first compensation capacitor Cst1, and the second reset control signal RST2 is set to a turn-on signal to turn on the second reset circuit 500, and the second reset circuit 500 applies the first reset signal VINI1 to the first electrode 400a of the light-emitting element 400 and the second electrode of the compensation control capacitor Ca.

[0110] Specifically, as shown in FIG2B and FIG3 , in the data writing and compensation phase 2, the second reset control signal RST2 is set to a high-level signal to turn on the second reset transistor T3, so that the first reset signal VINI1 can be applied to the first electrode (fourth node N4) of the light-emitting element OLED and the second electrode of the compensation control capacitor Ca, thereby making the voltage value of the first electrode (fourth node N4) of the light-emitting element OLED equal to the value Vini1 of the first reset signal VINI1, thereby preventing the light-emitting element OLED from emitting light in the data writing and compensation phase 2. At the same time, the data scanning signal G1 is set to a high-level signal to turn on the data writing transistor T1, so that the data signal DATA is applied to the first electrode of the first compensation capacitor Cst1.

[0111] For example, as shown in Figures 2B and 3, in the data writing and compensation stage 2, the difference between the initial voltage value Vc11 of the first electrode of the first compensation capacitor Cst1 before entering the data writing and compensation stage and its stable voltage value Vc12 during the data writing and compensation stage is a first change amount △Vc1; the difference between the initial voltage value Vc13 of the second electrode of the first compensation capacitor Cst1 before entering the data writing and compensation stage and its stable voltage value Vc14 during the data writing and compensation stage is a second change amount △Vc2, and the first change amount △Vc1 is equal to the second change amount △Vc2.

[0112] For example, as shown in FIG2B and FIG3 , the initial voltage value Vc11 of the first electrode of the first compensation capacitor Cst1 before entering the data writing and compensation phase is the value Vref of the reference signal REF, and the stable voltage value Vc12 of the first compensation capacitor Cst1 during the data writing and compensation phase is the value Vdata of the data signal DATA, so that the first variation ΔVc1 = Vdata - Vref. The initial voltage value Vc13 of the second electrode of the first compensation capacitor Cst1 before entering the data writing and compensation phase is the value Vini1 of the first reset signal VINI1. Since the voltages of the first and second electrodes of the first compensation capacitor Cst1 cannot suddenly change, the voltage of the second electrode of the first compensation capacitor Cst1 also has a first variation ΔVc1, that is, the second variation ΔVc2 is equal to the first variation ΔVc1. Therefore, the voltage variation of the second terminal of the driving transistor DT is also equal to the first variation ΔVc1. The initial voltage value of the second end of the driving transistor DT before entering the data writing and compensation phase is the value Vini1 of the first reset signal VINI1. Therefore, the stable voltage value of the second end of the driving transistor DT during the data writing and compensation phase is Vini1+ΔVc1(ΔVc2)=Vini1+Vdata-Vref.

[0113] For example, as shown in Figures 2B and 3, before entering the data writing and compensation stage, the initial voltage of the gate of the driving transistor DT is the second power supply voltage ELVDD, and the difference (Vgs) between the second power supply voltage ELVDD and the value Vini1 of the first reset signal VINI1 is greater than the threshold voltage Vth of the driving transistor DT, that is, Vgs=ELVDD-Vini1>Vth, so the driving transistor DT is in the on state, and the first electrode of the driving transistor DT is charged to the second electrode of the driving transistor DT until the driving transistor DT is cut off (turned off) so that the gate-source voltage Vgs of the driving transistor DT is equal to Vth. At this time, the voltage value of the gate of the driving transistor DT (the voltage value of the first electrode of the compensation control capacitor Ca) is Vini1+Vdata-Vref+Vth. Therefore, the charging process can enable information such as the threshold voltage Vth of the driving transistor DT to be stored in the compensation control capacitor Ca, thereby completing the data writing and compensation process.

[0114] For example, as shown in Figures 1 and 3, in the light-emitting stage 3, the first light-emitting control signal EM1 is set to a start signal to turn on the first light-emitting control circuit 600, and the first light-emitting control circuit 600 applies the second power supply voltage ELVDD to the first end 100a of the driving circuit 100; the second light-emitting control signal EM2 is set to a start signal to turn on the second light-emitting control circuit 700, and the second light-emitting control circuit 700 applies a driving current to the first electrode 400a of the light-emitting element 400 to drive it to emit light.

[0115] Correspondingly, as shown in Figures 2C and 3, in light-emitting phase 3, the first light-emitting control signal EM1 is set to a high-level signal to turn on the first light-emitting control transistor T4, and the second power supply voltage ELVDD is applied to the first electrode of the driving transistor DT. Simultaneously, the second light-emitting control signal EM2 is set to a high-level signal to turn on the second light-emitting control transistor T5. A driving current is applied to the light-emitting element OLED via the second light-emitting control transistor T5, causing it to emit light.

[0116] For example, as shown in FIG2C and FIG3 , in light-emitting phase 3, since the light-emitting element OLED is in a light-emitting state, the voltage value of the first electrode of the light-emitting element OLED (the voltage value of the fourth node N4) and the voltage value of the second electrode of the driving transistor DT both correspond to the voltage value Voled when the light-emitting element OLED emits light. Therefore, the change in the voltage value of the first electrode of the light-emitting element OLED is ΔV=Voled-Vini1. Accordingly, the compensation control capacitor Ca can play a self-bootstrapping role, so that the first electrode of the compensation control capacitor Ca also has a change ΔV, thereby causing the voltage value of the gate of the driving transistor DT (the voltage value of the second node N2) to have a change ΔV, thereby causing the voltage value of the gate of the driving transistor DT to be Vini1+Vdata-Vref+Vth+ΔV=Vini1+Vdata-Vref+Vth+Voled-Vini1. The driving transistor DT is in an on state, and the gate-source voltage Vgs of the driving transistor DT is Vini1+Vdata-Vref+Vth+Voled-Vini1-Voled=Vdata-Vref+Vth.

[0117] The value of the driving current I flowing through the light-emitting element can be obtained according to the following formula:

[0118] I=K×(Vgs-Vth) 2 , K is the conductivity coefficient of the driving transistor DT. That is:

[0119] I=K×(Vdata-Vref) 2

[0120] According to the above formula, the value I of the driving current flowing through the light-emitting element is no longer related to the threshold voltage Vth of the driving transistor DT. This can compensate for the pixel circuit, solve the problem of threshold voltage Vth drift of the driving transistor DT due to process technology and long-term operation, and eliminate its influence on the driving current, thereby improving the display effect of the display device using this pixel circuit.

[0121] For example, as shown in Figures 2B, 2C and 3, when entering the light-emitting stage 3 from the data writing and compensation stage 2, the data writing transistor T1 changes from the on state to the off state. During this process, since there is a parasitic capacitance between the gate of the data writing transistor T1 and its first electrode, and the parasitic capacitance is connected in series with the first storage capacitor Cst1, when the voltage of the gate of the data writing transistor T1 decreases, the parasitic capacitance between the gate of the data writing transistor T1 and its first electrode and the first storage capacitor Cst1 can perform a voltage division effect, thereby making the change in the voltage value of the first electrode of the first storage capacitor Cst1 smaller. For example, the voltage value of the parasitic capacitance between the gate of the data write transistor T1 and its first electrode can be C0, and the voltage value of the first storage capacitor Cst1 can be C1. Therefore, when the voltage value of the gate of the data write transistor T1 decreases by △V1, the change in the voltage value of the first storage capacitor Cst1 is △V1×C0 / (C0+C1). Since the voltage value C0 of the parasitic capacitance between the gate of the data write transistor T1 and its first electrode is usually much smaller than the voltage value C1 of the first storage capacitor Cst1, the change in the voltage value of the first storage capacitor Cst1 will also be correspondingly smaller. Therefore, by electrically connecting the first electrode of the data writing transistor T1 to the first electrode of the first storage capacitor Cst1, and electrically connecting the second electrode of the first storage capacitor Cst1 to the second electrode of the driving transistor DT, the influence of the data writing transistor T1 on the voltage of the second electrode of the driving transistor DT when it changes from an on state to an off state can be reduced, so that the change in the voltage value of the second electrode of the driving transistor DT is smaller. In this way, the difference between the gate voltage of the driving transistor DT and the voltage of the second electrode of the driving transistor DT (i.e., the gate-source voltage Vgs of the driving transistor DT) can be made basically unchanged, or fluctuate less, so as to make the driving current flowing through the light-emitting element more stable and make the brightness of the display panel more uniform.

[0122] In the pixel circuit provided in the embodiment of the present application, by combining the data writing transistor T1 with components such as the first storage capacitor Cst1, not only the technical problem of how to compensate for the threshold voltage Vth of the driving transistor DT is solved to eliminate its influence on the driving current; at the same time, when entering the light-emitting stage from the data writing and compensation stage, the data writing transistor T1 can be turned off with less influence on the gate-source voltage Vgs of the driving transistor DT, thereby making the driving current more stable and improving the display effect of the display panel.

[0123] For example, as shown in FIG2A , the capacitance C1 of the first compensation capacitor Cst1 may be 30 to 100 times the capacitance C0 of the parasitic capacitance between the gate of the data write transistor T1 and the first electrode of the data write transistor T1, for example, at least one of 30 to 50 times, 40 to 80 times, 50 to 70 times, and 60 to 90 times, but the embodiments of the present disclosure are not limited thereto. With this configuration, when the voltage value of the gate of the data write transistor T1 decreases by ΔV1, the change in the voltage value of the first storage capacitor Cst1 by ΔV1×C0 / (C0+C1) is small, thereby reducing the impact of the data write transistor T1 on the gate-source voltage Vgs of the drive transistor DT when the data write transistor T1 turns off.

[0124] For example, as shown in FIG2A , the capacitance value C1 of the first compensation capacitor Cst1 may be 100 fF to 300 fF, such as at least one of 100 fF to 150 fF, 120 fF to 180 fF, 200 fF to 250 fF, 230 fF to 250 fF, and 240 fF to 280 fF, but the embodiments of the present disclosure are not limited thereto. For example, the capacitance value C0 of the parasitic capacitance between the gate of the data write transistor T1 and its first electrode may be 3 fF to 5 fF, such as 3 fF, 3.5 fF, 4 fF, and 4.5 fF, but the embodiments of the present disclosure are not limited thereto.

[0125] FIG4 is a schematic block diagram of another pixel circuit provided by at least one embodiment of the present disclosure.

[0126] For example, as shown in FIG4 , the pixel circuit 20 includes a driving circuit 100, a data writing circuit 200 (a first reset circuit 300), a light-emitting element 400, a second reset circuit 500, a first light-emitting control circuit 600, a second light-emitting control circuit 700, a third reset circuit 800, and a compensation control circuit 900. Compared to the pixel circuit 10 shown in FIG1 , the pixel circuit 20 differs in that the control terminal 200m of the data writing circuit 200 is electrically connected to the control terminal 500m of the second reset circuit 500. For example, the data scanning signal G1 and the second reset control signal RST2 can be the same control signal to simultaneously control the opening and closing of the data writing circuit 200 and the second reset circuit 500, thereby simplifying the structure of the pixel circuit. For other structures in the pixel circuit 20, please refer to the relevant description of FIG1 in the above embodiment, and will not be repeated here.

[0127] Figure 5A is a circuit diagram of an implementation example of the pixel circuit shown in Figure 4; Figure 6 is a signal timing diagram of another driving method provided by at least one embodiment of the present disclosure. It should be noted that Figure 5A is a schematic diagram of the pixel circuit 102 in the reset phase; Figure 5B is a schematic diagram of the pixel circuit 102 shown in Figure 5A in the data writing and compensation phase; and Figure 5C is a schematic diagram of the pixel circuit 102 shown in Figure 5A in the light emitting phase. In addition, the transistors marked with dotted lines in Figures 5B and 5C are both in the off state during the corresponding phase.

[0128] For example, the pixel circuit shown in FIG. 4 may be implemented as the pixel circuit structure shown in FIG. 5A .

[0129] For example, as shown in FIG5A , the pixel circuit 102 includes a driving transistor DT, a data writing transistor T1 (a first reset transistor T2), a second reset transistor T3, a first light emission control transistor T4, a second light emission control transistor T5, a third reset transistor T6, a first compensation capacitor Cst1, a compensation control capacitor Ca, and a light-emitting element OLED. For example, the pixel circuit 102 differs from the pixel circuit 101 (as shown in FIG2A ) in that the gate of the data writing transistor T1 is electrically connected to the gate of the second reset transistor T3, the data writing transistor T1 and the second reset transistor T3 share a gate, the data scanning signal G1 serves as the second reset control signal RST2, and the type of the data writing transistor T1 is the same as the type of the second reset transistor T3.

[0130] For example, as shown in FIG5A , the timing diagram corresponding to the pixel circuit 102 can be found in FIG6 . For example, during the driving process of the pixel circuit 102, the operating state (e.g., on state or off state) of each transistor is the same as that of the pixel circuit 101 shown in FIG2A . Compared to the timing diagram shown in FIG3 , the timing states of the data signal DATA, the first reset control signal RST1, the second reset control signal RST2, the third reset control signal RST3, the data scan signal G1, the first light-emitting control signal EM1, and the second light-emitting control signal EM2 in the timing diagram of FIG6 remain unchanged. The difference is that the data scan signal G1 is multiplexed into the second reset control signal RST2.

[0131] For example, as shown in Figures 5A and 6, both the data write transistor T1 and the second reset transistor T3 are N-type transistors. For example, in reset phase 1, the data scan signal G1 is a high-level signal, and the data write transistor T1 functions as the second reset transistor T2. The data scan signal G1 can function as the first reset control signal RST1 to turn on the second reset transistor T2, thereby applying the reference signal REF to the first electrode of the data write transistor T1. Simultaneously, the data scan signal G1 also functions as the second reset control signal RST2 to turn on the second reset transistor T3, and the first reset signal VINI1 is applied to the first electrode of the light-emitting element OLED.

[0132] For example, as shown in Figures 5B and 6, in the data writing and compensation phase 2, the data scanning signal G1 is a high-level signal, and the data writing transistor T1 is turned on in response to the data scanning signal G1, thereby applying the data signal DATA to the first electrode of the first compensation capacitor Cst1. At the same time, the data scanning signal G1 also serves as the second reset control signal RST2, thereby turning on the second reset transistor T3, and applying the first reset signal VINI1 to the first electrode of the light-emitting element OLED.

[0133] For example, as shown in Figures 5C and 6, in light-emitting phase 3, the data scanning signal G1 is a low-level signal, and the data writing transistor T1 and the second reset transistor T3 are both turned off in response to the data scanning signal G1. The operation process and corresponding technical effects of the pixel circuit 102 shown in Figure 5A in the reset phase 1, data writing and compensation phase 2, and light-emitting phase 3 can be found in the description of Figures 2A to 2C in the above embodiment, and will not be repeated here.

[0134] For example, as shown in FIG5A , by making the data writing transistor T1 and the second reset transistor T3 in the pixel circuit 102 share a common gate, the on and off states of the data writing transistor T1 and the second reset transistor T3 can be simultaneously controlled by the same control signal (i.e., the data scanning signal G1), thereby simplifying the structure of the pixel circuit 102 and making the control method for the pixel circuit 102 simpler.

[0135] For example, referring to FIG5A , the gate of the data write transistor T1 and the gate of the second reset transistor T3 may also be independent of each other and not electrically connected. For example, as shown in FIG2A , the data scan signal G1 and the second reset control signal RST2 may be different signals, for example, the two may be electrically connected to different signal output terminals to respectively control the on and off states of the data write transistor T1 and the second reset transistor T3. For example, in some embodiments of the present disclosure, the gate of the data write transistor T1 and the gate of the reset control signal RST2 may be independent of each other, the data scan signal G1 and the second reset control signal RST2 may both be electrically connected to the same signal output terminal, and the data scan signal G1 is applied to the gate of the data write transistor T1, and the second reset control signal RST2 is applied to the gate of the second reset transistor T3. The embodiments of the present disclosure do not limit whether the gate of the data write transistor T1 and the gate of the reset control signal RST2 are electrically connected, and the specific embodiment can be flexibly adjusted according to design requirements.

[0136] FIG7 is a schematic block diagram of yet another pixel circuit provided by at least one embodiment of the present disclosure.

[0137] For example, as shown in FIG7 , the pixel circuit 30 includes a driving circuit 100, a data writing circuit 200, a first reset circuit 300, a light-emitting element 400, a second reset circuit 500, a first light-emitting control circuit 600, a second light-emitting control circuit 700, a third reset circuit 800, and a compensation control circuit 900. Compared to the pixel circuit 10 shown in FIG1 , the pixel circuit 30 differs in that the control terminal 200m of the data writing circuit 200 and the control terminal 300m of the first reset circuit 300 are independent of each other. The control terminal 200m of the data writing circuit 200 is configured to receive a data scanning signal G1, and the control terminal 300m of the first reset circuit 300 is configured to receive a first reset control signal RST1. The data scanning signal G1 and the first reset control signal RST1 can be different signals and can come from different signal terminals.

[0138] For other structures in the pixel circuit 30 , reference may be made to the relevant description regarding FIG. 1 in the above embodiment, and a repeated description will not be given here.

[0139] FIG8A is a circuit diagram of an implementation example of the pixel circuit shown in FIG7 ; FIG9 is a signal timing diagram of another driving method provided by at least one embodiment of the present disclosure. It should be noted that FIG8B is a schematic diagram of the pixel circuit 103 shown in FIG8A in the reset phase; FIG8C is a schematic diagram of the pixel circuit 103 shown in FIG8A in the data writing and compensation phase; and FIG8D is a schematic diagram of the pixel circuit 103 shown in FIG8A in the light emitting phase. In addition, the transistors marked with dotted lines in FIG8B-FIG8D all indicate that they are in the off state during the corresponding phase.

[0140] For example, the pixel circuit shown in FIG. 7 may be implemented as the pixel circuit structure shown in FIG. 8A .

[0141] For example, as shown in FIG8A , the pixel circuit 103 includes a driving transistor DT, a data writing transistor T1, a first reset transistor T2, a second reset transistor T3, a first light emission control transistor T4, a second light emission control transistor T5, a third reset transistor T6, a first compensation capacitor Cst1, a compensation control capacitor Ca, and a light-emitting element OLED. For example, the difference between the pixel circuit 103 and the pixel circuit 101 (as shown in FIG2A ) is that the data writing transistor T1 and the first reset transistor T2 are independently controlled transistors, the gate of the data writing transistor T1 is electrically connected to the data control terminal G1, the gate of the first reset transistor T2 is electrically connected to the first reset control terminal RST1, and the data control terminal G1 and the first reset control terminal RST1 are independent and different signal terminals, and the data signal terminal DATA and the reference signal terminal REF are independent and different signal terminals. This configuration allows the data writing transistor T1 and the first reset transistor T2 to be independently controlled, so that the pixel circuit 103 has a more flexible control method.

[0142] For example, the timing diagram corresponding to the pixel circuit 103 can be seen in FIG9 . For example, as shown in FIG8A and FIG9 , during the driving process of the pixel circuit 103, the operating state (e.g., on state or off state) of each transistor differs from that of the pixel circuit 101 shown in FIG2A in that the operating states of the data write transistor T1 and the first reset transistor T2 are different. For example, compared to the timing diagram shown in FIG3 , the timing states of the data signal DATA, the second reset control signal RST2, the third reset control signal RST3, the first light-emitting control signal EM1, and the second light-emitting control signal EM2 in the timing diagram of FIG9 remain unchanged, but the difference lies in the timing states of the data scan signal G1 and the first reset control signal RST1.

[0143] For example, as shown in Figures 8B and 9, in reset phase 1, the data scan signal G1 is a low-level signal, thereby turning off the data write transistor T1. The first reset control signal RST1 is a high-level signal, thereby turning on the first reset transistor T2. The reference signal REF is applied to the first electrode of the first compensation capacitor Cst1 via the first reset transistor T2.

[0144] For example, as shown in Figures 8C and 9, in the data writing and compensation phase 2, the data scanning signal G1 is a high-level signal, thereby turning on the data writing transistor T1. The data signal DATA is applied to the first electrode of the first compensation capacitor Cst1 via the data writing transistor T1, and then written to the second electrode of the driving transistor DT. The first reset control signal RST1 is a low-level signal, thereby turning off the first reset transistor T2.

[0145] For example, as shown in Figures 8D and 9, in light-emitting phase 3, the data scanning signal G1 and the first reset control signal RST1 are both low-level signals, thereby turning off the data writing transistor T1 and the first reset transistor T2. The operation process and corresponding technical effects of the pixel circuit 103 in reset phase 1, data writing and compensation phase 2, and light-emitting phase 3 shown in Figure 8A can be found in the description of Figures 2A to 2C in the above embodiment, and will not be repeated here.

[0146] For example, as shown in FIG8A , by making the data writing transistor T1 and the first reset transistor T2 independently controlled transistors, the control method of the pixel circuit 103 can be made more flexible to adapt to different design requirements.

[0147] For example, referring to FIG8A , in some embodiments of the present disclosure, when the data write transistor T1 and the first reset transistor T2 are independently controlled transistors, and the data control terminal G1 and the first reset control terminal RST1 are independent and different signal terminals, and the data signal terminal DATA and the reference signal terminal REF are independent and different signal terminals, the type of the data write transistor T1 may be different from the type of the first reset transistor T2. For example, the data write transistor T1 may be an N-type transistor and the first reset transistor T2 may be a P-type transistor; or the data write transistor T1 may be a P-type transistor and the first reset transistor T2 may be an N-type transistor. As long as the data write transistor T1 and the first reset transistor T2 are in specific states during different control phases, that is, the data write transistor T1 is in a OFF state during reset phase 1 and light emitting phase 3, and is in an ON state during data write and compensation phase 2; the first reset transistor T2 is in an ON state during reset phase 1, and is in a OFF state during data write and compensation phase 2 and light emitting phase 3, this can meet more flexible design requirements.

[0148] FIG10 is a schematic block diagram of yet another pixel circuit provided by at least one embodiment of the present disclosure.

[0149] For example, as shown in FIG10 , the pixel circuit 40 includes a driving circuit 100, a data writing circuit 200 (a first reset circuit 300), a light-emitting element 400, a second reset circuit 500, a first light-emitting control circuit 600, a second light-emitting control circuit 700, a third reset circuit 800, a compensation control circuit 900, and a direct reset circuit 550. Compared to the pixel circuit 10 shown in FIG1 , the pixel circuit 40 differs in that the direct reset circuit 550 is added. For other structures in the pixel circuit 40, please refer to the relevant description of FIG1 in the above embodiment, and will not be repeated here.

[0150] For example, as shown in FIG10 , a control terminal 550m of the direct reset circuit 550 is configured to receive a direct reset control signal RST0, a first terminal 550a of the direct reset circuit 550 is electrically connected to the second terminal 100b of the driver circuit 100, and a second terminal 550b of the direct reset circuit 550 is electrically connected to the second reset signal terminal VINI2 to receive the second reset signal VINI2. The direct reset circuit 550 is configured to, in response to the direct reset control signal RST0, directly apply the second reset signal VINI2 to the second terminal 100b of the driver circuit 100. For example, when the direct reset control signal RST0 is an on signal, the direct reset circuit 550 is turned on in response to the direct reset control signal RST0, thereby enabling the second reset signal VINI2 to be directly applied to the second terminal 100b of the driver circuit 100. The second reset signal VINI2 is directly applied to the second terminal 100b of the driver circuit 100, meaning that no other components, such as transistors and capacitors, are provided between the direct reset circuit 550 and the driver circuit 100. This allows the second reset signal VINI2 to be applied to the second terminal 100b of the driver circuit 100 without passing through any other components, such as transistors and capacitors, other than the reset circuit 550. This configuration allows for a more accurate and rapid reset operation on the second terminal 100b of the driver circuit 100 via the direct reset circuit 550, resulting in a more precise voltage at the second terminal 100b of the driver circuit 100 during the reset phase.

[0151] FIG11A is a circuit diagram of an implementation example of the pixel circuit shown in FIG10 ; FIG12 is a signal timing diagram of another driving method provided by at least one embodiment of the present disclosure. It should be noted that FIG11B is a schematic diagram of the pixel circuit 104 shown in FIG11A when it is in the reset phase; FIG11C is a schematic diagram of the pixel circuit 104 shown in FIG11A when it is in the data writing and compensation phase; and FIG11D is a schematic diagram of the pixel circuit 104 shown in FIG11A when it is in the light emitting phase. In addition, the transistors marked with dotted lines in FIG11B-FIG11D all indicate that they are in the off state in the corresponding phase.

[0152] For example, the pixel circuit shown in FIG. 10 may be implemented as the pixel circuit structure shown in FIG. 11A .

[0153] For example, as shown in FIG11A , the pixel circuit 104 includes a driving transistor DT, a data writing transistor T1 (a first reset transistor T2), a second reset transistor T3, a first emission control transistor T4, a second emission control transistor T5, a third reset transistor T6, a direct reset transistor T7, a first compensation capacitor Cst1, a compensation control capacitor Ca, and a light-emitting element OLED. For example, the pixel circuit 104 differs from the pixel circuit 101 (as shown in FIG2A ) in that the direct reset transistor T7 is added.

[0154] For example, as shown in FIG11A , the direct reset circuit 550 includes a direct reset transistor T7, a gate of which is electrically connected to the direct reset control signal terminal RST0 to receive the direct reset control signal RST0, a first electrode of the direct reset transistor T7 is electrically connected to the second terminal 100 b of the driving circuit 100, and a second electrode of the direct reset transistor T7 is electrically connected to the second reset signal terminal VINI2 to receive the second reset signal VINI2. For example, no other components, such as transistors or capacitors, are provided between the second electrode of the driving transistor DT and the direct reset transistor T7, so that when the direct reset transistor T7 is turned on, the second reset signal VINI2 can be directly applied to the second electrode of the driving transistor DT.

[0155] For example, the timing diagram corresponding to pixel circuit 104 can be seen in FIG12. For example, as shown in FIG11A and FIG12, the difference between pixel circuit 104 and pixel circuit 101 shown in FIG2A is the addition of a direct reset transistor T7, and the operating states (e.g., on state or off state) of the remaining transistors in different control stages are the same. For example, compared to the timing diagram shown in FIG3, the timing states of data signal DATA, second reset control signal RST2, third reset control signal RST3, first light-emitting control signal EM1, second light-emitting control signal EM2, and data scanning signal G1 in the timing diagram of FIG12 remain unchanged, and the difference is the addition of the timing state corresponding to direct reset control signal RST0.

[0156] For example, as shown in Figures 11B and 12, in reset phase 1, in pixel circuit 104, since the data write transistor T1 is multiplexed into the first reset transistor T2, and the data scan signal G1 is multiplexed into the first reset control signal RST1, the data scan signal G1 is set to a high-level signal to turn on the data write transistor T1, and the reference signal REF can be applied to the first electrode of the data write transistor T1, and then to the first electrode of the first compensation capacitor Cst1. Next, the first emission control signal EM1 is set to a high-level signal to turn on the first emission control transistor T4, and the third reset control signal RST3 is set to a high-level signal to turn on the third reset transistor T6. As a result, the second power supply voltage ELVDD can be applied to the first electrode of the drive transistor DT and applied to the gate of the drive transistor DT through the third reset transistor T6. At the same time, the second light-emitting control signal EM2 is set to a low-level signal to turn off the second light-emitting control transistor T5, and the second reset control signal RST2 is set to a high-level signal to turn on the second reset transistor T3, so that the first reset signal VINI1 can be applied to the first electrode (the fourth node N4) of the light-emitting element OLED, so that the voltage value of the first electrode of the light-emitting element OLED is the value Vini1 of the first reset signal VINI1.

[0157] For example, as shown in Figures 10 and 11B, in reset phase 1, the driving method further includes: setting the direct reset control signal RST0 to an on signal to turn on the direct reset circuit 550, applying the second reset signal VINI2 to the second terminal 100b of the driving circuit 100, and the value of the second reset signal VINI2 being Vini2, so that the initial voltage value of the second terminal 100b of the driving circuit 100 before entering the data writing and compensation phase is Vini2. Specifically, for example, as shown in Figures 11B and 12, setting the direct reset control signal RST0 to a high-level signal to turn on the direct reset transistor T7, thereby causing the second reset signal VINI2 to be applied to the second electrode of the driving transistor DT to reset the voltage of the second electrode of the driving transistor DT, and the voltage value of the second electrode of the driving transistor DT is the value Vini2 of the second reset signal VINI2.

[0158] For example, as shown in FIG11B and FIG12 , in the data writing and compensation phase 2, the second reset control signal RST2 is set to a high-level signal to turn on the second reset transistor T3, so that the first reset signal VINI1 can be applied to the first electrode (fourth node N4) of the light-emitting element OLED and the second electrode of the compensation control capacitor Ca, thereby making the voltage value of the first electrode of the light-emitting element OLED equal to the value Vini1 of the first reset signal VINI1, thereby preventing the light-emitting element OLED from emitting light in the data writing and compensation phase 2. At the same time, the data scanning signal G1 is set to a high-level signal to turn on the data writing transistor T1, so that the data signal DATA is applied to the first electrode of the first compensation capacitor Cst1.

[0159] For example, as shown in Figures 11C and 12, in the data writing and compensation stage 2, the difference between the initial voltage value Vc11 of the first electrode of the first compensation capacitor Cst1 before entering the data writing and compensation stage and its stable voltage value Vc12 during the data writing and compensation stage is a first change amount △Vc1; the difference between the initial voltage value Vc13 of the second electrode of the first compensation capacitor Cst1 before entering the data writing and compensation stage and its stable voltage value Vc14 during the data writing and compensation stage is a second change amount △Vc2, and the first change amount △Vc1 is equal to the second change amount △Vc2.

[0160] For example, as shown in Figures 11C and 12 , the initial voltage value Vc11 of the first electrode of the first compensation capacitor Cst1 before entering the data writing and compensation phase is the voltage value Vref corresponding to the reference signal REF, and the stable voltage value Vc12 of the first compensation capacitor Cst1 during the data writing and compensation phase is the voltage value Vdata corresponding to the data signal DATA, so that the first variation ΔVc1 = Vdata - Vref. The initial voltage value Vc13 of the second electrode of the first compensation capacitor Cst1 before entering the data writing and compensation phase is the value Vini2 of the second reset signal VINI2. Since the voltages of the first and second electrodes of the first compensation capacitor Cst1 cannot suddenly change, the voltage of the second electrode of the first compensation capacitor Cst1 also has the first variation ΔVc1. That is, the second variation ΔVc2 is equal to the first variation ΔVc1. Therefore, the voltage variation at the second terminal of the driving transistor DT is also the first variation ΔVc1. The initial voltage value of the second end of the driving transistor DT before entering the data writing and compensation phase is the value Vini2 of the second reset signal VINI2. Therefore, the stable voltage value of the second end of the driving transistor DT during the data writing and compensation phase is Vini2+ΔVc1(ΔVc2)=Vini2+Vdata-Vref.

[0161] For example, as shown in Figures 11C and 12, before entering the data writing and compensation stage, the initial voltage of the gate of the driving transistor DT is the second power supply voltage ELVDD, and the difference (Vgs) between the second power supply voltage ELVDD and the value Vini2 of the second reset signal VINI2 is greater than the threshold voltage Vth of the driving transistor DT, that is, Vgs=ELVDD-Vini2>Vth, so the driving transistor DT is in the on state, and the first electrode of the driving transistor DT is charged to the second electrode of the driving transistor DT until the driving transistor DT is cut off (turned off) so that the gate-source voltage Vgs of the driving transistor DT is equal to Vth. At this time, the voltage value of the gate of the driving transistor DT (the voltage value of the first electrode of the compensation control capacitor Ca) is Vini2+Vdata-Vref+Vth. Therefore, the charging process can enable information such as the threshold voltage Vth of the driving transistor DT to be stored in the compensation control capacitor Ca, thereby completing the data writing and compensation process.

[0162] For example, as shown in Figures 11D and 12, in light-emitting phase 3, the first light-emitting control signal EM1 is set to a high-level signal to turn on the first light-emitting control transistor T4, and the second power supply voltage ELVDD is applied to the first electrode of the driving transistor DT. At the same time, the second light-emitting control signal EM2 is set to a high-level signal to turn on the second light-emitting control transistor T5. A driving current is applied to the light-emitting element OLED via the second light-emitting control transistor T5, causing it to emit light.

[0163] For example, as shown in FIG11D and FIG12 , in light-emitting stage 3, since the light-emitting element OLED is in a light-emitting state, the voltage value of the first electrode of the light-emitting element OLED (the voltage value of the fourth node N4) and the voltage value of the second electrode of the driving transistor DT are both the voltage value Voled corresponding to when the light-emitting element OLED is emitting light. Therefore, the change in the voltage value of the first electrode of the light-emitting element OLED ΔV=Voled-Vini1. Accordingly, the compensation control capacitor Ca plays a bootstrap role, causing the first electrode of the compensation control capacitor Ca to also have a change ΔV, thereby causing the voltage value of the gate of the driving transistor DT (the voltage value of the second node N2) to have a change ΔV, thereby causing the voltage value of the gate of the driving transistor DT to be Vini2+Vdata-Vref+Vth+ΔV=Vini2+Vdata-Vref+Vth+Voled-Vini1. The driving transistor DT is in the on state, and the gate-source voltage of the driving transistor DT is Vgs=Vini2+Vdata−Vref+Vth+Voled−Vini1−Voled=(Vini2−Vini1)+Vdata−Vref+Vth.

[0164] The value of the driving current I flowing through the light-emitting element can be obtained according to the following formula:

[0165] I=K×(Vgs-Vth) 2 , K is the conductivity coefficient of the driving transistor DT. That is:

[0166] I=K×(Vini2-Vini1+Vdata-Vref) 2

[0167] For example, as shown in FIG11D , the value Vini1 of the first reset signal VINI1 may be equal to the value Vini2 of the second reset signal VINI2, thereby making the driving current value of the light emitting element OLED in the light emitting stage I=K×(Vdata-Vref) 2 For example, in some embodiments, the value Vini1 of the first reset signal VINI1 may be different from the value Vini2 of the second reset signal VINI2, which is not limited in the embodiments of the present disclosure.

[0168] According to the above formula, the value I of the driving current flowing through the light-emitting element is no longer related to the threshold voltage Vth of the driving transistor DT. This can compensate for the pixel circuit, solve the problem of threshold voltage Vth drift of the driving transistor DT due to process technology and long-term operation, and eliminate its influence on the driving current, thereby improving the display effect of the display device using this pixel circuit.

[0169] For example, as shown in Figures 11C, 11D, and 12, during data writing and compensation phase 2 and light emitting phase 3, the direct reset control signal RST0 is a low-level signal, and the direct reset transistor T7 is turned off in response to the direct reset control signal RST0. The operation and corresponding technical effects of the pixel circuit 104 shown in Figure 11A during the reset phase 1, data writing and compensation phase 2, and light emitting phase 3 can be found in the description of Figures 2A-2C in the above embodiments, and are not repeated here.

[0170] Of course, the embodiments of the present disclosure do not limit the type of the direct reset transistor T7. For example, the direct reset transistor T7 can be a P-type transistor, that is, when the direct reset control signal RST0 is a low-level signal, the direct reset transistor T7 is turned on; when the direct reset control signal RST0 is a high-level signal, the direct reset transistor T7 is turned off. The specific setting can be made according to design requirements.

[0171] FIG13 is a schematic block diagram of yet another pixel circuit provided by at least one embodiment of the present disclosure.

[0172] For example, as shown in FIG13 , the pixel circuit 50 includes a driving circuit 100, a data writing circuit 200 (a first reset circuit 300), a light-emitting element 400, a second reset circuit 500, a first light-emitting control circuit 600, a second light-emitting control circuit 700, a third reset circuit 800, a compensation control circuit 900, and an auxiliary compensation circuit 910. Compared to the pixel circuit 10 shown in FIG1 , the pixel circuit 50 differs in that the auxiliary compensation circuit 910 is added. The first terminal 910 a of the auxiliary compensation circuit 910 is electrically connected to the second terminal 100 b of the driving circuit 100, and the second terminal 910 b of the auxiliary compensation circuit 910 is electrically connected to the second voltage terminal ELVDD. For other structures in the pixel circuit 50, please refer to the relevant description of FIG1 in the above embodiment, and will not be repeated here.

[0173] Figure 14A is a circuit diagram of an implementation example of the pixel circuit shown in Figure 13 , and Figure 14A is a schematic diagram of the pixel circuit 105 shown in Figure 13 in a reset phase; Figure 14B is a schematic diagram of the pixel circuit 105 shown in Figure 13 in a data writing and compensation phase; and Figure 14C is a schematic diagram of the pixel circuit 105 shown in Figure 13 in a light emitting phase. In addition, transistors marked with dashed lines in Figures 14B and 14C are all in an off state during the corresponding phase.

[0174] For example, the pixel circuit shown in FIG. 13 may be implemented as the pixel circuit structure shown in FIG. 14A .

[0175] For example, as shown in Figures 13 and 14A, the pixel circuit 105 includes a driving transistor DT, a data writing transistor T1 (a first reset transistor T2), a second reset transistor T3, a first light emission control transistor T4, a second light emission control transistor T5, a third reset transistor T6, a first compensation capacitor Cst1, a compensation control capacitor Ca, a second compensation capacitor Cst2, and a light emitting element OLED. For example, the difference between the pixel circuit 104 and the pixel circuit 101 (as shown in Figure 2A) is that the second compensation capacitor Cst2 is added.

[0176] For example, as shown in Figures 13 and 14A, the auxiliary compensation circuit 910 includes a second compensation capacitor Cst2, and a first electrode of the second compensation capacitor Cst2 is electrically connected to the second terminal 100b of the driving circuit 100, and a second electrode of the second compensation capacitor Cst2 is configured to receive a first constant signal. For example, in the pixel circuit 105 shown in Figure 14A, the second terminal of the second compensation capacitor Cst2 is electrically connected to the second voltage terminal ELVDD, and the second power supply voltage ELVDD serves as the first constant signal, but the embodiments of the present disclosure are not limited thereto.

[0177] For example, the timing diagram corresponding to the pixel circuit 105 can be seen in FIG3. For example, as shown in FIG13 and FIG14A, the difference between the pixel circuit 105 and the pixel circuit 101 shown in FIG2A is that the second compensation capacitor Cst2 is added, and the operating states (e.g., on state or off state) of the remaining transistors in different working stages are the same.

[0178] For example, as shown in FIG3, FIG13 and FIG14A, in the reset phase 1, the driving method includes: setting the first reset control signal RST1 as a start signal to start the first reset circuit 300, and the first reset circuit 300 applies the reference signal REF to the first electrode of the first compensation capacitor Cst1; secondly, setting the first light-emitting control signal EM1 as a start signal to start the first light-emitting control circuit 600, and the first light-emitting control circuit 600 applies the second power supply voltage ELVDD to the first terminal 100a of the driving circuit 100; setting the third reset control signal RST3 as a start signal to start the third reset circuit 800, and the third reset circuit 800 applies the second power supply voltage ELVDD to The control terminal 100m of the driving circuit 100; the second light-emitting control signal EM2 is set as a start signal to turn on the second light-emitting control circuit 700; and the second reset control signal RST2 is set as a start signal to turn on the second reset circuit 500. The second reset circuit 500 applies the first reset signal VINI1 to the first electrode 400a of the light-emitting element 400. The first reset signal VINI1 is applied to the second terminal 100b of the driving circuit 100 via the second light-emitting control circuit 700. The value of the first reset signal VINI1 is Vini1, so that the initial voltage value of the second terminal 100b of the driving circuit 100 before entering the data writing and compensation stage 2 is Vini1.

[0179] Specifically, for example, as shown in Figures 3, 13, and 14A, in the pixel circuit 105, since the data write transistor T1 is multiplexed into the first reset transistor T2, and the data scan signal G1 is multiplexed into the first reset control signal RST1, the data scan signal G1 is set to a high-level signal to turn on the data write transistor T1, and the reference signal REF can be applied to the first electrode of the data write transistor T1, and then to the first electrode of the first compensation capacitor Cst1. Secondly, the first light-emitting control signal EM1 is set to a high-level signal to turn on the first light-emitting control transistor T4, and the third reset control signal RST3 is set to a high-level signal to turn on the third reset transistor T6. As a result, the second power supply voltage ELVDD can be applied to the first electrode of the drive transistor DT and applied to the gate of the drive transistor DT through the third reset transistor T6. At the same time, the second light-emitting control signal EM2 is set to a high-level signal to turn on the second light-emitting control transistor T5, and the second reset control signal RST2 is set to a high-level signal to turn on the second reset transistor T3, so that the first reset signal VINI1 can be applied to the first electrode (the fourth node N4) of the light-emitting element OLED, and applied to the second electrode (the third node N3) of the driving transistor DT through the second light-emitting control transistor T5, so that the voltage value of the second electrode of the driving transistor DT and the voltage value of the first electrode of the light-emitting element OLED are both the value Vini1 of the first reset signal VINI1.

[0180] For example, as shown in Figures 3, 13 and 14A, in the data writing and compensation stage 2, the driving method includes: setting the second reset control signal RST2 to a turn-on signal to turn on the second reset circuit 500, and the second reset circuit 500 applies the first reset signal VINI1 to the first electrode 400a of the light-emitting element 400 and the second electrode of the compensation control capacitor Ca.

[0181] Specifically, as shown in FIG3 and FIG14B , in the data writing and compensation phase 2, the second reset control signal RST2 is set to a high-level signal to turn on the second reset transistor T3, so that the first reset signal VINI1 can be applied to the first electrode (fourth node N4) of the light-emitting element OLED and the second electrode of the compensation control capacitor Ca, thereby making the voltage value of the first electrode of the light-emitting element OLED equal to the value Vini1 of the first reset signal VINI1, thereby preventing the light-emitting element OLED from emitting light in the data writing and compensation phase 2. At the same time, the data scanning signal G1 is set to a high-level signal to turn on the data writing transistor T1, so that the data signal DATA is applied to the first electrode of the first compensation capacitor Cst1.

[0182] For example, as shown in Figures 3 and 14B, in the data writing and compensation stage 2, the first compensation capacitor Cst1 and the second compensation capacitor Cst2 are connected in series, and the voltage Vc3 of the second end 100b of the driving circuit 100 is Vc3 = (Vdata-Vref)×[C1 / (C1+C2)]+Vini1, where Vdata represents the value of the data signal DATA, Vref represents the initial voltage value of the first electrode of the first compensation capacitor Cst1 before entering the data writing and compensation stage, C1 represents the capacitance value of the first compensation capacitor Cst1, C2 represents the capacitance value of the second compensation capacitor Cst2, and Vini1 represents the initial voltage value of the second end 100b of the driving circuit 100 before entering the data writing and compensation stage.

[0183] For example, as shown in FIG3 and FIG14B , the second electrode of the first compensation capacitor Cst1 is electrically connected to the first electrode of the second compensation capacitor Cst2 , and both are electrically connected to the second electrode of the driving transistor DT. Therefore, the first compensation capacitor Cst1 and the second compensation capacitor Cst2 are connected in series. Before entering the data writing and compensation phase (i.e., in reset phase 1), the initial voltage value of the first electrode of the first compensation capacitor Cst1 is equal to the value Vref of the reference signal REF. The stable voltage value of the first compensation capacitor Cst1 in the data writing and compensation phase is equal to the value Vdata of the data signal DATA. When switching from the data writing and compensation phase to the light-emitting phase, the second electrode of the second compensation capacitor Cst2 receives the first constant signal. The voltage change of the first electrode of the first compensation capacitor Cst1 is Vdata-Vref. Therefore, the difference between the voltage of the first electrode of the second compensation capacitor Cst2 and the voltage of the second electrode of the second compensation capacitor Cst2 can be obtained as (Vdata-Vref)×[C1 / (C1+C2)]. Since the voltage value of the second electrode of the second compensation capacitor Cst2 does not change (i.e., the value of the first constant signal), the voltage change of the first electrode of the second compensation capacitor Cst2 is (Vdata-Vref)×[C1 / (C1+C2)]. That is, the voltage change of the second electrode of the driving transistor DT is (Vdata-Vref)×[C1 / (C1+C2)]. Since the initial voltage value of the second electrode of the driving transistor DT before entering the data writing and compensation phase 2 (that is, the voltage value during the reset phase 1) is Vini1, therefore, during the data writing and compensation phase 2, the voltage Vc3 of the second electrode of the driving transistor DT is Vc3 = (Vdata-Vref)×[C1 / (C1+C2)]+Vini1.

[0184] For example, as shown in Figures 3 and 14B, before entering the data writing and compensation stage, the initial voltage of the gate of the driving transistor DT is the second power supply voltage ELVDD, and the difference (Vgs) between the second power supply voltage ELVDD and the value Vini1 of the first reset signal VINI1 is greater than the threshold voltage Vth of the driving transistor DT, that is, Vgs=ELVDD-Vini1>Vth. Therefore, the driving transistor DT is in the on state, and the first electrode of the driving transistor DT charges the second electrode of the driving transistor DT until the driving transistor DT is cut off (turned off), so that the gate-source voltage Vgs of the driving transistor DT is equal to Vth. At this time, the voltage value of the gate of the driving transistor DT (the voltage value of the first electrode of the compensation control capacitor Ca) is Vc3+Vth=(Vdata-Vref)×[C1 / (C1+C2)]+Vini1+Vth. Therefore, this charging process can store information such as the threshold voltage Vth of the driving transistor DT in the compensation control capacitor Ca, thereby completing the data writing and compensation process.

[0185] For example, as shown in Figures 3, 13 and 14C, in the light-emitting stage 3, the first light-emitting control signal EM1 is set to a turn-on signal to turn on the first light-emitting control circuit 600, and the first light-emitting control circuit 600 applies the second power supply voltage ELVDD to the first end 100a of the driving circuit 100; the second light-emitting control signal EM2 is set to a turn-on signal to turn on the second light-emitting control circuit 700, and the second light-emitting control circuit 700 applies a driving current to the first electrode 400a of the light-emitting element 400 to drive it to emit light.

[0186] Correspondingly, as shown in Figures 3 and 14C , in light-emitting phase 3, the first light-emitting control signal EM1 is set to a high-level signal to turn on the first light-emitting control transistor T4, and the second power supply voltage ELVDD is applied to the first electrode of the driving transistor DT. Simultaneously, the second light-emitting control signal EM2 is set to a high-level signal to turn on the second light-emitting control transistor T5. A driving current is applied to the light-emitting element OLED via the second light-emitting control transistor T5, causing it to emit light.

[0187] For example, as shown in Figures 3 and 14C, in the light-emitting stage 3, since the light-emitting element OLED is in a light-emitting state, the voltage value of the first electrode of the light-emitting element OLED (the voltage value of the fourth node N4) and the voltage value of the second electrode of the driving transistor DT (the voltage value of the third node N3) both correspond to the voltage value Voled when the light-emitting element OLED emits light. Therefore, the change in the voltage value of the first electrode of the light-emitting element OLED △V=Voled-Vini1. Correspondingly, the compensation control capacitor Ca plays a bootstrap role, so that the first electrode of the compensation control capacitor Ca also has a change △V, thereby making the voltage value of the gate of the driving transistor DT (the voltage value of the second node N2) have a change △V, so that the voltage value of the gate of the driving transistor DT is Vc3+Vth+△V=(Vdata-Vref)×[C1 / (C1+C2)]+Vini1+Vth+Voled-Vini1=(Vdata-Vref)×[C1 / (C1+C2)]+Vth+Voled, the driving transistor DT is in the on state, and the gate-source voltage Vgs of the driving transistor DT is Vdata-Vref)×[C1 / (C1+C2)]+Vth+Voled-Voled=(Vdata-Vref)×[C1 / (C1+C2)]+Vth.

[0188] The value of the driving current I flowing through the light-emitting element can be obtained according to the following formula:

[0189] I=K×(Vgs-Vth) 2 , K is the conductivity coefficient of the driving transistor DT. That is:

[0190] I=K×{(Vdata-Vref)×[C1 / (C1+C2)]} 2

[0191] According to the above formula, the value I of the driving current flowing through the light-emitting element is no longer related to the threshold voltage Vth of the driving transistor DT. This can compensate for the pixel circuit, solve the problem of threshold voltage Vth drift of the driving transistor DT due to process technology and long-term operation, and eliminate its influence on the driving current, thereby improving the display effect of the display device using this pixel circuit.

[0192] For example, as shown in Figures 3, 14B, and 14C, when entering the light-emitting stage 3 from the data writing and compensation stage 2, the data writing transistor T1 changes from the on state to the off state. During this process, since there is a parasitic capacitance between the gate of the data writing transistor T1 and its first electrode, and the parasitic capacitance is connected in series with the first storage capacitor Cst1, when the voltage of the gate of the data writing transistor T1 decreases, the parasitic capacitance between the gate of the data writing transistor T1 and its first electrode and the first storage capacitor Cst1 can perform a voltage division effect, thereby reducing the change in the voltage value of the first electrode of the first storage capacitor Cst1. This configuration can reduce the impact of the data writing transistor T1 on the voltage of the second electrode of the driving transistor DT when the data writing transistor T1 changes from the on state to the off state, thereby reducing the decrease in the voltage value of the second electrode of the driving transistor DT. As a result, the gate-source voltage Vgs of the driving transistor DT can be kept substantially unchanged or have a relatively small fluctuation, thereby facilitating a more stable driving current flowing through the light-emitting element OLED. In addition, when a parasitic capacitor exists between a signal line and the second electrode of the driving transistor DT, the second electrode of the driving transistor DT serves as one electrode of the parasitic capacitor, so that the parasitic capacitor is connected in series with the second storage capacitor Cst2. When the voltage of the other electrode of the parasitic capacitor changes, the parasitic capacitor and the second storage capacitor Cst2 can perform a voltage-dividing effect, so that the change in the voltage value of the first electrode of the second storage capacitor Cst2 is smaller, thereby further making the voltage of the second electrode of the driving transistor DT more stable, so that the brightness of the display panel is more uniform.

[0193] For example, as shown in FIG14A , the capacitance C2 of the second storage capacitor Cst2 may be 30 to 100 times the capacitance of the parasitic capacitance between the signal line and the second electrode of the driving transistor DT, for example, at least one of 30 to 40 times, 45 to 65 times, 55 to 75 times, and 60 to 80 times, but the embodiments of the present disclosure are not limited thereto. For example, the capacitance C2 of the second storage capacitor Cst2 may be 100 fF to 300 fF, for example, at least one of 120 fF to 150 fF, 140 fF to 180 fF, 210 fF to 240 fF, 230 fF to 250 fF, and 260 fF to 280 fF, but the embodiments of the present disclosure are not limited thereto. For example, the parasitic capacitance between the aforementioned signal line and the second electrode of the driving transistor DT may be 3fF to 5fF, such as 3fF, 3.5fF, 4fF, and 4.5fF, but the embodiments of the present disclosure are not limited thereto. This configuration can reduce the influence of voltage fluctuations of other signal lines on the gate-source voltage Vgs of the driving transistor DT, thereby making the driving current of the driving transistor DT more stable.

[0194] FIG15 is a schematic block diagram of yet another pixel circuit provided by at least one embodiment of the present disclosure.

[0195] For example, as shown in FIG15 , the pixel circuit 60 includes a driving circuit 100, a data writing circuit 200 (a first reset circuit 300), a light-emitting element 400, a second reset circuit 500, a first light-emitting control circuit 600, a second light-emitting control circuit 700, a third reset circuit 800, a compensation control circuit 900, and an auxiliary compensation circuit 910. Compared to the pixel circuit 50 shown in FIG13 , the pixel circuit 60 differs in that the auxiliary compensation circuit 910 is connected in a different manner. In the pixel circuit 60, the first terminal 910 a of the auxiliary compensation circuit 910 is electrically connected to the second terminal 100 b of the driving circuit 100, and the second terminal 910 b of the auxiliary compensation circuit 910 is electrically connected to the first reset signal terminal VINI1. For other structures in the pixel circuit 60, please refer to the relevant description of FIG13 in the above embodiment, and will not be repeated here.

[0196] FIG16 is a circuit diagram of an implementation example of the pixel circuit shown in FIG15 .

[0197] For example, the pixel circuit shown in FIG15 may be implemented as the pixel circuit structure shown in FIG16 .

[0198] For example, as shown in Figures 15 and 16, the pixel circuit 106 includes a driving transistor DT, a data writing transistor T1 (a first reset transistor T2), a second reset transistor T3, a first light emission control transistor T4, a second light emission control transistor T5, a third reset transistor T6, a first compensation capacitor Cst1, a compensation control capacitor Ca, a second compensation capacitor Cst2, and a light-emitting element OLED. For example, the difference between the pixel circuit 105 and the pixel circuit 104 (as shown in Figure 14A) is that the connection method of the second compensation capacitor Cst2 is different. At the same time, the driving method of the pixel circuit 106 shown in Figure 16 is the same as the driving method of the pixel circuit 105 shown in Figure 14A. For details, please refer to the relevant description of the above embodiment, and no repeated description is given here.

[0199] For example, as shown in Figures 15 and 16, the auxiliary compensation circuit 910 includes a second compensation capacitor Cst2, and a first electrode of the second compensation capacitor Cst2 is electrically connected to the second electrode of the driving transistor DT, and the second electrode of the second compensation capacitor Cst2 is configured to receive a first constant signal. For example, in the pixel circuit 106 shown in Figure 16, the second end of the second compensation capacitor Cst2 is electrically connected to the first reset signal end VINI1, and the first reset signal VINI1 serves as the first constant signal. This allows the connection method of the second compensation capacitor Cst2 to be more flexible to adapt to different design requirements.

[0200] For example, in some embodiments of the present disclosure, referring to FIG16 , the second electrode of the second compensation capacitor Cst2 may also be electrically connected to an external constant signal terminal outside the pixel circuit to receive the first constant signal from the external constant signal terminal. This arrangement allows the external constant signal terminal to serve as an independent signal input terminal, thereby independently controlling the voltage at the second electrode of the second compensation capacitor Cst2 to make it more stable.

[0201] FIG17 is a schematic block diagram of yet another pixel circuit provided by at least one embodiment of the present disclosure.

[0202] For example, as shown in FIG17 , the pixel circuit 60 includes a driving circuit 100, a data writing circuit 200 (a first reset circuit 300), a light-emitting element 400, a second reset circuit 500, a first light-emitting control circuit 600, a second light-emitting control circuit 700, a third reset circuit 800, a compensation control circuit 900, and an auxiliary circuit 1000. Compared to the pixel circuit 10 shown in FIG1 , the pixel circuit 70 differs in that the auxiliary circuit 1000 is added. For example, as shown in FIG17 , a first terminal 1000 a of the auxiliary circuit 1000 is electrically connected to the data writing circuit 200, and a second terminal 1000 b of the auxiliary circuit 1000 is configured to receive a second constant signal V0. For other structures in the pixel circuit 70, reference can be made to the relevant description of FIG1 in the above embodiment, and a repeated description is not given here.

[0203] FIG18 is a circuit diagram of another implementation example of the pixel circuit shown in FIG17 .

[0204] For example, the pixel circuit shown in FIG17 may be implemented as the pixel circuit structure shown in FIG18 .

[0205] For example, as shown in Figures 17 and 18, the pixel circuit 107 includes a driving transistor DT, a data writing transistor T1 (a first reset transistor T2), a second reset transistor T3, a first light emission control transistor T4, a second light emission control transistor T5, a third reset transistor T6, a first compensation capacitor Cst1, a compensation control capacitor Ca, an auxiliary capacitor Cb, and a light-emitting element OLED. For example, the difference between the pixel circuit 107 and the pixel circuit 101 (as shown in Figure 2A) is that the auxiliary capacitor Cb is added. At the same time, the driving method of the pixel circuit 107 shown in Figure 18 is the same as the driving method of the pixel circuit 101 shown in Figure 2A. For details, please refer to the relevant description of the above embodiment, and no repeated description is given here.

[0206] For example, as shown in Figures 17 and 18, the auxiliary circuit 1000 includes an auxiliary capacitor Cb, the first pole of the auxiliary capacitor Cb is electrically connected to the gate of the data write transistor T1, and the second pole of the auxiliary capacitor Cb is configured to receive the second constant signal V0. For example, in some embodiments of the present disclosure, the second pole of the auxiliary capacitor Cb can be electrically connected to the second voltage terminal ELVDD, and the second power supply voltage ELVDD serves as the second constant signal V0. For example, the second pole of the auxiliary capacitor Cb can be electrically connected to the first reset signal terminal VINI1, and the first reset signal VINI1 serves as the second constant signal V0. For example, the second pole of the auxiliary capacitor Cb can be electrically connected to an external constant signal terminal outside the pixel circuit to receive the first constant signal V0 from the external constant signal terminal. The specific setting can be based on design requirements. The embodiments of the present disclosure do not limit the type of the second constant signal.

[0207] For example, as shown in Figure 18, there is a parasitic capacitance between the gate of the data writing transistor T1 and its first electrode, and the parasitic capacitance is connected in series with the auxiliary capacitor Cb. When the data writing transistor T1 changes from an on state to an off state, the setting of the auxiliary capacitor Cb can slow down the change speed of the voltage of the gate of the data writing transistor T1, so that the reduction speed of the voltage of the gate of the data writing transistor T1 is reduced, thereby making the voltage fluctuation of the first electrode of the first compensation capacitor Cst1 smaller, and further reducing the fluctuation of the voltage of the gate of the driving transistor DT, so that the gate-source voltage Vgs of the driving transistor DT is more stable, which is conducive to improving the display effect of the display panel.

[0208] FIG19 is a circuit diagram of another implementation example of the pixel circuit shown in FIG1 .

[0209] For example, the pixel circuit shown in FIG1 may also be implemented as the pixel circuit structure shown in FIG19 .

[0210] For example, as shown in FIG19 , the pixel circuit 108 includes a driving transistor DT, a data writing transistor T1 (a first reset transistor T2), a second reset transistor T3, a first light emission control transistor T4, a second light emission control transistor T5, a third reset transistor T6, a first compensation capacitor Cst1, a compensation control capacitor Ca, and a light-emitting element OLED. For example, the pixel circuit 108 differs from the pixel circuit 101 in FIG2A in that the first compensation capacitor Cst1 is connected differently to the data writing transistor T1. For the remaining structure, refer to the description of FIG2A in the above embodiment and are not repeated here.

[0211] For example, as shown in Figures 1 and 19 , a first electrode of the first compensation capacitor Cst1 is electrically connected to a first electrode of the data write transistor T1, a second electrode of the first compensation capacitor Cst1 is electrically connected to a data signal terminal DATA to receive a data signal DATA, and a second electrode of the data write transistor T1 is electrically connected to a second terminal 100b of the driver circuit 100 (the second electrode of the driver transistor DT). A timing diagram corresponding to the pixel circuit 108 can be found in Figure 3 . The operation of the pixel circuit 108 can be found in the description of Figures 2A-2C in the above embodiments, and will not be repeated here.

[0212] For example, as shown in FIG19 , on the one hand, by combining the data write transistor T1 with the first storage capacitor Cst1 and other components, the technical problem of how to compensate for the threshold voltage Vth of the drive transistor DT can be solved to eliminate the influence of the threshold voltage Vth on the drive current of the drive transistor DT. On the other hand, since there is a parasitic capacitance between the gate of the data write transistor T1 and its first electrode, and one electrode of the parasitic capacitance is electrically connected to the first electrode of the first storage capacitor Cst1, the parasitic capacitance is connected in series with the first storage capacitor Cst1. For example, when the data signal DATA or the reference signal REF received by the second electrode of the first storage capacitor Cst1 fluctuates undesirably, the parasitic capacitance between the gate of the data write transistor T1 and its first electrode can act as a voltage divider with the first storage capacitor Cst1, thereby reducing the change in the voltage of the first electrode of the data write transistor T1, thereby reducing the fluctuation in the voltage of the gate of the drive transistor DT, making the gate-source voltage Vgs of the drive transistor DT more stable, thereby improving the display effect of the display panel.

[0213] Figure 20 is a schematic block diagram of a display device provided by at least one embodiment of the present disclosure. As shown in Figure 20, display device 01 includes any pixel circuit provided by the embodiments of the present disclosure. For example, pixel circuit 001 can be any pixel circuit provided by the embodiments of the present disclosure. Display device 01 can be, for example, an organic light-emitting diode display device, a quantum dot light-emitting diode display device, or other device with display functionality. The embodiments of the present disclosure are not limited thereto.

[0214] The other structures and functions of the display device 01 provided in the embodiment of the present disclosure can be implemented by referring to conventional technologies, and the embodiment of the present disclosure does not limit this. The technical effects of the display device 01 provided in the embodiment of the present disclosure can refer to the above description of the technical effects of the pixel circuit provided in the embodiment of the present disclosure, and will not be repeated here.

[0215] For example, the display device 01 provided in at least one embodiment of the present disclosure may be any product or component with a display function, such as a display panel, a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigator, etc., and the embodiments of the present disclosure are not limited to this.

[0216] There are a few points to note:

[0217] (1) The drawings of the embodiments of the present disclosure only involve structures related to the embodiments of the present disclosure, and other structures can refer to general designs.

[0218] (2) In the absence of conflict, features in the same embodiment and different embodiments of the present disclosure may be combined with each other.

[0219] The foregoing description is merely an exemplary embodiment of the present disclosure and is not intended to limit the scope of protection of the present disclosure, which is determined by the appended claims.

Claims

1. A pixel circuit, comprising: A driving circuit, comprising a control terminal, a first terminal and a second terminal, and configured to control the magnitude of a driving current flowing through the first terminal and the second terminal; as well as A data writing circuit comprises a first end and a second end, wherein the first end of the data writing circuit is electrically connected to the second end of the driving circuit, the second end of the data writing circuit is configured to receive a data signal, and the data writing circuit is configured to write the data signal to the second end of the driving circuit in response to a data scanning signal, and comprises a data writing transistor and a first compensation capacitor, wherein the gate of the data writing transistor is configured to receive the data scanning signal, and the first electrode of the first compensation capacitor is electrically connected to the first electrode of the data writing transistor.

2. The pixel circuit according to claim 1, wherein: The second electrode of the first compensation capacitor is electrically connected to the second end of the driving circuit, and the second electrode of the data writing transistor is electrically connected to the data signal end to receive the data signal.

3. The pixel circuit according to claim 2, wherein: The capacitance value of the first compensation capacitor is 30 to 100 times the capacitance value of the parasitic capacitance between the gate of the data writing transistor and the first electrode of the data writing transistor.

4. The pixel circuit according to claim 2 or 3, wherein: The capacitance value of the first compensation capacitor is 100fF to 300fF.

5. The pixel circuit according to claim 1, wherein: The second electrode of the first compensation capacitor is electrically connected to the data signal terminal to receive the data signal, and the second electrode of the data writing transistor is electrically connected to the second terminal of the driving circuit.

6. The pixel circuit according to any one of claims 2 to 5, further comprising: A first reset circuit, wherein the control end of the first reset circuit is configured to receive a first reset control signal, the first end of the first reset circuit is electrically connected to the first electrode of the first compensation capacitor, the second end of the first reset circuit is electrically connected to the reference signal end to receive a reference signal, and the first reset circuit is configured to respond to the first reset control signal to write the reference signal into the second end of the drive circuit with the first compensation capacitor.

7. The pixel circuit according to claim 6, wherein: The first reset circuit includes a first reset transistor, a gate of the first reset transistor is electrically connected to a first reset control terminal to receive the first reset control signal, a first electrode of the first reset transistor is electrically connected to a first electrode of the first compensation capacitor, and a second electrode of the first reset transistor is electrically connected to the reference signal terminal to receive the reference signal; The data writing transistor is multiplexed as the first reset transistor, and the data scanning signal is multiplexed as the first reset control signal. The second electrode of the data writing transistor is also electrically connected to the reference signal terminal to receive the reference signal, and is configured to apply the reference signal to the second terminal of the driving circuit together with the first compensation capacitor.

8. The pixel circuit according to claim 7, wherein: The data signal terminal is multiplexed as the reference signal terminal and is configured to receive the data signal and the reference signal respectively in different time periods; or, The data signal terminal and the reference signal terminal are different signal terminals independent of each other.

9. The pixel circuit according to claim 6, wherein: The first reset circuit includes a first reset transistor, a gate of the first reset transistor is electrically connected to a first reset control terminal to receive the first reset control signal, a first electrode of the first reset transistor is electrically connected to a first electrode of the first compensation capacitor, and a second electrode of the first reset transistor is electrically connected to the reference signal terminal to receive the reference signal; The data write transistor and the first reset transistor are transistors that are controlled independently of each other, the gate of the data write transistor is electrically connected to the data control end, the gate of the first reset transistor is electrically connected to the first reset control end, the data control end and the first reset control end are different signal ends that are independent of each other, and the data signal end and the reference signal end are different signal ends that are independent of each other.

10. The pixel circuit according to any one of claims 1 to 9, further comprising: a light emitting element, configured to emit light under the driving of the driving current, wherein the second end of the driving circuit is electrically connected to the first electrode of the light emitting element, the driving circuit is configured to control the magnitude of the driving current flowing through the light emitting element, and the second electrode of the light emitting element is electrically connected to the first voltage end to receive a first power supply voltage; a second reset circuit, wherein a control end of the second reset circuit is configured to receive a second reset control signal, a first end of the second reset circuit is electrically connected to the first electrode of the light emitting element, a second end of the second reset circuit is electrically connected to the first reset signal end to receive the first reset signal, and the second reset circuit is configured to reset the first reset signal in response to the second reset control signal A signal is applied to the first electrode of the light emitting element.

11. The pixel circuit according to claim 10, wherein: The second reset circuit includes a second reset transistor, a gate of the second reset transistor is electrically connected to a second reset control terminal to receive the second reset control signal, a first electrode of the second reset transistor is electrically connected to a first electrode of the light emitting element, and a second electrode of the second reset transistor is electrically connected to the first reset signal terminal to receive the first reset signal; The gate of the data writing transistor is electrically connected to the gate of the second reset transistor, the data writing transistor and the second reset transistor share a gate, the data scanning signal serves as the second reset control signal, and the type of the data transistor is the same as the type of the second reset transistor; or, The gate of the data transistor and the gate of the second reset transistor are independent of each other and are not electrically connected.

12. The pixel circuit according to claim 10 or 11, further comprising: a first light-emitting control circuit, wherein a control terminal of the first light-emitting control circuit is configured to receive a first light-emitting control signal, a first terminal of the first light-emitting control circuit is electrically connected to a first terminal of the driving circuit, a second terminal of the first light-emitting control circuit is electrically connected to a second voltage terminal to receive a second power supply voltage, and the first light-emitting control circuit is configured to apply the second power supply voltage to the first terminal of the driving circuit in response to the first light-emitting control signal; and A second light-emitting control circuit, wherein the control end of the second light-emitting control circuit is configured to receive a second light-emitting control signal, the second light-emitting control signal is different from the first light-emitting control signal, the first end of the second light-emitting control circuit is electrically connected to the second end of the drive circuit, the second end of the second light-emitting control circuit is electrically connected to the first electrode of the light-emitting element, and the second light-emitting control circuit is configured to apply the drive current to the light-emitting element in response to the second light-emitting control signal.

13. The pixel circuit according to any one of claims 10 to 12, further comprising: a direct reset circuit, wherein a control terminal of the direct reset circuit is configured to receive a direct reset control signal, a first terminal of the direct reset circuit is electrically connected to a second terminal of the drive circuit, a second terminal of the direct reset circuit is electrically connected to a second reset signal terminal to receive a second reset signal, and the direct reset circuit is configured to directly apply the second reset signal to the second terminal of the drive circuit in response to the direct reset control signal; The direct reset circuit includes a direct reset transistor, a gate of the direct reset transistor is electrically connected to a direct reset control signal terminal to receive a direct reset control signal, a first electrode of the direct reset transistor is electrically connected to a second terminal of the drive circuit, and a second electrode of the direct reset transistor is electrically connected to the second reset signal terminal to receive the second reset signal.

14. The pixel circuit according to claim 13, wherein: The value of the first reset signal is equal to the value of the second reset signal.

15. The pixel circuit according to any one of claims 12 to 14, wherein: The first light emitting control circuit comprises a first light emitting control transistor, a gate of the first light emitting control transistor is electrically connected to a first light emitting control terminal to receive the first light emitting control signal, a first electrode of the first light emitting control transistor is electrically connected to a first terminal of the driving circuit, and a second electrode of the first light emitting control transistor is electrically connected to the second voltage terminal to receive the second power supply voltage; The second light-emitting control circuit includes a second light-emitting control transistor, a gate of the second light-emitting control transistor is electrically connected to a second light-emitting control terminal to receive the second light-emitting control signal, a first electrode of the second light-emitting control transistor is electrically connected to a second terminal of the driving circuit, and a second electrode of the second light-emitting control transistor is electrically connected to a first electrode of the light-emitting element.

16. The pixel circuit according to any one of claims 10 to 15, further comprising: The auxiliary compensation circuit comprises a second compensation capacitor, wherein a first electrode of the second compensation capacitor is electrically connected to a second end of the driving circuit, and a second electrode of the second compensation capacitor is configured to receive a first constant signal.

17. The pixel circuit according to claim 16, wherein: The second electrode of the second compensation capacitor is electrically connected to the second voltage terminal, and the second power supply voltage serves as the first constant signal; or The second electrode of the second compensation capacitor is electrically connected to the first reset signal terminal, and the first reset signal serves as the first constant signal; or The second electrode of the second compensation capacitor is electrically connected to an external constant signal terminal outside the pixel circuit to receive the first constant signal from the external constant signal terminal.

18. The pixel circuit according to any one of claims 1 to 17, further comprising: The auxiliary circuit comprises an auxiliary capacitor, wherein a first electrode of the auxiliary capacitor is electrically connected to a gate of the data writing transistor, and a second electrode of the auxiliary capacitor is configured to receive a second constant signal.

19. The pixel circuit according to any one of claims 12 or 15, further comprising: a third reset circuit, wherein a control end of the third reset circuit is configured to receive a third reset control signal, a first end of the third reset circuit is electrically connected to a first end of the drive circuit, a second end of the third reset circuit is electrically connected to a control end of the drive circuit, and the third reset circuit is configured to allow the second power supply voltage to be applied to the control end of the drive circuit in response to the third reset control signal; and The compensation control circuit comprises a compensation control capacitor, wherein a first electrode of the compensation control capacitor is electrically connected to a control end of the driving circuit, and a second electrode of the compensation control capacitor is electrically connected to a first electrode of the light emitting element.

20. The pixel circuit according to claim 19, wherein: The driving circuit includes a driving transistor, the gate of the driving transistor serves as the control terminal of the driving circuit, the first electrode of the driving transistor serves as the first terminal of the driving circuit, and the second electrode of the driving transistor serves as the second terminal of the driving circuit; the third reset circuit includes a third reset transistor, the gate of the third reset transistor is electrically connected to the third reset control terminal to receive the third reset control signal, the first electrode of the third reset transistor is electrically connected to the first electrode of the driving transistor, and the second electrode of the third reset transistor is electrically connected to the gate of the driving transistor.

21. A display device, comprising the pixel circuit according to any one of claims 1 to 20.

22. A driving method for a pixel circuit, applicable to the pixel circuit according to any one of claims 1 to 20, the driving method comprising: In the data writing and compensation stage, the data scanning signal is set as a start signal to turn on the data writing transistor, and the data signal is written into the second end of the driving circuit through the data writing transistor and the first compensation capacitor.

23. The driving method according to claim 22, wherein: The pixel circuit further comprises a data writing circuit, wherein a control end of the data writing circuit is configured to receive a data scanning signal, a first end of the data writing circuit is electrically connected to a second end of the driving circuit, and a second end of the data writing circuit is electrically connected to a data signal end to receive the data signal; The driving method further includes: In the data writing and compensation phase, the data scanning signal is set to be an on signal to write the data signal into the second end of the driving circuit; and When entering the light-emitting stage from the data writing and compensation stage, the data scanning signal is changed from The on signal is converted into an off signal to turn off the data writing transistor, wherein in the light emitting phase, the data scanning signal remains as an off signal.

24. The driving method according to claim 22 or 23, wherein: In the step of writing the data signal into the second end of the driving circuit through the data writing transistor and the first compensation capacitor, The difference between the initial voltage value Vc11 of the first electrode of the first compensation capacitor before entering the data writing and compensation stage and the stable voltage value Vc12 during the data writing and compensation stage is a first variation ΔVc1. The difference between the initial voltage value Vc13 of the second electrode of the first compensation capacitor before entering the data writing and compensation stage and its stable voltage value Vc14 during the data writing and compensation stage is a second change amount △Vc2, and the first change amount △Vc1 is equal to the second change amount △Vc2.

25. The driving method according to claim 22 or 23, wherein: The pixel circuit further includes an auxiliary compensation circuit, the auxiliary compensation circuit includes a second compensation capacitor, wherein a first electrode of the second compensation capacitor is electrically connected to a second end of the driving circuit, and a second electrode of the second compensation capacitor is configured to receive a first constant signal; In the step of writing the data signal into the second end of the driving circuit through the data writing transistor and the first compensation capacitor, The first compensation capacitor is connected in series with the second compensation capacitor. During the data writing and compensation stage, the voltage Vc3 at the second end of the driving circuit is Vdata=(Vdata-Vref)×[C1 / (C1+C2)]+Vini1, where Vdata represents the value of the data signal, Vref represents the initial voltage value of the first electrode of the first compensation capacitor before entering the data writing and compensation stage, C1 represents the capacitance value of the first compensation capacitor, C2 represents the capacitance value of the second compensation capacitor, and Vini1 represents the initial voltage value of the second end of the driving circuit before entering the data writing and compensation stage.

26. The driving method according to claim 24 or 25, wherein: The pixel circuit further includes: a light emitting element, a first reset circuit, a second reset circuit, a third reset circuit, a first light emitting control circuit and a second light emitting control circuit. The second end of the driving circuit is electrically connected to the first electrode of the light-emitting element, and the driving circuit is configured to control the magnitude of the driving current flowing through the light-emitting element; the control end of the first reset circuit is configured to receive a first reset control signal, the first end of the first reset circuit is electrically connected to the first electrode of the first compensation capacitor, and the second end of the first reset circuit is electrically connected to the reference signal end. connected to receive a reference signal; the control end of the second reset circuit is configured to receive a second reset control signal, the first end of the second reset circuit is electrically connected to the first electrode of the light-emitting element, and the second end of the second reset circuit is electrically connected to the first reset signal end to receive the first reset signal; the control end of the third reset circuit is configured to receive a third reset control signal, the first end of the third reset circuit is electrically connected to the first end of the drive circuit, and the second end of the third reset circuit is electrically connected to the control end of the drive circuit; the control end of the first light-emitting control circuit is configured to receive a first light-emitting control signal, the first end of the first light-emitting control circuit is electrically connected to the first end of the drive circuit, and the second end of the first light-emitting control circuit is electrically connected to the second voltage end to receive a second power supply voltage; the control end of the second light-emitting control circuit is configured to receive a second light-emitting control signal, the first end of the second light-emitting control circuit is electrically connected to the second end of the drive circuit, and the second end of the second light-emitting control circuit is electrically connected to the first electrode of the light-emitting element; The driving method further comprises: in a reset phase before the compensation phase, The first reset control signal is set as a start signal to start the first reset circuit, wherein the first reset circuit applies the reference signal to the first electrode of the first compensation capacitor; the first light-emitting control signal is set as a start signal to start the first light-emitting control circuit, wherein the first light-emitting control circuit applies the second power supply voltage to the first end of the drive circuit; the third reset control signal is set as a start signal to start the third reset circuit, wherein the third reset circuit applies the second power supply voltage to the control end of the drive circuit; the second reset control signal is set as a start signal to start the second reset circuit, wherein the second reset circuit applies the first reset signal to the first electrode of the light-emitting element; and The second light-emitting control signal is set as a start signal to turn on the second light-emitting control circuit; the first reset signal is applied to the second end of the driving circuit via the second light-emitting control circuit, and the value of the first reset signal is Vini1, so that the initial voltage value of the second end of the driving circuit before entering the data writing and compensation stage is Vini1; and / or, The pixel circuit also includes a direct reset circuit, the control end of the direct reset circuit is configured to receive a direct reset control signal, the first end of the direct reset circuit is electrically connected to the second end of the drive circuit, and the second end of the direct reset circuit is electrically connected to the second reset signal end to receive the second reset signal; in the light-emitting stage, the driving method also includes: making the direct reset control signal an on signal to turn on the direct reset circuit, applying the second reset signal to the second end of the drive circuit, and the value of the second reset signal is Vini2, so that the second end of the drive circuit The initial voltage value of the terminal before entering the data writing and compensation phase is Vini2.

27. The driving method according to claim 22 or 23, wherein: The pixel circuit further includes a compensation control circuit, the compensation control circuit includes a compensation control capacitor, wherein a first electrode of the compensation control capacitor is electrically connected to the gate of the driving transistor, and a second electrode of the compensation control capacitor is electrically connected to the first electrode of the light-emitting element; The driving method also includes: in the data writing and compensation stage, setting the second reset control signal to a start signal to turn on the second reset circuit, wherein the second reset circuit applies the first reset signal to the first electrode of the light-emitting element and the second electrode of the compensation control capacitor.

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