Level conversion assembly, overcurrent protection method, and display device

Abstract

A level conversion assembly (50), an overcurrent protection method, and a display device. The level conversion assembly (50) comprises a level conversion module (51); and the level conversion module (51) comprises a control unit (511), a current measurement unit (512), a level conversion unit (513), and an overcurrent protection unit (514). When at a first falling edge of a digital clock signal (CPV), the control unit (511) determines, on the basis of a correspondence of a current display mode, a first analog clock signal corresponding to the first falling edge among a plurality of analog clock signals (CLK1-CLK8), and controls the current measurement unit (512) to measure the current of the first analog clock signal; and the moment of a falling edge of the digital clock signal (CPV) is at the last row of a high-level period or low-level period in a corresponding analog clock signal, so that the current measurement unit (512) can send an overcurrent signal to the overcurrent protection unit (514) when the current of the first analog clock signal is not within a current threshold range, thereby achieving the effect of improving the accuracy of overcurrent detection.

Description

Level conversion component, overcurrent protection method and display device Technical Field

[0001] The present application relates to the field of display technology, and in particular to a level conversion component, an overcurrent protection method, and a display device. Background Art

[0002] The level conversion component is a component in a display device, which is used to convert the level of a clock signal so as to drive a display panel in the display device to display.

[0003] A level conversion component includes a level conversion module and an overcurrent protection module. The level conversion module is used to implement level conversion. The overcurrent protection module is used to monitor the current of each circuit in the level conversion component in real time. When the current is greater than a preset threshold, it determines that an overcurrent phenomenon has occurred and performs an overcurrent protection operation (such as power off).

[0004] However, when the level conversion component operates normally, the current of some lines may also exceed the preset threshold value, which results in low accuracy of the level conversion component in detecting overcurrent phenomena.

[0005] Summary of the Invention

[0006] The present invention provides a level conversion component, an overcurrent protection method, and a display device. The technical solution is as follows:

[0007] According to a first aspect of the present application, a level conversion component is provided, the level conversion component being used in a display device, the level conversion component comprising a level conversion module, the level conversion module comprising a control unit, a current detection unit, a level conversion unit, and an overcurrent protection unit;

[0008] The level conversion unit is used to obtain a digital clock signal and obtain multiple analog clock signals based on the digital clock signal;

[0009] The control unit is configured to determine, at a first falling edge of the digital clock signal, a first analog clock signal corresponding to the first falling edge among the multiple analog clock signals based on a correspondence relationship of a current display mode, wherein the correspondence relationship includes the analog clock signal corresponding to the falling edge of the digital clock signal among the multiple analog clock signals, and the falling edge of the digital clock signal is located at the last row of a high-level period or the last row of a low-level period in the corresponding analog clock signal;

[0010] The control unit is used to control the current detection unit to detect the current of the first analog clock signal;

[0011] The current detection unit is configured to send an overcurrent signal to the overcurrent protection unit when the current of the first analog clock signal is not within a current threshold range.

[0012] Optionally, the level conversion module further includes a falling edge trigger, which is used to monitor the digital clock signal and send a falling edge signal to the control unit when a falling edge of the digital clock signal is detected.

[0013] Optionally, the control unit includes a shift register, which is electrically connected to the falling edge trigger, and the shift register is used to control the current detection unit to detect the current of the analog clock signal corresponding to the falling edge based on the corresponding relationship when triggered by the falling edge signal.

[0014] Optionally, the control unit further includes a controller and a conversion matrix circuit, and the controller is electrically connected to the conversion matrix circuit;

[0015] The conversion matrix circuit is electrically connected to the shift register and the current detection unit respectively;

[0016] The current detection unit includes a plurality of current detection sub-units, and the plurality of current detection sub-units are respectively used to detect the currents of the plurality of analog clock signals;

[0017] The controller is used to control the conversion matrix circuit to electrically connect the shift register to the first current detection subunit among the multiple current detection subunits at the first falling edge, and the first current detection subunit is used to detect the current of the first analog clock signal under the control of the shift register.

[0018] Optionally, the current detection subunit includes a switch unit and a current detection unit, the switch unit is electrically connected to the current detection unit, and the switch unit is electrically connected to the conversion matrix circuit;

[0019] The shift register is used to send a start signal to the conversion matrix circuit when receiving the falling edge signal, so that the conversion matrix circuit transmits the start signal to the switch unit in the first current detection subunit, and the switch unit is used to turn on the current detection unit in the first current detection subunit.

[0020] Optionally, the level conversion module also includes a memory, which stores clock signal data, and the clock signal data includes data of the multiple analog clock signals and the digital clock signal. The memory is electrically connected to the controller, and the controller is used to control the conversion matrix circuit based on the clock signal data so that the conversion matrix circuit electrically connects the shift register to the first current detection sub-unit among the multiple current detection sub-units at the first falling edge.

[0021] Optionally, the clock signal data includes the number of cycles of the analog clock signal, and the controller is used to control the shift register based on the number of cycles of the multiple analog clock signals so that the number of bits of the shift register is the same as the number of cycles of the analog clock signal.

[0022] Optionally, the conversion matrix circuit includes a plurality of input channels and a plurality of output channels, the plurality of input channels are electrically connected to the shift register, and the plurality of output channels are electrically connected to the plurality of current detection subunits;

[0023] The controller is further configured to determine a target display mode matching the current display mode from a plurality of preset display modes, wherein the plurality of preset display modes each have a corresponding relationship, wherein the corresponding relationship includes a connection relationship between the plurality of input channels and the plurality of output channels;

[0024] The controller is further configured to control the conversion matrix circuit based on the corresponding relationship between the target display modes.

[0025] Optionally, the display device includes a frame start signal line, and the level conversion module further includes a reset unit, and the reset unit is electrically connected to the frame start signal line and the shift register respectively;

[0026] The reset unit is used to reset the shift register when receiving the frame start signal in the frame start signal line.

[0027] Optionally, the reset unit includes a rising edge trigger and a reset switch, the rising edge trigger is electrically connected to the frame start signal line and the reset switch respectively, and the reset switch is electrically connected to the shift register.

[0028] Optionally, the display device includes at least two digital clock signal lines, the number of the control units is at least two, and the at least two control units are electrically connected to the at least two digital clock signal lines in a one-to-one correspondence.

[0029] Optionally, the display device includes a digital clock signal line, the number of the control unit is 1, and the control unit is electrically connected to the digital clock signal line.

[0030] Optionally, the digital clock signal includes a first digital clock signal and a second digital clock signal, and the level conversion unit is used to obtain the multiple analog clock signals arranged in sequence based on the first digital clock signal and the second digital clock signal, and among any two adjacent analog clock signals of the multiple analog clock signals, the latter analog clock signal is one row behind the previous analog clock signal.

[0031] Optionally, the number of the level conversion modules is two, and the two level conversion modules are respectively a first level conversion module and a second level conversion module, the first level conversion module and the second level conversion module are configured to jointly generate n analog clock signals, and among any two adjacent analog clock signals of the n analog clock signals, the latter analog clock signal is one row behind the previous analog clock signal;

[0032] The level conversion unit in the first level conversion module is used to obtain a first digital clock signal and a second digital clock signal, and generate an odd-numbered analog clock signal among the n analog clock signals based on the first digital clock signal and the second digital clock signal;

[0033] The level conversion unit in the second level conversion unit is used to obtain a third digital clock signal and a fourth digital clock signal, and generate an even-numbered analog clock signal among the n analog clock signals based on the third digital clock signal and the fourth digital clock signal;

[0034] The duty cycles of the first digital clock signal, the second digital clock signal, the third digital clock signal, and the fourth digital clock signal are all greater than 50%.

[0035] Optionally, the number of the level conversion modules is two, and the two level conversion modules are respectively a first level conversion module and a second level conversion module, the first level conversion module and the second level conversion module are used to jointly generate n analog clock signals, the n analog clock signals include multiple analog clock signal groups, each analog clock signal group includes two adjacent analog clock signals, and in any two adjacent analog clock signal groups, the latter analog clock signal group is one row behind the previous analog clock signal group;

[0036] The level conversion unit in the first level conversion module is used to obtain a first digital clock signal and a second digital clock signal, and generate an odd-numbered analog clock signal among the n analog clock signals based on the first digital clock signal and the second digital clock signal;

[0037] The level conversion unit in the second level conversion module is used to obtain a third digital clock signal and a fourth digital clock signal, and generate an even-numbered analog clock signal among the n analog clock signals based on the third digital clock signal and the fourth digital clock signal.

[0038] Optionally, the digital clock signal includes a first digital clock signal, and the level conversion unit is used to obtain the multiple analog clock signals arranged in sequence based on the first digital clock signal, and among any two adjacent analog clock signals among the multiple analog clock signals, the latter analog clock signal is one row behind the previous analog clock signal.

[0039] Optionally, the display device includes a driving circuit, the driving circuit is used to obtain the multiple analog clock signals output by the level conversion unit, and drive the display device to display based on the multiple analog clock signals;

[0040] The overcurrent protection unit is configured to determine whether an overcurrent phenomenon occurs based on the overcurrent signal when the overcurrent signal is received.

[0041] According to another aspect of an embodiment of the present application, an overcurrent protection method is provided for the above-mentioned level conversion component, the method comprising:

[0042] Acquire a digital clock signal, and obtain multiple analog clock signals based on the digital clock signal;

[0043] At a first falling edge of the digital clock signal, determining a first analog clock signal corresponding to the first falling edge among the multiple analog clock signals based on a corresponding relationship, wherein the corresponding relationship includes the analog clock signal corresponding to the falling edge of the digital clock signal among the multiple analog clock signals, and the falling edge of the digital clock signal is located at the last row of a high-level period or the last row of a low-level period in the corresponding analog clock signal;

[0044] detecting a current of the first analog clock signal;

[0045] When the current of the first analog clock signal is not within the current threshold range, overcurrent protection detection is performed.

[0046] Optionally, the performing overcurrent protection detection includes:

[0047] determining whether there are a preset number of analog clock signals among the plurality of analog clock signals whose currents are not within the current threshold range;

[0048] When currents of a preset number of analog clock signals among the plurality of analog clock signals are not within the current threshold range, it is determined that an overcurrent phenomenon occurs.

[0049] According to another aspect of an embodiment of the present application, a display device is provided, comprising a display panel and the above-mentioned level conversion component.

[0050] Optionally, the display device also includes a timing controller and a driving circuit, and the level conversion component is electrically connected to the timing controller and the driving circuit respectively. The timing controller is used to provide a digital clock signal to the level conversion component, and the driving circuit is used to drive the display panel based on the analog clock signal provided by the level conversion component.

[0051] The beneficial effects of the technical solutions provided in the embodiments of the present application include at least:

[0052] The control unit determines the first analog clock signal corresponding to the first falling edge of the digital clock signal based on the corresponding relationship of the current display mode at the first falling edge of the digital clock signal, and controls the current detection unit to detect the current of the first analog clock signal. Since the falling edge of the digital clock signal is located at the last row of the high level period or low level period in the corresponding analog clock signal, and under normal circumstances, the current of the last row of the high level period or low level period should be zero, the current detection unit can send an overcurrent signal to the overcurrent protection unit when the current of the first analog clock signal is not within the current threshold range. This solves the problem of low accuracy in detecting overcurrent phenomena in related technologies and achieves the effect of improving the accuracy of detecting overcurrent phenomena. BRIEF DESCRIPTION OF THE DRAWINGS

[0053] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0054] FIG1 is a schematic diagram of a partial structure of a display device according to an embodiment of the present application;

[0055] FIG2 is a schematic diagram of the level conversion component shown in FIG1 ;

[0056] FIG3 is a schematic diagram of the level conversion component shown in FIG2 generating an analog clock signal based on a digital clock signal;

[0057] FIG4 is a schematic diagram of voltage and current of a portion of the circuits in the schematic diagram shown in FIG2 ;

[0058] FIG5 is a schematic diagram of voltage and current at different refresh frequencies;

[0059] FIG6 is a schematic structural diagram of a level conversion component provided in an embodiment of the present application;

[0060] FIG7 is a schematic diagram of a digital clock signal and an analog clock signal of the level conversion component shown in FIG6 ;

[0061] FIG8 is a schematic structural diagram of another level conversion component provided in an embodiment of the present application;

[0062] FIG9 is a schematic structural diagram of another level conversion component provided in an embodiment of the present application;

[0063] FIG10 is a schematic diagram of an analog clock signal and a digital clock signal of the level conversion component shown in FIG9 ;

[0064] FIG11 is a schematic structural diagram of another level conversion component provided in an embodiment of the present application;

[0065] FIG12 is a schematic diagram of an analog clock signal and a digital clock signal of the level conversion component shown in FIG11;

[0066] FIG13 is a schematic diagram of an analog clock signal and a digital clock signal of the level conversion component shown in FIG11;

[0067] FIG14 is a flow chart of an overcurrent protection method provided by an embodiment of the present application;

[0068] FIG15 is a waveform diagram of a display device when an analog digital signal line is short-circuited;

[0069] FIG16 is a waveform diagram of another analog digital signal line short circuit in the display device;

[0070] FIG17 is a waveform diagram of another analog digital signal line short circuit in the display device;

[0071] FIG18 is a waveform diagram showing another analog digital signal line short circuit in a display device.

[0072] The above drawings illustrate specific embodiments of the present application, which will be described in more detail below. These drawings and the textual description are not intended to limit the scope of the present application in any way, but rather to illustrate the concepts of the present application to those skilled in the art by reference to specific embodiments. DETAILED DESCRIPTION

[0073] In order to make the objectives, technical solutions and advantages of this application clearer, the implementation methods of this application will be further described in detail below with reference to the accompanying drawings.

[0074] FIG1 is a schematic diagram of a partial structure of a display device according to an embodiment of the present application. FIG1 may include a timing controller 10 , a level conversion component 20 , and a driving circuit 30 .

[0075] The level conversion component 20 can be electrically connected to the timing controller (TCON) 10 and the driving circuit 30 respectively. The level conversion component 20 can include a level conversion integrated circuit (Level Shift IC). The timing controller 10 can input a digital clock signal (CPV) to the level conversion component 20. The level conversion component 20 can generate multiple analog clock signals (CLK) based on the digital clock signal and input these multiple analog clock signals into the driving circuit 30. The driving circuit 30 can drive the display panel in the display device based on the multiple analog clock signals. The driving circuit 30 can be a gate driving circuit or some other driving circuit. The driving circuit 30 can be located outside the display panel or inside the display panel.

[0076] Figure 2 is a schematic diagram of the level conversion component shown in Figure 1, and Figure 3 is a schematic diagram of the level conversion component shown in Figure 2 generating an analog clock signal based on a digital clock signal (the horizontal direction in Figure 3 can represent time, and the vertical direction can represent voltage). Please refer to Figures 2 and 3, wherein the level conversion component 20 receives two digital clock signals CPV1 and CPV2, and the level conversion component 20 can generate multiple analog clock signals based on these two digital clock signals CPV1 and CPV2 (Figure 2 shows the case of 8 analog clock signals CLK1 to CLK8, but the embodiment of the present application is not limited to this). Specifically, the level conversion component 20 can control the rising edge of the analog clock signal based on each rising edge of the digital clock signal CPV1, and control the falling edge of the analog clock signal based on each rising edge of the digital clock signal CPV2.

[0077] Exemplarily, the level conversion component 20 can generate the first rising edge of CLK1 at the first rising edge of the digital clock signal CPV1, and generate the first rising edge of CLK2 at the second rising edge of the digital clock signal CPV1, and so on, to generate eight rising edges of CLK; correspondingly, the level conversion component 20 can generate the first falling edge of CLK1 at the first rising edge of the digital clock signal CPV2, and generate the first falling edge of CLK2 at the second rising edge of the digital clock signal CPV2, and so on, to generate eight falling edges of CLK.

[0078] It should be noted that in each CLK, the period of time with a higher potential after the rising edge and before the falling edge can be called a high-level period, and the period of time with a lower potential after the falling edge and before the rising edge can be called a low-level period. Each CLK can include multiple high-level periods and low-level periods arranged at intervals. A high-level period and an adjacent low-level period can be called a CLK cycle. Each CLK cycle can be divided into multiple rows (1H shown in Figure 3 is a row), and one of the multiple rows of each CLK cycle can correspond to a sub-pixel row in the display panel. Each CLK cycle can include m rows of high level and n rows of low level, and m+n=the number of CLKs. For example, if there are 8 CLKs, then m+n=8. Figure 3 shows the case where m=4, n=4, and m+n=8.

[0079] In addition, the rows of analog clock signals involved in the embodiments of the present application may include rows in the spatial domain (referred to as spatial domain rows) and rows in the time domain (referred to as time domain rows). The rows in the spatial domain may be 1H in Figure 3. The rows in the spatial domain may correspond to a sub-pixel row, and the rows in the time domain may refer to the difference between adjacent analog clock signals in the time domain. For example, in Figure 3, the adjacent analog clock signals differ by one spatial domain row in the time domain. In this case, the time domain rows and the spatial domain rows are one-to-one. Of course, a time domain row may also correspond to two or more spatial domain rows. In the embodiments of the present application, unless otherwise specified, a row may refer to a time domain row.

[0080] FIG4 is a schematic diagram of voltage and current for a portion of the circuits in the schematic diagram shown in FIG2 . Referring to FIG4 , when the circuit containing the digital clock signal CLK1 is not short-circuited or otherwise faulty, a current will be generated in the circuit containing CLK1 due to the voltage jump at the rising edge of CLK1. The magnitude of this current is determined by the resistance and capacitance of the circuit containing CLK1, and this current decays rapidly. In some current level shifting groups, a detection time dt is determined within the CLK cycle. The detection time dt is then used to determine whether the current exceeds a threshold at this time, and based on this, whether overcurrent protection is to be performed. This detection time dt can be a time after the rising edge, separated by a preset time interval T1.

[0081] However, there are two problems with this:

[0082] On the one hand, the accuracy of the detection time dt is difficult to guarantee. The current accuracy of the detection time dt is plus or minus 20%, which may lead to large errors and thus misjudgment. For example, when two adjacent CLKs are short-circuited, the short-circuit current generated only exists within a line time, so the preset time length T1 is set to be less than a line time to ensure that such a short circuit can be detected. The line time is constantly decreasing with the demand for high resolution and high refresh rate. For example, the line time of 4K 120Hz is 3.7us, and the line time of 4K 240Hz and 8K 120Hz is 1.85us. In other words, the preset time length T1 must also become smaller and smaller.

[0083] When the preset duration T1 is set relatively short and CLK is short-circuited, the CLK current consists of two components: the normal current generated by the CLK voltage jump, which gradually decreases, generally reaching zero within 2 microseconds; and the short-circuit current. If the preset duration T1 is set improperly, the detection time dt may fall during the normal current decay period. Fluctuations in the preset duration T1 due to errors can cause the current value detected at the detection time dt to fluctuate widely, easily leading to false triggering or non-triggering. Improving the accuracy of the detection time dt significantly increases the cost of the level-shifting integrated circuit.

[0084] On the other hand, when the CLK line time changes, for example, the whole machine mode switches from a 60 Hz refresh mode to a 120 Hz refresh mode, the CLK line time changes from 7.4 us to 3.7 us. If the preset duration T1 is set according to 60 Hz, then after the mode is switched to 120 Hz, some short circuit and high current situations will occur and the protection cannot be triggered, as shown in Figure 5 below. Figure 5 is a schematic diagram of voltage and current at different refresh frequencies, wherein the first refresh rate can be 60 Hz and the second refresh rate can be 120 Hz. If the preset duration T1 is the same at the two refresh rates, then at the first refresh rate, the current detected at the detection moment dt will be greater than the threshold DL, and at the second refresh rate, the current detected at the detection moment dt will be less than the threshold DL, so there will be a problem of false triggering.

[0085] The level conversion component provided in the embodiments of the present application can solve some problems existing in the related art.

[0086] Figure 6 is a structural schematic diagram of a level conversion component provided in an embodiment of the present application. The level conversion component is used in a display device. The level conversion component 50 may include a level conversion module 51. The level conversion module 51 includes a control unit 511, a current detection unit 512, a level conversion unit 513 and an overcurrent protection unit 514.

[0087] The level conversion unit 513 is used to obtain the digital clock signal CPV, and obtain multiple analog clock signals based on the digital clock signal CPV ( FIG. 6 shows that the analog clock signals include CLK1 ˜ CLK8 , but this is not limiting).

[0088] The control unit 511 is used to determine the first analog clock signal corresponding to the first falling edge in multiple analog clock signals based on the corresponding relationship of the current display mode at the first falling edge of the digital clock signal, the corresponding relationship including the analog clock signal corresponding to the falling edge of the digital clock signal in multiple analog clock signals, and the moment at which the falling edge of the digital clock signal is located in the last row of the high level period or the last row of the low level period in the corresponding analog clock signal.

[0089] The control unit 511 is configured to control the current detection unit 512 to detect the current of the first analog clock signal.

[0090] The current detection unit 512 is configured to send an overcurrent signal to the overcurrent protection unit 514 when the current of the first analog clock signal is not within a current threshold range.

[0091] The current of the first analog clock signal may refer to the current of the circuit where the first analog clock signal is located. In addition, the embodiment of the present application does not limit the first analog clock signal to CLK1, and the first analog clock signal may be any one of multiple analog clock signals.

[0092] In summary, the level conversion component provided in the embodiment of the present application determines the first analog clock signal corresponding to the first falling edge in multiple analog clock signals based on the corresponding relationship of the current display mode through the control unit at the first falling edge of the digital clock signal, and controls the current detection unit to detect the current of the first analog clock signal. Since the falling edge of the digital clock signal is located at the last row of the high level period or low level period in the corresponding analog clock signal, and under normal circumstances, the current of the last row of the high level period or low level period should be zero, the current detection unit can send an overcurrent signal to the overcurrent protection unit when the current of the first analog clock signal is not within the current threshold range. In this way, the problem of low accuracy in detecting overcurrent phenomena in the related art is solved, and the accuracy of detecting overcurrent phenomena is improved.

[0093] In addition, when the CPV cycle, that is, the line time, changes, the refresh rate changes accordingly. However, in this application example, the correspondence between the falling edge of the digital clock signal and the analog clock signal does not change. The detection is still performed on the last line, and the detection effect does not change. That is, this solution is suitable for various situations where the refresh rate changes.

[0094] The above-mentioned current threshold range may be different in different application scenarios. For example, the current threshold range may be less than or equal to a specified value, and the specified value may be 30 mA to 200 mA.

[0095] The level conversion component provided in the embodiment of the present application can be applied to various display modes, and different display modes can correspond to different digital clock signals and different analog clock signals. When the digital clock signal and the analog clock signal are different, the corresponding relationship between the falling edge of the digital clock signal and the corresponding analog clock signal in multiple analog clock signals will also be different. However, in general, in this corresponding relationship, the moment at which the falling edge of the digital clock signal occurs will be located at the last row of the high level period or the last row of the low level period in the corresponding analog clock signal. The specific corresponding relationship for each case can be determined in advance based on the actual signal situation.

[0096] In an exemplary embodiment, the control unit 511 is used to determine a preset display mode that matches the current display mode from multiple preset display modes, and obtain a corresponding relationship between the preset display modes that match the current display mode, and multiple preset display modes all have corresponding corresponding relationships. For example, the first preset mode is to generate 8 analog clock signals CLK from two digital clock signals CPV1 and CPV2, wherein the 7th falling edge of CPV1 corresponds to the detection of the low-level period of CLK8, and the 8th falling edge corresponds to the detection of the low-level period of CLK1; the second preset mode is to generate 10 analog clock signals from two digital clock signals, wherein the 9th falling edge of CPV1 corresponds to the detection of the low-level period of CLK10, and the 10th falling edge corresponds to the detection of the low-level period of CLK1, and so on; in this way, the level conversion component can be applied to multiple display modes.

[0097] The level conversion assembly shown in FIG6 includes a level conversion unit 513, which can receive a digital clock signal and generate multiple analog clock signals based on the digital clock signal. The display device in which the level conversion assembly is used includes a digital clock signal line. The number of control units 511 is one, and the control unit 511 is electrically connected to the digital clock signal line.

[0098] For example, FIG7 is a schematic diagram of a digital clock signal and an analog clock signal of the level conversion component shown in FIG6. Referring to FIG7, the digital clock signal includes a first digital clock signal CPV1. The level conversion unit 513 is used to obtain a plurality of analog clock signals arranged in sequence based on the first digital clock signal CPV1, and among any two adjacent analog clock signals in the plurality of analog clock signals, the latter analog clock signal is one row behind the previous analog clock signal (shifted right by one CPV cycle in FIG7). FIG7 shows a case where the level conversion unit generates eight analog clock signals CLK1 to CLK8 based on the first digital clock signal CPV1, but the embodiment of the present application is not limited to this. FIG7 shows a case where one time domain row is equal to two space domain rows.

[0099] Specifically, the level conversion unit may determine the rising edge and the falling edge of each CLK based on each rising edge of CPV.

[0100] In this case, the corresponding relationship may include:

[0101] The first CPV falling edge corresponds to CLK2;

[0102] The second CPV falling edge corresponds to CLK3;

[0103] The third CPV falling edge corresponds to CLK4, CLK1;

[0104] The fourth CPV falling edge corresponds to CLK5, CLK2;

[0105] The fifth CPV falling edge corresponds to CLK6, CLK3;

[0106] The sixth CPV falling edge corresponds to CLK7, CLK4;

[0107] The 7th CPV falling edge corresponds to CLK8, CLK5;

[0108] The 8th CPV falling edge corresponds to CLK1, CLK6;

[0109] The 9th CPV falling edge corresponds to CLK2, CLK7;

[0110] The 10th CPV falling edge corresponds to CLK3, CLK8;

[0111] The 11th CPV falling edge corresponds to CLK4, CLK1;

[0112] Then cycle periodically.

[0113] Figure 8 is a structural schematic diagram of another level conversion component provided in an embodiment of the present application, wherein the level conversion module 51 also includes a falling edge trigger 515, which is used to monitor the digital clock signal CPV and send a falling edge signal to the control unit 511 when the falling edge of the digital clock signal CPV is detected.

[0114] The control unit 511 includes a shift register 511a, which is electrically connected to the falling edge trigger 515. The shift register 511a is used to store the falling edge signal bit by bit, that is, the first falling edge signal is stored in the first bit, the second falling edge signal is stored in the second bit, until the eighth falling edge signal is stored in the eighth bit. Because the number of bits of the shift register is controlled by the controller 511b, the number of bits is consistent with the number of analog clock signals CLK, and then the ninth falling edge signal is stored in the first bit, and so on.

[0115] The control unit 511 further includes a conversion matrix circuit 511 c . One end of the conversion matrix circuit 511 c is electrically connected to the shift register 511 a , and the other end is electrically connected to the current detection unit 512 .

[0116] The current detection unit 512 includes multiple current detection sub-units (512a, 512b, 512c, etc.), and the multiple current detection sub-units 5121 are respectively used to detect the currents of multiple analog clock signals. For example, the current detection sub-unit 512a is used to detect the current of the analog clock signal CLK1, and the current detection sub-unit 521b is used to detect the current of the analog clock signal CLK2.

[0117] The end of the conversion matrix circuit 511c electrically connected to the shift register 511a may include multiple input channels, and the order of the multiple input channels is consistent with the order of the bits of the shift register 511a, that is, the first bit of the shift register 511a corresponds to the first input channel of the conversion matrix circuit 511c, and so on; the end of the conversion matrix circuit 511c connected to the current detection unit 512 may include multiple output channels, and the order of the multiple output channels is consistent with the order of the analog clock signal, that is, the first output channel is connected to the current detection subunit 512a corresponding to the analog clock signal CLK1, the second output channel is connected to the current detection subunit 512b corresponding to the analog clock signal CLK2, and so on.

[0118] The controller 511b is also used to determine a target display mode that matches the current display mode among multiple preset display modes. The multiple preset display modes all have corresponding correspondences, which may include the connection relationship between multiple input channels and multiple output channels of the conversion matrix circuit 511c.

[0119] The controller 511b is also used to control the conversion matrix circuit 511c based on the corresponding relationship corresponding to the target display mode. The conversion matrix circuit 511c can modulate the corresponding relationship between the input channel and the output channel. For example, in one corresponding relationship, the first input channel is connected to the second output channel, the second input channel is connected to the third output channel, the third input channel is connected to the fourth output channel and the first output channel, the fourth output channel is connected to the fifth output channel and the second output channel, and so on.

[0120] Under such a structure, when the shift register 511a receives the falling edge signal triggered by the first falling edge, it can be electrically connected to the circuit for detecting CLK2 to detect the current of CLK2. When it receives the falling edge signal triggered by the second falling edge, it can be electrically connected to the circuit for detecting CLK3 to detect the current of CLK3. When it receives the falling edge signal triggered by the third falling edge, it can be electrically connected to the circuit for detecting CLK4 and CLK1 to detect the current of CLK4 and CLK1.

[0121] The memory 516 is used to store information such as the number of analog clock signals CLK, the number of digital clock signals, and the high-level period of CLK. The memory 516 is electrically connected to the controller 51b and controls the number of bits of the shift register 511a and the mode of the conversion matrix circuit 511c through the controller 51b.

[0122] The controller 511b is used to control the number of bits of the shift register and the preset mode of the conversion matrix circuit 511c. For example, the controller 511b obtains clock signal data from the memory 516. The clock signal data includes data of multiple analog clock signals and digital clock signals. For example, the clock signal data may include: the number of analog clock signals CLK is 8, the number of digital clock signals CPV is 1, and the CLK high-level period is 3 rows. The controller 511b sets the number of bits of the shift register to 8 bits (the same as the number of CLKs) and sets the preset mode of the conversion matrix to mode 1, that is, the first CPV falling edge corresponds to the detection of CLK2, the second CPV falling edge corresponds to the detection of CLK3, and the third (same number of high-level rows) CPV falling edge corresponds to the detection of CLK4 and also detects CLK1 at the same time.

[0123] Of course, the level conversion component provided in the embodiment of the present application can also achieve the effect of detecting the corresponding CLK based on the corresponding relationship through some other structures, for example, it can be achieved through a more complex circuit or control circuit, and the embodiment of the present application is not limited to this.

[0124] In an exemplary embodiment, the current detection subunit includes a switch unit s1 and a current detection unit s2 , wherein the switch unit s1 is electrically connected to the current detection unit s2 , and the switch unit s1 is electrically connected to the conversion matrix circuit 511 c .

[0125] The shift register 511a is used to send an on signal to the conversion matrix circuit 511c when receiving a falling edge signal, so that the conversion matrix circuit 511c transmits the on signal to the switch unit s1 in the first current detection subunit 512a, and the switch unit s1 is used to turn on the current detection unit s2 in the first current detection subunit 512a to detect the current of the corresponding CLK.

[0126] It should be noted that the first falling edge can be any falling edge in the digital clock signal, and the embodiment of the present application does not limit the first falling edge to the first falling edge; and the first current detection sub-unit 512a is a current detection sub-unit for detecting the current of the analog clock signal corresponding to the first falling edge, and the embodiment of the present application does not limit the first current detection sub-unit 512a to a current detection sub-unit for detecting CLK1.

[0127] Optionally, the display device includes a frame start signal line STV, and the level conversion module 51 further includes a reset unit 517 , which is electrically connected to the frame start signal line STV and the shift register 511 a .

[0128] The reset unit 517 is used to reset the shift register 511a when receiving the frame start signal in the frame start signal line STV. At the beginning of each frame, the shift register 511a can be reset so that the shift register 511a starts inputting from the first bit at the beginning of each frame.

[0129] Optionally, the reset unit 517 includes a rising edge trigger 5171 and a reset switch 5172. The rising edge trigger 5171 is electrically connected to the frame start signal line STV and the reset switch 5172, respectively. The reset switch 5172 is electrically connected to the shift register 511a. The reset unit 517 can trigger the reset switch 5172 at the rising edge of the frame start signal. The rising edge of the frame start signal is located before the first falling edge of the digital clock signal. This ensures that the corresponding relationship between each falling edge of the digital clock signal and the current detection unit is the same in each frame.

[0130] Of course, the level conversion component provided in the embodiment of the present application can also have other structures. For example, please refer to Figures 9 and 10. Figure 9 is a structural diagram of another level conversion component provided in the embodiment of the present application, and Figure 10 is a schematic diagram of an analog clock signal and a digital clock signal of the level conversion component shown in Figure 9. Among them, the digital clock signal includes a first digital clock signal CPV1 and a second digital clock signal CPV2. The level conversion unit 513 is used to obtain a plurality of analog clock signals CLK1, CLK2, CLK3... arranged in sequence based on the first digital clock signal CPV1 and the second digital clock signal CPV2, and among any two adjacent analog clock signals of the plurality of analog clock signals, the latter analog clock signal is one row behind the previous analog clock signal. Figure 10 shows the case where a time domain row is equal to a space domain row.

[0131] Optionally, the display device includes at least two digital clock signal lines (FIG. 9 shows a case where there are two digital clock signal lines, but this is not limiting. For example, the number of digital clock signal lines can also be 3, 4, 5, 6, or more), the number of control units 511 is at least two (FIG. 9 shows a case where there are two control units 511, but this is not limiting. For example, the number of control units 511 can also be 3, 4, 5, 6, or more), and the at least two control units 511 are electrically connected to the at least two digital clock signal lines in a one-to-one correspondence. The structure of each control unit 511 can be similar to the control unit 511 provided in the above embodiment. For example, the control unit 511 can include a shift register 511a, a controller 511b, and a conversion matrix circuit 511c. In addition, the level conversion component can include at least two falling edge triggers 515 corresponding to the at least two control units 511. The falling edge trigger 515 can be electrically connected to the shift register 511a in the corresponding control unit 511, the shift register 511a can be electrically connected to the conversion matrix circuit 511c, and the control area 511b can be electrically connected to the shift register 511a and the conversion matrix circuit 511c respectively. Among them, the controller 511b is used to control the conversion matrix circuit 511c to electrically connect the shift register to the first current detection subunit 512a among the multiple current detection subunits at the first falling edge. The first current detection subunit 512a is used to detect the first analog clock signal (the first analog clock signal can be) under the control of the shift register 511a.

[0132] Any one of CLK1 to CLK8, FIG9 shows the case where the first analog clock signal is CLK1, but the embodiment of the present application is not limited to this). Among them, the conversion matrix circuit 511c can electrically connect the shift register 511a to different current detection sub-units under the control of the control unit 511. The level conversion component provided in the embodiment of the present application can also achieve the effect of detecting the corresponding CLK based on the corresponding relationship through some other structures, for example, it can be achieved through a more complex circuit or control circuit, and the embodiment of the present application is not limited to this.

[0133] For the contents of the shift register 511a, the controller 511b and the conversion matrix circuit 511c, reference can be made to the above embodiments, which will not be described in detail in the embodiments of the present application.

[0134] In FIG9 , the display device includes a frame start signal line STV, and the level conversion module 51 further includes a reset unit 517 . The reset unit 517 is electrically connected to the frame start signal line STV and the shift registers 511 a in the two control units 511 .

[0135] The reset unit 517 can be used to reset the shift registers 511a in the two control units 511 when receiving the frame start signal in the frame start signal line STV. At the beginning of each frame, the shift register 511a can be reset so that the shift register 511a starts inputting from the first bit at the beginning of each frame.

[0136] The reset unit 517 may include a rising edge trigger 5171 and two reset switches 5172. The rising edge trigger 5171 is electrically connected to the frame start signal line STV and the two reset switches 5172, respectively. The two reset switches 5172 are electrically connected to the two shift registers 511a in the two control units 511. The reset unit 517 may trigger the reset switches 5172 at the rising edge of the frame start signal. The rising edge of the frame start signal is located before the first falling edge of the digital clock signal. This ensures that the corresponding relationship between each falling edge of the digital clock signal and the current detection unit is the same in each frame.

[0137] In addition, in order to clearly illustrate other structures, the level conversion unit is not shown in FIG9 , but this is not limited in the embodiment of the present application.

[0138] As can be seen from FIG10 , the falling edge of the first digital clock signal CPV1 corresponds to the current detection during the CLK low level period, and the falling edge of the second digital clock signal CPV2 corresponds to the current detection during the CLK high level period. Specifically, the corresponding relationship may include:

[0139] The first falling edges of the first digital clock signal CPV1 and the second digital clock signal CPV2 both correspond to CLK2;

[0140] The second falling edges of the first digital clock signal CPV1 and the second digital clock signal CPV2 both correspond to CLK3 , and so on, until the eighth falling edge corresponds to CLK1 , and then a periodic cycle is performed.

[0141] It should be noted that although the current cannot be detected in the first cycle of each frame of CLK1 due to the lack of CPV1 and CPV2 signals, detection is possible from the second cycle onwards, so there is basically no impact on the overcurrent detection.

[0142] It should be noted that the controller 511b of multiple control units 511 can be shared, that is, one controller 511b can control the shift register 511a and the conversion matrix circuit 511c in multiple control units 511. Figure 9 shows this situation. Of course, different controllers 511b can also control the shift register 511a and the conversion matrix circuit 511c in different control units 511 respectively. The embodiment of the present application does not limit this.

[0143] Figure 11 is a schematic diagram of the structure of another level conversion component provided in an embodiment of the present application, and Figure 12 is a schematic diagram of an analog clock signal and a digital clock signal of the level conversion component shown in Figure 11. Referring to Figures 11 and 12, there are two level conversion modules, namely a first level conversion module 51a and a second level conversion module 51b. The first level conversion module 51a and the second level conversion module 51b are configured to jointly generate n analog clock signals. Of any two adjacent analog clock signals among the n analog clock signals, the latter analog clock signal is one row behind the former analog clock signal. The structures of the first level conversion module 51a and the second level conversion module 51b can refer to at least one of the various level conversion modules provided in the above embodiments, and are not limited in this embodiment of the present application.

[0144] The level conversion unit 513 in the first level conversion module 51a is configured to obtain the first digital clock signal CPV1 and the second digital clock signal CPV2, and generate an odd-numbered analog clock signal among the n analog clock signals based on the first digital clock signal CPV1 and the second digital clock signal CPV2. The odd-numbered analog clock signal may be an odd-numbered analog clock signal among the n analog clock signals, such as CLK1, CLK3, and CLK5 in FIG12 .

[0145] The level conversion unit 513 in the second level conversion unit 51b is configured to obtain the third digital clock signal CPV3 and the fourth digital clock signal CPV4, and generate an even-numbered analog clock signal among the n analog clock signals based on the third digital clock signal CPV3 and the fourth digital clock signal CPV4. The odd-numbered analog clock signal may be an even-numbered analog clock signal among the n analog clock signals, such as CLK2, CLK4, and CLK6 in FIG12 .

[0146] The duty cycles of the first digital clock signal CPV1, the second digital clock signal CPV2, the third digital clock signal CPV3 and the fourth digital clock signal CPV4 are all greater than 50%, so that the current detection time can be located at the last row of CLK.

[0147] In addition, the CPV3 can be set back one row compared to CPV1, CPV2 can be set back four rows compared to CPV1, and CPV4 can be set back four rows compared to CPV3. Figure 12 shows the case where one spatial domain row is equal to one temporal domain row.

[0148] The corresponding relationship may include:

[0149] The first falling edge of CPV1 corresponds to CLK3, the second falling edge corresponds to CLK5, the third falling edge corresponds to CLK7, the fourth falling edge corresponds to CLK1, and the fifth falling edge corresponds to CLK3, and the cycle continues in this order.

[0150] The first falling edge of CPV2 corresponds to CLK3, the second falling edge corresponds to CLK5, the third falling edge corresponds to CLK7, the fourth falling edge corresponds to CLK1, and the fifth falling edge corresponds to CLK3, and the cycle continues in this order.

[0151] The first falling edge of CPV3 corresponds to CLK4, the second falling edge corresponds to CLK6, the third falling edge corresponds to CLK8, the fourth falling edge corresponds to CLK2, and the fifth falling edge corresponds to CLK4, and the cycle continues in this order.

[0152] The first falling edge of CPV4 corresponds to CLK4, the second falling edge corresponds to CLK6, the third falling edge corresponds to CLK8, the fourth falling edge corresponds to CLK2, and the fifth falling edge corresponds to CLK4, and the cycle continues in this order.

[0153] The level conversion component shown in FIG11 may also include other schematic diagrams of analog clock signals and digital clock signals. For example, FIG13 is a schematic diagram of an analog clock signal and a digital clock signal for the level conversion component shown in FIG11. Referring to FIG11 and FIG13, there are two level conversion modules, namely a first level conversion module 51a and a second level conversion module 51b. The first level conversion module 51a and the second level conversion module 51b are configured to collectively generate n analog clock signals. The n analog clock signals include multiple analog clock signal groups (CLK1 and CLK2 form a group, CLK3 and CLK4 form a group, and CLK5 and CLK6 form a group in FIG13). Each analog clock signal group includes two adjacent analog clock signals, and in any two adjacent analog clock signal groups, the latter analog clock signal group is one row behind the previous analog clock signal group. In FIG13, the adjacent analog clock signal groups differ by two spatial rows. FIG13 illustrates a case where one time domain row equals two spatial rows.

[0154] The level conversion unit 513 in the first level conversion module 51a is configured to obtain the first digital clock signal CPV1 and the second digital clock signal CPV2, and generate an odd-numbered analog clock signal among the n analog clock signals based on the first digital clock signal CPV1 and the second digital clock signal CPV2. The odd-numbered analog clock signal may be an odd-numbered analog clock signal among the n analog clock signals, such as CLK1, CLK3, and CLK5 in FIG13 .

[0155] The level conversion unit 513 in the second level conversion unit 51b is configured to obtain the third digital clock signal CPV3 and the fourth digital clock signal CPV4, and generate an even-numbered analog clock signal among the n analog clock signals based on the third digital clock signal CPV3 and the fourth digital clock signal CPV4. The odd-numbered analog clock signal may be an even-numbered analog clock signal among the n analog clock signals, such as CLK2, CLK4, and CLK6 in FIG. 13 .

[0156] The corresponding relationship may include:

[0157] The first falling edge of CPV1 corresponds to CLK3, the second falling edge corresponds to CLK5, the third falling edge corresponds to CLK7, the fourth falling edge corresponds to CLK1, and the fifth falling edge corresponds to CLK3, and so on. The first falling edge of CPV2 corresponds to CLK3, the second falling edge corresponds to CLK5, the third falling edge corresponds to CLK7, the fourth falling edge corresponds to CLK1, and the fifth falling edge corresponds to CLK3, and so on. The first falling edge of CPV3 corresponds to CLK4, the second falling edge corresponds to CLK6, the third falling edge corresponds to CLK8, the fourth falling edge corresponds to CLK2, and the fifth falling edge corresponds to CLK4, and so on. The first falling edge of CPV4 corresponds to CLK4, the second falling edge corresponds to CLK6, the third falling edge corresponds to CLK8, the fourth falling edge corresponds to CLK2, and the fifth falling edge corresponds to CLK4, and so on.

[0158] In an exemplary embodiment, the display device includes a driving circuit, which is used to obtain multiple analog clock signals output by the level conversion unit and drive the display device to display based on the multiple analog clock signals; the overcurrent protection unit 514 is used to determine whether an overcurrent phenomenon occurs based on the overcurrent signal when receiving the overcurrent signal. There are many ways for the overcurrent protection unit 514 to determine whether an overcurrent phenomenon occurs. For example, it can determine that an overcurrent phenomenon occurs after receiving a preset number of overcurrent signals, or it can determine that an overcurrent phenomenon occurs after receiving an overcurrent signal, or it can refer to related technologies, and the embodiments of the present application are not limited to this. After determining that an overcurrent phenomenon occurs, the overcurrent protection unit 514 can take overcurrent protection measures, which can include various measures such as power off and stopping operation, and the embodiments of the present application are not limited to this.

[0159] In summary, the level conversion component provided in the embodiment of the present application determines the first analog clock signal corresponding to the first falling edge in multiple analog clock signals based on the corresponding relationship of the current display mode through the control unit at the first falling edge of the digital clock signal, and controls the current detection unit to detect the current of the first analog clock signal. Since the falling edge of the digital clock signal is located at the last row of the high level period or low level period in the corresponding analog clock signal, and under normal circumstances, the current of the last row of the high level period or low level period should be zero, the current detection unit can send an overcurrent signal to the overcurrent protection unit when the current of the first analog clock signal is not within the current threshold range. In this way, the problem of low accuracy in detecting overcurrent phenomena in the related art is solved, and the accuracy of detecting overcurrent phenomena is improved.

[0160] FIG14 is a flow chart of an overcurrent protection method provided in an embodiment of the present application. The method can be used in any level conversion component provided in the above embodiments. The method may include the following steps:

[0161] Step 1301: Acquire a digital clock signal, and obtain multiple analog clock signals based on the digital clock signal.

[0162] Step 1302: At the first falling edge of the digital clock signal, determine the first analog clock signal corresponding to the first falling edge in multiple analog clock signals based on the corresponding relationship, the corresponding relationship includes the analog clock signal corresponding to the falling edge of the digital clock signal in multiple analog clock signals, and the moment at which the falling edge of the digital clock signal is located in the last row of the high level period or the last row of the low level period in the corresponding analog clock signal.

[0163] Step 1303: Detect the current of the first analog clock signal.

[0164] Step 1304 : When the current of the first analog clock signal is not within the current threshold range, perform overcurrent protection detection.

[0165] In summary, the overcurrent protection method provided by the embodiment of the present application determines the first analog clock signal corresponding to the first falling edge in multiple analog clock signals based on the corresponding relationship of the current display mode at the first falling edge of the digital clock signal, and detects the current of the first analog clock signal. Since the falling edge of the digital clock signal is located at the last row of the high level period or low level period in the corresponding analog clock signal, and under normal circumstances, the current of the last row of the high level period or low level period should be zero, the current detection unit can send an overcurrent signal to the overcurrent protection unit when the current of the first analog clock signal is not within the current threshold range. In this way, the problem of low accuracy in detecting overcurrent phenomena in the related art is solved, and the accuracy of detecting overcurrent phenomena is improved.

[0166] In an exemplary embodiment, the overcurrent protection detection in step 1304 may include:

[0167] 1. Determine whether there are a preset number of analog clock signals among a plurality of analog clock signals whose currents are not within a current threshold range.

[0168] 2. When currents of a preset number of analog clock signals among the plurality of analog clock signals are outside the current threshold range, it is determined that an overcurrent phenomenon occurs.

[0169] In this way, misjudgment caused by the current of a particular analog clock signal not being within the current threshold range can be avoided, thereby improving the accuracy of overcurrent detection.

[0170] In addition, some application examples of the level conversion component provided in the embodiments of the present application are described. Please refer to Figure 15, which is a waveform diagram of an analog digital signal line short-circuited in a display device. The CLK2 current waveform can be the current waveform when CLK2 and CLK1 are short-circuited. It can be seen that the current of CLK2 increases during the last high-level line and the last low-level line, that is, it is no longer equal to zero. Furthermore, by providing a level conversion component in the embodiments of the present application, the current of the last line of CLK2 can be detected to determine whether CLK1 and CLK2 are short-circuited.

[0171] Please refer to Figure 16, which is a waveform diagram of another analog digital signal line short circuit in a display device. The CLK3 current waveform can be the current waveform when CLK3 and CLK1 are short-circuited. It can be seen that the CLK3 current increases during the last two high-level lines and the last two low-level lines due to the short circuit, and thus the CLK3 current is no longer equal to zero during the last line of the high-level period or the low-level period. By providing a level conversion component in an embodiment of the present application, the current of the last line of CLK3 can be detected to determine whether CLK1 and CLK3 are short-circuited.

[0172] Please refer to Figure 17, which is a waveform diagram of another analog digital signal line short circuit in a display device. Figure 17 shows the current waveform when CLK and VGL (gate low voltage) are short-circuited, as well as the current waveform when CLK and VGH (gate high voltage) are short-circuited. It can be seen that the last row during CLK's high level period and the last row during CLK's low level period both have non-zero current. By providing a level conversion component in the embodiment of the present application, it is possible to detect the current of the last row of CLK to determine whether CLK and VGH or VGL are short-circuited.

[0173] Please refer to Figure 18, which is another waveform diagram of another analog digital signal line short circuit in a display device. The CLK2 current waveform can be the current waveform when CLK3, CLK2, and CLK1 are short circuited, and the CLK3 current waveform can be the current waveform when CLK3, CLK2, and CLK1 are short circuited. It can be seen that the currents of CLK2 and CLK3 are not zero in the last line of CLK2 due to the short circuit. By providing a level shifting component in an embodiment of the present application, it is possible to detect the currents of the last line of CLK2 and CLK3 to determine whether CLK2 and CLK3 are short circuited.

[0174] In summary, the level conversion component provided by the embodiments of the present application can be applied in various situations to achieve accurate detection of overcurrent phenomena.

[0175] In this application, the term "at least one of A and B" simply describes an association relationship between associated objects, indicating that three possible relationships exist. For example, "at least one of A and B" can mean: A exists alone, A and B exist simultaneously, and B exists alone. Similarly, "at least one of A, B, and C" means that seven possible relationships exist, indicating: A exists alone, B exists alone, C exists alone, A and B exist simultaneously, A and C exist simultaneously, C and B exist simultaneously, and A, B, and C exist simultaneously. Similarly, "at least one of A, B, C, and D" means that fifteen possible relationships exist, indicating: A exists alone, B exists alone, C exists alone, D exists alone, A and B exist simultaneously, A and C exist simultaneously, A and D exist simultaneously, C and B exist simultaneously, D and B exist simultaneously, C and D exist simultaneously, C and D exist simultaneously, A, B, and C exist simultaneously, A, B, and D exist simultaneously, A, C, and D exist simultaneously, B, C, and D exist simultaneously, and A, B, C, and D exist simultaneously.

[0176] In this application, the terms "first", "second", "third" and "fourth" are used for descriptive purposes only and should not be understood as indicating or implying relative importance. The term "plurality" refers to two or more, unless otherwise expressly limited.

[0177] In the several embodiments provided in this application, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are merely schematic. For example, the division of the units is merely a logical function division. In actual implementation, there may be other division methods, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0178] The units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of these units may be selected to achieve the purpose of this embodiment according to actual needs.

[0179] Those skilled in the art will understand that all or part of the steps to implement the above embodiments may be accomplished by hardware, or by a program to instruct the relevant hardware, and the program may be stored in a computer-readable storage medium, which may be a read-only memory, a disk, or an optical disk, etc.

[0180] The above description is merely an optional embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present application shall be included in the scope of protection of the present application.

Claims

1. A level conversion component, characterized in that, The level conversion component is used in a display device. The level conversion component includes a level conversion module, and the level conversion module includes a control unit, a current detection unit, a level conversion unit, and an overcurrent protection unit; The level conversion unit is used to obtain a digital clock signal and obtain a plurality of analog clock signals based on the digital clock signal; The control unit is used to, at the first falling edge of the digital clock signal, determine the first analog clock signal corresponding to the first falling edge among the plurality of analog clock signals based on the corresponding relationship of the current display mode. The corresponding relationship includes the analog clock signal corresponding to the falling edge of the digital clock signal among the plurality of analog clock signals, and the moment when the falling edge of the digital clock signal is located at the last line of the high-level period or the last line of the low-level period in the corresponding analog clock signal; The control unit is used to control the current detection unit to detect the current of the first analog clock signal; The current detection unit is used to send an overcurrent signal to the overcurrent protection unit when the current of the first analog clock signal is not within the current threshold range; 2. The level conversion component according to claim 1, wherein The level conversion module further includes a falling edge trigger, and the falling edge trigger is used to monitor the digital clock signal and send a falling edge signal to the control unit when the falling edge of the digital clock signal is detected; 3. The level conversion component according to claim 2, characterized in that, The control unit includes a shift register, and the shift register is electrically connected to the falling edge trigger. The shift register is used to, under the trigger of the falling edge signal, control the current detection unit to detect the current of the analog clock signal corresponding to the falling edge based on the corresponding relationship; 4. The level conversion component according to claim 3, wherein The control unit further includes a controller and a conversion matrix circuit, and the controller is electrically connected to the conversion matrix circuit; The conversion matrix circuit is electrically connected to the shift register and the current detection unit respectively; The current detection unit includes a plurality of current detection sub-units, and the plurality of current detection sub-units are respectively used to detect the currents of the plurality of analog clock signals; The controller is used to control the conversion matrix circuit to electrically connect the shift register to the first current detection sub-unit among the plurality of current detection sub-units at the first falling edge. The first current detection sub-unit is used to detect the current of the first analog clock signal under the control of the shift register; 5. The level conversion component according to claim 4, characterized in that, The current detection sub-unit includes a switch unit and a current detection unit. The switch unit is electrically connected to the current detection unit, and the switch unit is electrically connected to the conversion matrix circuit; The shift register is used to send an enabling signal to the conversion matrix circuit when the falling edge signal is received, so that the conversion matrix circuit transmits the enabling signal to the switch unit in the first current detection sub-unit, and the switch unit is used to turn on the current detection unit in the first current detection sub-unit.

6. The level conversion component according to claim 4, wherein The level conversion module further includes a memory that stores clock signal data, where the clock signal data includes data of the multiple analog clock signals and the digital clock signal. The memory is electrically connected to the controller, and the controller is configured to control the conversion matrix circuit based on the clock signal data, so that when the first falling edge occurs, the conversion matrix circuit electrically connects the shift register to a first current detection sub-unit among the multiple current detection sub-units.

7. The level conversion component according to claim 6, characterized in that, The clock signal data includes the number of cycles of the analog clock signal, and the controller is configured to control the shift register based on the number of cycles of the multiple analog clock signals, so that the number of bits of the shift register is the same as the number of cycles of the analog clock signal.

8. The level conversion component according to claim 6, wherein The conversion matrix circuit includes multiple input channels and multiple output channels. The multiple input channels are electrically connected to the shift register, and the multiple output channels are electrically connected to the multiple current detection sub-units. The controller is further configured to determine a target display mode that matches the current display mode among multiple preset display modes. Each of the multiple preset display modes has a corresponding relationship, and the corresponding relationship includes the connection relationship between the multiple input channels and the multiple output channels. The controller is further configured to control the conversion matrix circuit based on the corresponding relationship corresponding to the target display mode.

9. The level conversion component according to claim 3, wherein The display device includes a frame start signal line, and the level conversion module further includes a reset unit. The reset unit is electrically connected to the frame start signal line and the shift register respectively. The reset unit is configured to reset the shift register when receiving a frame start signal in the frame start signal line.

10. The level conversion component according to claim 9, wherein The reset unit includes a rising edge trigger and a reset switch. The rising edge trigger is electrically connected to the frame start signal line and the reset switch respectively, and the reset switch is electrically connected to the shift register.

11. The level conversion component according to any one of claims 1 to 10, characterized in that, The display device includes at least two digital clock signal lines, and the number of control units is at least two. The at least two control units are electrically connected to the at least two digital clock signal lines in a one-to-one correspondence.

12. The level conversion component according to any one of claims 1 to 10, characterized in that, The display device includes one digital clock signal line, and the number of control units is 1. The control unit is electrically connected to the one digital clock signal line.

13. The level conversion component according to any one of claims 1 to 10, characterized in that, The digital clock signal includes a first digital clock signal and a second digital clock signal. The level conversion unit is configured to obtain the multiple analog clock signals arranged in sequence based on the first digital clock signal and the second digital clock signal. Among any two adjacent analog clock signals of the multiple analog clock signals, the latter analog clock signal retreats one row compared to the former analog clock signal.

14. The level conversion component according to any one of claims 1 to 10, characterized in that The number of level conversion modules is 2. The two level conversion modules are a first level conversion module and a second level conversion module respectively. The first level conversion module and the second level conversion module are configured to jointly generate n analog clock signals. Among any two adjacent analog clock signals of the n analog clock signals, the latter analog clock signal retreats one row compared to the former analog clock signal. The level conversion unit in the first level conversion module is configured to obtain a first digital clock signal and a second digital clock signal, and generate the odd-numbered analog clock signals among the n analog clock signals based on the first digital clock signal and the second digital clock signal; The level conversion unit in the second level conversion unit is configured to obtain a third digital clock signal and a fourth digital clock signal, and generate the even-numbered analog clock signals among the n analog clock signals based on the third digital clock signal and the fourth digital clock signal; The duty cycles of the first digital clock signal, the second digital clock signal, the third digital clock signal, and the fourth digital clock signal are all greater than 50%.

15. The level conversion component according to any one of claims 1 to 10, characterized in that, The number of the level conversion modules is 2. The two level conversion modules are a first level conversion module and a second level conversion module respectively. The first level conversion module and the second level conversion module are configured to jointly generate n analog clock signals. The n analog clock signals include multiple groups of analog clock signals. Each group of analog clock signals includes two adjacent analog clock signals. In any two adjacent groups of analog clock signals, the latter group of analog clock signals is one row behind the former group of analog clock signals; The level conversion unit in the first level conversion module is configured to obtain a first digital clock signal and a second digital clock signal, and generate the odd-numbered analog clock signals among the n analog clock signals based on the first digital clock signal and the second digital clock signal; The level conversion unit in the second level conversion module is configured to obtain a third digital clock signal and a fourth digital clock signal, and generate the even-numbered analog clock signals among the n analog clock signals based on the third digital clock signal and the fourth digital clock signal.

16. The level conversion component according to any one of claims 1 to 10, characterized in that, The digital clock signal includes a first digital clock signal. The level conversion unit is configured to obtain the multiple analog clock signals arranged in sequence based on the first digital clock signal. Among any two adjacent analog clock signals in the multiple analog clock signals, the latter analog clock signal is one row behind the former analog clock signal.

17. The level conversion component according to any one of claims 1 to 10, characterized in that, The display device includes a driving circuit. The driving circuit is configured to obtain the multiple analog clock signals output by the level conversion unit, and drive the display device to display based on the multiple analog clock signals; The overcurrent protection unit is configured to determine whether an overcurrent phenomenon occurs based on the overcurrent signal when receiving the overcurrent signal.

18. An overcurrent protection method, characterized in that, For the level conversion component according to any one of claims 1 to 17, the method includes: Obtain a digital clock signal, and obtain multiple analog clock signals based on the digital clock signal; At the first falling edge of the digital clock signal, determine the first analog clock signal corresponding to the first falling edge in the plurality of analog clock signals based on the corresponding relationship, where the corresponding relationship includes the analog clock signal corresponding to the falling edge of the digital clock signal in the plurality of analog clock signals, and the moment when the falling edge of the digital clock signal is located at the last row of the high-level period or the last row of the low-level period in the corresponding analog clock signal; Detect the current of the first analog clock signal; When the current of the first analog clock signal is not within the current threshold range, perform overcurrent protection detection.

19. A display device, characterized in that, The display device includes a display panel and the level conversion component according to any one of claims 1 to 17.

20. The display device according to claim 19, wherein, The display device further includes a timing controller and a driving circuit. The level conversion component is electrically connected to the timing controller and the driving circuit respectively. The timing controller is configured to provide a digital clock signal to the level conversion component, and the driving circuit is configured to drive the display panel based on the analog clock signal provided by the level conversion component.

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