Semiconductor device

Abstract

Provided is a semiconductor device. The semiconductor device comprises: a drift layer; a first voltage withstanding ring; a first polycrystalline silicon field plate, arranged above the surface of the first voltage withstanding ring, a first via hole being formed in the first polycrystalline silicon field plate; a first dielectric layer, arranged above the surface of the first polycrystalline silicon field plate, a second via hole and a third via hole being formed in the first dielectric layer, the second via hole corresponding to the first via hole, and the third via hole and the second via hole being arranged at an interval on the surface of the first dielectric layer; and a first metal field plate, arranged above the surface of the first dielectric layer and provided with a first electrical connecting portion and a second electrical connecting portion, the first electrical connecting portion sequentially passing through the second via hole and the first via hole to be electrically connected to the first voltage withstanding ring, and the second electrical connecting portion passing through the third via hole to be electrically connected to the first polycrystalline silicon field plate. Therefore, the first voltage withstanding ring, the first polycrystalline silicon field plate, and the first metal field plate can be equipotential, thereby improving the voltage withstanding capability and reliability of the semiconductor device.

Description

semiconductor devices

[0001] This disclosure claims the priority of Chinese patent application No. CN202311118361.1, filed on August 31, 2023; the priority of Chinese patent application No. CN202311283477.0, filed on September 28, 2023; the priority of Chinese patent application No. CN202311519777.4, filed on November 15, 2023; and the priority of Chinese patent application No. CN202311556350.1, filed on November 20, 2023, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present disclosure relates to the field of semiconductor technology, and in particular to a semiconductor device. Background Art

[0003] For semiconductor devices, the PN junction at the edge of the chip is a curved surface where the electric field lines are relatively concentrated, the electric field strength is strong, the voltage per unit length is large, and voltage breakdown is more likely to occur there.

[0004] To improve this situation, a terminal structure will be designed at the edge of the chip to optimize the electric field distribution and increase the breakdown voltage.

[0005] Summary of the Invention

[0006] A semiconductor device is provided. The semiconductor device includes: a drift layer of a first conductivity type; a first voltage-resistant ring of a second conductivity type, the first voltage-resistant ring being disposed in a portion of the drift layer corresponding to a terminal region of the semiconductor device; a first polysilicon field plate, the first polysilicon field plate being disposed above a surface of the first voltage-resistant ring and electrically connected to the first voltage-resistant ring, the first polysilicon field plate having a first via hole; a first dielectric layer, the first dielectric layer being disposed above the surface of the first polysilicon field plate, the first dielectric layer having a second via hole and a third via hole, the second via hole corresponding to the first via hole, the third via hole and the second via hole being spaced apart on the surface of the first dielectric layer; and a first metal field plate, the first metal field plate being disposed above the surface of the first dielectric layer, the first metal field plate having a first electrical connection portion and a second electrical connection portion, the first electrical connection portion sequentially passing through the second via hole and the first via hole and electrically connected to the first voltage-resistant ring, and the second electrical connection portion passing through the third via hole and electrically connected to the first polysilicon field plate. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] FIG1 is a cross-sectional view of a semiconductor device according to some embodiments of the present disclosure;

[0008] FIG2 is a partial cross-sectional view of a semiconductor device according to some embodiments of the present disclosure;

[0009] 3 is a partial cross-sectional view of another location of a semiconductor device according to some embodiments of the present disclosure;

[0010] FIG4 is a partial cross-sectional view of a semiconductor device according to another embodiment of the present disclosure;

[0011] FIG5 is a partial schematic diagram of a polysilicon field plate according to some embodiments of the present disclosure;

[0012] FIG6 is a top view of a semiconductor device according to some embodiments of the present disclosure;

[0013] FIG7 is a cross-sectional view of a semiconductor device according to some embodiments of the present disclosure;

[0014] FIG8 is a schematic diagram of area A in FIG7 ;

[0015] FIG9 is a schematic diagram of area A in FIG7 ;

[0016] FIG10 is a schematic diagram of a withstand voltage curve of a semiconductor device according to some embodiments of the present disclosure;

[0017] 11 is a schematic diagram of a withstand voltage curve of a semiconductor device according to a comparative embodiment;

[0018] FIG12 is a schematic diagram of a semiconductor device according to some embodiments of the present disclosure;

[0019] FIG13 is a schematic diagram of a layout design of a transition area according to some embodiments of the present disclosure;

[0020] FIG14 is a cross-sectional view of a transition zone along the AA direction according to some embodiments of the present disclosure;

[0021] FIG15 is a cross-sectional view of a transition zone along direction BB according to some embodiments of the present disclosure;

[0022] FIG16 is a cross-sectional view of a transition zone along the CC direction according to some embodiments of the present disclosure;

[0023] FIG17 is a flow chart of a method for manufacturing a semiconductor device according to some embodiments of the present disclosure;

[0024] 18 is a flowchart of a method for manufacturing a semiconductor device according to another embodiment of the present disclosure;

[0025] FIG19 is a cross-sectional view of structure 1 according to some embodiments of the present disclosure;

[0026] FIG20 is a cross-sectional view of structure 2 according to some embodiments of the present disclosure;

[0027] FIG21 is a cross-sectional view of structure 3 according to some embodiments of the present disclosure;

[0028] FIG22 is a cross-sectional view of structure 4 according to some embodiments of the present disclosure;

[0029] FIG23 is a cross-sectional view of structure 5 according to some embodiments of the present disclosure;

[0030] FIG24 is a cross-sectional view of structure 6 according to some embodiments of the present disclosure;

[0031] FIG25 is a cross-sectional view of structure 7 according to some embodiments of the present disclosure.

[0032] Reference numerals: 100, semiconductor device; 103, termination region; 101, active region; 102, transition region; 104, gate pad; 10, drift layer; 20, first voltage-resistant ring; 30, first polysilicon field plate; 31, first via; 40, first dielectric layer; 41, second via; 42, third via; 50, first metal field plate; 51, first electrical connection; 52, second electrical connection; 60, first field oxide layer; 61, fourth via; 70, field stop layer; 80, collector layer; 90, collector metal layer; 20a, second voltage-resistant ring; 30a, second polysilicon field plate; 30b, third polysilicon field plate; 31a, main body; 32a, cover portion; 33a, extension portion; 40a, third dielectric layer; 41a, first through-hole; 42a, second through-hole; 50a, second metal field plate; 51a, third electrical connection; 52a, fourth electrical connection; 60a, second field oxide layer; 61a, field oxide body; 62, protrusion; 81, emitter metal layer; 82, gate bus; 11, well layer; 12, base layer; 13, carrier storage layer; 14, fourth dielectric layer; 20b, first trench; 30c, second trench; 40c, oxide insulating layer; 50b, trench gate polysilicon; 60b, planar gate polysilicon; 70a, substrate; 71a, first main surface; 72a, second main surface. DETAILED DESCRIPTION

[0033] The following will be combined with the accompanying drawings to clearly and completely describe some embodiments of the present disclosure. Obviously, the embodiments described are only some embodiments of the present disclosure, rather than all embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by ordinary technicians in this field are within the scope of protection of the present disclosure.

[0034] Unless the context requires otherwise, throughout the specification and claims, the term "comprise" and its other forms, such as the third person singular form "comprises" and the present participle form "comprising", are to be interpreted as open and inclusive, that is, "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "example", "specific example" or "some examples" are intended to indicate that the particular features, structures, materials or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present disclosure. The schematic representation of the above terms does not necessarily refer to the same embodiment or example. In addition, the particular features, structures, materials or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

[0035] In the following, the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of the technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of some embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.

[0036] When describing some embodiments, the word "connected" and its derivatives may be used. The term "connected" should be understood broadly. For example, "connected" can mean a fixed connection, a removable connection, or an integral connection; it can be directly connected or indirectly connected through an intermediary. The term "coupled" indicates, for example, that two or more components are in direct physical or electrical contact. The embodiments disclosed herein are not necessarily limited to the contents herein.

[0037] “A and / or B” includes the following three combinations: A only, B only, and a combination of A and B.

[0038] The use of "adapted to" or "configured to" herein is intended to be open and inclusive language that does not exclude devices adapted or configured to perform additional tasks or steps.

[0039] Additionally, the use of “based on” is meant to be open and inclusive, as a process, step, calculation, or other action “based on” one or more stated conditions or values ​​may, in practice, be based on additional conditions or values ​​beyond those stated.

[0040] In the related art, the metal field plate and polysilicon field plate at the voltage-resistant ring in the terminal region of a semiconductor device do not contact each other, resulting in different electric potentials between the two, which affects the electric field distribution in this region and reduces the reliability of the semiconductor device. This problem occurs because in the related art, a dielectric layer is provided between the polysilicon field plate and the metal field plate at at least the last voltage-resistant ring in the terminal region. The dielectric layer separates the metal field plate and the polysilicon field plate, resulting in the metal field plate and the polysilicon field plate not contacting each other, resulting in different electric potentials between the two, affecting the electric field distribution in this region and reducing reliability.

[0041] Furthermore, when field oxygen exists above the terminal well region, the polysilicon field plate, the metal field plate, and the well region, or two of them, do not contact each other, forming a floating electric field, which also affects the electric field distribution in the region and reduces reliability.

[0042] To this end, some embodiments of the present disclosure provide a semiconductor device, which can achieve equal potential between the metal field plate and the voltage-resistant ring by allowing the first electrical connection portion to pass through the second via and the first via in sequence and electrically connect to the voltage-resistant ring. Furthermore, by allowing the second electrical connection portion on the metal field plate to pass through the third via and electrically connect to the polysilicon field plate, the voltage-resistant ring, the polysilicon field plate and the metal field plate can be made equal in potential, thereby improving the voltage resistance and reliability of the semiconductor device.

[0043] Furthermore, in related art, a transition region exists between the terminal region and the active region of the device, and this transition region has a relatively complex structure. However, the structural design of this transition region in related art is not rational, and the device is prone to breakdown in the transition region when subjected to reverse voltage, resulting in low voltage resistance and reliability of the semiconductor device.

[0044] The reason for this problem is that the polysilicon field plate in the related technology is arranged on the upper surface of the voltage-resistant ring, a dielectric layer is provided on the upper surface of the polysilicon field plate, and a metal field plate is provided on the upper surface of the dielectric layer, and the metal field plate in the transition zone is not in direct contact with the polysilicon field plate. This will cause the device to easily break down in the transition zone when it is subjected to reverse voltage, resulting in low voltage resistance and reliability of the semiconductor device.

[0045] In addition, in the related art, the insulated gate bipolar transistor includes an active region, a terminal region and a transition region. In order to ensure the normal operation and voltage resistance of the transition region, the transition region includes a well layer and a base layer. The depth and concentration of the dopant in the well layer are greater than the depth and concentration of the dopant in the base layer. In this way, the dopant in the well layer will diffuse into the base layer, resulting in the formation of a curved surface between the well layer and the base layer. When the device is in reverse voltage resistance, electric field concentration is prone to occur at this position, and the electric field strength is large, which may cause the safe operating area to become smaller and the reliability of the device to be reduced.

[0046] Embodiments of the present disclosure will be described in detail below. The embodiments described with reference to the accompanying drawings are exemplary. Embodiments of the present disclosure will be described in detail below.

[0047] The following describes a semiconductor device 100 according to some embodiments of the present disclosure with reference to FIG1-FIG5 . The semiconductor device 100 is, for example, an IGBT (Insulated Gate Bipolar Transistor). In the following description, N and P represent the conductivity type of the semiconductor. In this disclosure, the first conductivity type is N-type, and the second conductivity type is P-type.

[0048] As shown in Figures 1 and 3, the semiconductor device 100 disclosed in the present invention may include a drift layer 10 of the first conductive type, a field stop layer 70 of the first conductive type is arranged below the drift layer 10 of the first conductive type, a collector layer 80 of the second conductive type is arranged below the field stop layer 70, and a collector metal layer 90 is arranged below the collector layer 80. In this way, the basic structure of the semiconductor structure can be formed to ensure the normal operation of the semiconductor device 100.

[0049] The semiconductor device 100 of the present disclosure may include a first voltage-resistant ring 20 of the second conductivity type. The first voltage-resistant ring 20 is disposed on a portion of the surface of the drift layer 10 corresponding to the termination region 103 of the semiconductor device 100 .

[0050] The first voltage-resistant ring 20 can optimize the electric field distribution of the terminal area 103 and improve the voltage resistance of the terminal area 103, thereby avoiding the problem of voltage breakdown occurring there due to the strong electric field strength in the terminal area 103 and the high voltage per unit length.

[0051] The semiconductor device 100 of the present disclosure may include a first polysilicon field plate 30 , which is disposed above the surface of the first voltage-resistant ring 20 and electrically connected to the first voltage-resistant ring 20 . The first polysilicon field plate 30 is provided with a first via 31 .

[0052] The semiconductor device 100 of the present disclosure may include a first dielectric layer 40, which is disposed above a surface of the first polysilicon field plate 30 facing away from the first voltage-resistant ring 20. The first dielectric layer 40 is provided with a second via 41 and a third via 42. The second via 41 corresponds to the first via 31, and the third via 42 is spaced apart from the second via 41 on the surface of the first dielectric layer 40.

[0053] The semiconductor device 100 disclosed herein may include a first metal field plate 50, which is provided with a first electrical connection portion 51 and a second electrical connection portion 52. The first electrical connection portion 51 passes through the second via 41 and the first via 31 in sequence, and the first electrical connection portion 51 is electrically connected to the first voltage-resistant ring 20. The second electrical connection portion 52 passes through the third via 42 and is electrically connected to the first polysilicon field plate 30.

[0054] In some examples, the first electrical connection portion 51 can be electrically connected to the surface of the first voltage-resistant ring 20 facing the first metal field plate 50 . The second electrical connection portion 52 can be electrically connected to the surface of the first polysilicon field plate 30 facing away from the first voltage-resistant ring 20 .

[0055] In some embodiments, the first electrical connection portion 51 may be a protrusion-shaped structure extending toward the first voltage-resistant ring 20 , and one end of the protrusion-shaped structure facing away from the first metal field plate 50 is electrically connected to the first voltage-resistant ring 20 .

[0056] In some embodiments, the second electrical connection portion 51 may also be a protrusion-shaped structure extending toward the first voltage-resistant ring 20 , and one end of the protrusion-shaped structure facing away from the first metal field plate 50 is electrically connected to the first polysilicon field plate 30 .

[0057] The semiconductor device 100 provided in some embodiments of the present disclosure arranges the first polysilicon field plate 30 above the surface of the first voltage-resistant ring 20, arranges the first dielectric layer 40 above the surface of the first polysilicon field plate 30, and arranges the first metal field plate 50 above the surface of the first dielectric layer 40. In this way, the main junction depletion region can be effectively widened outward, the electric field concentration phenomenon can be avoided, and the breakdown voltage can be increased, thereby improving the voltage resistance of the terminal region 103 and even the semiconductor device 100, and reducing the probability of the semiconductor device 100 being broken down at the curved junction surface of the PN junction.

[0058] In some embodiments, the semiconductor device 100 provided by the present disclosure has a first via 31 opened in the first polysilicon field plate 30, a second via 41 provided in the first dielectric layer 40, the first via 31 corresponds to the second via 41, and a first electrical connection portion 51 is provided on the first metal field plate 50, so that the first electrical connection portion 51 can pass through the second via 41 and the first via 31 in sequence, and the first electrical connection portion 51 can be in contact with and electrically connected to the first voltage-resistant ring 20, thereby realizing electrical connection between the first metal field plate 50 and the first voltage-resistant ring 20, so that the first metal field plate 50 and the first voltage-resistant ring 20 have the same electric potential.

[0059] In some embodiments, the first via hole 31 and the second via hole 41 can be coaxially arranged to facilitate the passage of the first electrical connection portion 51 .

[0060] In some embodiments, by providing a third via 42 in the first dielectric layer 40 and correspondingly providing a second electrical connection portion 52 on the first metal field plate 50, the second electrical connection portion 52 only needs to pass through the third via 42, and the second electrical connection portion 52 can be in contact and electrically connected with the first polysilicon field plate 30, thereby achieving electrical connection between the first metal field plate 50 and the first polysilicon field plate 30, making the first metal field plate 50 and the first polysilicon field plate 30 have the same electric potential.

[0061] In some embodiments, the third via hole 42 and the second via hole 41 may not be spaced apart from each other on the surface of the first dielectric layer 40 , that is, the third via hole 42 and the second via hole 41 may be connected.

[0062] Accordingly, the first electrical connection portion 51 and the second electrical connection portion 52 can also contact each other on the first metal field plate 50.

[0063] In some other embodiments, the third via hole 42 and the second via hole 41 can be spaced apart on the surface of the first dielectric layer 40 .

[0064] In a specific embodiment, the third via 42 and the second via 41 are spaced apart in the left-right direction of the first dielectric layer 40. This requires correspondingly extending the length of the first polysilicon field plate 30 in the left-right direction, so that the first polysilicon field plate 30 can correspond to the second via 41 and the third via 42. This can increase the area of ​​the first polysilicon field plate 30, improve the electric field modulation capability of the first polysilicon field plate 30 on the terminal region 103, avoid electric field concentration, and make the electric field distribution in the terminal region 103 more uniform, thereby improving the breakdown voltage of the semiconductor device 100 and enhancing the voltage resistance of the semiconductor device 100.

[0065] In some embodiments, the third via 42 and the second via 41 are spaced apart on the surface of the first dielectric layer 40, and the first electrical connection portion 51 and the second electrical connection portion 52 can also be spaced apart correspondingly on the first metal field plate 50. This not only facilitates the opening of the second via 41 and the first via 31 on the first dielectric layer 40, and facilitates the setting of the first electrical connection portion 51 and the second electrical connection portion 52 on the first metal field plate 50, which can reduce the manufacturing difficulty, but also allows the first electrical connection portion 51 to pass through the first via 31 and the second via 41, and the second electrical connection portion 52 to pass through the third via 42 at the same time, which can improve assembly efficiency.

[0066] In some embodiments, the spacing distance between the third via hole 42 and the second via hole 41 is greater than or equal to 2 μm. For example, the spacing distance between the third via hole 42 and the second via hole 41 may be 2 μm, 5 μm, or 10 μm.

[0067] If the interval between the third via 42 and the second via 41 is too small, for example, the interval is 1 μm, the distance between the third via 42 and the second via 41 will be too small, which will increase the manufacturing difficulty of the first electrical connection part 51 and the second electrical connection part 52 on the first metal field plate 50 and improve the assembly efficiency.

[0068] If the interval between the third via hole 42 and the second via hole 41 is too large, for example, 20 μm, the distance between the third via hole 42 and the second via hole 41 will be too large, increasing the use area of ​​the first polysilicon field plate 30 and further increasing the manufacturing cost of the semiconductor device.

[0069] In this way, the equipotential of the first voltage-resistant ring 20, the first polysilicon field plate 30 and the first metal field plate 50 can be achieved, thereby avoiding the occurrence of a floating electric field due to the lack of interconnection among one of the structures, and avoiding the floating electric field being disturbed by the outside world when the semiconductor device 100 is working, resulting in uneven electric field distribution in the terminal area 103 and causing reduced voltage resistance and reliability. The voltage resistance capability of the semiconductor device 100 can be improved, and the reliability of the semiconductor device 100 can be improved.

[0070] Therefore, by allowing the first electrical connection part 51 to pass through the second via 41 and the first via 31 in sequence and be electrically connected to the first voltage-resistant ring 20, and by allowing the second electrical connection part 52 to pass through the third via 42 and be electrically connected to the first polysilicon field plate 30, the first voltage-resistant ring 20, the first polysilicon field plate 30 and the first metal field plate 50 are made to have the same electric potential, thereby improving the voltage resistance and reliability of the semiconductor device 100.

[0071] 1-4 , in some embodiments, in the height direction of the semiconductor device, the projections of the second via 41 and the first via 31 can at least partially fall within the projection of the first pressure-resistant ring 20 .

[0072] For example, in the height direction of the semiconductor device 100 , the projection of the first via 31 can fall within the projection of the first pressure-resistant ring 20 , while the projection of the second via 41 can fall outside the projection of the first pressure-resistant ring 20 .

[0073] For another example, in the height direction of the semiconductor device 100 , the projection of the first via 31 can fall within the projection of the first pressure-resistant ring 20 , and a portion of the projection of the second via 41 can fall within the projection of the first pressure-resistant ring 20 .

[0074] For another example, in the height direction of the semiconductor device 100 , the projection of the first via 31 can fall within the projection of the first pressure-resistant ring 20 , and the projection of the second via 41 can fall within the projection of the first pressure-resistant ring 20 .

[0075] Furthermore, in the height direction of the semiconductor device 100 , the projection of the second via 41 can fall within the projection of the first pressure-resistant ring 20 , while the projection of the first via 31 can fall outside the projection of the first pressure-resistant ring 20 .

[0076] Furthermore, in the height direction of the semiconductor device 100 , the projection of the second via 41 can fall within the projection of the first pressure-resistant ring 20 , and a portion of the projection of the first via 31 can fall within the projection of the first pressure-resistant ring 20 .

[0077] In combination with Figures 1-4, in some embodiments, the second via 41 and the first via 31 are arranged above the two side boundaries of the first voltage-resistant ring 20, and at least part of the two sides of the first metal field plate 50 and the first polysilicon field plate 30 are able to be flush with the two side boundaries of the first voltage-resistant ring 20.

[0078] For example, both sides of the first metal field plate 50 and the first polysilicon field plate 30 can be flush with both sides of the first voltage-resistant ring 20 , or both sides of the first metal field plate 50 and the first polysilicon field plate 30 extend out of both side boundaries of the first voltage-resistant ring 20 respectively.

[0079] Specifically, by arranging the second via 41 and the first via 31 above the boundaries of the first pressure-resistant ring 20 on both sides, when the first electrical connection part 51 on the first metal field plate 50 is sequentially passed through the second via 41 and the first via 31, it can be directly contacted and electrically connected with the first pressure-resistant ring 20, and the end of the first electrical connection part 51 can be ensured to be in complete contact with the first pressure-resistant ring 20, thereby not only making the electrical connection between the first metal field plate 50 and the first pressure-resistant ring 20 simpler to implement, but also ensuring that there is sufficient contact area between the first metal field plate 50 and the first pressure-resistant ring 20, ensuring the stability of the electrical connection between the first metal field plate 50 and the first pressure-resistant ring 20, and thus more stably and reliably ensuring the equipotential between the first metal field plate 50 and the first pressure-resistant ring 20.

[0080] The two sides of the first metal field plate 50 and the first polysilicon field plate 30 are respectively extended out of the two side boundaries of the first voltage-resistant ring 20. This can improve the electric field modulation capability of the first metal field plate 50 and the first polysilicon field plate 30 on the terminal area 103, avoid electric field concentration, and make the electric field distribution in the terminal area 103 more uniform, thereby increasing the breakdown voltage of the semiconductor device 100 and enhancing the voltage resistance of the semiconductor device 100.

[0081] In some embodiments, in the height direction of the semiconductor device, the projection of the first metal field plate 50 can fall within the projection of the first voltage-resistant ring 20 , and the projection of the first polysilicon field plate 30 can fall within the projection of the first voltage-resistant ring 20 .

[0082] For another example, both sides of the first metal field plate 50 can extend to the boundaries of both sides of the first voltage-resistant ring 20, so that the boundaries of both sides of the first metal field plate 50 are flush with the boundaries of both sides of the first voltage-resistant ring 20. Both sides of the first polysilicon field plate 30 can extend to the boundaries of both sides of the first voltage-resistant ring 20, so that the boundaries of both sides of the first polysilicon field plate 30 are flush with the boundaries of both sides of the first voltage-resistant ring 20.

[0083] As shown in combination with FIG. 3 and FIG. 4 , the diameter of the first via hole 31 is larger than the diameter of the second via hole 41 .

[0084] Specifically, the first polysilicon field plate 30 is located below the first dielectric layer 40. During the production process, a first via hole 31 can be first opened on the first polysilicon field plate 30, and then the first dielectric layer 40 can be set on the first polysilicon field plate 30. Then, a second via hole 41 is opened on the first dielectric layer 40 corresponding to the first via hole 31. By setting the aperture of the first via hole 31 to be larger than the aperture of the second via hole 41, it is possible to avoid affecting the morphology and size of the first via hole 31 when opening the second via hole 41, thereby ensuring the reliability of the first polysilicon field plate 30 and even the semiconductor device 100.

[0085] In some embodiments, the aperture of the first via hole 31 can also be equal to the aperture of the second via hole 41, and when the first electrical connection portion 51 passes through the first via hole 31 and the second via hole 41, the first electrical connection portion 51 can contact the inner peripheral wall of the first via hole 31 and the second via hole 41. Alternatively, the first electrical connection portion 51 can not contact the inner peripheral wall of the first via hole 31 and the second via hole 41.

[0086] In other embodiments, the aperture of the first via hole 31 can be smaller than the aperture of the second via hole 41. In this case, the first electrical connection portion 51 can contact the inner circumferential wall of the first via hole 31, and the first electrical connection portion 51 can also not contact the inner circumferential wall of the second via hole 41. Alternatively, the first electrical connection portion 51 can contact the inner circumferential wall of the first via hole 31, and the first electrical connection portion 51 can also contact the inner circumferential wall of the second via hole 41.

[0087] In some embodiments, as shown in FIG. 3 , the first electrical connection portion 51 and the first polysilicon field plate 30 are circumferentially spaced apart from each other on the inner wall of the first via hole 31 .

[0088] By circumferentially spacing the first electrical connection portion 51 from the inner wall of the first via hole 31 corresponding to the polysilicon, it is convenient for the first electrical connection portion 51 to penetrate the first via hole 31, and damage to the inner wall of the first polysilicon field plate 30 corresponding to the first via hole 31 during the penetration of the first electrical connection portion 51 can be avoided, thereby improving the reliability of the semiconductor device 100.

[0089] In a specific implementation, when the aperture of the second via 41 is smaller than the aperture of the first via 31, the side wall of the second via 41 toward one end of the first pressure-resistant ring 20 can extend into the first via 31, so that when the first electrical connection part 51 is passed through the first via 31 and the second via 41, direct contact between the first electrical connection part 51 and the side wall of the first via 31 is avoided, thereby reducing the damage of the first electrical connection part to the first polysilicon field plate 30 when the first electrical connection part is inserted into the first via 31.

[0090] As shown in FIG. 5 , the first via hole 31 is in at least one of a square, a rectangle, a circle and a diamond shape.

[0091] Specifically, the design shape of the first via 31 can be at least one of a square, a rectangle, a circle, and a diamond. Correspondingly, the shape of the second via 41 and the shape of the cross section of the first electrical connection portion 51 can be designed. This can make the shape of the first via 31 simple, facilitate the opening of the first via 31 and the second via 41, and the manufacture of the first electrical connection portion 51, and reduce the production difficulty of the semiconductor device 100.

[0092] In some embodiments, as shown in FIG. 5 , there may be a plurality of first vias 31 , which are spaced apart on the upper surface of the first polysilicon field plate 30 , and a plurality of first electrical connection portions 51 , which correspond to the plurality of first vias 31 .

[0093] Specifically, the first via hole 31 may be provided in plurality, and correspondingly, the first electrical connection portion 51 and the second via hole 41 may also be provided in plurality.

[0094] By making multiple first electrical connection parts 51 correspond to multiple first vias 31, multiple first electrical connection parts 51 can pass through the first vias 31 and the second vias 41, and be in contact and electrically connected with the first voltage-resistant ring 20, so that the first metal field plate 50 and the first voltage-resistant ring 20 can have multiple electrical connections, thereby improving the stability and reliability of the electrical connection between the first metal field plate 50 and the first voltage-resistant ring 20, and more stably and reliably ensuring the equipotential between the first metal field plate 50 and the first voltage-resistant ring 20.

[0095] It should be noted that the plurality of first via holes 31 are spaced apart on the first polysilicon field plate 30 , so as to ensure that the first polysilicon field plate 30 remains intact after the holes are opened.

[0096] In some embodiments, if there are multiple first vias 31, the multiple first vias 31 can be interconnected on the upper surface of the first polysilicon field plate 30. Similarly, there can be multiple first electrical connection portions 51, and the multiple first electrical connection portions 51 are arranged corresponding to the multiple first vias 31. It is understood that the multiple first electrical connection portions 51 can be spaced apart from each other.

[0097] As shown in Figure 4, the semiconductor device 100 may further include a first field oxygen layer 60, which is arranged above the surface of the first voltage-resistant ring 20 and at least partially located between the first polysilicon field plate 30 and the first voltage-resistant ring 20. The first field oxygen layer 60 is provided with a fourth via 61, and the fourth via 61 corresponds to the first via 31 and the second via 41. The first electrical connection portion 51 passes through the second via 41, the first via 31 and the fourth via 61 in sequence and is electrically connected to the first voltage-resistant ring 20.

[0098] Specifically, there may be a first field oxygen layer 60 between the first voltage-resistant ring 20 and the first polysilicon field plate 30. The first field oxygen layer 60 can isolate the first voltage-resistant ring 20 from the first polysilicon field plate 30 and the first electrical connection portion 51 of the first metal field plate 50, resulting in failure of the electrical connection between the first voltage-resistant ring 20 and the first metal field plate 50.

[0099] By opening a fourth via 61 corresponding to the first via 31 and the second via 41 in the first field oxygen layer 60, the field oxygen between the first polysilicon field plate 30 and the first voltage-resistant ring 20 can be at least partially removed. After the first electrical connection portion 51 can be sequentially penetrated by the second via 41, the first via 31 and the fourth via 61, the first electrical connection portion 51 can be electrically connected to the first voltage-resistant ring 20, that is, the contact electrical connection between the first metal field plate 50 and the first voltage-resistant ring 20 can be achieved, thereby ensuring the equipotential of the first voltage-resistant ring 20 and the first metal field plate 50.

[0100] In some embodiments, as shown in Figure 4, the aperture of the fourth via 61 is equal to the aperture of the second via 41. This not only ensures that the first electrical connection portion 51 can pass through the fourth via 61 smoothly, facilitating the electrical connection between the first metal field plate 50 and the first voltage-resistant ring 20, but also facilitates the simultaneous formation of the fourth via 61 and the second via 41, thereby improving the production efficiency of the semiconductor device 100.

[0101] In some embodiments, the apertures of the fourth via hole 61 and the second via hole 41 may be different. For example, the aperture of the fourth via hole 61 may be larger than that of the second via hole 41 .

[0102] In some other embodiments, the diameter of the fourth via hole 61 may be smaller than the diameter of the second via hole 41 .

[0103] 1 , the semiconductor device 100 includes an active region 101 and a transition region 102 . The transition region 102 is disposed between the active region 101 and the terminal region 103 . There are multiple first pressure-resistant rings 20 , which are spaced apart.

[0104] In some embodiments, there may be two, three, four, five or even more first pressure-resistant rings 20. In some embodiments, there may be four first pressure-resistant rings 20, and the four first pressure-resistant rings 20 are spaced apart in the terminal area.

[0105] Specifically, the active region 101 can bear most of the forward current during forward conduction and can also bear a high blocking voltage when a reverse voltage is applied. When a reverse voltage is applied to the semiconductor device 100, the terminal region 103 can alleviate the electric field crowding at the edge of the active region 101, thereby achieving the purpose of improving the reverse breakdown voltage of the semiconductor device 100.

[0106] Taking into account the large voltage borne by the terminal area 103, multiple first voltage-resistant rings 20 are arranged in the terminal area 103, and the multiple first voltage-resistant rings 20 are arranged at intervals. In this way, the multiple first voltage-resistant rings 20 can optimize the electric field distribution of the terminal area 103, increase the breakdown voltage of the terminal area 103, and thus improve the voltage resistance of the terminal area 103.

[0107] In some embodiments of the present disclosure, as shown in FIG1 , a first polysilicon field plate 30 and a first metal field plate 50 are correspondingly disposed above one of the plurality of first voltage-resistant rings 20 that is remote from the transition region 102. Specifically, the one of the plurality of first voltage-resistant rings 20 that is remote from the transition region 102 bears the highest voltage. By disposing the first polysilicon field plate 30 and the first metal field plate 50 correspondingly above the one, the structure of the semiconductor device 100 is simplified, and the production difficulty and cost of the semiconductor device 100 are reduced, while the voltage resistance and reliability of the terminal region 103 are improved.

[0108] In some other embodiments of the present disclosure, a first polysilicon field plate 30 and a first metal field plate 50 are correspondingly disposed above at least one of the plurality of first voltage-resistant rings 20 .

[0109] In some embodiments, if the termination region 103 has a plurality of first voltage-resistant rings 20 , a first polysilicon field plate 30 and a first metal field plate 50 may be correspondingly disposed above each first voltage-resistant ring 20 .

[0110] For example, the first polysilicon field plate 30 and the first metal field plate 50 are disposed on the first voltage-resistant ring 20 farthest from the transition region 102 . Alternatively, the first polysilicon field plate 30 and the first metal field plate 50 can be disposed on the first voltage-resistant ring 20 closest to the transition region 102 .

[0111] In a specific implementation, a first polysilicon field plate 30 and a first metal field plate 50 may also be correspondingly arranged above at least one of the multiple first voltage-resistant rings 20. This can increase the number of first polysilicon field plates 30 and first metal field plates 50, thereby optimizing the electric field distribution of the terminal area 103, improving the voltage resistance of the terminal area 103 and even the semiconductor device 100, and improving the reliability of the semiconductor device 100.

[0112] Of course, whether the first polysilicon field plate 30 and the first metal field plate 50 are correspondingly arranged above one of the multiple first voltage-resistant rings 20 away from the transition zone 102, or the first polysilicon field plate 30 and the first metal field plate 50 are correspondingly arranged above at least one of the multiple first voltage-resistant rings 20, it is necessary to ensure the equipotential of the first polysilicon field plate 30, the first dielectric layer 40 and the first metal field plate 50, which will not be elaborated here.

[0113] In some embodiments of the present disclosure, there are multiple first polysilicon field plates 30, and the multiple first polysilicon field plates 30 are arranged at intervals. The multiple first polysilicon field plates 30 are all provided with first vias 31. A second dielectric layer is provided between two adjacent first polysilicon field plates 30. The first vias 31 on the multiple first polysilicon field plates 30 correspond to each other. The second dielectric layer is provided with a fifth via, and the fifth via corresponds to the first via 31. The first electrical connection portion 51 passes through the fifth via, the first via 31, and the second via 41 and is electrically connected to the first voltage-resistant ring 20.

[0114] Specifically, when the terminal region 103 includes a plurality of first polysilicon field plates 30 spaced apart and a second dielectric layer is provided between the plurality of first polysilicon field plates 30, first vias 31 corresponding to each other can be provided on the plurality of first polysilicon field plates 30, and a fifth via corresponding to the first via 31 can be provided on the second dielectric layer. In this way, the first electrical connection portion 51 can simultaneously penetrate a plurality of fifth vias, a plurality of first vias 31 and a second via 41, and be electrically connected to the first voltage-resistant ring 20, thereby realizing mutual electrical connection between the first metal field plate 50 and the first voltage-resistant ring 20, and the plurality of first polysilicon field plates 30 can also be electrically connected to the first metal field plate 50 by opening holes in the first polysilicon field plate 30 and the second dielectric layer located above them. In this way, even if there are multiple first polysilicon field plates 30, the improvement of the electric field distribution in the terminal region 103 can be guaranteed, and the voltage resistance and reliability of the semiconductor device 100 can be improved.

[0115] Based on the above embodiments, some embodiments of the present disclosure further provide a semiconductor device, which may include a drift layer of a first conductivity type;

[0116] In some embodiments, the semiconductor device may include a second voltage-resistant ring of a second conductivity type;

[0117] In some embodiments, the semiconductor device may include a third dielectric layer;

[0118] In some embodiments, the semiconductor device may include a second metal field plate;

[0119] In some embodiments, the semiconductor device may include a second polysilicon field plate.

[0120] In some embodiments, a second voltage-resistant ring is disposed on the upper surface of the drift layer and corresponds to the transition region of the semiconductor device, a third dielectric layer is disposed on the upper surface of the second voltage-resistant ring, a second metal field plate is disposed on the upper surface of the third dielectric layer, a second polysilicon field plate is disposed on the upper surface of the second voltage-resistant ring and is located between the third dielectric layer and the second voltage-resistant ring, and the second metal field plate is at least partially in contact with the second polysilicon field plate.

[0121] By arranging the second polysilicon field plate on the upper surface of the second voltage-resistant ring, the second polysilicon field plate is located between the third dielectric layer and the second voltage-resistant ring, and the second metal field plate is at least partially in contact with the second polysilicon field plate. This can optimize the electric field distribution in the transition zone, significantly improve the breakdown voltage of the semiconductor device, and significantly improve the voltage resistance and reliability of the semiconductor device.

[0122] The following describes a semiconductor device 100 according to some embodiments of the present disclosure with reference to FIG6-11. The semiconductor device 100 is, for example, an IGBT (Insulated Gate Bipolar Transistor). In the following description, N and P represent the conductivity type of the semiconductor. In this disclosure, the first conductivity type is N-type and the second conductivity type is P-type.

[0123] As shown in Figure 7, the semiconductor device 100 disclosed in the present invention may include a drift layer 10 of the first conductivity type, a field stop layer 70 of the first conductivity type is arranged below the drift layer 10 of the first conductivity type, a collector layer 80 of the second conductivity type is arranged below the field stop layer 70, and a collector metal layer 90 is arranged below the collector layer 80. In this way, the basic structure of the semiconductor device 100 can be formed to ensure the normal operation of the semiconductor device 100.

[0124] The semiconductor device 100 of the present disclosure may include a second voltage-resistant ring 20 a of the second conductivity type, which is disposed on a portion of the surface of the drift layer 10 corresponding to the transition region 102 of the semiconductor device 100 .

[0125] By arranging the second voltage-resistant ring 20a on the surface of the drift layer 10 corresponding to the transition zone 102 of the semiconductor device 100, the electric field distribution of the transition zone 102 can be optimized, the voltage resistance of the transition zone 102 can be improved, and the problem of voltage breakdown easily occurring at this location due to the transition zone 102 of the semiconductor device 100 being located between the terminal area 103 and the active area 101 and having a relatively complex structure can be reduced.

[0126] 7 , 10 and 11 , the semiconductor device 100 of the present disclosure may include a third dielectric layer 40 a , and the third dielectric layer 40 a is disposed on the upper surface of the second pressure-resistant ring 20 a .

[0127] The semiconductor device 100 of the present disclosure may include a second metal field plate 50 a , which is disposed on the upper surface of the third dielectric layer 40 a .

[0128] By setting the third dielectric layer 40a on the upper surface of the second voltage-resistant ring 20a and setting the second metal field plate 50a on the upper surface of the third dielectric layer 40a, a portion of the second metal field plate 50a can be in direct contact with the second voltage-resistant ring 20a, and another portion can be in contact with the third dielectric layer 40a. In this way, when the semiconductor device 100 is subjected to a reverse bias voltage, the second metal field plate 50a can offset the effect of the positive charge in the third dielectric layer 40a on the surface, repel surface electrons, and widen the surface depletion region at the interface, thereby increasing the breakdown voltage.

[0129] The semiconductor device 100 disclosed herein may include a second polysilicon field plate 30a, which is disposed on the upper surface of the second voltage-resistant ring 20a. The second polysilicon field plate 30a is located between the third dielectric layer 40a and the second voltage-resistant ring 20a, and the second metal field plate 50a is at least partially in contact with the second polysilicon field plate 30a.

[0130] Considering that the contact area between the second metal field plate 50a and the second voltage-resistant ring 20a is small, the improvement in the voltage-resistant capability of the semiconductor device 100 in the transition region 102 is limited. Compared with the comparative embodiment in which the first polysilicon field plate is not provided, some embodiments of the present disclosure provide a second polysilicon field plate 30a between the third dielectric layer 40a and the second voltage-resistant ring 20a. The second polysilicon field plate 30a can achieve large-area direct contact with the second voltage-resistant ring 20a, and the second metal field plate 50a can be at least partially in contact with the second polysilicon field plate 30a, so that the second polysilicon field plate 30a and the second metal field plate 50a have the same electric potential.

[0131] In some embodiments, the second metal field plate 50 a can completely connect to the second polysilicon field plate 30 a .

[0132] In this way, when the semiconductor device 100 is subjected to a reverse bias voltage, the second metal field plate 50a and the second polysilicon field plate 30a can offset the influence of the positive charge in the third dielectric layer 40a on the surface, repel surface electrons, and widen the surface depletion region at the interface, thereby significantly improving the surface charge and electric field distribution at the contact position between the second polysilicon field plate 30a and the second voltage-resistant ring 20a, effectively reducing the surface charge of the semiconductor device 100, and further significantly improving the breakdown voltage of the semiconductor device 100, thereby preventing the transition region 102 of the semiconductor device 100 from being broken down and failing, and improving the voltage resistance and reliability of the semiconductor device 100.

[0133] Therefore, by arranging the second polysilicon field plate 30a on the upper surface of the second voltage-resistant ring 20a, the second polysilicon field plate 30a is located between the third dielectric layer 40a and the second voltage-resistant ring 20a, and the second metal field plate 50a is at least partially in contact with the second polysilicon field plate 30a, the electric field distribution in the transition region 102 can be optimized, the breakdown voltage of the semiconductor device 100 can be significantly improved, and the voltage resistance and reliability of the semiconductor device 100 can be significantly improved.

[0134] 7 , the semiconductor device 100 may further include a second field oxide layer 60 a , which is disposed on the upper surface of the second voltage-resistant ring 20 a and located between the second polysilicon field plate 30 a and the second voltage-resistant ring 20 a .

[0135] By providing the second field oxide layer 60 a in the semiconductor device 100 and positioning the second field oxide layer 60 a on the upper surface of the second voltage-resistant ring 20 a , the second field oxide layer 60 a can be used to achieve isolation and prevent the occurrence of parasitic transistors.

[0136] By setting the second field oxide layer 60a between the second polysilicon field plate 30a and the second voltage-resistant ring 20a, the second polysilicon field plate 30a can be located above the second field oxide layer 60a. The second polysilicon field plate 30a can modulate the electric field in the contact area between it and the second field oxide layer 60a, making the electric field distribution more uniform, thereby improving the voltage resistance and reliability of the semiconductor device 100.

[0137] As shown in FIG8 , the second field oxide layer 60a may include a field oxide body 61a. The field oxide body 61a may at least partially cover the upper surface of the second voltage-resistant ring 20a, with another portion of the field oxide body 61a extending outside the second voltage-resistant ring 20a. The upper surface of the field oxide body 61a may be covered with the second polysilicon field plate 30a and the third dielectric layer 40a.

[0138] The second field oxide layer 60a may further include a protrusion 62 disposed at one end of the field oxide body 61a. The protrusion 62 is at least partially covered by the second polysilicon field plate 30a. The side of the protrusion facing away from the second polysilicon field plate 30a may also contact the second voltage-resistant ring 20a. The second polysilicon field plate 30a may completely cover the protrusion 62. The protrusion 62 may be disposed on a side of the semiconductor device 100 near the active area, thereby ensuring that the side of the second polysilicon field plate 30a near the active area 101 covers the protrusion 62.

[0139] The width of the protrusion 62 in the thickness direction of the semiconductor device 100 gradually decreases in a direction toward the active region 101 to form the protrusion 62 .

[0140] In other embodiments, the protrusion 62 a can also be provided at one end of the field oxide body 61 a facing the terminal region 103 , and the side of the second polysilicon field plate 30 a close to the terminal region 103 covers the protrusion 62 .

[0141] Specifically, considering the growth process of the second field oxide layer 60a, the second field oxide layer 60a includes a field oxide body 61a and a protrusion 62. The protrusion 62 is located at one end of the field oxide body 61a. In the protrusion 62 area, the surface charge of the semiconductor device 100 is concentrated, and the electric field distribution is relatively uneven, which is a weak area of ​​the transition region 102. By at least partially covering the protrusion 62 in the second polysilicon field plate 30a, the second polysilicon field plate 30a can improve the surface charge and electric field distribution in the protrusion 62 area, thereby increasing the breakdown voltage, improving the voltage resistance of the semiconductor device 100, and improving the reliability of the semiconductor device 100.

[0142] 8 , the second polysilicon field plate 30a may include a main body 31a located above the field oxide body 61a , covered with a third dielectric layer 40a , and electrically connected to the second metal field plate 50a .

[0143] The second polysilicon field plate 30a may include a covering portion 32a, which is connected between the main portion 31a and the extension portion 33a. The covering portion 32a faces the protrusion 62 relative to the main portion 31a, covers the upper surface of the protrusion 62, and the upper surface of the covering portion 32a is covered with the third dielectric layer 40a.

[0144] The second polysilicon field plate 30a may include an extension portion 33a, which is arranged near the active area 101 relative to the protrusion 62. The extension portion 33a extends outside the protrusion 62 and contacts the second pressure-resistant ring 20a, so that the extension portion 33a can completely cover the end of the protrusion 62 facing away from the field oxide body 61a.

[0145] By covering the main body 31a on the upper surface of the field oxide body 61a and the covering portion 32a on the upper surface of the protrusion 62, the second polysilicon field plate 30a can cover the second field oxide layer 60a, ensuring the uniform distribution of the electric field on the surface above the second field oxide layer 60a in the transition region 102.

[0146] By making the extension portion 33 a cover the outside of the protruding nozzle 62 , the extension portion 33 a can modulate the electric field in the area outside the protruding nozzle 62 , thereby ensuring uniform distribution of the electric field in the area outside the protruding nozzle 62 .

[0147] In this way, the structure and setting position of the second polysilicon field plate 30a can be optimized, and the electric field modulation capability of the second polysilicon field plate 30a on the transition region 102 can be improved, thereby avoiding electric field concentration, making the electric field distribution in the transition region 102 more uniform, and improving the voltage resistance of the semiconductor device 100 and the reliability of the semiconductor device 100.

[0148] 8 , the length of the extension portion 33a is L, and L satisfies the relationship: L ≥ 2 μm. For example, the length L of the extension portion 33a can be 2 μm, 3 μm, 4 μm, or 5 μm. In an exemplary embodiment, the length L of the extension portion 33a can also be 10 μm.

[0149] Specifically, by setting the length of the extension portion 33a within a reasonable range, that is, setting the length of the second polysilicon field plate 30a extending to one side relative to the protrusion 62 within a reasonable range, it can be ensured that the second polysilicon field plate 30a can optimize the electric field distribution in the area near the protrusion 62, and avoid the length of the extension portion 33a being too short, resulting in local electric field concentration on the side close to the protrusion 62 and away from the main body 31a, thereby ensuring the uniformity of the overall electric field distribution in the transition zone 102, and improving the reliability of the transition zone 102 and even the semiconductor device 100.

[0150] 9 , a first through-hole 41 a is provided on the third dielectric layer 40 a , and a third electrical connection portion 51 a is provided on the second metal field plate 50 a . The third electrical connection portion 51 a passes through the first through-hole 41 a and contacts the second polysilicon field plate 30 a .

[0151] Specifically, the third dielectric layer 40a is located between the second polysilicon field plate 30a and the second metal field plate 50a. By providing a first through-hole 41a on the third dielectric layer 40a and providing a third electrical connection portion 51a on the second metal field plate 50a, it is only necessary to make the third electrical connection portion 51a pass through the first through-hole 41a and make the third electrical connection portion 51a contact the second polysilicon field plate 30a. In this way, the second metal field plate 50a can be at least partially in contact with the second polysilicon field plate 30a, which can make the connection between the second metal field plate 50a and the second polysilicon field plate 30a simpler, more convenient, more stable and more reliable.

[0152] In some examples, the outer side of the third electrical connection portion 51a can be connected to the inner wall of the first through-hole 41a, and one end of the third electrical connection portion 51a facing away from the second metal field plate 50a is connected to the second polysilicon field plate 30a.

[0153] Alternatively, the outer side of the third electrical connection portion 51a does not contact the inner wall of the first through-hole 41a, and one end of the third electrical connection portion 51a facing away from the second metal field plate 50a is connected to the second polysilicon field plate 30a.

[0154] In some embodiments, the cross-sectional shape of the third electrical connection portion 51a is the same as the hole shape of the first through-hole 41a. For example, the cross-sectional shape of the third electrical connection portion 51a can be circular, the hole shape of the first through-hole 41a can be circular, and the diameter of the third electrical connection portion 51a can be less than or equal to the inner diameter of the first through-hole 41a.

[0155] In some embodiments, the third electrical connection portion 51 a may be a protruding structure extending toward the second voltage-resistant ring 20 a , where one end of the protruding structure facing away from the second metal field plate 50 a meets the second polysilicon field plate 30 a .

[0156] As shown in FIG. 9 , the second metal field plate 50 a is at least partially in contact with the second voltage-resistant ring 20 a , and the second metal field plate 50 a and the second voltage-resistant ring 20 a have the same potential.

[0157] Specifically, by at least partially contacting the second metal field plate 50a with the second voltage-resistant ring 20a, the second metal field plate 50a can be made to have the same electric potential as the second voltage-resistant ring 20a, and since the second metal field plate 50a is also at least partially contacting the second polysilicon field plate 30a, the second metal field plate 50a and the second polysilicon field plate 30a have the same electric potential. In this way, the second voltage-resistant ring 20a, the second metal field plate 50a and the second polysilicon field plate 30a can be made to have the same electric potential, which can avoid the occurrence of a floating electric field in the transition region 102 and avoid the floating electric field being disturbed by the outside world when the semiconductor device 100 is working, resulting in uneven electric field distribution in the transition region 102 and causing reduced voltage resistance and reliability, thereby improving the voltage resistance capability of the semiconductor device 100 and improving the reliability of the semiconductor device 100.

[0158] In some embodiments, the second metal field plate 50 a can be in complete contact with the second voltage-resistant ring 20 a , so that the second metal field plate 50 a and the second voltage-resistant ring 20 a have the same electrical potential.

[0159] In some embodiments, as shown in Figure 9, a second through-hole 42a is provided on the third dielectric layer 40a, and a fourth electrical connection portion 52a is provided on the second metal field plate 50a. The fourth electrical connection portion 52a passes through the second through-hole 42a and contacts the second voltage-resistant ring 20a. The fourth electrical connection portion 52a is spaced apart from the second polysilicon field plate 30a.

[0160] Specifically, in the area of ​​the transition region 102 where the second polysilicon field plate 30 a is not provided, at least a portion of the third dielectric layer 40 a is still located between the second voltage-resistant ring 20 a and the second metal field plate 50 a .

[0161] By setting a second through-hole 42a on the third dielectric layer 40a and setting a fourth electrical connection portion 52a on the second metal field plate 50a, the fourth electrical connection portion 52a is spaced apart from the second polysilicon field plate 30a. In this way, it is only necessary to make the fourth electrical connection portion 52a pass through the second through-hole 42a and make the fourth electrical connection portion 52a contact the second voltage-resistant ring 20a, so that the second metal field plate 50a can be at least partially connected to the second voltage-resistant ring 20a, which can make the connection between the second metal field plate 50a and the second voltage-resistant ring 20a simpler, more convenient, stable and reliable.

[0162] In some embodiments, the fourth electrical connection portion 52 a may be a protrusion-shaped structure extending toward the second voltage-resistant ring 20 a , and one end of the protrusion-shaped structure facing away from the second metal field plate 50 a contacts the second voltage-resistant ring 20 a .

[0163] In some embodiments, the outer side of the fourth electrical connection portion 52a can be connected to the inner wall of the second through hole 42a, and one end of the fourth electrical connection portion 52a facing away from the second metal field plate 50a is connected to the second pressure-resistant ring 20a.

[0164] Alternatively, the outer peripheral side of the fourth electrical connection portion 52a does not contact the inner peripheral wall of the second through hole 42a, and one end of the fourth electrical connection portion 52a facing away from the second metal field plate 50a is connected to the second pressure-resistant ring 20a.

[0165] In some embodiments, the cross-sectional shape of the fourth electrical connection portion 52a can be the same as the hole shape of the second through-hole 42a. For example, the cross-sectional shape of the fourth electrical connection portion 52a can be circular, the hole shape of the second through-hole 42a can be circular, and the diameter of the fourth electrical connection portion 52a can be less than or equal to the inner diameter of the second through-hole 42a.

[0166] As shown in conjunction with FIG6 and FIG7 , the semiconductor device 100 further includes a source region 101 . The active region 101 can bear most of the forward current during forward conduction and can also bear a high blocking voltage when a reverse voltage is applied.

[0167] The active region 101 is provided with an emitter metal layer 81 . The emitter metal layer 81 may serve as an emitter of the semiconductor device 100 and play a role of conduction and connection.

[0168] The semiconductor device 100 also has a terminal region 103, which is arranged at the periphery of the active region 101. The transition region 102 is connected between the active region 101 and the terminal region 103. In this way, when a reverse voltage is applied to the semiconductor device 100, the terminal region 103 can alleviate the electric field crowding at the edge of the active region 101, thereby achieving the purpose of improving the reverse breakdown voltage of the semiconductor device 100.

[0169] The semiconductor device 100 further includes a transition region 102 in which a gate bus 82 is provided. The parallel gates in the semiconductor device 100 are connected to gate pads via the gate bus 82 and are connected to an external gate driving circuit via the gate pads.

[0170] 6 , the second metal field plate 50a is connected to the emitter metal layer 81 of the active region 101. Specifically, considering that the second metal field plate 50a is in contact with the second polysilicon field plate 30a, by connecting the second metal field plate 50a to the emitter metal layer 81 of the active region 101, the second metal field plate 50a, the second polysilicon field plate 30a, and the emitter metal layer 81 of the active region 101 can be brought to the same potential. This can make the electric field distribution in the transition region 102 more uniform, thereby improving the withstand voltage capability of the transition region 102 and, therefore, the semiconductor device 100.

[0171] As shown in FIG. 7 , a third polysilicon field plate 30 b is provided in the terminal region 103 , and the second polysilicon field plate 30 a and the third polysilicon field plate 30 b are made of the same material and are spaced apart.

[0172] Specifically, considering that the electric field strength in the terminal region 103 is relatively strong and the voltage per unit length is relatively large, it is easier for voltage breakdown to occur there. By setting a third polysilicon field plate 30b in the terminal region 103, the third polysilicon field plate 30b can effectively widen the main junction depletion region outward, avoiding the electric field concentration phenomenon, thereby increasing the breakdown voltage of the terminal region 103 and improving the voltage resistance of the terminal region 103 and even the semiconductor device 100.

[0173] In some embodiments, by setting the materials of the second polysilicon field plate 30a and the third polysilicon field plate 30b to be the same, the second polysilicon field plate 30a and the third polysilicon field plate 30b are spaced apart. In this way, during the manufacturing process of the semiconductor device 100, the second polysilicon field plate 30a and the third polysilicon field plate 30b can be manufactured and formed simultaneously, and the processes of the second polysilicon field plate 30a and the third polysilicon field plate 30b can be combined without adding redundant processes, which can simplify the production process of the semiconductor device 100.

[0174] On the basis of the above embodiments, an embodiment of the present application further provides a semiconductor device, comprising a substrate;

[0175] In some embodiments, the semiconductor device further includes a drift layer of the first conductivity type;

[0176] In some embodiments, the semiconductor device further includes a well layer of a second conductivity type;

[0177] In some embodiments, the semiconductor device further includes a base layer of the second conductivity type;

[0178] In some embodiments, the semiconductor device further includes a first trench.

[0179] In some embodiments, a base body of the semiconductor device has a first main surface and a second main surface, and the first main surface and the second main surface are spaced apart from each other in a first direction.

[0180] In some embodiments, the drift layer is disposed on the substrate and located between the first main surface and the second main surface.

[0181] In some embodiments, a well layer of the second conductivity type is arranged on a side of the drift layer facing the first main surface corresponding to a portion of the transition zone of the semiconductor device, and a side of the well layer adjacent to the first main surface constitutes a portion of the first main surface, and the length of the well layer extends in the second direction and the depth extends in the first direction.

[0182] A base layer of the second conductive type is arranged on the side of the drift layer facing the first main surface, the length of the base layer extends in the second direction and extends from the active area of ​​the semiconductor device to the transition area of ​​the semiconductor device, the side of the base layer adjacent to the first main surface constitutes a part of the first main surface, the depth of the base layer extends in the first direction, the base layer and the well layer are arranged in the second direction, and the depth of the well layer is greater than the depth of the base layer.

[0183] A first trench, the first trench is arranged in the transition region, the depth of the first trench extends from the first main surface toward the first direction, the length of the first trench extends in the third direction, the first trench is located between the well layer and the base layer in the second direction, and both sides of the first trench in the second direction are in contact with the well layer and the base layer respectively, wherein the first direction, the second direction and the third direction are perpendicular to each other.

[0184] By setting the first trench so that the first trench is located between the well layer and the base layer, the first trench can block the second conductive type dopant of the well layer from diffusing toward the base layer, thereby avoiding the formation of a curved surface in the transition region, optimizing the electric field distribution in the transition region, and avoiding electric field concentration, thereby improving the reliability of the semiconductor device and increasing the safe operating area of ​​the semiconductor device.

[0185] The following describes a semiconductor device 100 according to the present invention with reference to FIG12-FIG25. The semiconductor device 100 can be manufactured using a method for manufacturing the semiconductor device 100. The semiconductor device 100 can be an insulated gate bipolar transistor. In the following description, N and P represent the conductivity type of the semiconductor. In this disclosure, the first conductivity type is N-type and the second conductivity type is P-type.

[0186] 12 to 16 , the semiconductor device 100 according to the present disclosure may include a substrate 70 a , a drift layer 10 of a first conductivity type, a well layer 11 of a second conductivity type, and a base layer 12 of a second conductivity type.

[0187] The semiconductor device 100 may include a substrate 70a having a first main surface 71a and a second main surface 72a. The first main surface 71a and the second main surface 72a are spaced apart from each other in a first direction. The first direction may be the height direction of the substrate in FIG. 14 . The first main surface 71a is located at the top of the substrate, and the second main surface 72a is located at the bottom of the substrate.

[0188] The semiconductor device 100 may include a drift layer 10 . The drift layer 10 is disposed in a substrate 70 a . The drift layer 10 is located between a first main surface 71 a and a second main surface 72 a .

[0189] The semiconductor device 100 may include a well layer 11. The well layer 11 is disposed in a portion of the drift layer 10 on a side facing the first main surface 71 a, corresponding to a transition region 102 of the semiconductor device 100. A side of the well layer 11 adjacent to the first main surface 71 a constitutes a portion of the first main surface 71 a. The length of the well layer 11 extends in the second direction, and the depth of the well layer 11 extends in the first direction. The second direction may be the horizontal direction in FIG. 14 .

[0190] The semiconductor device 100 may include a base layer 12, which is arranged on a side of the drift layer 10 facing the first main surface 71a corresponding to a portion of the transition zone 102 of the semiconductor device 100. The side of the base layer 12 adjacent to the first main surface 71a constitutes a portion of the first main surface 71a. The length of the base layer 12 extends in the second direction and extends from the active area 101 of the semiconductor device 100 to the transition zone 102 of the semiconductor device 100. The depth of the base layer 12 extends in the first direction, so that the base layer 12 and the well layer 11 are arranged in the second direction. In this way, the basic structure of the transition zone 102 of the semiconductor device 100 can be formed to ensure the normal operation of the semiconductor device 100.

[0191] Considering that the transition region 102 of the semiconductor device 100 is located between the terminal region 103 and the active region 101, the structure of the transition region 102 is relatively complex and voltage breakdown is more likely to occur there. By setting the well layer 11, the depth of the well layer 11 is set to be greater than the depth of the base layer 12, and the doping concentration of the second conductive type dopant in the well layer 11 is greater than the doping concentration of the second conductive type dopant in the base layer 12, the electric field distribution in the transition region 102 can be optimized and the voltage resistance of the transition region 102 can be improved.

[0192] As shown in conjunction with FIG. 13 and FIG. 14 , the semiconductor device 100 may further include a first trench 20 b. The first trench 20 b is disposed in the transition region 102. The depth of the first trench 20 b extends from the first main surface 71 a toward the first direction. The length of the first trench 20 b extends in the third direction. The first trench 20 b is located between the well layer 11 and the base layer 12 in the second direction. Both sides of the first trench 20 b in the second direction are in contact with the well layer 11 and the base layer 12, respectively. The first direction, the second direction, and the third direction are mutually perpendicular, and the third direction is perpendicular to both the first direction and the second direction.

[0193] Specifically, considering that the base layer 12 is spaced apart from the well layer 11 in the second direction, and there is a difference in the doping concentration of the second conductive type dopant in the base layer 12 and the well layer 11, the second conductive type dopant in the well layer 11 will diffuse toward the base layer 12 in the second direction, and due to the difference in depth between the base layer 12 and the well layer 11, a curved surface will be formed at the junction of the base layer 12 and the well layer 11. When the semiconductor device 100 is in reverse withstand voltage, electric field concentration will occur at this position, and the electric field intensity is large, which may cause the safe operating area to become smaller, and the reliability of the semiconductor device 100 will be reduced.

[0194] The semiconductor device 100 may further include a second trench 30 c . By providing the second trench 30 c , an oxidized insulating layer 40 c may be grown and polysilicon may be deposited in the second trench 30 c , and the first trench 20 b may be located between the well layer 11 and the base layer 12 in the second direction.

[0195] The first trench 20b has two side walls spaced apart in the second direction, and the two side walls of the first trench 20b extend in the first direction. By making the two side walls of the first trench 20b in the second direction contact the well layer 11 and the base layer 12 respectively, the first trench 20b can be blocked between the well layer 11 and the base layer 12 in the second direction, thereby blocking the second conductive type dopant in the well layer 11 from diffusing toward the base layer 12, thereby avoiding the formation of a curved surface in the transition region 102. When the semiconductor device 100 withstands reverse voltage, the electric field concentration in the transition region 102 is avoided, the reliability of the semiconductor device 100 can be improved, and the safe operating area of ​​the semiconductor device 100 can be increased.

[0196] By setting the first trench 20b so that the first trench 20b is located between the well layer 11 and the base layer 12, the first trench 20b can block the second conductive type dopant of the well layer 11 from diffusing toward the base layer 12, thereby avoiding the formation of a curved surface in the transition region 102, optimizing the electric field distribution in the transition region 102, and avoiding electric field concentration, thereby improving the reliability of the semiconductor device 100 and increasing the safe operating area of ​​the semiconductor device 100.

[0197] As shown in FIG14 , the depth of the first trench 20 b is D1, and the depth of the base layer 12 is D2. D1 and D2 satisfy the relationship: D1 ≥ D2. For example, the depth of the first trench 20 b can be equal to the depth of the base layer 12, or the depth of the first trench 20 b can be greater than the depth of the base layer 12.

[0198] By setting the depth of the first trench 20b to be no less than the depth of the base layer 12, it can be ensured that the first trench 20b completely blocks the base layer 12 in the first direction, thereby more reliably blocking the second conductive type dopant in the well layer 11 from diffusing into the base layer 12, avoiding the generation of a curved surface at the junction of the well layer 11 and the base layer 12, thereby improving the reliability of the semiconductor device 100 and increasing the safe operating area of ​​the semiconductor device 100.

[0199] 14 , the depth of the well layer 11 is D3, and D1 and D3 satisfy the relationship: D1 ≤ D3. For example, the depth of the well layer 11 can be equal to the depth of the first trench 20b, or the depth of the well layer 11 can be greater than the depth of the first trench 20b.

[0200] Specifically, the first groove 20b is also provided with a bottom wall, which connects the two side walls toward the ends of the second main surface 72a. The curvature of the bottom wall is small, and electric field concentration is prone to occur. By setting the depth of the first groove 20b to be no greater than the depth of the well layer 11, it can be ensured that the well layer 11 wraps at least part of the bottom wall of the first groove 20b, thereby optimizing the electric field near the bottom wall and avoiding electric field concentration, thereby ensuring the voltage resistance of the semiconductor device 100 and the reliability of the semiconductor device 100.

[0201] As shown in Figures 13 to 16, the semiconductor device 100 may further include a carrier storage layer 13 of the first conductivity type, which is arranged on the side of the drift layer 10 facing the first main surface 71a, and the carrier storage layer 13 is located between the drift layer 10 and the base layer 12. The length of the carrier storage layer 13 extends in the second direction and extends from the active area 101 of the semiconductor device 100 to the transition area 102 of the semiconductor device 100.

[0202] The carrier storage layer 13 is located on the side of the first trench 20b facing the base layer 12 in the second direction. The depth of the carrier storage layer 13 extends in the first direction. The depth of the carrier storage layer 13 is D4. D4, D2 and D1 satisfy the relationship: D4+D2≤D1.

[0203] In some embodiments, the sum of the depth of the carrier storage layer 13 and the depth of the base layer 12 is equal to the depth of the first trench 20b. Alternatively, the sum of the depth of the carrier storage layer 13 and the depth of the base layer 12 is less than the depth of the first trench 20b.

[0204] By arranging the carrier storage layer 13 on the side of the drift layer 10 facing the first main surface 71a, and extending the length of the carrier storage layer 13 in the second direction and extending from the active area 101 of the semiconductor device 100 to the transition area 102 of the semiconductor device 100, the carrier storage layer 13 is at least partially located between the drift layer 10 and the base layer 12, and the depth of the carrier storage layer 13 extends in the first direction. In this way, the carrier storage layer 13 plays a role in blocking holes, which can promote the injection of electrons into the drift layer 10, thereby enhancing the conductivity modulation effect, reducing the forward conduction voltage drop of the semiconductor device 100, and improving the normal operation of the semiconductor device 100.

[0205] In some embodiments, by setting the sum of the depth of the carrier storage layer 13 and the depth of the base layer 12 to be less than the depth of the first trench 20b, the first trench 20b can completely block the carrier storage layer 13 in the first direction, thereby preventing the first conductive type dopant in the carrier storage layer 13 from diffusing to the well layer 11, avoiding the carrier storage layer 13 and the well layer 11 from generating a PN junction with a small curvature in the second direction, optimizing the electric field distribution in the transition region 102, avoiding electric field concentration, and further improving the reliability of the semiconductor device 100 and increasing the safe operating area of ​​the semiconductor device 100.

[0206] As shown in Figures 13 and 16, the semiconductor device 100 may further include a second trench 30c, the depth of the second trench 30c extends from the first main surface 71a toward the first direction to the drift layer 10, the length of the second trench 30c extends in the second direction, and the second trench 30c extends from the active area 101 of the semiconductor device 100 to the transition area 102 of the semiconductor device 100 in the second direction, and there are multiple second trenches 30c, and the multiple second trenches 30c are arranged at intervals in the third direction.

[0207] By setting the second trench 30c, the second trench 30c extends from the first main surface 71a toward the first direction to the drift layer 10, and the second trench 30c is extended in the second direction. By growing the oxide insulating layer 40c in the second trench 30c, depositing polysilicon, and setting the first conductive type emitter layer on both sides of the second trench 30c, the second trench 30c can have a conductive channel and have current flow capability.

[0208] In some embodiments, the second trench 30c can be set as a plurality, and the plurality of second trenches 30c are spaced apart in the third direction. When the second trench 30c extends in the second direction, it can extend from the active area 101 to the transition area 102. In this way, the plurality of second trenches 30c can be connected to the gate pad 104 through the planar gate polysilicon 60b of the transition area 102, so that the current can be drawn out to ensure the normal operation of the semiconductor device 100.

[0209] In some embodiments, the number of the second grooves 30c can be 2, 3, 4, 5 or even more. In some embodiments, the number of the second grooves 30c can be 6.

[0210] In some embodiments, the depths of the second trench 30 c and the first trench 20 b may be the same.

[0211] By setting the depth of the first trench 20 b to be the same as the depth of the second trench 20 c , the first trench 20 b and the second trench 30 c can be etched simultaneously, thereby simplifying the process flow of the semiconductor device 100 .

[0212] The method for manufacturing the semiconductor device 100 according to the present disclosure can be used to manufacture the above-mentioned semiconductor device 100 .

[0213] In some embodiments of the present disclosure, as shown in FIG17 , a method for manufacturing a semiconductor device 100 may include the following steps:

[0214] A second conductive type dopant with a first doping concentration is implanted into a portion of the drift layer 10 corresponding to the transition region 102 on a side facing the first main surface 71 a to form a well layer 11 with a first depth.

[0215] When manufacturing the semiconductor device 100, a substrate material can be first provided as a drift layer 10, and a second conductive type dopant with a first doping concentration is implanted into a portion of the drift layer 10 corresponding to the transition region 102 on a side facing the first main surface 71a to form a well layer 11 of a first depth, thereby improving the voltage resistance of the transition region 102.

[0216] A second conductive type dopant of a second doping concentration is injected into the side of the drift layer 10 facing the first main surface 71a to form a base layer 12 of a second depth arranged in a second direction with the well layer 11, wherein the second doping concentration is less than the first doping concentration and the second depth is less than the first depth.

[0217] The second doping concentration is less than the first doping concentration, and the second depth is less than the first depth. For example, the doping concentration of the second conductive type dopant in the well layer 11 is greater than the doping concentration of the second conductive type dopant in the base layer 12, and the depth of the well layer 11 in the first direction is greater than the depth of the base layer 12 in the first direction. In this way, while ensuring the withstand voltage capability of the transition region 102, there will be a depth difference and a concentration difference between the well layer 11 and the base layer 12.

[0218] A first trench 20 b extending from the first main surface 71 a toward the first direction is etched between the well layer 11 and the base layer 12 .

[0219] By etching a first trench 20b extending from the first main surface 71a toward the first direction between the well layer 11 and the base layer 12, the first trench 20b can be blocked between the well layer 11 and the base layer 12, thereby preventing the second conductive type dopant of the well layer 11 from diffusing toward the base layer 12, thereby improving the reliability of the semiconductor device 100.

[0220] It should be noted that the first conductive type dopant may be phosphorus ions, and the second conductive type dopant may be boron ions, which are not specifically limited here.

[0221] As shown in FIG17 , the step of etching the first trench 20 b extending from the first main surface 71 a toward the first direction between the well layer 11 and the base layer 12 may include:

[0222] The first trench 20 b and a boundary of the ion implantation region of the well layer 11 facing the base layer 12 are spaced apart from each other in the second direction.

[0223] After the second conductive type dopant is implanted into a portion of the drift layer 10 corresponding to the transition region 102 on a side facing the first main surface 71 a , the second conductive type dopant diffuses in the second direction.

[0224] The finally formed well layer 11 will extend beyond the ion implantation region of the well layer 11 in the second direction. By etching a first trench 20b extending from the first main surface 71a toward the first direction between the well layer 11 and the base layer 12, the first trench 20b and the boundary of the ion implantation region of the well layer 11 toward the side of the base layer 12 are spaced apart from each other in the second direction. This can reserve a distance for the diffusion of the second conductive type dopant in the well layer 11 in the second direction, ensure that the first trench 20b can be located between the well layer 11 and the subsequent base layer 12, avoid electric field concentration, and thus increase the safe operating area of ​​the semiconductor device 100.

[0225] In some embodiments, the first trench 20 b and the boundary of the ion implantation region of the well layer 11 facing the base layer 12 are separated by a distance D5 in the second direction, where D5 satisfies the relationship: 0.5 μm ≤ D5 ≤ 2.0 μm. In some examples, D5 can be 0.5 μm, 0.7 μm, 1 μm, 1.3 μm, 1.7 μm, or 2.0 μm.

[0226] Specifically, by setting the spacing distance between the first trench 20b and the boundary of the ion injection region of the well layer 11 on one side toward the base layer 12 in the second direction within a reasonable range, this not only ensures that the first trench 20b is located between the well layer 11 and the subsequently formed base layer 12, thereby avoiding the formation of a curved surface between the well layer 11 and the base layer 12, but also ensures that the base layer 12 formed after the second conductive type dopant diffuses in the second direction will at least partially wrap the bottom wall of the first trench 20b, thereby avoiding electric field concentration in the first trench 20b. In this way, the electric field distribution in the transition zone 102 can be optimized, the safe operating area of ​​the semiconductor device 100 can be increased, and the reliability of the semiconductor device 100 can be improved.

[0227] In some embodiments of the present disclosure, as shown in FIG18 , after the step of implanting a second conductive type dopant with a first doping concentration into a portion of the drift layer 10 facing the first main surface 71 a corresponding to the transition region 102 to form a well layer 11 of a first depth, and before the step of implanting a second conductive type dopant with a second doping concentration into the side of the drift layer 10 facing the first main surface 71 a to form a base layer 12 of a second depth arranged in a second direction with the well layer 11, wherein the second doping concentration is less than the first doping concentration and the second depth is less than the first depth, the method for manufacturing the semiconductor device 100 may further include:

[0228] Dopants of the first conductivity type are implanted into the side of the drift layer 10 facing the first main surface 71 a to form a carrier storage layer 13 .

[0229] Specifically, during the process of manufacturing the semiconductor device 100, after forming the well layer 11 and before forming the base layer 12, a first conductive type dopant can be injected into the side of the drift layer 10 facing the first main surface 71a, so that a carrier storage layer 13 can be formed in the semiconductor device 100, thereby improving the working performance of the semiconductor device 100.

[0230] In some embodiments, the carrier storage layer 13 is at least partially located between the drift layer 10 and the base layer 12, and the carrier storage layer 13 and the well layer 11 are spaced apart in the second direction, so that the well layer 11 and the carrier storage layer 13 can also be separated by the first trench 20b. The first trench 20b can block the first conductive type dopant in the carrier storage layer 13 from diffusing into the well layer 11, thereby preventing the formation of a PN junction with a small curvature and optimizing the electric field distribution.

[0231] In some embodiments, as shown in FIG. 18 , after the step of implanting a first conductive type dopant into the side of the drift layer 10 facing the first main surface 71 a to form the carrier storage layer 13 , the method for manufacturing the semiconductor device 100 may further include:

[0232] A high temperature gas at a first preset temperature is used to push the trap at a high temperature for a first preset time.

[0233] In this way, by using a high-temperature gas at a first preset temperature and a high-temperature push-trap for a first preset time, the rate and uniformity of distribution and diffusion of the first conductive type dopant in the substrate can be improved, thereby optimizing the working performance of the carrier storage layer 13 and even the semiconductor device 100 and improving the reliability of the semiconductor device 100.

[0234] In some embodiments, the high-temperature gas may be N2, the first preset temperature may be 1150°C, and the first preset time may be 120 minutes, which are not specifically limited here.

[0235] As shown in FIG17 and FIG18 , after the step of implanting a second conductive type dopant into a portion of the drift layer 10 facing the first main surface 71 a corresponding to the transition region 102 to form the well layer 11, the method for manufacturing the semiconductor device 100 may further include:

[0236] High temperature gas at a second preset temperature is used to push the trap for a second preset time.

[0237] In this way, by using high-temperature gas at a second preset temperature and a second preset time to push the well, the rate and uniformity of the distribution and diffusion of the second conductive type dopant in the substrate can be improved, thereby optimizing the working performance of the well layer 11 and even the semiconductor device 100 and improving the reliability of the semiconductor device 100.

[0238] In some embodiments, the high-temperature gas may be N2, the second preset temperature may be 1150°C, and the second preset time may be 80 minutes, which are not specifically limited here.

[0239] As shown in FIG17 and FIG18 , after the step of implanting a second conductivity type dopant of a second doping concentration into the side of the drift layer 10 facing the first main surface 71 a to form a base layer 12 of a second depth arranged in the second direction with the well layer 11, the method for manufacturing the semiconductor device 100 may further include:

[0240] A high temperature gas at a third preset temperature is used to push the trap at a high temperature for a third preset time.

[0241] In this way, by using a high-temperature gas at a third preset temperature and a high-temperature push-well for a third preset time, the rate and uniformity of distribution and diffusion of the second conductive type dopant in the substrate can be improved, thereby optimizing the working performance of the base layer 12 and even the semiconductor device 100 and improving the reliability of the semiconductor device 100.

[0242] In some embodiments, the high-temperature gas may be N 2 , the third preset temperature may be 1150° C., and the third preset time may be 80 minutes, which are not specifically limited here.

[0243] 17 and 18 , after etching the first trench 20 b extending from the first main surface 71 a toward the first direction between the well layer 11 and the carrier storage layer 13 , the method for manufacturing the semiconductor device 100 may further include:

[0244] An oxidized insulating layer 40 c is grown on the surface of the well layer 11 , the first trench 20 b and the base layer 12 ; polysilicon is deposited on the surface of the oxidized insulating layer 40 c and etched; a fourth dielectric layer 14 is deposited on the surface of the polysilicon, the well layer 11 and the base layer 12 .

[0245] Specifically, after etching the first trench 20 b extending from the first main surface 71 a toward the first direction between the well layer 11 and the base layer 12 , the oxidized insulating layer 40 c may be grown on the surfaces of the well layer 11 , the first trench 20 b and the carrier storage layer 13 .

[0246] Then, polysilicon is deposited on the surface of the oxidized insulating layer 40c, so that the polysilicon can be located on the surface of the well layer 11, in the first trench 20b and on the surface of the base layer 12. The polysilicon is then etched to retain the polysilicon located in the first trench 20b to form a trench gate polysilicon 50b, and to retain part of the polysilicon on the surface of the well layer 11 to form a planar gate polysilicon 60b.

[0247] A fourth dielectric layer 14 is then deposited on the surfaces of the polysilicon, the well layer 11 and the base layer 12 . The fourth dielectric layer 14 can protect the surfaces of the polysilicon, the well layer 11 and the base layer 12 , thereby improving the structural reliability of the semiconductor device 100 .

[0248] 17 and 18 , while etching the first trench 20 b extending from the first main surface 71 a toward the first direction between the well layer 11 and the base layer, the semiconductor device 100 may further include:

[0249] The second trench 30c is etched to extend from the first main surface 71a toward the first direction to the drift layer 10, wherein the second trench 30c extends in the second direction, there are multiple second trenches 30c, and the multiple second trenches 30c are spaced apart in the third direction, and the second trench 30c and the first trench 20b have the same depth.

[0250] In this way, the first trench 20b and the second trench 30c can be formed simultaneously, and in subsequent steps, an oxide insulating layer 40c can be grown in the second trench 30c and polysilicon can be deposited to connect the second trench 30c to the gate, thereby simplifying the manufacturing method of the semiconductor device 100 and ensuring the normal operation of the semiconductor device 100.

[0251] The following describes the manufacturing method of the semiconductor device 100 by way of example with reference to FIG. 14 and FIG. 19 to FIG. 24 :

[0252] As shown in FIG19 , a substrate material is provided, wherein the substrate material may be a phosphorus-doped silicon substrate with a resistivity of 25 ohm.cm, to form a structure 1 .

[0253] As shown in Figure 20, based on structure 1, impurity boron ions are injected with an energy of 60keV and a dose of 5E13cm -2 Then, a high-temperature well-pushing process is performed, wherein the high-temperature well-pushing process uses N2 gas at a high temperature of 1150° C. for 80 minutes to form a well layer 11. Structure 2 is formed.

[0254] As shown in Figure 21, based on structure 2, impurity phosphorus ions are injected with an energy of 200keV and a dose of 5E12cm -2 , and perform high temperature trapping, wherein the high temperature trapping uses N2 gas at a high temperature of 1150° C. for 120 minutes to form a carrier storage layer 13. Structure 3 is formed.

[0255] As shown in FIG22 , on the basis of structure 3, a first trench 20 b is etched to form structure 4.

[0256] As shown in FIG23 , on the basis of structure 4, 1100° C. gas O 2 is injected to form a 0.12 μm thick silicon dioxide as an insulating oxide insulating layer 40 c, thereby forming structure 5 .

[0257] As shown in FIG24 , based on structure 5 , 0.8 μm thick polysilicon is deposited in the first trench 20 b and on the flat surface, and the excess polysilicon is etched away to form structure 6 .

[0258] As shown in Figure 25, based on structure 6, impurity boron ions are injected with an energy of 100keV and a dose of 2E13cm -2 Then, a high temperature well-driving process is performed, wherein the high temperature well-driving process uses N2 gas at a high temperature of 1150° C. for 80 minutes to form the base layer 12. Structure 7 is formed.

[0259] As shown in FIG14 , a 1 μm thick silicon dioxide layer is deposited on the basis of structure 7 as a fourth dielectric layer 14, thereby forming a semiconductor device 100. It should be noted that the semiconductor device 100 provided with a carrier storage layer 13 is used as an example here. The specific manufacturing process of a semiconductor device 100 without a carrier storage layer 13 is similarly obtainable and is not further described here.

[0260] Although the embodiments of the present disclosure have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions and alterations may be made to the embodiments without departing from the principles and spirit of the present disclosure, the scope of which is defined by the claims and their equivalents.

Claims

1. A semiconductor device comprising: a drift layer of a first conductivity type; A first voltage-resistant ring of a second conductivity type, wherein the first voltage-resistant ring is disposed at a portion of the drift layer corresponding to a terminal region of the semiconductor device; A first polysilicon field plate, wherein the first polysilicon field plate is disposed above the surface of the first pressure-resistant ring, and the first polysilicon field plate is provided with a first via hole; A first dielectric layer, wherein the first dielectric layer is disposed above the surface of the first polysilicon field plate, the first dielectric layer is provided with a second via hole and a third via hole, the second via hole corresponds to the first via hole, and the third via hole and the second via hole are spaced apart on the surface of the first dielectric layer; A first metal field plate, wherein the first metal field plate is disposed above the surface of the first dielectric layer, the first metal field plate is provided with a first electrical connection portion and a second electrical connection portion, the first electrical connection portion sequentially passes through the second via hole and the first via hole and is electrically connected to the first voltage-resistant ring, and the second electrical connection portion passes through the third via hole and is electrically connected to the first polysilicon field plate.

2. The semiconductor device according to claim 1, wherein The second via hole and the first via hole are arranged above and within the boundaries of both sides of the first voltage-resistant ring, and both sides of the first metal field plate and the first polysilicon field plate extend out of the boundaries of both sides of the first voltage-resistant ring respectively.

3. The semiconductor device according to claim 1, wherein The aperture of the first via hole is larger than the aperture of the second via hole.

4. The semiconductor device according to claim 3, wherein: The first electrical connection portion and the first polysilicon field plate are circumferentially spaced apart from each other corresponding to the inner wall of the first via hole.

5. The semiconductor device according to claim 3, wherein: There are a plurality of the first via holes, which are spaced apart on the surface of the first polysilicon field plate. There are a plurality of the first electrical connection portions, which correspond to the plurality of the first via holes.

6. The semiconductor device according to claim 1, wherein It also includes a first field oxygen layer, which is arranged above the surface of the first voltage-resistant ring and between the first polysilicon field plate and the first voltage-resistant ring. The first field oxygen layer is provided with a fourth via hole, and the fourth via hole corresponds to the first via hole and the second via hole. The first electrical connection part passes through the second via hole, the first via hole and the fourth via hole in sequence and is electrically connected to the first voltage-resistant ring.

7. The semiconductor device according to claim 6, wherein: The aperture of the fourth via hole is equal to the aperture of the second via hole.

8. The semiconductor device according to claim 1, wherein It also includes an active area and a transition area, the transition area is arranged between the active area and the terminal area, there are multiple first voltage-resistant rings, the multiple first voltage-resistant rings are arranged at intervals, and the first polysilicon field plate and the first metal field plate are correspondingly arranged above one of the multiple first voltage-resistant rings far away from the transition area.

9. The semiconductor device according to claim 1, wherein: There are a plurality of the first pressure-resistant rings, and the plurality of the first pressure-resistant rings are arranged at intervals. The first polysilicon field plate and the first metal field plate are correspondingly arranged above at least one of the plurality of the first pressure-resistant rings.

10. The semiconductor device according to claim 1, wherein There are multiple first polysilicon field plates, and the multiple first polysilicon field plates are arranged at intervals. The multiple first polysilicon field plates are all provided with a first via hole. A second dielectric layer is provided between two adjacent first polysilicon field plates. The first via holes on the multiple first polysilicon field plates correspond to each other. The second dielectric layer is provided with a fifth via hole, and the fifth via hole corresponds to the first via hole. The first electrical connection portion passes through the fifth via hole, the first via hole and the second via hole and is electrically connected to the first voltage-resistant ring.

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