Terminal structure with optimized reliability for power device and preparation method therefor and application thereof, and power device and preparation method therefor

Abstract

Disclosed in the present application are a terminal structure with optimized reliability for a power device and a preparation method therefor and an application thereof, and a power device and a preparation method therefor. The terminal structure comprises a phosphorus-containing silicon oxide layer, a silicon nitride layer, a silicon-rich silicon nitride semi-insulating layer, an undoped silicon dioxide layer and an organic dielectric layer, wherein the silicon-rich silicon nitride semi-insulating layer is of a structure in which silicon-rich silicon nitride layers and ultrathin silicon nitride barrier layers are alternately stacked. The terminal structure effectively blocks the intrusion of external water vapor into a power device, thus improving the robustness of the power device under moisture conditions; and multiple layers of silicon-rich silicon nitride are used as a semi-insulating layer, such that the electric field on the surface of the power device has a uniform gradient distribution, thus preventing the accumulation of the electric field at a device terminal, and improving the breakdown resistance of the device under a high voltage. The leakage current of the device can be reduced, and the reliability of the device can be improved; moreover, the process complexity is reduced, and the costs are saved on.

Description

Terminal structure with optimized reliability for power device, preparation method and application thereof, power device and preparation method thereof

[0001] This application claims priority to the Chinese patent application filed with the China Patent Office on August 25, 2023, with application number CN202311079046.2 and invention name “Power device and manufacturing method with optimized reliability terminal structure”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present application relates to the technical field of semiconductor device structure design and manufacturing, and in particular to a terminal structure with optimized reliability for a power device, a preparation method and application thereof, a power device and a preparation method thereof. Background Art

[0003] With the development of power electronics technology, power semiconductor devices are covering an increasing number of application scenarios, requiring continuous improvement in their performance and reliability. In recent years, the application of power devices in harsh environmental conditions has become increasingly important, leading to increasingly stringent pre-shipment testing conditions for power devices. Currently, the high-voltage, high-temperature, and high-humidity reverse bias test (H3TRB) has become a fundamental test method for verifying the reliability of power semiconductor devices.

[0004] In the design and manufacturing of power semiconductor devices, the device's terminals and passivation layer are key structural layers that influence device reliability. Terminal design and passivation layer structure affect the device's leakage current and breakdown field during H3TRB testing. Therefore, optimizing the design of device terminals and passivation layer structure is a key factor in optimizing device reliability.

[0005] The terminals of power semiconductor devices are very sensitive to high electric fields. In order to avoid electric field concentration at the device terminals and cause breakdown at a lower breakdown voltage, power semiconductor devices require a reliable terminal design. In order to obtain reliable terminals and eliminate free bonds formed on the device surface, a passivation layer stack can be formed at the terminals of the wafer. The terminal structure uses semi-insulating and insulating materials. Common insulating layers include polyimide or undoped SiO2. In order to prevent sodium and potassium ions from penetrating through the oxide layer, silicon nitride layers and phosphorus or boron doped SiO2 layers can be used as diffusion barriers to improve the device's protection against ion contamination. Semi-insulating layers are often used as a combination of terminals and passivation layers. By adjusting the conductivity of the semi-insulating layer, the surface potential of the power semiconductor device can be continuously reduced, reducing the risk of terminal breakdown under high voltage.

[0006] In addition to improving the reliability of power semiconductor devices, water vapor intrusion into the device under high temperature and high humidity conditions during actual power device module operation is also a significant factor affecting device reliability. During device reliability testing, the combination of high voltage and high temperature and humidity accelerates the process of water vapor intrusion into the device. After water vapor has penetrated the power device module for a long time, it is difficult to expel it from the module at high temperatures, causing it to accumulate within the device module. A drop in temperature during operation causes the water vapor to condense, which can severely alter material properties and ultimately lead to device failure. During this process, the silicon nitride layer reacts with the intruding water under high voltage and oxidizes. This oxidation process reduces the density of the silicon nitride, degrading its performance as a passivation layer. Water vapor then further intrudes into the underlying aluminum layer, causing device leakage current to increase and ultimately leading to breakdown. Furthermore, the oxidation process caused by the electrochemical reaction alters the structure of the silicon nitride and aluminum layers, leading to increased localized stress in the device terminal area and mechanical degradation of the device terminal.

[0007] The prior art in this field includes a semiconductor device comprising a semiconductor wafer and a passivation layer stack formed on its surface. The passivation layer comprises an amorphous semi-insulating layer, a first nitride layer, an intermediate layer, and a second nitride layer. This structure fails to account for moisture intrusion into the nitride layer, which can cause device leakage current to increase and ultimately lead to breakdown. Another semiconductor device structure comprises a semi-insulating polysilicon layer, a silicon nitride layer, and a silicon dioxide layer. While this structure accounts for moisture intrusion into the silicon nitride layer, the introduction of the semi-insulating polysilicon layer increases device leakage current, resulting in increased device power consumption and reduced device lifespan. It also increases process complexity and device cost.

[0008] Summary of the Invention

[0009] The prior art suffers from issues such as poor robustness against water vapor intrusion or complex manufacturing processes for power devices. To simplify the manufacturing process costs of power devices while ensuring robustness of device terminals against water vapor intrusion, the present application provides a terminal structure with optimized reliability for a power device, a preparation method and application thereof, a power device, and a preparation method thereof.

[0010] This application relates to a power device structural design and manufacturing method, comprising a wafer and a passivation layer structure formed at a device terminal on the wafer surface. The terminal comprises, in descending order from the wafer surface, a phosphorus-containing silicon oxide layer, a silicon nitride layer, a silicon-rich silicon nitride semi-insulating layer, an undoped silicon dioxide layer, and an organic dielectric layer. The silicon-rich silicon nitride semi-insulating layer comprises alternating layers of silicon-rich silicon nitride and silicon nitride. This invention can improve device reliability while reducing leakage current, reducing process complexity, and saving costs.

[0011] In the power device of the present application, a semiconductor wafer is provided. The wafer can be made of a wide-bandgap semiconductor material such as silicon or silicon carbide, gallium nitride, etc. First, a MOS structure is formed on the front side of the wafer until the top metal process is completed. The manufacturing and process methods of the MOS structure before this are well known to relevant industry insiders. Then, a layer of thickness of 10 ... The phosphorus-doped silicon oxide layer can relieve the stress of the subsequent silicon nitride layer on the substrate. On the other hand, the phosphorus impurities can form ion traps to improve the protection of the device against ion contamination. Then, a layer of thickness of 1000 nm is deposited on the silicon dioxide layer by plasma enhanced chemical vapor deposition (PECVD). The silicon nitride layer protects the substrate from mechanical damage and metal ion intrusion. To reduce the stress of the silicon nitride layer, alternating high- and low-frequency PECVD deposition is used, with high- and low-frequency times of 11 to 13 seconds and 5 to 7 seconds, respectively, and a high- and low-frequency time ratio of 0.60 to 0.70. The stress of the deposited Si3N4 layer is less than 50 MPa.

[0012] The upper layer of silicon nitride is a silicon-rich silicon nitride semi-insulating layer. The silicon-rich silicon nitride semi-insulating layer is a layered structure of silicon-rich silicon nitride and silicon nitride alternately arranged. Silicon-rich silicon nitride and silicon nitride are deposited in sequence by plasma enhanced chemical vapor deposition (PECVD). The thickness of silicon-rich silicon nitride and silicon nitride deposited in a single pass is respectively and The thickness of the final silicon-rich silicon nitride semi-insulating layer is In the silicon-rich silicon nitride layer, the silicon content gradually decreases with deposition, and eventually remains the same as the silicon content in silicon nitride. The silicon content is adjusted by the sputtering power of the Si target and the Si3N4 target in PECVD. Due to the presence of silicon cores, the properties of silicon-rich silicon nitride are close to those of semiconductors, and its conductivity can be adjusted by regulating the silicon content; the silicon nitride ultra-thin barrier layer can limit the mutual diffusion of silicon between different silicon-rich silicon nitride layers. The multilayer structure of alternating silicon-rich silicon nitride and silicon nitride ultra-thin barrier layers is used as a semi-insulating layer. On the one hand, by adjusting the conductivity of different layers, the surface potential can be continuously reduced, so that the electric field on the surface of the device is uniformly distributed, effectively improving the breakdown of the device under high voltage; on the other hand, it helps to provide a fixed interface charge on the surface of the device, providing a flow path for the trapped charge accumulated on the surface of the device.

[0013] On the silicon-rich silicon nitride semi-insulating layer is an undoped silicon dioxide layer grown by high-density plasma chemical vapor deposition (HDP CVD) with a thickness of The undoped silicon dioxide layer effectively blocks water vapor, while the hydrogen-oxygen bonds within it ensure good adhesion of the subsequent organic dielectric layer, avoiding the unreliable adhesion of the organic dielectric layer deposited directly on the silicon nitride layer. Finally, an organic dielectric layer, such as polyimide or organosilicon, is deposited on the undoped silicon dioxide layer to effectively block water vapor from outside the device.

[0014] The proposed power device terminal structure, comprising a phosphorus-containing silicon oxide layer, silicon nitride, a silicon-rich silicon nitride semi-insulating layer, an undoped silicon dioxide layer, and an organic dielectric layer, effectively blocks the intrusion of external moisture into the device, improving its robustness in humid conditions. The introduction of multiple layers of silicon-rich silicon nitride as semi-insulating layers creates a uniform gradient distribution of the electric field on the power device surface, preventing electric field accumulation at the device terminals and enhancing the device's breakdown resistance under high voltages. This terminal structure design effectively optimizes device reliability in harsh operating environments.

[0015] The silicon-rich silicon nitride semi-insulating layer proposed in this application is composed of silicon-rich silicon nitride and an ultra-thin silicon nitride barrier layer. The conductivity of the silicon-rich silicon nitride is adjusted by controlling the silicon content in the silicon-rich silicon nitride. The ultra-thin silicon nitride barrier layer acts as a shielding layer to prevent silicon diffusion between layers of different silicon-rich silicon nitrides. The semi-insulating layer material can be grown in the same PECVD reaction chamber as the silicon nitride layer, simplifying the process and reducing device manufacturing costs.

[0016] The phosphorus-containing silicon oxide layer and the undoped silicon dioxide layer proposed in this application, wherein the phosphorus-containing silicon oxide layer effectively relieves the stress of the subsequent silicon nitride layer on the substrate, and at the same time, phosphorus doping can form an ion trap, thereby improving the protection of the device against ion contamination; the undoped silicon dioxide layer can effectively block water vapor, and in addition, the hydrogen-oxygen bonds present in the undoped silicon dioxide layer can ensure that the subsequent organic dielectric layer has good adhesion, thereby avoiding the unreliable adhesion of the organic dielectric layer directly deposited on the silicon nitride layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] FIG1 is a schematic structural diagram of a power device in the prior art.

[0018] FIG2 is a schematic diagram of the structure of a power device provided in a typical implementation case of the present application.

[0019] Figure 3 is a schematic diagram of the composite structure of a silicon-rich silicon nitride semi-insulating layer in a power device provided by the typical embodiment of the present application in Figure 2. The direction of the arrows in the figure indicates the direction of material deposition in the silicon-rich silicon nitride semi-insulating layer.

[0020] Explanation of the accompanying symbols: 1. Metal layer; 2. Gate-source isolation layer; 3. N+ source region; 4. Polycrystalline gate; 5. P-type doped region; 6. Gate oxide layer; 7. Drift region; 8. Phosphorus-doped silicon dioxide layer; 9. Silicon nitride layer; 10. Silicon-rich silicon nitride semi-insulating layer; 11. Undoped silicon dioxide layer; 12. Organic dielectric layer; 13. Silicon-rich silicon nitride layer; 14. Silicon nitride ultra-thin barrier layer. DETAILED DESCRIPTION

[0021] The following is a specific implementation of the present application in conjunction with the accompanying drawings, which clearly and completely describes the technical solutions in the present application, but the present application is not limited to the following implementations. Obviously, the described embodiments are part of the embodiments of the present application, rather than all of the embodiments. According to the following description and claims, the advantages and features of the present application will be clearer. It should be noted that the drawings are all in a very simplified form and use non-precise ratios, which are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present application. All other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of this application.

[0022] The present application can be implemented in different forms and should not be construed as being limited to the embodiments presented herein. On the contrary, providing these embodiments will make the disclosure thorough and complete and fully convey the scope of the present application to those skilled in the art. In the accompanying drawings, for clarity, the sizes and relative sizes of layers and regions may be exaggerated, and the same reference numerals represent the same elements throughout. In the description of the present application, it should be noted that the orientation or positional relationship indicated by the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inside", "outside", etc. is based on the orientation or positional relationship shown in the accompanying drawings, and is only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present application. In addition, the terms "first", "second", and "third" are used for descriptive purposes only and cannot be understood as indicating or implying relative importance.

[0023] The specific implementation of the present application is as follows. Figures 2 and 3 are structural diagrams of the present application, and the dimensions in the figures are not proportional. The region shown in Figure 2 includes a metal layer 1, a gate-source isolation layer 2, an N+ source region 3, a polycrystalline gate 4, a P-type doped region 5, a gate oxide layer 6, a drift region 7, a phosphorus-doped silicon dioxide layer 8, a silicon nitride layer 9, a silicon-rich silicon nitride semi-insulating layer 10, an undoped silicon dioxide layer 11, and an organic dielectric layer 12. Regions 1 to 7 constitute a MOS structure, and regions 8, 9, 10, 11, and 12 are power device terminal structures, including a passivation layer, a semi-insulating layer, and an organic dielectric layer. The region shown in Figure 3 is a silicon-rich silicon nitride semi-insulating layer, including a silicon-rich silicon nitride layer 13, a silicon nitride ultra-thin barrier layer 14, and a structure in which the silicon-rich silicon nitride layer and the silicon nitride ultra-thin barrier layer are alternately arranged.

[0024] The direction of the arrows in the drawings indicates the direction of material deposition in the silicon-rich silicon nitride semi-insulating layer.

[0025] In the power device structure shown in Figure 2, region 1 is an aluminum-copper metal layer, serving as a metal interconnect; region 2 is a gate-source isolation layer composed of silicon dioxide and boron-phosphorus-doped silicon dioxide; regions 3, 5, and 7 are N-type silicon or P-type silicon;

[0026] Region 4 is a gate formed of polysilicon, which can withstand high temperatures and has a self-aligned effect; Region 6 is a gate oxide layer composed of a high-quality silicon dioxide layer. Regions 1 to 7 form a MOS structure. Regions 8, 9, 10, 11, and 12 are the terminal structures of the power device, including a passivation layer, a semi-insulating layer, and an organic dielectric layer. Figure 3 shows the specific structure of the silicon-rich silicon nitride semi-insulating layer 10, which is a multi-layered composite layer including a silicon-rich silicon nitride layer region 13 and a silicon nitride ultra-thin barrier layer region 14. The silicon-rich silicon nitride layer 13 and the silicon nitride ultra-thin barrier layer 14 are alternately stacked to form the silicon-rich silicon nitride semi-insulating layer 10. The direction of the arrow in Figure 3 indicates the direction of material deposition in the silicon-rich silicon nitride semi-insulating layer.

[0027] In the structure shown, the phosphorus-containing silicon oxide layer 8, silicon nitride layer 9, silicon-rich silicon nitride semi-insulating layer 10, undoped silicon dioxide layer 11, and organic dielectric layer 12 form the terminal structure of the semiconductor power device. This terminal structure effectively blocks the intrusion of external water vapor into the device, improving the device's robustness under humid conditions. The introduced silicon-rich silicon nitride multilayer 10 serves as a semi-insulating layer, where the conductivity of the silicon-rich silicon nitride is adjusted by controlling the silicon content in the silicon-rich silicon nitride. The silicon nitride ultra-thin barrier layer acts as a shielding layer to prevent the diffusion of silicon between layers of different silicon-rich silicon nitrides. This ensures a uniform gradient distribution of the electric field on the surface of the power device, preventing electric field concentration at the device terminal and enhancing the device's breakdown resistance under high voltage. This terminal structure design effectively optimizes the device's reliability in harsh operating environments. The growth of the semi-insulating layer material can be carried out in the same PECVD reaction chamber as the silicon nitride layer, simplifying the process flow and saving device manufacturing costs.

[0028] Among them, the phosphorus-containing silicon oxide layer 8 and the undoped silicon dioxide layer 11, the phosphorus-containing silicon oxide layer 8 can effectively relieve the stress of the subsequent silicon nitride layer on the substrate, and at the same time, doping with phosphorus can form an ion trap, thereby improving the protection of the device against ion contamination; the undoped silicon dioxide layer 11 can effectively block water vapor. In addition, the hydrogen-oxygen bonds present in the undoped silicon dioxide layer 11 can ensure that the subsequent organic dielectric layer 12 has good adhesion, thereby avoiding the unreliable adhesion of the organic dielectric layer directly deposited on the silicon nitride layer 9.

[0029] The manufacturing process of these structures is described below.

[0030] First, a MOS structure is formed. This MOS structure is fabricated on an N-type single-crystal silicon substrate or a wide-bandgap semiconductor such as SiC. The substrate is not limited to the aforementioned materials, but is preferably a wide-bandgap semiconductor material. Conventional MOS structure fabrication methods are well known to those skilled in the art.

[0031] As shown in FIG2 , an N-type drift region 7 is grown on a SiC substrate by PECVD; then a layer with a thickness of The SiO2 is used as a hard mask layer for subsequent trench gate etching.

[0032] Then, photoresist is spin-coated on the hard mask layer, and after baking, exposure, and development, SiO2 is etched; then, SiO2 is used as a hard mask to etch the N-drift region, and a groove with a depth of about 5 microns is formed in a part of the N-drift region to serve as the gate groove.

[0033] After removing the sacrificial oxide layer, a high-quality silicon oxide layer is grown by HDP CVD to serve as the gate oxide layer 6 .

[0034] Using LPCVD process to deposit a layer of thickness After the polysilicon is etched, a trench-type polysilicon gate 4 is formed.

[0035] The P-type doped region 5 is formed by B ion implantation and high temperature push-in junction.

[0036] By adopting the method of As ion implantation and high temperature push-in junction, an N+ source region 3 is formed in the P-type doping region 5 near the gate in the silicon trench.

[0037] Tetraethyl orthosilicate and boron-phosphorus-doped silicon dioxide (TEOS+BPSG) are deposited, and then lead hole photolithography is performed to form a gate-source isolation layer 2.

[0038] AlCu metal deposition is performed by magnetron sputtering, and a front metal layer 1 is formed by metal etching, thereby completing the manufacture of the MOS structure part.

[0039] The manufacturing process of the terminal structure is then carried out. First, a thickness of 1000 mm is deposited on the front metal layer 1 by HDP CVD. The phosphorus-containing silicon oxide layer 8 is deposited by HDP CVD SiO2 process, which has low process temperature and good step coverage.

[0040] Further, a layer with a thickness of In order to reduce the stress of the silicon nitride Si3N4 layer 9, high and low frequency PECVD is used here for alternating deposition, where the high and low frequency times are 13s and 7s respectively, and the high and low frequency time ratio is 0.65. The stress of the Si3N4 layer 9 after deposition is about 30MPa.

[0041] Then, a multilayer composite silicon-rich silicon nitride semi-insulating layer 10 consisting of silicon-rich silicon nitride 13 and silicon nitride ultra-thin barrier layer 14 alternately stacked is deposited on the Si3N4 layer 9 by PECVD process. The thickness of the silicon-rich silicon nitride and silicon nitride ultra-thin barrier layer deposited in a single pass is and The total thickness of the final silicon-rich silicon nitride semi-insulating layer is The silicon content in the silicon-rich silicon nitride layer is adjusted by the sputtering power of the Si target and the Si3N4 target in PECVD. The Si content in the silicon-rich silicon nitride layer gradually decreases and eventually becomes consistent with the Si content in the silicon nitride ultra-thin barrier layer.

[0042] The power device PAD region is formed by spin-coating photoresist on the Si3N4 layer 9, baking, exposing, and developing, and then etching the Si3N4. Annealing at 400 degrees Celsius for 30 minutes densifies the passivation layer structure and releases residual electrons and metal stress from etching.

[0043] A multilayer composite silicon-rich silicon nitride semi-insulating layer is grown by high-density plasma chemical vapor deposition (HDPCVD) with a thickness of undoped silicon dioxide layer 11.

[0044] Polyimide was spin-coated on the undoped silicon dioxide layer 11 and baked in an oxygen-free environment at 425 degrees Celsius for 60 minutes. The polyimide layer was finally cured to form an organic dielectric layer 12. The thickness after curing was 10 μm. This completed the entire device fabrication process of this application.

[0045] FIG1 shows a structure of a power device in the prior art, and its manufacturing method is basically the same as that of the above embodiment, but does not include the terminal structure in this application.

[0046] Performance comparison tests were conducted on the existing comparative structure shown in FIG1 and the structure of the present application shown in FIG2. H3TRB reliability tests were conducted on the power devices provided by the embodiments of the present application and the comparative structure, including tests on the change of leakage current over time and the change of leakage current over BV withstand voltage. The results are as follows:

[0047] A power device provided in an embodiment of the present application has a leakage current of 10nA, 10nA, and 10nA at 0.5BV, 0.8BV, and 1.0BV, respectively, as BV increases; the leakage current after H3TRB test for 1000 hours, 1500 hours, and 3000 hours is 0.2mA, 0.2mA, and 0.2mA, respectively.

[0048] A power device provided by the comparison structure has a leakage current of 0.1mA, 1mA, and 10mA at 0.5BV, 0.8BV, and 1.0BV, respectively, as BV increases; the leakage current after H3TRB test for 1000 hours and 1500 hours is 0.5mA and 10mA, respectively. After 3000 hours, obvious burn spots have appeared on the surface of the power device, and the power device has been damaged by breakdown.

[0049] Result analysis:

[0050] Based on the above test results, it can be clearly seen that the power device with the terminal structure provided in the embodiment of the present application significantly reduces the device leakage current compared with the prior art; in the reliability H3TRB test, the device leakage current remains almost unchanged up to 3000 hours, which significantly improves the device reliability.

[0051] It should be understood that the above embodiments are merely illustrative of the technical concepts and features of this application. Their purpose is to enable those familiar with the art to understand the content of this application and implement it accordingly. They are not intended to limit the scope of protection of this application. Any equivalent changes or modifications made in accordance with the spirit and substance of this application shall be included within the scope of protection of this application.

Claims

1. A terminal structure with optimized reliability for a power device, characterized in that: The terminal structure comprises, from bottom to top, a phosphorus-containing silicon oxide layer, a silicon nitride layer, a silicon-rich silicon nitride semi-insulating layer, an undoped silicon dioxide layer and an organic dielectric layer.

2. The terminal structure according to claim 1, characterized in that: The silicon-rich silicon nitride semi-insulating layer is a composite layer formed by alternately stacking multiple layers of silicon-rich silicon nitride layers and silicon nitride ultra-thin barrier layers.

3. The terminal structure according to claim 2, characterized in that: The thickness of the single-layer silicon-rich silicon nitride layer and the silicon nitride ultra-thin barrier layer are and The total thickness of the silicon-rich silicon nitride semi-insulating layer is 4. The terminal structure according to claim 1 or 3, characterized in that: The thickness of the phosphorus-containing silicon oxide layer is The thickness of the silicon nitride layer is The thickness of the undoped silicon dioxide layer is The thickness of the organic medium layer is 10 um.

5. The method for preparing the terminal structure according to any one of claims 1 to 4, characterized in that: The following steps are involved: forming a phosphorus-containing silicon oxide layer on a surface of a substrate; forming a silicon nitride layer on the phosphorus-containing silicon oxide layer; forming a silicon-rich silicon nitride semi-insulating layer on the silicon nitride layer; forming an undoped silicon dioxide layer on the surface of the silicon-rich silicon nitride semi-insulating layer; Polyimide is spin-coated on the surface of the undoped silicon dioxide layer and cured to form an organic dielectric layer.

6. The preparation method according to claim 5, characterized in that: The phosphorus-containing silicon oxide layer is formed by HDP CVD deposition using a low-temperature process.

7. The preparation method according to claim 5, characterized in that: The silicon nitride layer is formed by a PECVD process; the PECVD process is a high-frequency and low-frequency PECVD method of alternating deposition.

8. The preparation method according to claim 7, characterized in that: In the high- and low-frequency PECVD method, the high- and low-frequency times in the alternating deposition are 11 to 13 seconds and 5 to 7 seconds respectively, the high- and low-frequency time ratio is 0.60 to 0.70, and the stress of the deposited silicon nitride layer is less than 50 MPa.

9. The preparation method according to claim 5, characterized in that: The formation process of the silicon-rich silicon nitride semi-insulating layer is: a silicon-rich silicon nitride layer and a silicon nitride layer are sequentially deposited by plasma enhanced chemical vapor deposition.

10. The preparation method according to claim 5, characterized in that: The undoped silicon dioxide layer is formed by using a HDP CVD process.

11. The preparation method according to claim 5, characterized in that: The curing conditions are: baking in an oxygen-free environment at 425° C. for 60 minutes.

12. Use of the terminal structure according to any one of claims 1 to 4 or the terminal structure prepared by the preparation method according to any one of claims 5 to 11 in a power device.

13. A power device having a terminal structure with optimized reliability, characterized in that: It includes a semiconductor substrate, a MOS structure and a terminal structure stacked in sequence from bottom to top; The terminal structure is the terminal structure described in any one of claims 1 to 4 or the terminal structure prepared by the preparation method described in any one of claims 5 to 11.

14. The power device according to claim 13, characterized in that: The semiconductor substrate is Si or a wide bandgap semiconductor.

15. The power device according to claim 14, characterized in that: The semiconductor substrate includes a silicon substrate, a silicon carbide substrate, a gallium nitride substrate, a silicon germanium substrate, and a gallium arsenide substrate.

16. The power device according to claim 13, characterized in that: The MOS structure is a planar MOS or a trench MOS.

17. The power device according to claim 16, characterized in that: When the MOS structure is a trench MOS, the structure of the power device is as follows: the power device is formed in a semiconductor substrate, a drift region is formed in the semiconductor substrate, a substrate in the drift region is etched to form a trench, the trench is filled with polysilicon, and a gate dielectric layer is used as isolation between the polysilicon and the trench substrate; The drift region also has a P-type doped region; the N+ type source region of the power device is located in the P-type doped region, and the polysilicon and the source region are isolated by a gate-source isolation layer; the surface of the gate-source isolation layer is a front metal layer led out from the front.

18. The power device according to claim 16 or 17, characterized in that: The method for preparing the trench MOS comprises: Forming an N-drift region in the semiconductor substrate, and depositing a hard mask layer on the surface of the drift region; Spin-coating photoresist on the hard mask layer, hardening and developing, then etching the hard mask layer to pattern the hard mask layer, and then etching the N-drift region of the semiconductor substrate using the hard mask layer as a pattern definition to form a trench in the gate region of the N-drift region; Removing the hard mask layer, and then forming a high-quality silicon oxide layer as a gate dielectric layer of the MOS structure; Depositing a polysilicon layer and etching back to fill the trench with polysilicon to form a trench-type polysilicon gate; Through ion implantation and high temperature push junction, a P-type doped region is formed; Forming the source region of the MOS structure by ion implantation and high temperature junction pushing; Complete the deposition of tetraethyl orthosilicate and boron-phosphorus-doped silicon dioxide, and then perform lead hole photolithography to form a gate-source isolation layer; Deposit and etch the front-side connection metal. The hard mask layer is a silicon oxide layer with a thickness of 19. The power device according to claim 18, characterized in that: The depth of the groove formed by etching in the N-drift region is 5 um.

20. The power device according to claim 18, characterized in that: The polysilicon is deposited by LPCVD method, and the deposition thickness is Ensure that the trench is fully filled, and then etch back until the polysilicon in the trench is flush with the surface of the semiconductor substrate.

21. The power device according to claim 13, characterized in that: The power device also includes a PAD region; The PAD region is located in a region of the terminal structure where a silicon-rich silicon nitride semi-insulating layer is not formed on the surface of the silicon nitride layer.

22. The method for preparing a power device according to any one of claims 13 to 21, characterized in that: The following steps are involved: Providing a semiconductor substrate, the semiconductor substrate comprising a front surface and a back surface opposite to the front surface; A MOS structure is fabricated on the front side of the semiconductor substrate; A terminal structure is prepared on the surface of the MOS structure according to the preparation method according to any one of claims 5 to 11.

23. The preparation method according to claim 22, characterized in that: When the power device further includes a PAD region, the preparation of the PAD region includes the following steps: In the area on the surface of the silicon nitride layer in the terminal structure where no silicon-rich silicon nitride semi-insulating layer is formed, photoresist is spin-coated, and after baking, exposure and development, the silicon nitride is etched to form the PAD area of ​​the power device; then annealing is performed at a temperature of 400 degrees Celsius for 30 minutes.

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