Memory device control method and apparatus, electronic device, and storage medium

Abstract

The present application relates to the technical field of error correction for memory devices. Provided in the embodiments are a memory device control method and apparatus, an electronic device and a storage medium. The method comprises: in response to monitoring error information of a memory device, acquiring sideband error correction code information; acquiring on-die error correction code information; determining bit width information of the memory device and error scenario information under the bit width information; by means of the sideband error correction code information and the on-die error correction code information, determining the position information of a cache line in the memory device with respect to the error information; and, when the position information is matched with the error scenario information, executing an operation of isolating the memory device. When an error occurs which cannot be covered by the current memory error correction code, the present application may also isolate a storage memory, thereby effectively reducing the probability of downtime caused by errors of the memory device.

Description

Memory device control method, device, electronic device and storage medium

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to the Chinese patent application filed with the China Patent Office on August 29, 2023, with application number 202311098886.3, and entitled “A memory device control method, device, electronic device and storage medium”, all contents of which are incorporated by reference into this application. Technical Field

[0003] The present application relates to the technical field of memory device error correction, and in particular to a memory device control method, a memory device control apparatus, a server, an electronic device, and a computer non-volatile readable storage medium. Background Art

[0004] ECC, short for Error Correction Code, is a mechanism for detecting and correcting errors. It is crucial for data security and high-reliability applications.

[0005] Currently, related technologies usually use ECC to correct errors in memory devices, but conventional ECC cannot cover all error distribution locations, resulting in the risk of downtime when uncorrectable errors occur in the memory.

[0006] Summary of the Invention

[0007] The embodiments of the present application provide a memory device control method, apparatus, electronic device, and computer non-volatile readable storage medium to solve the problem of how to reduce the probability of downtime due to memory device failure.

[0008] The present application discloses a memory device control method, which may include:

[0009] In response to error information from a monitored memory device, sideband error correction information is obtained;

[0010] Obtain error correction information on particles;

[0011] Determine the bit width information for the memory device and the error scenario information based on the bit width information;

[0012] Determine location information of the cache line of the memory device for the error information using the sideband error correction information and the on-chip error correction information;

[0013] When the location information matches the error scenario information, an isolation operation is performed on the memory device.

[0014] Optionally, the memory device includes a first particle and a second particle, the first particle and the second particle correspond to the same cache line, and the bit width information is four units; the error scenario information is that when the cache line is read for the first particle at a first time, there are multiple bit errors in the burst information of the cache line, and when the cache line is read for the second particle at a second time, there are multiple bit errors in the burst information.

[0015] Optionally, the memory device includes a first particle and a second particle, the first particle and the second particle correspond to the same cache line, and the bit width information is four units; the error scenario information is that when the cache line is read for the first particle at a first time, there are multiple bit errors in the burst information of the cache line, and when the cache line is read for the second particle at a second time, there is a single bit error in the burst information, and there are multiple target bit errors in the 128-bit data contained in the continuous pre-read file of the second particle, and the target bit errors are in the same cache line.

[0016] Optionally, the memory device includes a first particle and a second particle, the first particle and the second particle correspond to the same cache line, and the bit width information is four units; the error scenario information is that when the cache line is read for the first particle at a first time, there are multiple bit errors in the burst information of the cache line, and when the cache line is read for the second particle at a second time, there is a single bit error in the burst information, and there are multiple target bit errors in the 128-bit data contained in the continuous pre-read file of the second particle, and the target bit errors are in different cache lines.

[0017] Optionally, the memory device includes a first particle and a second particle, the first particle and the second particle correspond to the same cache line, and the bit width information is eight units; the error scenario information is that when the cache line is read for the first particle at a first time, there are multiple bit errors in the burst information of the cache line, and when the cache line is read for the second particle at a second time, there are multiple bit errors in the burst information.

[0018] Optionally, the memory device includes a first particle and a second particle, the first particle and the second particle correspond to the same cache line, and the bit width information is eight units; the error scenario information is that when the cache line is read for the first particle at a first time, there are multiple bit errors in the burst information of the cache line, and when the cache line is read for the second particle at a second time, there is a single bit error in the burst information, and there are multiple target bit errors in the 128-bit data contained in the continuous pre-read file of the second particle, and the target bit errors are in the same cache line.

[0019] Optionally, the memory device includes a first particle and a second particle, the first particle and the second particle correspond to the same cache line, and the bit width information is sixteen units; the error scenario information is that when the cache line is read for the first particle at a first time, there are multiple bit errors in the burst information of the cache line, and when the cache line is read for the second particle at a second time, there are multiple bit errors in the burst information.

[0020] Optionally, the memory device includes a first particle and a second particle, the first particle and the second particle correspond to the same cache line, and the bit width information is sixteen units; the error scenario information is that when the cache line is read for the first particle at a first time, there are multiple bit errors in the burst information of the cache line, and when the cache line is read for the second particle at a second time, there is a single bit error in the burst information, and there are multiple target bit errors in the 128-bit data contained in the continuous pre-read file of the second particle.

[0021] Optionally, the memory device is loaded on a server, the server is configured with a basic input and output system, the memory device has a corresponding memory controller, and further includes:

[0022] In response to error information of the memory device monitored, the memory controller is used to perform a patrol operation on the memory device, and the basic input and output system is triggered to perform a system management interrupt operation.

[0023] Optionally, the step of obtaining sideband error correction information includes:

[0024] Use BIOS to obtain sideband error correction information.

[0025] Optionally, the step of obtaining error correction information on the particle includes:

[0026] Use basic input and output system to obtain error correction information on the particle.

[0027] Optionally, the method is applied to an error detection and correction procedure, further comprising:

[0028] When the position information does not match the error scene information, the basic input and output system is used to exit the error checking and correction program.

[0029] Optionally, the server is configured with an operating system, and the step of performing the isolation operation on the memory device includes:

[0030] Generate power management standard event information for memory devices using basic input and output systems;

[0031] The basic input and output system is used to send power management standard event information to the operating system to control the operating system to execute system control interrupt on the memory device.

[0032] Optionally, it also includes:

[0033] When the location information matches the error scene information, a repair operation is performed on the memory device.

[0034] Optionally, the step of performing a repair operation on the memory device includes:

[0035] An adaptive dual-device data correction mechanism is used to perform repair operations on memory devices.

[0036] Optionally, the step of performing a repair operation on the memory device includes:

[0037] Use the post-packaging repair mechanism to perform repair operations on memory devices.

[0038] Optionally, the step of performing a repair operation on the memory device includes:

[0039] A partial cache line spare mechanism is used to perform repair operations on memory devices.

[0040] Optionally, it also includes:

[0041] The operating system calls the platform error interface to generate offline page information for the memory device.

[0042] The present application also discloses a memory device control device, including:

[0043] A sideband error correction information acquisition module is used to respond to error information of the memory device monitored and obtain sideband error correction information;

[0044] An on-particle error correction information acquisition module, used to obtain on-particle error correction information;

[0045] A bit width information determination module is used to determine the bit width information of a memory device and error scenario information under the bit width information;

[0046] A location information determination module, configured to determine location information of the error information in a cache line of a memory device using sideband error correction information and on-chip error correction information;

[0047] The isolation operation execution module is used to perform an isolation operation on the memory device when the location information matches the error scenario information.

[0048] Optionally, the memory device includes a first particle and a second particle, the first particle and the second particle correspond to the same cache line, and the bit width information is four units; the error scenario information is that when the cache line is read for the first particle at a first time, there are multiple bit errors in the burst information of the cache line, and when the cache line is read for the second particle at a second time, there are multiple bit errors in the burst information.

[0049] Optionally, the memory device includes a first particle and a second particle, the first particle and the second particle correspond to the same cache line, and the bit width information is four units; the error scenario information is that when the cache line is read for the first particle at a first time, there are multiple bit errors in the burst information of the cache line, and when the cache line is read for the second particle at a second time, there is a single bit error in the burst information, and there are multiple target bit errors in the 128-bit data contained in the continuous pre-read file of the second particle, and the target bit errors are in the same cache line.

[0050] Optionally, the memory device includes a first particle and a second particle, the first particle and the second particle correspond to the same cache line, and the bit width information is four units; the error scenario information is that when the cache line is read for the first particle at a first time, there are multiple bit errors in the burst information of the cache line, and when the cache line is read for the second particle at a second time, there is a single bit error in the burst information, and there are multiple target bit errors in the 128-bit data contained in the continuous pre-read file of the second particle, and the target bit errors are in different cache lines.

[0051] Optionally, the memory device includes a first particle and a second particle, the first particle and the second particle correspond to the same cache line, and the bit width information is eight units; the error scenario information is that when the cache line is read for the first particle at a first time, there are multiple bit errors in the burst information of the cache line, and when the cache line is read for the second particle at a second time, there are multiple bit errors in the burst information.

[0052] Optionally, the memory device includes a first particle and a second particle, the first particle and the second particle correspond to the same cache line, and the bit width information is eight units; the error scenario information is that when the cache line is read for the first particle at a first time, there are multiple bit errors in the burst information of the cache line, and when the cache line is read for the second particle at a second time, there is a single bit error in the burst information, and there are multiple target bit errors in the 128-bit data contained in the continuous pre-read file of the second particle, and the target bit errors are in the same cache line.

[0053] Optionally, the memory device includes a first particle and a second particle, the first particle and the second particle correspond to the same cache line, and the bit width information is sixteen units; the error scenario information is that when the cache line is read for the first particle at a first time, there are multiple bit errors in the burst information of the cache line, and when the cache line is read for the second particle at a second time, there are multiple bit errors in the burst information.

[0054] Optionally, the memory device includes a first particle and a second particle, the first particle and the second particle correspond to the same cache line, and the bit width information is sixteen units; the error scenario information is that when the cache line is read for the first particle at a first time, there are multiple bit errors in the burst information of the cache line, and when the cache line is read for the second particle at a second time, there is a single bit error in the burst information, and there are multiple target bit errors in the 128-bit data contained in the continuous pre-read file of the second particle.

[0055] Optionally, the error scenario information is the number of bit errors in burst information occurring in the same cache line at different target particles at different times.

[0056] Optionally, the memory device is loaded on a server, the server is configured with a basic input and output system, the memory device has a corresponding memory controller, and further includes:

[0057] In response to error information of the memory device monitored, the memory controller is used to perform a patrol operation on the memory device, and the basic input and output system is triggered to perform a system management interrupt operation.

[0058] Optionally, the sideband error correction information acquisition module includes:

[0059] The sideband error correction information acquisition submodule is used to acquire the sideband error correction information using the basic input and output system.

[0060] Optionally, the on-particle error correction information acquisition module includes:

[0061] The on-particle error correction information acquisition submodule is used to acquire on-particle error correction information using a basic input and output system.

[0062] Optionally, the method is applied to an error detection and correction procedure, further comprising:

[0063] The error checking and correction program exit module is used to use the basic input and output system to exit the error checking and correction program when the position information does not match the error scene information.

[0064] Optionally, the server is configured with an operating system, and the isolation operation execution module includes:

[0065] A power management standard event information generation submodule is used to generate power management standard event information for memory devices using a basic input and output system;

[0066] The memory device execution system control interrupt submodule is used to use the basic input and output system to send power management standard event information to the operating system to control the operating system to execute the system control interrupt on the memory device.

[0067] Optionally, it also includes:

[0068] The repair module is used to perform a repair operation on the memory device when the location information matches the error scene information.

[0069] Optionally, the repair module includes:

[0070] The first repair submodule is configured to perform a repair operation on the memory device by adopting an adaptive dual-device data correction mechanism.

[0071] Optionally, the repair module includes:

[0072] The second repair submodule is used to perform a repair operation on the memory device using a post-encapsulation repair mechanism.

[0073] Optionally, the repair module includes:

[0074] The third repair submodule is configured to perform a repair operation on the memory device by adopting a partial cache line spare mechanism.

[0075] Optionally, it also includes:

[0076] The offline page information generation module is used to generate offline page information for the memory device by using the operating system to call the platform error interface.

[0077] An embodiment of the present application also discloses a server, which is equipped with a memory device and is used to respond to error information monitored from the memory device and obtain sideband error correction information; obtain on-grain error correction information; determine bit width information for the memory device and error scenario information under the bit width information; determine location information of the cache line of the memory device for the error information through the sideband error correction information and the on-grain error correction information; and perform an isolation operation on the memory device when the location information matches the error scenario information.

[0078] The embodiment of the present application further discloses an electronic device, comprising a processor, a communication interface, a memory, and a communication bus, wherein the processor, the communication interface, and the memory communicate with each other via the communication bus;

[0079] Memory for storing computer programs;

[0080] The processor is used to implement the method of the embodiment of the present application when executing the program stored in the memory.

[0081] An embodiment of the present application further discloses a computer non-volatile readable storage medium having instructions stored thereon, which, when executed by one or more processors, causes the processors to execute a method as in an embodiment of the present application.

[0082] The embodiments of the present application include the following advantages:

[0083] In an embodiment of the present application, sideband error correction information is obtained by responding to error information of a memory device monitored; on-grain error correction information is obtained; bit width information for the memory device and error scenario information under the bit width information are determined; location information of the error information in a cache line of the memory device is determined through the sideband error correction information and the on-grain error correction information; when the location information matches the error scenario information, an isolation operation is performed on the memory device, thereby achieving isolation of the storage memory when an error that is not covered by the current memory error correction mechanism occurs, thereby effectively reducing the probability of downtime due to memory device errors. BRIEF DESCRIPTION OF THE DRAWINGS

[0084] FIG1 is a schematic diagram of cache line data in actual application;

[0085] FIG2 is a flowchart of a method for controlling a memory device according to an embodiment of the present invention;

[0086] FIG3 is a schematic diagram A of a memory chip provided in an embodiment of the present application;

[0087] FIG4 is a schematic diagram B of a memory chip provided in an embodiment of the present application;

[0088] FIG5 is a schematic diagram C of a memory chip provided in an embodiment of the present application;

[0089] FIG6 is a schematic diagram of cache line data provided by an embodiment of the present application;

[0090] FIG7 is a schematic diagram D of a memory chip provided in an embodiment of the present application;

[0091] FIG8 is a schematic diagram E of a memory chip provided in an embodiment of the present application;

[0092] FIG9 is a schematic diagram F of a memory chip provided in an embodiment of the present application;

[0093] FIG10 is a schematic diagram G of a memory chip provided in an embodiment of the present application;

[0094] FIG11 is a flow chart of a memory device control method provided in an embodiment of the present application;

[0095] FIG12 is a structural block diagram of a memory device control apparatus provided in an embodiment of the present application;

[0096] FIG13 is a hardware structure block diagram of an electronic device provided in an embodiment of the present application;

[0097] FIG14 is a schematic diagram of a computer non-volatile readable storage medium provided in an embodiment of the present application. DETAILED DESCRIPTION

[0098] In order to make the above-mentioned purposes, features and advantages of the present application more obvious and easy to understand, the present application is further described in detail below with reference to the accompanying drawings and specific implementation methods.

[0099] In order to enable those skilled in the art to better understand the embodiments of the present application, some technical terms involved in the embodiments of the present application are explained below.

[0100] ECC: Error Checking and Correcting, error checking and correction;

[0101] BIOS (Basic Input Output System) is an industry-standard firmware interface on IBM PC-compatible systems. The BIOS is the first software loaded when a computer boots up. It is essentially a set of programs hard-coded into a ROM chip on the computer's motherboard. It stores the computer's most important basic input and output routines, the post-boot self-test routine, and the system startup routine. It can read and write detailed system configuration information from the CMOS. Its primary function is to provide the lowest-level, most direct hardware configuration and control for the computer. The BIOS also provides system parameters to the operating system. System hardware changes are hidden from the BIOS, and programs utilize BIOS functionality rather than directly controlling the hardware. Modern operating systems bypass the abstraction layer provided by the BIOS and directly control hardware components.

[0102] UCE: Uncorrectable Error, uncorrectable error;

[0103] CE: Correctable Error, correctable error;

[0104] CPER: Common Platform Error Record, common platform error record;

[0105] ACPI: Advanced Configuration and Power Management Interface, which can be used as a power management standard in practical applications;

[0106] APEI: ACPIPlatform Error Interface, platform error interface for ACPI;

[0107] IMC: Integrated Memory Controller, integrated memory controller;

[0108] A memory controller generally refers to a memory controller. A memory controller is a crucial component of a computer system, controlling memory and responsible for data exchange between the memory and the CPU. The memory controller determines important parameters such as the maximum memory capacity, the number of memory banks, the memory type and speed, and the memory granule data depth and width. In other words, it determines the computer system's memory performance, significantly impacting the overall performance of the system.

[0109] ADDDC: Adaptive Double Device Data Correction (Multiple Region) multi-region adaptive dual device data error correction technology;

[0110] PPR: Post Package Repair, post-package repair technology;

[0111] PCLS: Partial Cache Line Sparing, partial cache line spare;

[0112] DDR: Double Data Rate, DDR SDRAM = Double Data Rate Synchronous Dynamic Random Access Memory, which is commonly referred to as DDR. SDRAM is the abbreviation of Synchronous Dynamic Random Access Memory.

[0113] DIMM stands for Dual-Inline-Memory-Modules, and its Chinese name is Dual Inline Memory Module. It refers to a new type of memory stick that appeared after the launch of the Pentium CPU. It provides a 64-bit data channel.

[0114] cache line: cache line;

[0115] Bit: Bit, unit of information volume.

[0116] In practical applications, the ECC mechanisms commonly used in related technologies include:

[0117] Side-band ECC:

[0118] Side-band ECC is the same as the ECC of standard DDR memory. Both ECC generation and verification are performed by the memory controller. For DDR5, the data channel width is 32 bits, with an additional dedicated 8-bit ECC channel. DDR5 also supports dual channels (80 bits total), and the DIMM end also has dedicated ECC storage particles.

[0119] Read and write operations are as follows:

[0120] Write: The Memory Controller calculates the ECC based on the 32-bit data and then writes it to the ECC location on the DIMM side through the ECC channel.

[0121] Read: The memory controller reads the data and ECC, calculates the ECC based on the data, and then performs verification by comparing the read ECC with the calculated ECC.

[0122] Error correction technologies such as ADDDC add additional ECC particles to the memory, and the process is implemented by IMC. Error correction only allows each burst of information (DDR5: 40 bits) to occur on one particle. When each burst of information occurs on more than two particles, accurate error correction cannot be guaranteed.

[0123] On-die ECC:

[0124] On-die ECC is a new feature introduced with DDR5. With the dual improvements in DDR speed and process technology, the probability of memory problems has greatly increased. To reduce memory problems, DDR chips can verify their own data (128-bit data, 8-bit ECC). In other words, DDR5 chips have their own ECC generation, verification, and storage functions, meaning all operations are performed within the DIMM chip. Therefore, ECC data does not need to be transmitted to the memory controller. This feature is transparent to the memory controller and can be used simultaneously with side-band ECC without interfering with each other. This enhances the memory's RAS characteristics without increasing the IMC load. The specific read and write operations are as follows:

[0125] Write: The Memory Controller transfers the data to the DIMM, and the DIMM calculates the ECC and stores it in the DIMM.

[0126] Read: The DIMM reads the data and the corresponding ECC. The DIMM calculates the ECC again and verifies it against the read ECC.

[0127] As can be seen from the above, On-Die ECC is a supplement to the defect of existing memory ECC technology in correcting single or multi-bit errors (unit error or multi-bit error) on a single burst of information on a single chip. It can realize independent error correction of 16 bursts of information (128 bits) of data accessed in a single time on each chip, that is, single bit errors can be corrected even if multiple chips have single bit errors at the same time. The two play a complementary role.

[0128] In addition, as can be seen from the above, On-Die ECC adds 8 bits of ECC check bits for every 128 bits of data.

[0129] For DDR5 x4 particles, if prefetch is 16, the data length of each prefetch is 64 bits. For On Die ECC, the length of each prefetch is still 128 bits. Therefore, each read and write requires an additional 64 bits to be read from the internal array for ECC calculation. When writing data, since the data length is only 64 bits, 64 bits of data also need to be read from the internal array to form a 128-bit ECC calculation with the write data. That is, for x4 particles, each 8-bit ECC check value corresponds to two 64-bit sections.

[0130] For DDR5 x8 particles, prefetch 16, the data length of each prefetch is 128 bits, which just meets the On Die ECC verification requirements.

[0131] For DDR5 x16 chips, prefetch 16 means that the data length of each prefetch is 256 bits, corresponding to two independent sets of 128-bit data and 8-bit check bits, and the check and error correction process is performed in parallel;

[0132] Burst refers to the length of a burst. A burst is a method of continuously transmitting data between adjacent memory cells in the same row. The number of memory cells (columns) involved in the continuous transmission is the burst length. In DDR SDRAM, it refers to the number of continuous transmission cycles. It generally corresponds to the number of prefetch bits.

[0133] Refer to Figure 1, which is a schematic diagram of cache line data in actual applications. It shows two cache lines in an x4-bit-wide memory. Region 101 represents one cache line, region 102 represents another cache line, and the remaining data is on-ECC ECC data, which is not counted in data statistics. Region 103 includes two side-band ECC data.

[0134] For example, if side-band ECC is used, each burst of data (DDR5: 40 bits) errors occurs on one die. If each burst error occurs on more than two die, accurate error correction cannot be guaranteed. On-die ECC, on the other hand, only allows one error per 128 bits per die. More than two errors cannot be corrected, leading to the risk of downtime.

[0135] To address the above-mentioned issues, an embodiment of the present application provides a memory device control method, which determines, for a memory device of a specific bitwidth, its high-risk scenarios outside the existing ECC coverage. When error information for the memory device is obtained, it can match the high-risk scenarios based on the Side-band ECC information and the on-die Ecc information. When a successful match is made, the error is determined to be a high-risk error, thereby controlling the memory and reducing the risk of downtime due to memory errors.

[0136] 2 , a flowchart of a memory device control method provided in an embodiment of the present application is shown, which may specifically include the following steps:

[0137] Step 201, in response to monitoring error information of a memory device, obtaining sideband error correction information;

[0138] Step 202, obtaining error correction information on the particle;

[0139] Step 203: Determine the bit width information of the memory device and the error scenario information under the bit width information;

[0140] Step 204 , determining location information of the cache line of the memory device for the error information using the sideband error correction information and the on-chip error correction information;

[0141] Step 205: When the location information matches the error scenario information, an isolation operation is performed on the memory device.

[0142] In a specific implementation, the embodiment of the present application can be applied to a server, which can be used to monitor the correctable error information Correctable Error for a memory device, and when the correctable error information Correctable Error is monitored, the server obtains the error information after Side-band ECC processing in response to the correctable error information Correctable Error, that is, the sideband error correction information. At the same time, the error information after on-die ECC repair, that is, the on-chip error correction information, can be obtained.

[0143] Embodiments of the present application can also determine error scenario information under the bit width information for memory devices of various different bit widths after determining the bit width information. For example, the error scenario information may include the number of bit errors in burst information, whether different target particles have the same cache line at different times.

[0144] SPD is an erasable EEPROM on the memory module, which records a lot of important information about the memory, such as the memory chip and module manufacturer, operating frequency, operating voltage, speed, capacity, voltage, row and column address bandwidth and other parameters.

[0145] In a specific implementation, the embodiment of the present application can read the bit width information of the memory device from the SPD after the memory device is inserted into the server.

[0146] A bank refers to the storage array within a memory module. Due to manufacturing processes, the storage array of a memory chip is typically small, requiring the use of several arrays to work independently. A memory module typically has four to eight banks, depending on the design and specifications of the memory module.

[0147] In practical applications, the side-band error correction information Side-band ECC may include the system address, faulty particle, Bank, row, column information, etc., and the on-die error correction information On-die Ecc may include the faulty particle, Bank, and row information.

[0148] In practice, each cache line is read aligned, i.e., 512 bytes aligned.

[0149] Therefore, the location of the error information in the cache line can be determined through the row and column information in Side-band ECC and on-die Ecc.

[0150] When the error information matches the error scenario information at the cache line location, the error information can be determined to be a high-risk error, and isolation operations can be performed on it to prevent the server from crashing due to the error.

[0151] In an embodiment of the present application, sideband error correction information is obtained by responding to error information of a memory device monitored; on-grain error correction information is obtained; bit width information for the memory device and error scenario information under the bit width information are determined; location information of the error information in a cache line of the memory device is determined through the sideband error correction information and the on-grain error correction information; when the location information matches the error scenario information, an isolation operation is performed on the memory device, thereby achieving isolation of the storage memory when an error that is not covered by the current memory error correction mechanism occurs, thereby effectively reducing the probability of downtime due to memory device errors.

[0152] Based on the above embodiment, a modified embodiment of the above embodiment is proposed. It should be noted that, in order to simplify the description, only the differences from the above embodiment are described in the modified embodiment.

[0153] In an optional embodiment of the present application, the memory device includes a first particle and a second particle, the first particle and the second particle correspond to the same cache line, and the bit width information is four units; the error scenario information is that when the cache line is read for the first particle at a first time, there are multiple bit errors in the burst information of the cache line, and when the cache line is read for the second particle at a second time, there are multiple bit errors in the burst information.

[0154] Refer to FIG3 , which is a schematic diagram A of a memory chip provided in an embodiment of the present application;

[0155] When the memory device is an X4-bit wide memory, the first particle is particle A and the second particle is particle E. Exemplarily, the error scenario information is: when a cache line address of particle A is read at time I, it is found that multiple bit errors occur in a burst. When the same cache line address of particle E is read at time II, it is also found that multiple bit errors occur in the burst.

[0156] In an optional embodiment of the present application, a memory device includes a first particle and a second particle, the first particle and the second particle correspond to the same cache line, and the bit width information is four units; the error scenario information is that when the cache line is read for the first particle at a first time, there are multiple bit errors in the burst information of the cache line, and when the cache line is read for the second particle at a second time, there is a single bit error in the burst information, and there are multiple target bit errors in the 128-bit data contained in the continuous pre-read file of the second particle, and the target bit errors are in the same cache line.

[0157] Refer to FIG4 , which is a schematic diagram B of a memory chip provided in an embodiment of the present application;

[0158] When the memory device is an X4-bit-wide memory, the first particle is particle A and the second particle is particle E. Exemplarily, the error scenario information is that when a cache line address of particle A is read at time I, multiple bit errors are found in a burst of particle A. When the same cache line address of particle E is read at time II, a single bit error is also found in the burst. In addition, more than one bit error is found in the 128-bit data contained in the continuous prefetch 16 of this particle (the error is in a cache line).

[0159] Optionally, the memory device includes a first particle and a second particle, the first particle and the second particle correspond to the same cache line, and the bit width information is four units; the error scenario information is that when the cache line is read for the first particle at a first time, there are multiple bit errors in the burst information of the cache line, and when the cache line is read for the second particle at a second time, there is a single bit error in the burst information, and there are multiple target bit errors in the 128-bit data contained in the continuous pre-read file of the second particle, and the target bit errors are in different cache lines.

[0160] Refer to FIG5 , which is a schematic diagram C of a memory chip provided in an embodiment of the present application;

[0161] When the memory device is an X4-bit-wide memory, the first particle is particle A and the second particle is particle E. Exemplarily, the error scenario information is that when reading a cache line address of particle A at time I, multiple bit errors are found in a burst. When reading the same cache line address of particle E at time II, a single bit error is also found in the burst. In addition, more than one bit error is found in the 128-bit data contained in the continuous prefetch 16 of this particle (the error spans cache lines).

[0162] The above describes the specific error scenario information for x4-bit-width memory. By determining the error scenario information for x4-bit-width memory, the coverage of the current ECC mechanism is broadened, thereby further reducing the risk of downtime caused by memory device errors.

[0163] Refer to Figure 6, which is a schematic diagram of cache line data provided by an embodiment of the present application. As can be seen from the figure, for DDR5 x8 particles, prefetch 16, the data length of each prefetch is 128 bits and will not cross the cache line.

[0164] In an optional embodiment of the present application, the memory device includes a first particle and a second particle, the first particle and the second particle correspond to the same cache line, and the bit width information is eight units; the error scenario information is that when the cache line is read for the first particle at a first time, there are multiple bit errors in the burst information of the cache line, and when the cache line is read for the second particle at a second time, there are multiple bit errors in the burst information.

[0165] Refer to FIG7 , which is a schematic diagram D of a memory chip provided in an embodiment of the present application;

[0166] When the memory device is an x8-bit wide memory, the first particle is particle A and the second particle is particle E. Exemplarily, the error scenario information is that when a cache line address of particle A is read at time I, multiple bit errors are found in a burst. When the same cache line address of particle E is read at time II, multiple bit errors are also found in the burst.

[0167] In an optional embodiment of the present application, the memory device includes a first particle and a second particle, the first particle and the second particle correspond to the same cache line, and the bit width information is eight units; the error scenario information is that when the cache line is read for the first particle at a first time, there are multiple bit errors in the burst information of the cache line, and when the cache line is read for the second particle at a second time, there is a single bit error in the burst information, and there are multiple target bit errors in the 128-bit data contained in the continuous pre-read file of the second particle, and the target bit errors are in the same cache line.

[0168] Refer to FIG8 , which is a schematic diagram E of a memory chip provided in an embodiment of the present application;

[0169] When the memory device is an x8-bit wide memory, the first particle is particle A and the second particle is particle E. Exemplarily, the error scenario information is that when a cache line address of particle A is read at time I, multiple bit errors are found in a burst of particle A. When the same cache line address of particle E is read at time II, a single bit error is also found in the burst. In addition, more than one bit error is found in the 128-bit data contained in the continuous prefetch 16 of this particle (the error is in a cache line).

[0170] The above describes the determination of specific error scenario information for x8-bit-width memory. By determining error scenario information for x8-bit-width memory, the coverage of the current ECC mechanism is broadened, thereby further reducing the risk of downtime due to memory device errors.

[0171] In an optional embodiment of the present application, the memory device includes a first particle and a second particle, the first particle and the second particle correspond to the same cache line, and the bit width information is sixteen units; the error scenario information is that when the cache line is read for the first particle at a first time, there are multiple bit errors in the burst information of the cache line, and when the cache line is read for the second particle at a second time, there are multiple bit errors in the burst information.

[0172] FIG9 is a schematic diagram F of a memory chip provided in an embodiment of the present application;

[0173] When the memory device is an x16-bit wide memory, the first particle is particle A and the second particle is particle E. Exemplarily, the error scenario information is that when a cache line address of particle A is read at time I, it is found that multiple bit errors occur in a burst of particle A. When the same cache line address of particle E is read at time II, multiple bit errors are also found in the burst.

[0174] In an optional embodiment of the present application, the memory device includes a first particle and a second particle, the first particle and the second particle correspond to the same cache line, and the bit width information is sixteen units; the error scenario information is that when the cache line is read for the first particle at a first time, there are multiple bit errors in the burst information of the cache line, and when the cache line is read for the second particle at a second time, there is a single bit error in the burst information, and there are multiple target bit errors in the 128-bit data contained in the continuous pre-read file of the second particle.

[0175] Refer to FIG10 , which is a schematic diagram G of a memory chip provided in an embodiment of the present application;

[0176] When the memory device is an x16-bit wide memory, the first particle is particle A and the second particle is particle E. Exemplarily, the error scenario information is that when a cache line address of particle A is read at time I, multiple bit errors are found in a burst of particle A. When the same cache line address of particle E is read at time II, a single bit error is also found in the burst. In addition, more than one bit error is found in the 128-bit (on-die ECC calculation area) data contained in the continuous prefetch 16 of this particle.

[0177] The above describes the specific error scenario information for x16-bit memory. By determining the error scenario information for x8-bit memory, the coverage of the current ECC mechanism is broadened, thereby further reducing the risk of downtime caused by memory device errors.

[0178] When the above error scenario information occurs, there is a risk that the cache line error is uncorrectable. Therefore, when the error information matches the cache line location and the error scenario information, use fault isolation measures or fault repair measures to promptly address the risk and avoid more serious errors (downtime).

[0179] In an optional embodiment of the present application, a memory device is installed in a server, the server is configured with a basic input / output system (BIOS), and the memory device has a corresponding memory controller (IMC). In a specific implementation, the embodiment of the present application can respond to monitoring error information from the memory device by using the memory controller to perform a memory device inspection operation on the memory device IMC, triggering the basic input / output system to execute a system management interrupt (SMI), thereby further reducing the risk of server downtime due to memory errors.

[0180] In an optional embodiment of the present application, the step of obtaining the sideband error correction information includes: obtaining the sideband error correction information using a basic input and output system.

[0181] Optionally, the step of obtaining error correction information on the particle includes:

[0182] Use basic input and output system to obtain error correction information on the particle.

[0183] Since the BIOS is the first system started when the computer is turned on, obtaining sideband error correction information and on-chip error correction information from the BIOS can effectively improve the efficiency of obtaining ECC.

[0184] In an optional embodiment of the present application, the method is applied to an error detection and correction program, further comprising:

[0185] When the position information does not match the error scene information, the basic input and output system is used to exit the error checking and correction program.

[0186] In a specific implementation, when the location information does not match the error scene information, it can be determined that the error is not an uncorrectable error, that is, the risk of the error is not high, and the error checking and correction program can be directly exited to reduce thread occupancy.

[0187] In an optional embodiment of the present application, the server is configured with an operating system, and the step of performing the isolation operation on the memory device includes:

[0188] Generate power management standard event information for memory devices using basic input and output systems;

[0189] The basic input and output system is used to send power management standard event information to the operating system to control the operating system to execute system control interrupt on the memory device.

[0190] In actual applications, the server can be configured with an operating system OS. This application can use the basic input and output system to generate power management standard event information for the memory device, and use the basic input and output system to send power management standard event information to the operating system to control the operating system to execute system control interrupt on the memory device. Optionally, the operating system can also call the platform error interface to generate offline page information for the memory device, that is, the OS can use APEI to page offline the faulty memory to prevent subsequent error addresses from continuing to access, resulting in error escalation.

[0191] In an optional embodiment of the present application, it further includes:

[0192] When the location information matches the error scene information, a repair operation is performed on the memory device.

[0193] In a specific implementation, in addition to performing an isolation operation on a faulty memory device, the embodiment of the present application can also perform a repair operation on it, thereby improving the availability of the server.

[0194] Optionally, the step of performing a repair operation on the memory device includes:

[0195] An adaptive dual device data correction mechanism ADDDC is used to perform repair operations on memory devices.

[0196] ADDDC stands for Adaptive DDDC, which is divided into SR (Single Region) and MR (Multi Regions).

[0197] The main function of ADDDC-SR is that within the same Rank, DDDC can replace a total of two memory fault particles (X8 particle memory does not support this function).

[0198] ADDDC-MR, in virtual lockstep mode, can repair DRAM hard faults. When a hard fault occurs at the bank / rank level, it is mapped out using adaptive virtual lockstep. In addition, ADDDC-MR+1 can tolerate two such hard faults and then correct a single bit fault.

[0199] The embodiments of the present application can perform repair operations on memory devices by adopting an adaptive dual-device data correction mechanism to improve the repair capability of high-risk errors.

[0200] Optionally, the step of performing a repair operation on the memory device includes:

[0201] The post-packaging repair mechanism (PPR) is used to perform repair operations on memory devices.

[0202] Post Package Repair (PPR): The embodiment of the present application can perform repair operations on memory devices by adopting the post-package repair mechanism PPR to improve the repair capability of high-risk errors.

[0203] Optionally, the embodiment of the present application may further adopt a partial cache line spare mechanism PCLS to perform a repair operation on the memory device to improve the repair capability of high-risk errors.

[0204] In order to enable those skilled in the art to better understand the embodiments of the present application, an example is used below to illustrate the embodiments of the present application.

[0205] Refer to FIG11 , which is a flow chart of a memory device control method provided in an embodiment of the present application.

[0206] The implementation process can be jointly implemented by the BIOS system and the OS system. The implementation process of BIOS and OS is as follows:

[0207] 1) When the memory generates a CE and triggers a system management interrupt (SMI), the BIOS collects error information after Side-band ECC processing;

[0208] 2) At the same time, set the system management interrupt operation SMI to complete the inspection. When the memory controller IMC completes the inspection, the SMI is triggered, and the BIOS actively collects the error information after the on-die ECC repair;

[0209] 3) The BIOS collects error information from on-die ECC and side-band ECC processing and determines whether the memory bit width used by the current system meets the several scenario modes for each bit width;

[0210] 4) The program exits when the scenario mode is not satisfied;

[0211] 5) When the scenario mode is met, the BIOS APEI SCI mode is used, the APEI common platform error record flag CPER flag is set, and the executable page first address is filled into the APEI table;

[0212] The OS uses APEI to page the faulty memory offline to prevent subsequent access to the erroneous address, which would cause the error to escalate.

[0213] It should be noted that for the method embodiments, for the sake of simplicity, they are all expressed as a series of action combinations, but those skilled in the art should be aware that the embodiments of the present application are not limited by the order of the actions described, because according to the embodiments of the present application, certain steps can be performed in other orders or simultaneously. Secondly, those skilled in the art should also be aware that the embodiments described in the specification are preferred embodiments, and the actions involved are not necessarily required by the embodiments of the present application.

[0214] 12 shows a block diagram of a memory device control apparatus provided in an embodiment of the present application, which may include the following modules:

[0215] The sideband error correction information acquisition module 1201 is configured to acquire sideband error correction information in response to monitoring error information of a memory device;

[0216] An on-particle error correction information acquisition module 1202 is configured to acquire on-particle error correction information;

[0217] A bit width information determination module 1203 is configured to determine bit width information for a memory device and error scenario information associated with the bit width information;

[0218] A location information determination module 1204 is configured to determine location information of the error information in a cache line of a memory device using sideband error correction information and on-chip error correction information;

[0219] The isolation operation execution module 1205 is configured to execute an isolation operation on the memory device when the location information matches the error scenario information.

[0220] Optionally, the memory device includes a first particle and a second particle, the first particle and the second particle correspond to the same cache line, and the bit width information is four units; the error scenario information is that when the cache line is read for the first particle at a first time, there are multiple bit errors in the burst information of the cache line, and when the cache line is read for the second particle at a second time, there are multiple bit errors in the burst information.

[0221] Optionally, the memory device includes a first particle and a second particle, the first particle and the second particle correspond to the same cache line, and the bit width information is four units; the error scenario information is that when the cache line is read for the first particle at a first time, there are multiple bit errors in the burst information of the cache line, and when the cache line is read for the second particle at a second time, there is a single bit error in the burst information, and there are multiple target bit errors in the 128-bit data contained in the continuous pre-read file of the second particle, and the target bit errors are in the same cache line.

[0222] Optionally, the memory device includes a first particle and a second particle, the first particle and the second particle correspond to the same cache line, and the bit width information is four units; the error scenario information is that when the cache line is read for the first particle at a first time, there are multiple bit errors in the burst information of the cache line, and when the cache line is read for the second particle at a second time, there is a single bit error in the burst information, and there are multiple target bit errors in the 128-bit data contained in the continuous pre-read file of the second particle, and the target bit errors are in different cache lines.

[0223] Optionally, the memory device includes a first particle and a second particle, the first particle and the second particle correspond to the same cache line, and the bit width information is eight units; the error scenario information is that when the cache line is read for the first particle at a first time, there are multiple bit errors in the burst information of the cache line, and when the cache line is read for the second particle at a second time, there are multiple bit errors in the burst information.

[0224] Optionally, the memory device includes a first particle and a second particle, the first particle and the second particle correspond to the same cache line, and the bit width information is eight units; the error scenario information is that when the cache line is read for the first particle at a first time, there are multiple bit errors in the burst information of the cache line, and when the cache line is read for the second particle at a second time, there is a single bit error in the burst information, and there are multiple target bit errors in the 128-bit data contained in the continuous pre-read file of the second particle, and the target bit errors are in the same cache line.

[0225] Optionally, the memory device includes a first particle and a second particle, the first particle and the second particle correspond to the same cache line, and the bit width information is sixteen units; the error scenario information is that when the cache line is read for the first particle at a first time, there are multiple bit errors in the burst information of the cache line, and when the cache line is read for the second particle at a second time, there are multiple bit errors in the burst information.

[0226] Optionally, the memory device includes a first particle and a second particle, the first particle and the second particle correspond to the same cache line, and the bit width information is sixteen units; the error scenario information is that when the cache line is read for the first particle at a first time, there are multiple bit errors in the burst information of the cache line, and when the cache line is read for the second particle at a second time, there is a single bit error in the burst information, and there are multiple target bit errors in the 128-bit data contained in the continuous pre-read file of the second particle.

[0227] Optionally, the memory device is loaded on a server, the server is configured with a basic input and output system, the memory device has a corresponding memory controller, and further includes:

[0228] In response to error information of the memory device monitored, the memory controller is used to perform a patrol operation on the memory device, and the basic input and output system is triggered to perform a system management interrupt operation.

[0229] Optionally, the sideband error correction information acquisition module includes:

[0230] The sideband error correction information acquisition submodule is used to acquire the sideband error correction information using the basic input and output system.

[0231] Optionally, the on-particle error correction information acquisition module includes:

[0232] The on-particle error correction information acquisition submodule is used to acquire on-particle error correction information using a basic input and output system.

[0233] Optionally, the method is applied to an error detection and correction procedure, further comprising:

[0234] The error checking and correction program exit module is used to use the basic input and output system to exit the error checking and correction program when the position information does not match the error scene information.

[0235] Optionally, the server is configured with an operating system, and the isolation operation execution module includes:

[0236] A power management standard event information generation submodule is used to generate power management standard event information for memory devices using a basic input and output system;

[0237] The memory device execution system control interrupt submodule is used to use the basic input and output system to send power management standard event information to the operating system to control the operating system to execute the system control interrupt on the memory device.

[0238] Optionally, it also includes:

[0239] The repair module is used to perform a repair operation on the memory device when the location information matches the error scene information.

[0240] Optionally, the repair module includes:

[0241] The first repair submodule is configured to perform a repair operation on the memory device by adopting an adaptive dual-device data correction mechanism.

[0242] Optionally, the repair module includes:

[0243] The second repair submodule is used to perform a repair operation on the memory device using a post-encapsulation repair mechanism.

[0244] Optionally, the repair module includes:

[0245] The third repair submodule is configured to perform a repair operation on the memory device by adopting a partial cache line spare mechanism.

[0246] Optionally, it also includes:

[0247] The offline page information generation module is used to generate offline page information for the memory device by using the operating system to call the platform error interface.

[0248] As for the device embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.

[0249] An embodiment of the present application also discloses a server, which is equipped with a memory device and is used to respond to error information monitored from the memory device and obtain sideband error correction information; obtain on-grain error correction information; determine bit width information for the memory device and error scenario information under the bit width information; determine location information of the cache line of the memory device for the error information through the sideband error correction information and the on-grain error correction information; and perform an isolation operation on the memory device when the location information matches the error scenario information.

[0250] As for the server embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.

[0251] In addition, an embodiment of the present application also provides an electronic device, including: a processor, a memory, and a computer program stored in the memory and runnable on the processor. When the computer program is executed by the processor, the various processes of the above-mentioned memory device control method embodiment are implemented, and the same technical effect can be achieved. To avoid repetition, it will not be repeated here.

[0252] The embodiment of the present application also provides a computer non-volatile readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, each process of the above-mentioned memory device control method embodiment is implemented, and the same technical effect is achieved. To avoid repetition, it is not described here. Among them, the computer non-volatile readable storage medium is, for example, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk.

[0253] FIG13 is a schematic diagram of the hardware structure of an electronic device implementing various embodiments of the present application.

[0254] The electronic device 1300 includes but is not limited to components such as a radio frequency unit 1301, a network module 1302, an audio output unit 1303, an input unit 1304, a sensor 1305, a display unit 1306, a user input unit 1307, an interface unit 1308, a memory 1309, a processor 1310, and a power supply 1311. Those skilled in the art will appreciate that the electronic device structure shown in FIG13 does not constitute a limitation on the electronic device, and the electronic device may include more or fewer components than shown, or combine certain components, or arrange the components differently. In the embodiments of the present application, the electronic device includes but is not limited to a mobile phone, a tablet computer, a laptop computer, a PDA, a vehicle-mounted terminal, a wearable device, and a pedometer.

[0255] It should be understood that in the embodiments of the present application, the RF unit 1301 may be used to receive and transmit signals during information transmission or calls. Specifically, it receives downlink data from the base station and transmits it to the processor 1310 for processing; in addition, it transmits uplink data to the base station. Typically, the RF unit 1301 includes, but is not limited to, an antenna, at least one amplifier, a transceiver, a coupler, a low-noise amplifier, a duplexer, and the like. Furthermore, the RF unit 1301 may communicate with the network and other devices via a wireless communication system.

[0256] The electronic device provides users with wireless broadband Internet access through the network module 1302, such as helping users to send and receive emails, browse web pages, and access streaming media.

[0257] The audio output unit 1303 can convert audio data received by the RF unit 1301 or the network module 1302 or stored in the memory 1309 into an audio signal and output it as sound. In addition, the audio output unit 1303 can also provide audio output related to a specific function performed by the electronic device 1300 (for example, a call signal reception sound, a message reception sound, etc.). The audio output unit 1303 includes a speaker, a buzzer, a receiver, etc.

[0258] The input unit 1304 is used to receive audio or video signals. The input unit 1304 may include a graphics processing unit (GPU) 13041 and a microphone 13042. The graphics processor 13041 processes image data of still pictures or videos obtained by an image capture device (such as a camera) in video capture mode or image capture mode. The processed image frames can be displayed on the display unit 1306. The image frames processed by the graphics processor 13041 can be stored in the memory 1309 (or other storage medium) or transmitted via the radio frequency unit 1301 or the network module 1302. The microphone 13042 can receive sound and process such sound into audio data. In the case of a telephone call mode, the processed audio data can be converted into a format that can be sent to a mobile communication base station via the radio frequency unit 1301 for output.

[0259] The electronic device 1300 also includes at least one sensor 1305, such as a light sensor, a motion sensor, and other sensors. Specifically, the light sensor includes an ambient light sensor and a proximity sensor, wherein the ambient light sensor can adjust the brightness of the display panel 13061 according to the brightness of the ambient light, and the proximity sensor can turn off the display panel 13061 and / or the backlight when the electronic device 1300 is moved to the ear. As a type of motion sensor, the accelerometer sensor can detect the magnitude of acceleration in all directions (generally three axes), and can detect the magnitude and direction of gravity when stationary. It can be used to identify the posture of the electronic device (such as horizontal and vertical screen switching, related games, magnetometer posture calibration), vibration recognition related functions (such as pedometer, tapping), etc.; the sensor 1305 can also include a fingerprint sensor, a pressure sensor, an iris sensor, a molecular sensor, a gyroscope, a barometer, a hygrometer, a thermometer, an infrared sensor, etc., which will not be repeated here.

[0260] The display unit 1306 is used to display information input by the user or information provided to the user. The display unit 1306 may include a display panel 13061, which may be configured in the form of a liquid crystal display (LCD), an organic light-emitting diode (OLED), or the like.

[0261] The user input unit 1307 can be used to receive input digital or character information, and to generate key signal input related to the user settings and function control of the electronic device. Specifically, the user input unit 1307 includes a touch panel 13071 and other input devices 13072. The touch panel 13071, also known as a touch screen, can collect user touch operations on or near it (such as operations performed by the user using any suitable object or accessory such as a finger, stylus, etc. on or near the touch panel 13071). The touch panel 13071 may include two parts: a touch detection device and a touch controller. Among them, the touch detection device detects the user's touch direction, detects the signal caused by the touch operation, and transmits the signal to the touch controller; the touch controller receives the touch information from the touch detection device and converts it into touch point coordinates, which are then sent to the processor 1310, which receives the command sent by the processor 1310 and executes it. In addition, the touch panel 13071 can be implemented using various types such as resistive, capacitive, infrared, and surface acoustic wave. In addition to the touch panel 13071, the user input unit 1307 may further include other input devices 13072. Specifically, the other input devices 13072 may include but are not limited to a physical keyboard, function keys (such as volume control keys, switch keys, etc.), a trackball, a mouse, and an operating stick, which will not be described in detail here.

[0262] Furthermore, the touch panel 13071 may be overlaid on the display panel 13061. When the touch panel 13071 detects a touch operation on or near the touch panel 13071, the touch operation is transmitted to the processor 1310 to determine the type of touch event. The processor 1310 then provides a corresponding visual output on the display panel 13061 based on the type of touch event. Although in FIG13 , the touch panel 13071 and the display panel 13061 are two independent components to implement the input and output functions of the electronic device, in some embodiments, the touch panel 13071 and the display panel 13061 may be integrated to implement the input and output functions of the electronic device, which is not limited herein.

[0263] The interface unit 1308 is an interface for connecting external devices to the electronic device 1300. For example, the external devices may include a wired or wireless headset port, an external power supply (or battery charger) port, a wired or wireless data port, a memory card port, a port for connecting a device with an identification module, an audio input / output (I / O) port, a video I / O port, a headphone port, etc. The interface unit 1308 may be used to receive input (e.g., data information, power, etc.) from the external device and transmit the received input to one or more elements within the electronic device 1300, or may be used to transmit data between the electronic device 1300 and the external device.

[0264] Memory 1309 can be used to store software programs and various data. Memory 1309 may primarily include a program storage area and a data storage area. The program storage area may store an operating system and at least one application required for a function (such as a sound playback function or an image playback function); the data storage area may store data generated based on the use of the phone (such as audio data, a phone book, etc.). Furthermore, memory 1309 may include high-speed random access memory and non-volatile memory, such as at least one disk storage device, flash memory device, or other volatile solid-state storage device.

[0265] Processor 1310 is the control center of the electronic device. It connects all parts of the electronic device using various interfaces and circuits. By running or executing software programs and / or modules stored in memory 1309 and accessing data stored in memory 1309, it performs various functions of the electronic device and processes data, thereby monitoring the entire electronic device. Processor 1310 may include one or more processing units; preferably, processor 1310 may integrate an application processor and a modem processor, wherein the application processor primarily processes the operating system, user interface, and application programs, while the modem processor primarily handles wireless communications. It is understood that the modem processor may not be integrated into processor 1310.

[0266] The electronic device 1300 may also include a power supply 1311 (such as a battery) to supply power to each component. Preferably, the power supply 1311 may be logically connected to the processor 1310 through a power management system, thereby enabling the power management system to manage functions such as charging, discharging, and power consumption.

[0267] In addition, the electronic device 1300 includes some functional modules not shown, which will not be described here.

[0268] It should be noted that, in this document, the terms "comprises," "includes," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, article, or apparatus comprising a series of elements includes not only those elements but also other elements not explicitly listed, or elements inherent to such process, method, article, or apparatus. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of other identical elements in the process, method, article, or apparatus comprising the element.

[0269] Through the description of the above implementation methods, those skilled in the art can clearly understand that the above-mentioned embodiment methods can be implemented by means of software plus the necessary general hardware platform, and of course can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art, can be embodied in the form of a software product, which is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk), and includes a number of instructions for enabling a terminal (which can be a mobile phone, computer, server, air conditioner, or network device, etc.) to execute the methods of each embodiment of the present application.

[0270] As shown in FIG14 , in another embodiment provided in the present application, a computer non-volatile readable storage medium 1401 is also provided, in which instructions are stored. When the computer non-volatile readable storage medium 1401 is run on a computer, the computer executes the memory device control method in the above embodiment.

[0271] The embodiments of the present application are described above in conjunction with the accompanying drawings, but the present application is not limited to the above-mentioned specific implementation methods. The above-mentioned specific implementation methods are merely illustrative and not restrictive. Under the guidance of this application, ordinary technicians in this field can also make many forms without departing from the purpose of this application and the scope of protection of the claims, all of which are within the protection of this application.

[0272] Those skilled in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed in the embodiments of this application can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.

[0273] Those skilled in the art will clearly understand that, for the convenience and brevity of description, the specific working processes of the systems, devices and units described above can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0274] In the embodiments provided in this application, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are merely schematic. For example, the division of units is only a logical function division. In actual implementation, there may be other division methods, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0275] Units described as separate components may or may not be physically separate, and components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of these units may be selected to achieve the purpose of this embodiment according to actual needs.

[0276] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0277] If the function is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art, or the part of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes several instructions for enabling a computer device (which can be a personal computer, server, or network device, etc.) to execute all or part of the steps of the various embodiments of the present application. The aforementioned storage medium includes various media that can store program codes, such as a USB flash drive, a mobile hard disk, a ROM, a RAM, a magnetic disk, or an optical disk.

[0278] The above are only specific embodiments of the present application, but the scope of protection of this application is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this application should be included in the scope of protection of this application. Therefore, the scope of protection of this application should be based on the scope of protection of the claims.

Claims

1. A memory device control method, characterized in that: include: In response to monitoring error information of the memory device, obtaining sideband error correction information; Obtain error correction information on particles; Determine bit width information for the memory device and error scenario information under the bit width information; Determine location information of a cache line of the memory device for the error information by using the sideband error correction information and the on-chip error correction information; When the location information matches the error scenario information, an isolation operation is performed on the memory device.

2. The memory device control method according to claim 1, characterized in that: The memory device includes a first particle and a second particle, the first particle and the second particle correspond to the same cache line, and the bit width information is four units; the error scenario information is that when the cache line is read for the first particle at a first time, there are multiple bit errors in the burst information of the cache line, and when the cache line is read for the second particle at a second time, there are multiple bit errors in the burst information.

3. The memory device control method according to claim 1, characterized in that: The memory device includes a first particle and a second particle, the first particle and the second particle correspond to the same cache line, and the bit width information is four units; the error scenario information is that when the cache line is read for the first particle at a first time, there are multiple bit errors in the burst information of the cache line, and when the cache line is read for the second particle at a second time, there is a single bit error in the burst information, and there are multiple target bit errors in the 128-bit data contained in the continuous pre-read file of the second particle, and the target bit errors are in the same cache line.

4. The memory device control method according to claim 1, characterized in that: The memory device includes a first particle and a second particle, the first particle and the second particle correspond to the same cache line, and the bit width information is four units; the error scenario information is that when the cache line is read for the first particle at a first time, there are multiple bit errors in the burst information of the cache line, and when the cache line is read for the second particle at a second time, there is a single bit error in the burst information, and there are multiple target bit errors in the 128-bit data contained in the continuous pre-read file of the second particle, and the target bit errors are in different cache lines.

5. The memory device control method according to claim 1, characterized in that: The memory device includes a first particle and a second particle, the first particle and the second particle correspond to the same cache line, and the bit width information is eight units or sixteen units; the error scenario information is that when the cache line is read for the first particle at a first time, there are multiple bit errors in the burst information of the cache line, and when the cache line is read for the second particle at a second time, there are multiple bit errors in the burst information.

6. The memory device control method according to claim 1, characterized in that: The memory device includes a first particle and a second particle, the first particle and the second particle correspond to the same cache line, and the bit width information is eight units; the error scenario information is that when the cache line is read for the first particle at a first time, there are multiple bit errors in the burst information of the cache line, and when the cache line is read for the second particle at a second time, there is a single bit error in the burst information, and there are multiple target bit errors in the 128-bit data contained in the continuous pre-read file of the second particle, and the target bit errors are in the same cache line.

7. The memory device control method according to claim 1, characterized in that: The memory device includes a first particle and a second particle, the first particle and the second particle correspond to the same cache line, and the bit width information is sixteen units; the error scenario information is that when the cache line is read for the first particle at a first time, there are multiple bit errors in the burst information of the cache line, and when the cache line is read for the second particle at a second time, there is a single bit error in the burst information, and there are multiple target bit errors in 128-bit data contained in a continuous pre-read file of the second particle.

8. The memory device control method according to claim 1, characterized in that: The memory device is loaded on a server, the server is configured with a basic input and output system, the memory device has a corresponding memory controller, and the method further includes: In response to monitoring error information of the memory device, the memory controller is used to perform a patrol operation on the memory device, and the basic input and output system is triggered to perform a system management interrupt operation.

9. The memory device control method according to claim 8, characterized in that: The step of obtaining sideband error correction information comprises: The basic input and output system is used to obtain sideband error correction information.

10. The memory device control method according to claim 9, characterized in that: The step of obtaining error correction information on the particle comprises: The basic input and output system is used to obtain error correction information on the particle.

11. The memory device control method according to claim 8, characterized in that: The method is applied to a misdetection and correction procedure and also includes: When the position information does not match the error scene information, the error checking and correction program is exited using the basic input and output system.

12. The memory device control method according to claim 8, characterized in that: The server is configured with an operating system, and the step of performing an isolation operation on the memory device comprises: Using the basic input and output system to generate power management standard event information for the memory device; The basic input and output system is used to send the power management standard event information to the operating system to control the operating system to execute a system control interrupt on the memory device.

13. The memory device control method according to claim 8, characterized in that: Also includes: When the location information matches the error scenario information, a repair operation is performed on the memory device.

14. The memory device control method according to claim 13, characterized in that: The step of performing a repair operation on the memory device comprises: An adaptive dual-device data correction mechanism is used to perform a repair operation on the memory device.

15. The memory device control method according to claim 13, characterized in that: The step of performing a repair operation on the memory device comprises: A post-packaging repair mechanism is used to perform a repair operation on the memory device.

16. The memory device control method according to claim 13, characterized in that: The step of performing a repair operation on the memory device comprises: A partial cache line spare mechanism is used to perform a repair operation on the memory device.

17. The memory device control method according to claim 12, characterized in that: Also includes: The operating system is used to call a platform error interface to generate offline page information for the memory device.

18. The method according to claim 1, characterized in that The error scenario information is the number of bit errors in burst information occurring in the same cache line for different target particles at different times.

19. A memory device control device, characterized in that: include: The sideband error correction information acquisition module is used to respond to the error information of the memory device monitored, obtain the sideband Error correction information; An on-particle error correction information acquisition module, used to acquire on-particle error correction information; A bit width information determination module, used to determine the bit width information for the memory device and error scenario information under the bit width information; A location information determination module, configured to determine location information of a cache line of the memory device for the error information through the sideband error correction information and the on-chip error correction information; An isolation operation execution module is used to perform an isolation operation on the memory device when the location information matches the error scenario information.

20. A server, characterized in that: The server is loaded with a memory device, and is used to obtain sideband error correction information in response to error information of the memory device monitored; and obtain error correction information on the particle; Determine bit width information for the memory device and error scenario information under the bit width information; Determine location information of a cache line of the memory device for the error information by using the sideband error correction information and the on-chip error correction information; When the location information matches the error scenario information, an isolation operation is performed on the memory device.

21. An electronic device, characterized in that: It includes a processor, a communication interface, a memory and a communication bus, wherein the processor, the communication interface and the memory communicate with each other through the communication bus; The memory is used to store computer programs; The processor is used to implement the method according to any one of claims 1 to 18 when executing the program stored in the memory.

22. A computer non-volatile storage medium having instructions stored thereon, which when executed by one or more processors, causes the processors to perform the method according to any one of claims 1 to 18.

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