High-voltage light-emitting diode chip and preparation method therefor

Abstract

Provided are a high-voltage light-emitting diode chip and a preparation method therefor, relating to the field of electronic devices. The high-voltage light-emitting diode chip comprises: a substrate and a plurality of sub-chips, wherein the plurality of sub-chips are sequentially connected in series on the substrate in a first direction, each sub-chip comprises two P-N junctions, the two P-N junctions are arranged side by side in a second direction, and the second direction is perpendicular to the first direction; the sub-chip at one end of the first direction is provided with a P-type pad, each of the sub-chips has an isolation trench extended in the first direction so as to isolate two P-N junctions in the same sub-chip, and the isolation trenches in the sub-chips are located on a same straight line and are all located between the P-type pad and an N-type pad. Thus, the current spreading uniformity of the high-voltage light-emitting diode chip can be improved.

Description

High-voltage light-emitting diode chip and preparation method thereof

[0001] This application claims priority to Chinese patent application No. 202311112503.3, filed on August 31, 2023, entitled “High-voltage light-emitting diode chip and its preparation method”, the entire contents of which are incorporated herein by reference. Technical Field

[0002] The present disclosure belongs to the field of electronic devices, and in particular relates to a high-voltage light-emitting diode chip and a preparation method thereof. Background Art

[0003] High voltage (HV) light emitting diode chips are an important component of lighting equipment.

[0004] In the related art, a high-voltage light-emitting diode chip generally includes a plurality of sub-chips connected in series through an ISO bridge process, and each sub-chip includes a PN junction.

[0005] However, as the size of the sub-chip increases, the current spreading uniformity of the high-voltage light-emitting diode chip becomes poor, which affects the performance of the high-voltage light-emitting diode chip.

[0006] Summary of the Invention

[0007] Embodiments of the present disclosure provide a high-voltage light-emitting diode chip and a method for manufacturing the same.

[0008] In a first aspect, an embodiment of the present disclosure provides a high-voltage light-emitting diode chip, comprising: a substrate and a plurality of sub-chips, wherein the plurality of sub-chips are connected in series in sequence along a first direction on the substrate, the sub-chip comprising two PN junctions, the two PN junctions being arranged side by side along a second direction, and the second direction being perpendicular to the first direction; the sub-chip located at one end of the first direction has a P-type pad, and the sub-chip located at the other end of the first direction has an N-type pad, each of the sub-chips having an isolation trench, the isolation trench extending along the first direction to isolate the two PN junctions in the same sub-chip, the isolation trenches in each of the sub-chips being located on the same straight line, and being located between the P-type pad and the N-type pad.

[0009] Optionally, the two PN junctions in the same sub-chip are arranged symmetrically with respect to the isolation trench.

[0010] Optionally, the isolation trench extends from a side of the sub-chip away from the substrate to the N-type semiconductor layer.

[0011] Optionally, a separation trench is provided between two adjacent sub-chips, and the separation trench extends along the second direction; each of the separation trenches is connected to ends of the isolation trenches in two adjacent sub-chips.

[0012] Optionally, the separation trench extends from a side of the sub-chip away from the substrate to the substrate.

[0013] Optionally, the sub-chip includes an N-type semiconductor layer, a light-emitting layer and a P-type semiconductor layer stacked in sequence on the substrate; the sub-chips except the sub-chip with the P-type pad have a P-type electrode line, and the P-type electrode line is connected to the P-type semiconductor layer; the sub-chips except the sub-chip with the N-type pad have an N-type electrode line, and the N-type electrode line is connected to the N-type semiconductor layer; the N-type electrode line of one sub-chip is connected to the P-type electrode line of another adjacent sub-chip; the P-type pad is connected to the P-type semiconductor layer, and the N-type pad is connected to the N-type semiconductor layer.

[0014] Optionally, the P-type electrode line includes a trunk, a first branch and a second branch, one end of the trunk is connected to one end of the N-type electrode line, and the other end of the trunk is respectively connected to one end of the first branch and one end of the second branch, and the first branch and the second branch are symmetrically arranged on both sides of the trunk in the second direction.

[0015] Optionally, the N-type electrode line extends along the first direction.

[0016] Optionally, all the sub-chips except the sub-chip with the P-type pad have two P-type electrode lines, and the two P-type electrode lines are symmetrically arranged on both sides of the straight line where the separation groove is located; all the sub-chips except the sub-chip with the N-type pad have two N-type electrode lines, and the two N-type electrode lines are symmetrically arranged on both sides of the straight line where the isolation groove is located.

[0017] Optionally, the P-type pad includes a block-shaped P-type pad body and two strip-shaped P-type pad branches, the P-type pad body is respectively connected to one end of the two strip-shaped P-type pad branches, and the two strip-shaped P-type pad branches are symmetrically arranged on both sides of the P-type pad body in the second direction.

[0018] Optionally, the P-type pad is a symmetrical structure, and the symmetry axis of the P-type pad coincides with the straight line where the isolation trench is located.

[0019] Optionally, the N-type pad includes a block-shaped N-type pad body and two strip-shaped N-type pad branches, the N-type pad body is respectively connected to one end of the two strip-shaped N-type pad branches, and the two strip-shaped N-type pad branches are symmetrically arranged on both sides of the N-type pad body in the second direction.

[0020] Optionally, the N-type pad is a symmetrical structure, and the symmetry axis of the N-type pad coincides with a straight line on which the isolation trench is located.

[0021] Optionally, the sub-chip further includes a buffer layer; the buffer layer is grown between the substrate and the N-type semiconductor layer.

[0022] Optionally, the sub-chip further includes a transparent conductive layer, and the transparent conductive layer is located on a side of the P-type conductive layer facing away from the substrate.

[0023] In a second aspect, an embodiment of the present disclosure provides a method for preparing a high-voltage light-emitting diode chip, the method comprising:

[0024] providing a substrate;

[0025] forming a plurality of sub-chips on the substrate, the plurality of sub-chips being sequentially connected in series along a first direction on the substrate, each of the sub-chips comprising two PN junctions, the two PN junctions being arranged side by side along a second direction, the second direction being perpendicular to the first direction;

[0026] Among them, the sub-chip located at one end of the first direction has a P-type pad, and the sub-chip located at the other end of the first direction has an N-type pad. Each of the sub-chips has an isolation trench, and the isolation trench extends along the first direction to isolate the two PN junctions in the same sub-chip. The isolation trenches in each of the sub-chips are located on the same straight line and are all located between the P-type pad and the N-type pad.

[0027] Optionally, forming a plurality of sub-chips on the substrate includes:

[0028] forming an epitaxial layer on the substrate, wherein the epitaxial layer comprises an N-type semiconductor layer, a light-emitting layer, and a P-type semiconductor layer stacked sequentially on the substrate;

[0029] An isolation trench is formed on the epitaxial layer, wherein the isolation trench extends along the first direction;

[0030] A plurality of separation trenches are opened on the epitaxial layer. The plurality of separation trenches are sequentially spaced apart along the first direction, and each of the separation trenches extends along the second direction.

[0031] Optionally, forming an isolation trench on the epitaxial layer includes:

[0032] The P-type semiconductor layer and the light-emitting layer are etched by a dry etching process until the isolation trench extending to the N-type semiconductor layer is formed.

[0033] Optionally, a plurality of separation trenches are opened on the epitaxial layer, including:

[0034] The P-type semiconductor layer, the light-emitting layer and the N-type semiconductor layer are etched by a dry etching process until the separation trench extending to the substrate is formed. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0036] FIG1 is a top view of a high-voltage light-emitting diode chip provided in an embodiment of the present disclosure;

[0037] FIG2 is a cross-sectional view of a high-voltage light-emitting diode chip provided in an embodiment of the present disclosure taken along the AA direction;

[0038] FIG3 is a flow chart of a method for preparing a high-voltage light-emitting diode chip according to an embodiment of the present disclosure;

[0039] FIG4 is a flow chart of another method for preparing a high-voltage light-emitting diode chip provided in an embodiment of the present disclosure.

[0040] The symbols in the figure mean the following:

[0041] 10. Substrate;

[0042] 20. Sub-chip;

[0043] 210, PN junction;

[0044] 221, P-type pad; 222, N-type pad;

[0045] 221a, P-type pad main body; 221b, P-type pad branch;

[0046] 222a, N-type pad body; 222b, N-type pad branch;

[0047] 231, N-type semiconductor layer; 232, light-emitting layer; 233, P-type semiconductor layer; 234, buffer layer; 235, AlGaN layer; 236, transparent conductive layer;

[0048] 241, P-type electrode line; 242, N-type electrode line;

[0049] 241a, main trunk; 241b, first branch; 241c, second branch;

[0050] 30. Isolation trench;

[0051] 40. Separating grooves. DETAILED DESCRIPTION

[0052] In order to make the objectives, technical solutions and advantages of the present disclosure more clear, the embodiments of the present disclosure will be further described in detail below with reference to the accompanying drawings.

[0053] An embodiment of the present disclosure provides a high-voltage light-emitting diode chip, and FIG1 is a top view of the high-voltage light-emitting diode chip. Referring to FIG1 , the high-voltage light-emitting diode chip includes a substrate 10 (see FIG2 ) and a plurality of sub-chips 20, wherein the plurality of sub-chips 20 are sequentially connected in series along a first direction on the substrate 10. Each sub-chip 20 includes two PN junctions 210, and the two PN junctions 210 are arranged side by side along a second direction, and the second direction is perpendicular to the first direction. The sub-chip 20 located at one end of the first direction has a P-type pad 221, and the sub-chip 20 located at the other end of the first direction has an N-type pad 222. For example, in FIG1 , the top sub-chip 20 has a P-type pad 221, and the bottom sub-chip 20 has an N-type pad 222. In other embodiments, the bottom sub-chip 20 has a P-type pad 221, and the top sub-chip 20 has an N-type pad 222.

[0054] Each sub-chip 20 has an isolation trench 30 extending along a first direction to isolate the two PN junctions 210 in the same sub-chip 20. The isolation trenches 30 in each sub-chip 20 are located on the same straight line and are located between the P-type pad 221 and the N-type pad 222.

[0055] In FIG1 , the direction indicated by the solid arrow is the first direction, the direction indicated by the dotted arrow is the second direction, and the direction indicated by the hollow arrow is the current direction.

[0056] After voltage is applied to the N-type pad 222 and the P-type pad 221, current flows sequentially through each sub-chip 20 along the first direction, from the P-type pad 221 to the N-type pad 222. Because each sub-chip 20 includes two PN junctions 210, current within each sub-chip 20 tends to flow along the second direction toward the center of the sub-chip 20. Because there is an isolation trench 30 between the P-type pad 221 and the N-type pad 222, the isolation trench 30 isolates the two PN junctions 210 of the same sub-chip 20, effectively limiting current flow in the second direction and promoting current flow in the first direction. This improves the current diffusion capability of each sub-chip 20 and, in turn, enhances the current diffusion uniformity of the high-voltage LED chip.

[0057] In this embodiment, the two PN junctions 210 of the same sub-chip 20 are arranged symmetrically with respect to the isolation trench 30 .

[0058] In the above implementation, the positional relationship between the PN junction 210 and the isolation trench 30 is arranged in this way, which can ensure that the isolation trench 30 is located in the middle of the two PN junctions 210, so that the current on both sides can be isolated by the isolation trench 30, avoiding the current of the PN junctions 210 on both sides from flowing to the middle of the sub-chip 20, promoting the current to flow along the first direction, and making the light emission distribution of each sub-chip 20 more uniform.

[0059] In this embodiment, one end of the isolation trench 30 is as close as possible to the P-type pad 221, and the other end of the isolation trench 30 is as close as possible to the N-type pad 222. In this way, current overflow from the gap of the isolation trench 30 can be avoided as much as possible, further ensuring the isolation effect of the isolation trench 30.

[0060] That is, in this embodiment, the current will be divided starting from the P-type pad 221 , and the current will be transferred equivalently, so that the light emission distribution of each sub-chip 20 is more uniform.

[0061] Optionally, the P-type pad 221 includes a block-shaped P-type pad body 221a and two strip-shaped P-type pad branches 221b. The P-type pad body 221a is connected to one end of each of the two strip-shaped P-type pad branches 221b, and the two strip-shaped P-type pad branches 221b are symmetrically arranged on both sides of the P-type pad body 221a in the second direction. By symmetrically arranging the two strip-shaped P-type pad branches 221b on both sides of the P-type pad body 221a, current can be quickly directed to both sides of the sub-chip, thereby improving current expansion capability.

[0062] Exemplarily, the P-type pad 221 is a symmetrical structure, and the axis of symmetry of the P-type pad 221 coincides with the straight line where the isolation groove 30 is located. In this way, the current can be expanded symmetrically in each sub-chip 30 about the straight line where the isolation groove 30 is located, which is conducive to further improving the uniformity of current expansion.

[0063] Optionally, the N-type pad 222 includes a block-shaped N-type pad body 222a and two strip-shaped N-type pad branches 222b. The N-type pad body 222a is connected to one end of each of the two strip-shaped N-type pad branches 222b, and the two strip-shaped N-type pad branches 222b are symmetrically arranged on both sides of the N-type pad body 222a in the second direction. By symmetrically arranging the two strip-shaped N-type pad branches 222b on both sides of the N-type pad body 222a, current can be quickly directed to both sides of the sub-chip, thereby improving current expansion capability.

[0064] For example, the N-type pad 222 is a symmetrical structure, and the axis of symmetry of the N-type pad 222 coincides with the line where the isolation trench 30 is located. In this way, the current can be symmetrically expanded in each sub-chip 30 about the line where the isolation trench 30 is located, which is conducive to further improving the uniformity of current expansion.

[0065] Optionally, the shapes of the P-type pad body 221a and the N-type pad body 222a can be different to facilitate distinguishing the P-type pad 221 from the N-type pad 222. For example, as shown in FIG1 , the P-type pad body 221a is circular, and the N-type pad body 222a is composed of a rectangle and a semicircle.

[0066] It should be noted that the embodiment of the present disclosure does not limit the shapes of the P-type pad body 221a and the N-type pad body 222a, and they can be any other suitable shapes, such as rectangle, triangle, ellipse or irregular shapes.

[0067] 1 , in this embodiment, a separation trench 40 is provided between two adjacent sub-chips 20 , and the separation trench 40 extends along the second direction. Each separation trench 40 is connected to the ends of the isolation trenches 30 in the two adjacent sub-chips 20 .

[0068] In the above implementation, the separation trench 40 is formed during the ISO lithography process of bridging the sub-chips 20. Multiple sub-chips 20, or relatively independent light-emitting units, can be formed through the separation trench 40. Connecting the separation trench 40 to the end of the isolation trench 30 in the adjacent sub-chip 20 ensures that the isolation trench 30 completely isolates the two PN junctions 210 of the corresponding sub-chip 20, further ensuring the isolation effect of the isolation trench 30.

[0069] For example, one end of the isolation trench 30 on the sub-chip 20 having an N-type pad 222 is close to the N-type pad 222, and the other end is connected to the separation trench 40. One end of the isolation trench 30 on the sub-chip 20 having a P-type pad 221 is close to the P-type pad 221, and the other end is connected to the separation trench 40. Both ends of the isolation trench 30 on other sub-chips 20 (referring to sub-chips 20 without N-type pads 222 or P-type pads 221) are connected to the separation trench 40.

[0070] FIG2 is a cross-sectional view of the high-voltage LED chip along the AA direction. It is worth noting that FIG1 shows four sub-chips 20. However, since the sub-chips 20 located in the middle have the same structure in the first direction, they are omitted in FIG2 , and only the two sub-chips 20 located at the ends are shown. Furthermore, the number of sub-chips 20 in FIG1 is merely an example. In other embodiments, the high-voltage LED chip may include other numbers of sub-chips, for example, three or five.

[0071] 2 , in this embodiment, the sub-chip 20 includes an N-type semiconductor layer 231, a light-emitting layer 232, and a P-type semiconductor layer 233, which are sequentially stacked on the substrate 10. All sub-chips 20, except for the sub-chip 20 with a P-type pad 221, have a P-type electrode line 241 connected to the P-type semiconductor layer 233. All sub-chips 20, except for the sub-chip 20 with an N-type pad 222, have an N-type electrode line 242 connected to the N-type semiconductor layer 231. The N-type electrode line 242 of one sub-chip 20 is connected to the P-type electrode line 241 of another adjacent sub-chip 20. The P-type pad 221 is connected to the P-type semiconductor layer 233, and the N-type pad 222 is connected to the N-type semiconductor layer 231.

[0072] In the above implementation, the N-type semiconductor layer 231, the light-emitting layer 232, and the P-type semiconductor layer 233 are stacked in sequence to form an epitaxial layer. The P-type electrode line 241 is connected to the P-type semiconductor layer 233, and the N-type electrode line 242 is connected to the N-type semiconductor layer 231. By connecting the P-type electrode line 241 and the N-type electrode line 242, two adjacent sub-chips 20 can be connected in series.

[0073] The N-type semiconductor layer 231 provides an electron supply region, the P-type semiconductor layer 233 provides a hole supply region, and the light-emitting layer 232 is a functional region for generating photoelectrons. When current flows through, holes in the P-type semiconductor layer 233 and electrons in the N-type semiconductor layer 231 migrate toward the light-emitting layer 232, where they recombine and emit light, effectively energizing the sub-chip 20.

[0074] Optionally, the P-type electrode line 241 includes a trunk 241a, a first branch 241b, and a second branch 241c. One end of the trunk 241a is connected to one end of the N-type electrode line 242, and the other end of the trunk 241a is connected to one end of the first branch 241b and one end of the second branch 241c, respectively. The first branch 241b and the second branch 241c are symmetrically arranged on both sides of the trunk 241a in the second direction. The arrangement of the first branch 241b and the second branch 241c facilitates the lateral expansion of the current in the sub-chip 20 (i.e., the expansion in the second direction).

[0075] Exemplarily, the first branch 241b and the second branch 241c each form an obtuse angle with the main stem 241a. That is, for each P-type electrode line, in the first direction, the distance between the end of the first branch 241b connected to the main stem 241a and the P-type pad 221 is smaller than the distance between the end of the first branch 241b not connected to the main stem 241a and the P-type pad 221. Similarly, in the first direction, the distance between the end of the second branch 241c connected to the main stem 241a and the P-type pad 221 is smaller than the distance between the end of the second branch 241c not connected to the main stem 241a and the P-type pad 221.

[0076] Optionally, the N-type electrode line 242 extends along the first direction.

[0077] In the embodiment of the present disclosure, all sub-chips 20 except the sub-chip 20 with the P-type pad 221 have two P-type electrode lines 241, and the two P-type electrode lines 241 are symmetrically arranged on both sides of the straight line where the separation groove 40 is located. That is, in the sub-chips 20 except the sub-chip 20 with the P-type pad 221, each PN junction 210 is connected to a P-type electrode line 241. All sub-chips 20 except the sub-chip 20 with the N-type pad 222 have two N-type electrode lines 242, and the two N-type electrode lines 242 are symmetrically arranged on both sides of the straight line where the isolation groove 30 is located. That is, in the sub-chips 20 except the sub-chip 20 with the N-type pad 222, each PN junction 210 is connected to an N-type electrode line 242. In this way, the current in each PN junction 210 can be promoted to flow in the first direction.

[0078] For example, the N-type electrode line 242 is located in the middle of the PN junction 210 in the first direction, and the trunk 241a is located in the middle of the PN junction 210 in the first direction. This facilitates uniform current expansion in each PN junction.

[0079] Exemplarily, the N-type semiconductor layer 231 is an N-type GaN layer, the P-type semiconductor layer 233 is a P-type GaN layer, and the light-emitting layer 232 is a multiple quantum well (MQW) layer. The material of the MQW layer can be selected based on the light-emitting color of the high-voltage light-emitting diode, and this disclosure does not limit this. For example, the light-emitting layer 232 includes an InGaN well layer and a GaN barrier layer that are periodically stacked in sequence.

[0080] The periodically stacked InGaN well layers and GaN barrier layers enhance carrier confinement, improving radiative recombination efficiency. Furthermore, the In-rich quantum dots formed in the light-emitting layer 232 due to In-rich growth conditions or uneven In composition also effectively confine carriers, making it difficult for carriers to be captured by non-radiative recombination centers, thereby improving radiative recombination efficiency.

[0081] Illustratively, the P-type electrode line 241 and the N-type electrode line 242 include a titanium layer and an aluminum layer stacked in sequence, or may include a chromium layer, a titanium layer and an aluminum layer stacked in sequence, or may include a chromium layer and an aluminum layer stacked in sequence. The present disclosure does not limit the composition of the P-type electrode line 241 and the N-type electrode line 242.

[0082] In the embodiment of the present disclosure, the isolation trench 30 extends from a side of the sub-chip 20 away from the substrate 10 to the N-type semiconductor layer 231 .

[0083] In the above implementation, the isolation trench 30 completely cuts off the P-type semiconductor layer 233 and the light-emitting layer 232 of the sub-chip 20. In this way, the isolation trench 30 can completely isolate the two PN junctions 210 of the corresponding sub-chip 20, further ensuring the isolation effect of the isolation trench 30.

[0084] Furthermore, in order to facilitate the connection of the N-type electrode line 242 , the isolation trench 30 also exposes a portion of the N-type semiconductor layer 231 .

[0085] In this embodiment, the separation trench 40 extends from a side of the sub-chip 20 away from the substrate 10 to the substrate 10 .

[0086] In the above implementation, the separation trench 40 completely separates the P-type semiconductor layer 233, light-emitting layer 232, and N-type semiconductor layer 231 of the sub-chip 20, completely isolating the epitaxial layers of two adjacent sub-chips 20, with the sub-chips 20 connected only by the P-type electrode lines 241 and the N-type electrode lines 242. This ensures the relative independence of each sub-chip 20, effectively ensuring the reliability of the high-voltage LED chip.

[0087] 2 , in this embodiment, the sub-chip 20 further includes a buffer layer 234 . The buffer layer 234 is grown on a side of the substrate 10 facing the N-type semiconductor layer 231 .

[0088] In the above implementation, the buffer layer 234 is provided on one side of the substrate 10 . The buffer layer 234 can effectively reduce the lattice mismatch problem between the substrate 10 and the N-type semiconductor layer 231 , thereby reducing the generation of dislocations and cracks.

[0089] Exemplarily, the buffer layer 234 is a U-type GaN layer.

[0090] In this embodiment, the sub-chip 20 further includes an AlGaN layer 235 . The AlGaN layer 235 is grown on a side of the buffer layer 234 facing away from the substrate 10 and is sandwiched between the N-type semiconductor layer 231 and the buffer layer 234 .

[0091] In the above implementation, the AlGaN layer 235 can further eliminate the lattice mismatch problem between the buffer layer 234 and the N-type semiconductor layer 231 , thereby reducing the generation of dislocations and cracks.

[0092] Optionally, the sub-chip 20 further includes a transparent conductive layer 236 , which is grown on a side of the P-type semiconductor layer 233 facing away from the substrate 10 .

[0093] Optionally, the transparent conductive layer 236 includes but is not limited to an indium tin oxide (ITO) layer or an indium zinc oxide (IZO) layer.

[0094] Optionally, the substrate 10 is any one of a Si substrate, an Al 2 O 3 substrate, a GaN substrate, an AlN substrate, a GaAs substrate, a diamond substrate, and a sapphire substrate.

[0095] FIG3 is a flow chart of a method for preparing a high-voltage light-emitting diode chip according to an embodiment of the present disclosure. Referring to FIG3 , in this embodiment, the preparation process is used to prepare the high-voltage light-emitting diode chip shown in FIG1 and FIG2 . The preparation method includes:

[0096] In step 301 , a substrate 10 is provided.

[0097] In step 302 , a plurality of sub-chips 20 are formed on a substrate 10 .

[0098] A plurality of sub-chips 20 are sequentially connected in series along a first direction on the substrate 10 . Each sub-chip 20 includes two PN junctions 210 . The two PN junctions 210 are arranged side by side along a second direction perpendicular to the first direction.

[0099] Among them, the sub-chip 20 located at one end of the first direction has a P-type pad 221, and the sub-chip 20 located at the other end of the first direction has an N-type pad 222. Each sub-chip 20 has an isolation trench 30, and the isolation trench 30 extends along the first direction to isolate the two PN junctions 210 in the same sub-chip 20. The isolation trenches 30 in each sub-chip 20 are located on the same straight line and are all located between the P-type pad 221 and the N-type pad 222.

[0100] FIG4 is a flow chart of another method for preparing a high-voltage light-emitting diode chip according to an embodiment of the present disclosure. Referring to FIG4 , the preparation process is used to prepare the high-voltage light-emitting diode chip shown in FIG1 and FIG2 . The preparation method includes:

[0101] In step 401 , a substrate 10 is provided.

[0102] In step 402 , an N-type semiconductor layer 231 , a light emitting layer 232 , and a P-type semiconductor layer 233 are sequentially grown on one side of the substrate 10 to form an epitaxial layer.

[0103] In step 403 , a dry etching process is used to etch the P-type semiconductor layer 233 and the light emitting layer 232 until an isolation trench 30 extending to the N-type semiconductor layer 231 is formed.

[0104] Through step 403 , an isolation trench can be opened on the epitaxial layer.

[0105] Exemplarily, step 403 includes the following steps:

[0106] First, a photoresist with a MESA partition pattern is formed on the P-type semiconductor layer 233 , where the MESA partition pattern corresponds to the isolation trench 30 .

[0107] Then, a dry etching process is used to etch the P-type semiconductor layer 233 and the light emitting layer 232 .

[0108] Finally, excess photoresist on the P-type semiconductor layer 233 is removed.

[0109] In step 404 , a dry etching process is used to etch the P-type semiconductor layer 233 , the light emitting layer 232 , and the N-type semiconductor layer 231 until a separation trench 40 extending to the substrate 10 is formed.

[0110] Through step 404 , separation trenches can be opened on the epitaxial layer.

[0111] Exemplarily, the process of step 404 is similar to that of step 403 and will not be described again here.

[0112] Through steps 402 to 404 , a plurality of sub-chips 20 can be formed on the substrate 10 .

[0113] The high-voltage light-emitting diode chip prepared by the preparation method provided by the embodiment of the present disclosure has an isolation trench 30 and a separation trench 40 provided on its epitaxial layer. The separation trench 40 separates the chip into multiple sub-chips 20, and the isolation trench 30 separates the chip into two groups of PN junctions 210.

[0114] Unless otherwise defined, the technical or scientific terms used herein shall have the ordinary meaning understood by persons of ordinary skill in the field to which the present disclosure belongs. The words “first”, “second”, “third” and similar terms used in the patent application specification and claims of the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, words such as “a” or “an” do not indicate a quantity limitation, but rather indicate the presence of at least one. Words such as “include” or “comprise” mean that the elements or objects appearing before “include” or “comprises” include the elements or objects listed after “include” or “comprises” and their equivalents, and do not exclude other elements or objects. Words such as “connect” or “connected” are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. “Up”, “down”, “left”, “right” and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0115] The above description is merely an optional embodiment of the present disclosure and is not intended to limit the present disclosure. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present disclosure shall be included in the scope of protection of the present disclosure.

Claims

1. A high voltage light emitting diode chip, comprising: A substrate (10) and a plurality of sub-chips (20), wherein the plurality of sub-chips (20) are sequentially connected in series along a first direction on the substrate (10), each of the sub-chips (20) comprises two PN junctions (210), and the two PN junctions (210) are arranged side by side along a second direction, wherein the second direction is perpendicular to the first direction; The sub-chip (20) located at one end of the first direction has a P-type pad (221), and the sub-chip (20) located at the other end of the first direction has an N-type pad (222). Each of the sub-chips (20) has an isolation groove (30), and the isolation groove (30) extends along the first direction to isolate two PN junctions (210) in the same sub-chip (20). The isolation grooves (30) in each of the sub-chips (20) are located on the same straight line and are located between the P-type pad (221) and the N-type pad (222).

2. The high-voltage light-emitting diode chip according to claim 1, wherein: The two PN junctions (210) in the same sub-chip (20) are arranged symmetrically with respect to the isolation trench (30).

3. The high-voltage light-emitting diode chip according to claim 1 or 2, wherein: The isolation trench (30) extends from a side of the sub-chip (20) away from the substrate (10) to the N-type semiconductor layer (231).

4. The high-voltage light-emitting diode chip according to any one of claims 1 to 3, wherein: A separation groove (40) is provided between two adjacent sub-chips (20), and the separation groove (40) extends along the second direction; Each of the separation grooves (40) is connected to the ends of the isolation grooves (30) in two adjacent sub-chips (20) of the separation groove.

5. The high-voltage light-emitting diode chip according to claim 4, wherein: The separation groove (40) extends from a side of the sub-chip (20) away from the substrate (10) to the substrate (10).

6. The high-voltage light-emitting diode chip according to any one of claims 1 to 5, wherein: The sub-chip (20) comprises an N-type semiconductor layer (231), a light-emitting layer (232) and a P-type semiconductor layer (233) which are sequentially stacked on the substrate (10); The sub-chips (20) other than the sub-chip (20) having the P-type pad (221) all have a P-type electrode line (241), the P-type electrode line (241) being connected to the P-type semiconductor layer (233); the sub-chips (20) other than the sub-chip (20) having the N-type pad (222) all have an N-type electrode line (242), the N-type electrode line (242) being connected to the N-type semiconductor layer (231); the N-type electrode line (242) of one sub-chip (20) is connected to the P-type electrode line (241) of another adjacent sub-chip (20); The P-type pad (221) is connected to the P-type semiconductor layer (233), and the N-type pad (222) is connected to the N-type semiconductor layer (231).

7. The high-voltage light-emitting diode chip according to claim 6, wherein: The P-type electrode line (241) includes a trunk (241a), a first branch (241b) and a second branch (241c), one end of the trunk (241a) is connected to one end of the N-type electrode line (242), the other end of the trunk (241a) is respectively connected to one end of the first branch (241b) and one end of the second branch (241c), and the first branch (241b) and the second branch (241c) are symmetrically arranged on both sides of the trunk (241a) in the second direction.

8. The high-voltage light-emitting diode chip according to claim 7, wherein: The N-type electrode line (242) extends along the first direction.

9. The high-voltage light-emitting diode chip according to any one of claims 6 to 8, wherein: The sub-chips (20) other than the sub-chip (20) having the P-type pad (221) all have two P-type electrode lines (241), and the two P-type electrode lines (241) are symmetrically arranged on both sides of the straight line where the separation groove (40) is located; The sub-chips (20) other than the sub-chip (20) having the N-type pad (222) all have two N-type electrode lines (242), and the two N-type electrode lines (242) are symmetrically arranged on both sides of the straight line where the isolation groove (30) is located.

10. The high-voltage light-emitting diode chip according to any one of claims 1 to 9, wherein: The P-type pad (221) includes a block-shaped P-type pad body (221a) and two strip-shaped P-type pad branches (221b), wherein the P-type pad body (221a) is respectively connected to one end of the two strip-shaped P-type pad branches (221b), and the two strip-shaped P-type pad branches (221b) are symmetrically arranged on both sides of the P-type pad body (221a) in the second direction.

11. The high-voltage light-emitting diode chip according to any one of claims 1 to 10, wherein: The P-type pad (221) is a symmetrical structure, and the symmetry axis of the P-type pad (221) coincides with the straight line where the isolation groove (30) is located.

12. The high-voltage light-emitting diode chip according to any one of claims 1 to 11, wherein: The N-type pad (222) comprises a block-shaped N-type pad body (222a) and two strip-shaped N-type pad branches (222b), wherein the N-type pad body (222a) is respectively connected to one end of the two strip-shaped N-type pad branches (222b), and the two strip-shaped N-type pad branches (222b) are symmetrically arranged on both sides of the N-type pad body (222a) in the second direction.

13. The high-voltage light-emitting diode chip according to any one of claims 1 to 12, wherein: The N-type pad (222) is a symmetrical structure, and the symmetry axis of the N-type pad (222) coincides with the straight line where the isolation groove (30) is located.

14. The high-voltage light-emitting diode chip according to any one of claims 6 to 9, wherein: The sub-chip (20) further includes a buffer layer (234); The buffer layer (234) is between the substrate (10) and the N-type semiconductor layer (231).

15. The high-voltage light-emitting diode chip according to any one of claims 6 to 9, wherein: The sub-chip (20) further comprises a transparent conductive layer (236), wherein the transparent conductive layer (236) is located on a side of the P-type conductive layer (233) that is away from the substrate (10).

16. A method for preparing a high voltage light emitting diode chip, comprising: Providing a substrate (10); A plurality of sub-chips (20) are formed on the substrate (10), the plurality of sub-chips (20) are sequentially connected in series along a first direction on the substrate (10), each of the sub-chips (20) comprises two PN junctions (210), the two PN junctions (210) are arranged side by side along a second direction, and the second direction is perpendicular to the first direction. Towards; The sub-chip (20) located at one end of the first direction has a P-type pad (221), and the sub-chip (20) located at the other end of the first direction has an N-type pad (222). Each of the sub-chips (20) has an isolation groove (30), and the isolation groove (30) extends along the first direction to isolate the two PN junctions (210) in the same sub-chip (20). The isolation grooves (30) in each of the sub-chips (20) are located on the same straight line and are located between the P-type pad (221) and the N-type pad (222).

17. The preparation method according to claim 16, wherein: The method of forming a plurality of sub-chips on the substrate (10) comprises: forming an epitaxial layer on the substrate, wherein the epitaxial layer comprises an N-type semiconductor layer (231), a light-emitting layer (232), and a P-type semiconductor layer (233) which are sequentially stacked on the substrate (10); An isolation trench (30) is formed on the epitaxial layer, wherein the isolation trench (30) extends along the first direction; A plurality of separation grooves (40) are provided on the epitaxial layer, the plurality of separation grooves (40) are sequentially arranged at intervals along the first direction, and each of the separation grooves (40) extends along the second direction.

18. The preparation method according to claim 17, wherein: The step of opening an isolation trench (30) on the epitaxial layer comprises: The P-type semiconductor layer (233) and the light-emitting layer (232) are etched using a dry etching process to form the isolation trench (30) extending to the N-type semiconductor layer (231).

19. The preparation method according to claim 17 or 18, wherein: The step of opening a plurality of separation grooves (40) on the epitaxial layer comprises: The P-type semiconductor layer (233), the light-emitting layer (232) and the N-type semiconductor layer (231) are etched using a dry etching process to form the separation groove (40) extending to the substrate (10).

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