Multi-layer chip packaging structure and preparation method therefor

Abstract

The present invention provides a multi-layer chip packaging structure and a preparation method therefor. The preparation method for the multi-layer chip packaging structure comprises: wrapping a plurality of first chips on a first carrier plate by means of a first plastic packaging layer; then forming first redistribution layers located on solder pads of the first chips and first metal bumps located on the first redistribution layers to obtain a first semiconductor intermediate structure, and cutting the first semiconductor intermediate structure to form a plurality of first intermediate substructures; and then wrapping the plurality of first intermediate substructures and a plurality of second chips on a second carrier plate by means of a second plastic packaging layer, and forming second redistribution layers located on the second chips and the first intermediate substructures. The preparation method for the multi-layer chip packaging structure of the present invention can reduce the packaging size; in addition, multi-layer chip packaging structures prepared by using the method have a small size, and more chips can be integrated in a packaging structure having a small size.

Description

Multi-layer chip packaging structure and preparation method thereof Technical Field

[0001] The present invention relates to the technical field of semiconductor packaging, and in particular to a multi-layer chip packaging structure and a preparation method thereof. Background Art

[0002] With the development of 5G mobile phones, more performance and features are required to be integrated into smaller and smaller spaces. Therefore, various chip integration packaging solutions such as SIP packaging (System in Package) and DSM packaging (Double Side Molding) are becoming more and more popular.

[0003] The current market demand for package size is getting smaller and smaller, and existing chip integrated packaging solutions are increasingly unable to meet the market demand for small size. Therefore, it is necessary to provide a new chip packaging structure preparation method to reduce the package size and obtain a small-sized package structure.

[0004] Summary of the Invention

[0005] The object of the present invention is to provide a method for preparing a multi-layer chip packaging structure to reduce the package size and integrate more chips in a smaller package structure.

[0006] In order to achieve the above-mentioned and other related objects, the present invention provides a method for preparing a multi-layer chip packaging structure, comprising the following steps:

[0007] A first carrier board and a plurality of first chips are provided, each of the first chips including a front side and a back side, and having a solder pad on its front side, and the front sides of the plurality of first chips are fixed toward the first carrier board; a first plastic encapsulation layer is formed to bury the plurality of first chips, and the first carrier board is removed to expose the solder pads of the first chips; a first redistribution layer is formed on the solder pads of the first chips, and a plurality of first metal bumps are formed on the surface of the first redistribution layer facing away from the first chips to obtain a first semiconductor intermediate structure, and the first semiconductor intermediate structure is cut to form a plurality of first intermediate substructures; a second carrier board and a plurality of second chips are provided, each of the second chips including a front side and a back side, and having a solder pad on its front side, and the front sides of the plurality of second chips and the first metal bumps of the plurality of first intermediate substructures are fixed toward the second carrier board; a second plastic encapsulation layer is formed to bury the plurality of second chips and the first intermediate substructures, and the second carrier board is removed to expose the solder pads of the second chips and the surface of the first metal bumps facing away from the first chip; a second redistribution layer is formed on the surface of the solder pads and the first metal bumps of the second chips facing away from the first chip.

[0008] Optionally, in the method for preparing the multi-layer chip packaging structure, the second chip is located between multiple first metal bumps of the first intermediate substructure, and the front surface of the second chip is coplanar with the surface of the first metal bumps facing away from the first chip.

[0009] Optionally, in the preparation method of the multi-layer chip packaging structure, after the step of forming the second redistribution layer, the preparation method further includes: forming a first solder ball on the surface of the second redistribution layer facing away from the second chip to obtain a first packaging structure.

[0010] Optionally, in the method for preparing the multi-layer chip packaging structure, after the step of obtaining the first packaging structure, the method further comprises: cutting the first packaging structure to form a plurality of packaging sub-structures.

[0011] Optionally, in the preparation method of the multi-layer chip packaging structure, after the step of forming the second redistribution layer, the preparation method further includes: forming a plurality of second metal bumps on the surface of the second redistribution layer facing away from the second chip to obtain a second semiconductor intermediate structure.

[0012] Optionally, in the preparation method of the multi-layer chip packaging structure, after the step of obtaining the second semiconductor intermediate structure, the preparation method further includes: cutting the second semiconductor intermediate structure to form a plurality of second intermediate substructures; providing a third carrier and a plurality of third chips, each of the third chips including a front side and a back side, and having a solder pad on the front side, and the front sides of the plurality of third chips and the second metal bumps of the plurality of second intermediate substructures are fixed toward the third carrier; forming a third sealing layer to bury the plurality of third chips and the second intermediate substructures, and removing the third carrier to expose the surface of the solder pads and the second metal bumps of the third chip facing away from the second chip; forming a third redistribution layer on the surface of the solder pads and the second metal bumps of the third chip facing away from the second chip, and forming a second solder ball on the surface of the third redistribution layer facing away from the third chip to obtain a second packaging structure.

[0013] Optionally, in the preparation method of the multi-layer chip packaging structure, the third chip is located between the multiple second metal bumps of the second intermediate substructure, and the front surface of the third chip is coplanar with the surface of the second metal bumps facing away from the second chip.

[0014] Optionally, in the preparation method of the multi-layer chip packaging structure, after the step of obtaining the second semiconductor intermediate structure, the preparation method also includes: providing a plurality of fourth chips, each of the fourth chips including a front side and a back side, and having a solder pad on the front side, and the front sides of the plurality of fourth chips are fixed on the surface of the second redistribution layer facing away from the second chip; forming a fourth plastic packaging layer to embed the plurality of fourth chips and the second semiconductor intermediate structure; thinning the fourth plastic packaging layer until the surface of the second metal bump facing away from the second chip is exposed; and forming a third solder ball on the surface of the second metal bump facing away from the second chip to obtain a third packaging structure.

[0015] Optionally, in the method for preparing the multi-layer chip packaging structure, the fourth chip is located between the second metal bumps of the second semiconductor intermediate structure.

[0016] In order to achieve the above-mentioned objectives and other related objectives, the present invention also provides a multi-layer chip packaging structure prepared by the above-mentioned preparation method, comprising: a plurality of first intermediate substructures, and each of the first intermediate substructures comprises a first chip, a first plastic encapsulation layer, a first redistribution layer and a first metal bump, wherein the first chip comprises a front side and a back side, and its front side has a solder pad; the first plastic encapsulation layer encapsulates the first chip and exposes the front side of the first chip; the first redistribution layer is located on the solder pad on the front side of the first chip; the first metal bump is located on the surface of the first redistribution layer facing away from the first chip; a plurality of second chips, each of the second chips comprises a front side and a back side, and its front side has a solder pad; a second plastic encapsulation layer encapsulates the plurality of second chips and the first intermediate substructure, and exposes the surface of the first metal bump facing away from the first chip and the solder pad of the second chip; a second redistribution layer is located on the solder pad of the second chip and the surface of the first metal bump facing away from the first chip.

[0017] Optionally, in the multi-layer chip packaging structure, the multi-layer chip packaging structure further includes: a first solder ball located on a surface of the second redistribution layer facing away from the second chip.

[0018] Optionally, in the multi-layer chip packaging structure, the multi-layer chip packaging structure also includes: a plurality of second metal bumps, which are located on the surface of the second redistribution layer facing away from the second chip, and the plurality of second metal bumps, a plurality of first intermediate substructures, a plurality of second chips, a second plastic packaging layer and a second redistribution layer constitute a plurality of second intermediate substructures; a plurality of third chips, each of the third chips includes a front side and a back side, and a front side has a solder pad; a third plastic packaging layer, which embeds the plurality of third chips and the second intermediate substructures and exposes the solder pads of the third chips and the surface of the second metal bumps facing away from the second chip; a third redistribution layer, which is located on the surface of the solder pads of the third chip and the second metal bumps facing away from the second chip; and a second solder ball, which is located on the surface of the third redistribution layer facing away from the third chip.

[0019] Optionally, in the multi-layer chip packaging structure, the multi-layer chip packaging structure also includes: a second metal bump, located on the surface of the second redistribution layer facing away from the second chip; a plurality of fourth chips, each of the fourth chips including a front side and a back side, and having a solder pad on the front side, the front side of the fourth chip being located on the surface of the second redistribution layer facing away from the second chip; a fourth plastic encapsulation layer, embedding the fourth chip in the second redistribution layer and exposing the surface of the second metal bump facing away from the second chip; and a third solder ball, located on the surface of the second metal bump facing away from the second chip.

[0020] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:

[0021] In the method for preparing a multi-layer chip packaging structure provided by the present invention, multi-layer chip packaging is achieved through RDL (rewiring) technology: after the first layer of chips (first chip) completes the first plastic packaging, rewiring is performed and metal bumps are formed. Then, the chips are plastic-sealed again with the second layer of chips (second chip). After the second plastic packaging, rewiring is performed again to complete the double-layer packaging. This method can reduce the package size. The multi-layer chip packaging structure prepared by this method is small in size, allowing more chips to be integrated into the smaller package structure, resulting in higher material utilization, lower costs, and higher product reliability.

[0022] In addition, the present invention can also perform a third plastic packaging together with a third layer of multi-chips (third chip or fourth chip) after completing the double-layer packaging, and then perform rewiring again after the third plastic packaging to complete the three-layer packaging and obtain a three-layer chip packaging structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] FIG1 is a flow chart of a method for preparing a multi-layer chip packaging structure provided by the present invention;

[0024] FIG2 is a schematic diagram of a product structure corresponding to step S11 in a method for preparing a multi-layer chip packaging structure provided by the present invention;

[0025] 3 is a schematic diagram of the product structure after the first plastic sealing layer is formed in a method for preparing a multi-layer chip packaging structure provided by the present invention;

[0026] FIG4 is a schematic diagram of a product structure corresponding to step S12 in a method for preparing a multi-layer chip packaging structure provided by the present invention;

[0027] 5 is a schematic diagram of the product structure corresponding to the formation of the first redistribution layer in the method for preparing a multi-layer chip packaging structure provided by the present invention;

[0028] 6 is a schematic diagram of the corresponding product structure after forming the first metal bump in the method for preparing a multi-layer chip packaging structure provided by the present invention;

[0029] 7 is a schematic diagram of the product structure corresponding to step S13 in the method for preparing a multi-layer chip packaging structure provided by the present invention;

[0030] FIG8 is a schematic diagram of the product structure corresponding to step S14 in the method for preparing a multi-layer chip packaging structure provided by the present invention;

[0031] 9 is a schematic diagram of the corresponding product structure after the second plastic sealing layer is formed in the preparation method of a multi-layer chip packaging structure provided by the present invention;

[0032] 10 is a schematic diagram of the product structure corresponding to step S15 in the method for preparing a multi-layer chip packaging structure provided by the present invention;

[0033] 11 is a schematic diagram of the product structure corresponding to step S16 in the method for preparing a multi-layer chip packaging structure provided by the present invention;

[0034] 12 is a schematic diagram of the product structure corresponding to step S17 in the method for preparing a multi-layer chip packaging structure provided by the present invention;

[0035] 13 is a schematic diagram of the product structure corresponding to step S18 in the method for preparing a multi-layer chip packaging structure provided by the present invention;

[0036] 14 is a schematic diagram of the product structure corresponding to step S27 in another method for preparing a multi-layer chip packaging structure provided by the present invention;

[0037] 15 is a schematic diagram of the product structure corresponding to step S29 in another method for preparing a multi-layer chip packaging structure provided by the present invention;

[0038] 16 is a schematic diagram of the product structure corresponding to step S210 in another method for preparing a multi-layer chip packaging structure provided by the present invention;

[0039] 17 is a schematic diagram of the product structure corresponding to step S212 in another method for preparing a multi-layer chip packaging structure provided by the present invention;

[0040] FIG18 is a schematic diagram of the product structure corresponding to step S38 in another method for preparing a multi-layer chip packaging structure provided by the present invention;

[0041] FIG19 is a schematic diagram of the product structure corresponding to step S39 in another method for preparing a multi-layer chip packaging structure provided by the present invention;

[0042] FIG20 is a schematic diagram of a product structure corresponding to step S310 in another method for preparing a multi-layer chip packaging structure provided by the present invention;

[0043] FIG21 is a schematic diagram of a product structure corresponding to step S311 in another method for preparing a multi-layer chip packaging structure provided by the present invention. DETAILED DESCRIPTION

[0044] The following describes in further detail the multi-layer chip package structure and its manufacturing method proposed by the present invention, in conjunction with the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the drawings are highly simplified and not to exact scale, and are intended solely to facilitate and clarify the purpose of illustrating the embodiments of the present invention.

[0045] In order to reduce the size of the chip packaging structure product, improve product reliability, and achieve higher material utilization and lower cost, the present invention provides a method for preparing a multi-layer chip packaging structure. Referring to Figure 1, the method for preparing the multi-layer chip packaging structure may specifically include the following steps:

[0046] Step S11: providing a first carrier board and a plurality of first chips, wherein each of the first chips includes a front surface and a back surface, and the front surface of the first chip has a solder pad, and the front surfaces of the plurality of first chips are fixed toward the first carrier board;

[0047] Step S12: forming a first plastic packaging layer to embed the plurality of first chips, and removing the first carrier to expose the solder pads of the first chips;

[0048] Step S13: forming a first redistribution layer on the bonding pad of the first chip, and forming a plurality of first metal bumps on a surface of the first redistribution layer facing away from the first chip to obtain a first semiconductor intermediate structure, and cutting the first semiconductor intermediate structure to form a plurality of first intermediate substructures;

[0049] Step S14: providing a second carrier board and a plurality of second chips, wherein each second chip includes a front surface and a back surface, and the front surface of the second chip has a solder pad, and the front surfaces of the plurality of second chips and the first metal bumps of the plurality of first intermediate substructures are fixed toward the second carrier board;

[0050] Step S15: forming a second plastic packaging layer to embed the plurality of second chips and the first intermediate substructure, and removing the second carrier to expose the bonding pads of the second chips and the surface of the first metal bumps facing away from the first chip;

[0051] Step S16: forming a second redistribution layer on the bonding pads of the second chip and the surface of the first metal bumps facing away from the first chip.

[0052] Referring to Figure 2, step S11 is performed to mount the multiple first chips 101 on the first carrier 102. In the embodiment, the number of the first chips 101 can be two, three, all chips after one wafer is cut, or even all chips after multiple wafers are cut. This embodiment does not limit the number of first chips 101. The multiple first chips 101 can be the same chip or different chips, that is, the structure and function of each first chip 101 can be the same or different. Each of the first chips 101 includes a front side 101a and a back side 101b, and the front side 101a of each first chip 101 has a solder pad 1011, and the front side 101a can also have a protective layer covering the solder pad 1011 (not shown in the figure), and the material of the protective layer can be an insulating resin material. The first chip 101 can include at least one of a bare chip and a packaged chip, but is not limited thereto.

[0053] In this embodiment, the first carrier 102 is preferably a hard plate, which may include a glass plate, a ceramic plate and a metal plate, but is not limited thereto. The front side 101a of the first chip 101 is fixed toward the first carrier 102, and may be fixed by bonding, pressing or by adhesive or the like. For example, adhesive may be provided between the first carrier 102 and the first chip 101 to achieve fixation therebetween. Specifically, an entire surface of adhesive may be coated on the surface of the first carrier 102, and a plurality of first chips 101 may be placed on the adhesive. The adhesive may be made of an easily peelable material, such as a releasable double-sided tape, so as to peel the first carrier 102 and the first chip 101 apart.

[0054] 3 , step S12 is performed to plastic-encapsulate the plurality of first chips 101 to form a first plastic encapsulation layer 103. The first plastic encapsulation layer 103 is formed on the surface of the first carrier board 102 between each first chip 101 and to embed each first chip 101. The material of the first plastic encapsulation layer 103 can be epoxy resin, polyimide resin, benzocyclobutene resin, polybenzoxazole resin, polybutylene terephthalate, polycarbonate, polyethylene terephthalate, polyethylene, polypropylene, polyolefin, polyurethane, polyolefin, polyethersulfone, polyamide, polyurethane, ethylene-vinyl acetate copolymer, or polyvinyl alcohol.

[0055] Referring to Figure 4 , after forming the first plastic encapsulation layer 103, the first carrier 102 is removed, exposing the front surface 101a of the first chip 101 and the bottom surface 103a of the first plastic encapsulation layer 103. In this embodiment, the first carrier 102 can be removed using conventional removal methods such as laser lift-off, which will not be described in detail here. In this embodiment, the bottom surface 103a of the first plastic encapsulation layer 103 can be coplanar with the front surface 101a of the first chip 101.

[0056] Referring to FIG5 , step S13 is performed to form a first redistribution layer (RDL) 104. The first redistribution layer 104 is formed on the front side 101a of the first chip 101. Specifically, the first redistribution layer 104 is formed on the pad 1011 of the first chip 101. The first redistribution layer 104 may include a single redistribution line 1041 or multiple redistribution lines 1041, and the multiple redistribution lines 1041 may be electrically connected to each other. In this embodiment, a first dielectric layer 105 may be formed around the first redistribution layer 104. The first redistribution layer 104 can be formed by a layer-by-layer process and can be formed using thin film technology. In this embodiment, the first redistribution layer 104 includes embedded redistribution lines. For example, the redistribution line 1041 can be created by first forming a seed layer and then forming a metal (e.g., copper) pattern. Alternatively, the redistribution line 1041 can be formed by deposition (e.g., sputtering) and etching. The redistribution line 1041 is preferably made of a metal material, such as, but not limited to, copper, titanium, nickel, gold, combinations thereof, or alloys thereof. The metal pattern of the redistribution line 1041 is then embedded in an optionally patterned first dielectric layer 105. The first dielectric layer 105 can be made of any suitable material, such as an oxide or a polymer. The first redistribution layer 104 may further include a metal pad 1042. Specifically, the surface of the first redistribution layer 104 facing away from the first chip 101 includes the metal pad 1042.

[0057] Referring to FIG6 , after the step of forming the first redistribution layer 104, a first metal bump 106 is formed on the metal pad 1042 to obtain a first semiconductor intermediate structure. The material of the first metal bump 106 can include a metal material, such as copper, titanium, nickel, gold, and a combination or alloy thereof, but is not limited thereto. The first metal bump 106 can be formed using a suitable processing technology and can be formed from various suitable materials (e.g., copper) and layers. In this embodiment, the first metal bump 106 is formed by a plating technique, such as using a patterned photoresist layer to electroplate to define the column structure size, and then removing the patterned photoresist layer.

[0058] Referring to FIG. 7 , after obtaining the first semiconductor intermediate structure, the first semiconductor intermediate structure is cut to form a plurality of first intermediate substructures 11. In this embodiment, the cutting process preferably follows the scribe lines between adjacent first chips. In other embodiments, the cutting process may not follow the scribe lines between adjacent first chips. In this embodiment, the first semiconductor intermediate structure is cut prior to subsequent placement and encapsulation of the second layer of chips (second chips). This reduces the difficulty of filling the second encapsulation layer, making the process easier to implement and achieving a better encapsulation effect.

[0059] In this embodiment, each of the first intermediate substructures 11 includes a first chip 101, a first plastic encapsulation layer 103, a first redistribution layer 104, and first metal bumps 106. Furthermore, the first dielectric layer 105 may also be included. The number of first chips 101 and first metal bumps 106 included in each of the first intermediate substructures 11 is preferably multiple, but is not limited thereto.

[0060] Referring to Figure 8, step S14 is performed to provide a second carrier 202 and a plurality of second chips 201, and the plurality of second chips 201 and the plurality of first intermediate substructures 11 are mounted on the second carrier 202. In this embodiment, the number of the second chips 201 can be two, three, all the chips after a wafer is cut, or even all the chips after multiple wafers are cut. This embodiment does not limit the number of second chips 201. The plurality of second chips 201 can be the same type of chip or different chips, that is, the structure and function of each second chip 201 can be the same or different. In this embodiment, the second chip 201 and the first chip 101 can be the same type of chip or different chips, that is, the structure and function of the second chip 201 and the first chip 101 can be the same or different. Each second chip 201 includes a front side 201a and a back side 201b. The front side 201a of each second chip 201 has a bonding pad 2011. The front side 201a may also have a protective layer (not shown) covering the bonding pad 2011. The protective layer may be made of an insulating resin material. The second chip 201 may include at least one of a bare chip and a packaged chip, but is not limited thereto.

[0061] In this embodiment, the second carrier 202 is preferably a hard plate, which may include a glass plate, a ceramic plate, and a metal plate, but is not limited thereto. The front surface 201a of the second chip 201 and the surface of the first metal bumps 106 of the first intermediate substructure 11 facing away from the first chip 101 are fixed to the second carrier 202, and the fixation may be achieved by bonding, pressing, or by adhesive. For example, adhesive may be provided between the second carrier 202, the second chip 201, and the first metal bumps 106. Specifically, an entire surface of the second carrier 202 may be coated with adhesive, and a plurality of second chips 201 and a plurality of first metal bumps 106 of the first intermediate substructure 11 may be placed on the adhesive. The adhesive may be made of an easily peelable material, such as a releasable double-sided tape, so that the second carrier 202, the second chip 201, and the first intermediate substructure 11 can be peeled apart.

[0062] In this embodiment, the second chip 201 is located between the plurality of first metal bumps 106 of the first intermediate substructure 11. Specifically, one or more second chips 201 are mounted between the plurality of first metal bumps 106 of each first intermediate substructure 11, and the first metal bumps 106 are thicker than the thickness of the second chip 201. In this embodiment, the front surface of the second chip 201 is coplanar with the surface of the first metal bumps 106 facing away from the first chip.

[0063] Referring to FIG9 , step S15 is performed to plastic-encapsulate the plurality of second chips 201 and the first intermediate substructure 11 to form a second plastic encapsulation layer 203. A second plastic encapsulation layer 203 is formed on the surface of the second carrier 202 to embed each second chip 201 and the first intermediate substructure 11. The material of the second plastic encapsulation layer 203 can be epoxy resin, polyimide resin, benzocyclobutene resin, polybenzoxazole resin, polybutylene terephthalate, polycarbonate, polyethylene terephthalate, polyethylene, polypropylene, polyolefin, polyurethane, polyolefin, polyethersulfone, polyamide, polyurethane, ethylene-vinyl acetate copolymer, or polyvinyl alcohol. Because this embodiment first cuts the first semiconductor intermediate structure and then mounts and plastic encapsulates the second chip, filling the second plastic encapsulation layer can be easier to achieve, and the filling effect of the second plastic encapsulation layer is also better. Specifically, the filling effects between adjacent second chips 201 , between adjacent first intermediate substructures 11 , and between the second chip 201 and the first intermediate substructure 11 are all relatively good.

[0064] Referring to Figure 10 , after forming the second plastic encapsulation layer 203, the second carrier 202 is removed, exposing the front surface 201a of the second chip 201, the surface of the first metal bumps 106 facing away from the first chip 101, and the bottom surface 203a of the second plastic encapsulation layer 203. In this embodiment, the second carrier 202 can be removed using conventional removal methods such as laser lift-off, which will not be described in detail here. In this embodiment, the bottom surface 203a of the second plastic encapsulation layer 203 and the surface of the first metal bumps 106 facing away from the first chip 101 can be coplanar with the front surface 201a of the second chip 201.

[0065] Referring to FIG. 11 , step S16 is performed to form a second redistribution layer 204, thereby obtaining the package intermediate structure 12. The second redistribution layer 204 is formed on the second chip 201 and the first intermediate substructure 11. Specifically, the second redistribution layer 204 is formed on the bonding pads 2011 of the second chip 201 and on the surface of the first metal bumps 106 facing away from the first chip 101. The first chip 101 and the second chip 201 can be interconnected via the second redistribution layer 204, the first metal bumps 106, and the first redistribution layer 104.

[0066] The second redistribution layer 204 may include a single redistribution line or multiple redistribution lines, and the multiple redistribution lines may be electrically connected to each other. In this embodiment, a second dielectric layer 205 is formed around the second redistribution layer 204. The second redistribution layer 204 can be formed by a layer-by-layer process and can be formed using thin film technology. In this embodiment, the second redistribution layer 204 includes embedded redistribution lines. For example, the redistribution lines of the second redistribution layer 204 can be created by first forming a seed layer and then forming a metal (e.g., copper) pattern. Alternatively, the redistribution lines of the second redistribution layer 204 can be formed by deposition (e.g., sputtering) and etching. The material of the redistribution lines of the second redistribution layer 204 is preferably a metal material, for example, copper, titanium, nickel, gold, and combinations or alloys thereof, but not limited thereto. The metal pattern of the redistribution lines of the second redistribution layer 204 is then embedded in the optionally patterned second dielectric layer 205. The second dielectric layer 205 can be any suitable material, such as an oxide or a polymer. The second redistribution layer 204 may further include a metal pad. Specifically, a surface of the second redistribution layer 204 facing away from the second chip 201 includes a metal pad.

[0067] Referring to FIG. 12 , after forming the second redistribution layer 204, the manufacturing method further includes step S17: forming first solder balls 207 on the surface of the second redistribution layer 204 facing away from the second chip 201 (i.e., the metal pads of the second redistribution layer 204), thereby forming a first package structure. Specifically, in this embodiment, after forming the second redistribution layer 204, subsequent solder balls 207 are implanted. The material of the first solder balls 207 can be tin, but is not limited thereto. The first package structure of this embodiment is a double-layer chip package structure, preferably a double-layer multi-chip package structure, i.e., this embodiment packages a layer of multiple first chips 101 and a layer of multiple second chips 201 to form a double-layer multi-chip package structure.

[0068] Referring to FIG13 , after the step of forming the first solder balls 207, the preparation method further includes step S18: cutting the first packaging structure to form a plurality of packaging substructures. The packaging substructure in this step is a first packaging substructure. Each of the first packaging substructures in this embodiment may include a plurality of first chips 101, a plurality of second chips 201, a first plastic encapsulation layer 103, a second plastic encapsulation layer 203, a first redistribution layer 104, a second redistribution layer 204, a plurality of first metal bumps 106, and a plurality of first solder balls 207, and the number of the first chip 101 and the second chip 201 contained in each of the first packaging substructures is at least one, preferably a plurality.

[0069] The present invention also provides another method for preparing a multi-layer chip packaging structure, specifically a method for preparing a three-layer chip packaging structure. This method differs from the previous embodiment in that, after obtaining an intermediate packaging structure through steps S11 to S16, this embodiment packages the intermediate packaging structure together with a third chip to obtain a three-layer chip packaging structure.

[0070] The preparation method of the three-layer chip packaging structure may specifically include:

[0071] Step S21: providing a first carrier board and a plurality of first chips, wherein each of the first chips includes a front surface and a back surface, and the front surface of the first chip has a solder pad, and the front surfaces of the plurality of first chips are fixed toward the first carrier board;

[0072] Step S22: forming a first plastic packaging layer to embed the plurality of first chips, and removing the first carrier to expose the solder pads of the first chips;

[0073] Step S23: forming a first redistribution layer on the bonding pad of the first chip, and forming a plurality of first metal bumps on a surface of the first redistribution layer facing away from the first chip to obtain a first semiconductor intermediate structure, and cutting the first semiconductor intermediate structure to form a plurality of first intermediate substructures;

[0074] Step S24: providing a second carrier board and a plurality of second chips, wherein each second chip includes a front surface and a back surface, and the front surface of the second chip has a solder pad, and the front surfaces of the plurality of second chips and the first metal bumps of the plurality of first intermediate substructures are fixed toward the second carrier board;

[0075] Step S25: forming a second plastic packaging layer to embed the plurality of second chips and the first intermediate substructure, and removing the second carrier to expose the bonding pads of the second chips and the surface of the first metal bumps facing away from the first chip;

[0076] Step S26: forming a second redistribution layer on the bonding pads of the second chip and the surface of the first metal bumps facing away from the first chip;

[0077] Step S27: forming a plurality of second metal bumps on a surface of the second redistribution layer facing away from the second chip to obtain a second semiconductor intermediate structure;

[0078] Step S28: cutting the second semiconductor intermediate structure to form a plurality of second intermediate substructures;

[0079] Step S29: providing a third carrier board and a plurality of third chips, wherein each of the third chips includes a front surface and a back surface, and the front surface of the third chip has a solder pad, and the front surfaces of the third chips and the second metal bumps of the second intermediate substructures are fixed toward the third carrier board;

[0080] Step S210: forming a third sealing layer to embed the plurality of third chips and the second intermediate substructure, and removing the third carrier to expose the bonding pads and the second metal bumps of the third chips facing away from the second chip;

[0081] Step S211: forming a third redistribution layer on the surface of the bonding pads and the second metal bumps of the third chip facing away from the second chip;

[0082] Step S212 : forming second solder balls on a surface of the third redistribution layer facing away from the third chip to obtain a second package structure.

[0083] In this embodiment, the specific process of steps S21 to S26 can refer to steps S11 to S16 ( FIG. 1 to FIG. 11 ) to obtain the package intermediate structure 12 , which will not be described in detail here.

[0084] Referring to FIG. 14 , step S27 is performed to form a second metal bump 206 to obtain a second semiconductor intermediate structure. The material of the second metal bump 206 may include a metal material, such as copper, titanium, nickel, gold, and combinations or alloys thereof, but is not limited thereto. The second metal bump 206 may be formed using a suitable processing technique and may be formed from various suitable materials (e.g., copper) and layers. In this embodiment, the second metal bump 206 is formed by a plating technique, such as electroplating a patterned photoresist layer to define the pillar structure size, and then removing the patterned photoresist layer.

[0085] Step S28 is performed to cut the second semiconductor intermediate structure to form a plurality of second intermediate substructures 21. Each of the second intermediate substructures 21 in this embodiment may include a first chip 101, a second chip 201, a first plastic encapsulation layer 103, a second plastic encapsulation layer 203, a first redistribution layer 104, a second redistribution layer 204, a first metal bump 106, and a second metal bump 206. Furthermore, the first dielectric layer 105 and the second dielectric layer 205 may also be included. Preferably, the number of the first chip 101 and the second chip 201 included in each of the second intermediate substructures 21 is plural.

[0086] Referring to FIG. 15 , step S29 is performed to provide a third carrier 302 and a plurality of third chips 301, and the plurality of third chips 301 and the second intermediate substructure 21 are mounted on the third carrier 302. In this embodiment, the number of the third chips 301 can be two, three, all the chips after a wafer is cut, or even all the chips after multiple wafers are cut. This embodiment does not limit the number of third chips 301. The plurality of third chips 301 can be the same type of chip or different chips, that is, the structure and function of each third chip 301 can be the same or different. In this embodiment, the third chip 301 and the first chip 101 and the second chip 201 can be the same type of chip or different chips, that is, the structure and function of the third chip 301 can be the same or different from the first chip 101 and the second chip 201. Each of the third chips 301 includes a front side 301a and a back side 301b. The front side 301a of each third chip 301 has a bonding pad 3011. The front side 301a may also have a protective layer (not shown) covering the bonding pad 3011. The protective layer may be made of an insulating resin material. The third chip 301 may include at least one of a bare chip and a packaged chip, but is not limited thereto.

[0087] In this embodiment, the third carrier 302 is preferably a hard plate, which may include, but is not limited to, a glass plate, a ceramic plate, or a metal plate. The front surface 301a of the third chip 301 and the surface of the second metal bumps 206 facing away from the second chip 201 are mounted on the third carrier 302 and may be fixed by bonding, pressing, or adhesive. For example, adhesive may be provided between the third carrier 302 and the third chip 301 and the second metal bumps 206. Specifically, an entire surface of the third carrier 302 may be coated with adhesive, and multiple third chips 301 and multiple second metal bumps 206 of the second intermediate substructure 21 may be placed on the adhesive. The adhesive may be made of an easily removable material, such as releasable double-sided tape, to facilitate separation of the third carrier 302, the third chip 301, and the second intermediate substructure 21.

[0088] In this embodiment, the third chip 301 is located between the plurality of second metal bumps 206 of the second intermediate substructure 21. Specifically, one or more third chips 301 are mounted between the plurality of second metal bumps 206 of each second intermediate substructure 21, and the second metal bumps 206 are taller than the thickness of the third chip 301. In this embodiment, the front surface of the third chip 301 is coplanar with the surface of the second metal bumps 206 facing away from the second chip.

[0089] Referring to FIG. 16 , step S210 is performed to plastic-encapsulate the plurality of third chips 301 and the second intermediate substructure 21 to form a third plastic encapsulation layer 303. A third plastic encapsulation layer 303 is formed on the surface of the third carrier 302, encapsulating each of the third chips 301 and the second intermediate substructure 21. The material of the third plastic encapsulation layer 303 can be epoxy resin, polyimide resin, benzocyclobutene resin, polybenzoxazole resin, polybutylene terephthalate, polycarbonate, polyethylene terephthalate, polyethylene, polypropylene, polyolefin, polyurethane, polyolefin, polyethersulfone, polyamide, polyurethane, ethylene-vinyl acetate copolymer, or polyvinyl alcohol. Because this embodiment first cuts the second semiconductor intermediate structure before mounting and plastic encapsulating the third chip, filling the third plastic encapsulation layer 303 is easier to achieve, and the filling effect of the third plastic encapsulation layer 303 is also better. Specifically, the filling effects between adjacent third chips 301 , between adjacent second intermediate substructures 21 , and between the third chip 301 and the second intermediate substructure 21 are all relatively good.

[0090] Continuing with Figure 16 , after forming the third plastic encapsulation layer 303, the third carrier 302 is removed, exposing the front surface 301a of the third chip 301, the surface of the second metal bumps 206 facing away from the second chip 201, and the bottom surface 303a of the third plastic encapsulation layer 303. In this embodiment, the third carrier 302 can be removed using conventional removal methods such as laser lift-off, which will not be described in detail here. In this embodiment, the bottom surface 303a of the third plastic encapsulation layer 303 and the surface of the second metal bumps 206 facing away from the second chip 201 can be coplanar with the front surface 301a of the third chip 301.

[0091] Referring to FIG. 17 , step S211 is performed to form a third redistribution layer 304. The third redistribution layer 304 is formed on the third chip 301 and the second intermediate substructure 21. Specifically, the third redistribution layer 304 is formed on the bonding pad 3011 of the third chip 301 and on the surface of the second metal bump 206 facing away from the second chip 201. The third chip 301, the second chip 201, and the first chip 101 can be interconnected via the third redistribution layer 304, the second metal bump 206, the second redistribution layer 204, the first metal bump 106, and the first redistribution layer 104.

[0092] The third redistribution layer 304 may include a single redistribution line or multiple redistribution lines, and the multiple redistribution lines may be electrically connected to each other. In this embodiment, a third dielectric layer 305 is formed around the third redistribution layer 304. The third redistribution layer 304 can be formed by a layer-by-layer process and can be formed using thin film technology. In this embodiment, the third redistribution layer 304 includes embedded redistribution lines. For example, the redistribution lines of the third redistribution layer 304 can be created by first forming a seed layer and then forming a metal (e.g., copper) pattern. Alternatively, the redistribution lines of the third redistribution layer 304 can be formed by deposition (e.g., sputtering) and etching. The material of the redistribution lines of the third redistribution layer 304 is preferably a metal material, such as copper, titanium, nickel, gold, and combinations or alloys thereof, but is not limited thereto. The metal pattern of the redistribution lines of the third redistribution layer 304 is then embedded in the optionally patterned third dielectric layer 305. The third dielectric layer 305 can be any suitable material, such as an oxide or a polymer. The third redistribution layer 304 may further include a metal pad. Specifically, a surface of the third redistribution layer 304 facing away from the third chip 301 includes a metal pad.

[0093] Continuing with FIG. 17 , step S212 is performed: second solder balls 307 are formed on the surface of the third redistribution layer 304 facing away from the third chip 301 (i.e., the metal pads of the third redistribution layer 304) to form a second package structure. Specifically, in this embodiment, after forming the third redistribution layer 304, subsequent ball implantation is performed to form the second solder balls 307. The material of the second solder balls 307 can be tin, but is not limited thereto. The second package structure of this embodiment is a three-layer chip package structure, preferably a three-layer multi-chip package structure, i.e., this embodiment packages a layer of multiple first chips 101, a layer of multiple second chips 201, and a layer of multiple third chips 301 to form a three-layer multi-chip package structure.

[0094] After the step of forming the second solder balls 307 in this embodiment, the preparation method further includes step S211: cutting the second package structure to form a plurality of second package substructures. Each of the second package substructures in this embodiment includes a first chip 101, a second chip 201, a third chip 301, a first plastic encapsulation layer 103, a second plastic encapsulation layer 203, a third plastic encapsulation layer 303, a first redistribution layer 104, a second redistribution layer 204, a third redistribution layer 304, a first metal bump 106, a second metal bump 206, and a second solder ball 307. In addition, the first dielectric layer 105, the second dielectric layer 205, and the third dielectric layer 305 may also be included. The number of the first chip 101, the second chip 201, and the third chip 301 included in each second package substructure is preferably multiple.

[0095] In addition, the present invention can also cyclically execute steps S27 to S211 and then execute step S212 to obtain a four-layer chip packaging structure, a five-layer chip packaging structure, etc., which will not be described in detail here.

[0096] The present invention also provides another method for preparing a multi-layer chip packaging structure, specifically a method for preparing a three-layer flip-chip structure. This method differs from the previous embodiment in that, after obtaining a package intermediate structure through steps S11 to S16, this embodiment packages the package intermediate structure together with a fourth chip to obtain a three-layer flip-chip structure, wherein the fourth chip is a flip-chip.

[0097] The method for preparing the three-layer chip may specifically include:

[0098] Step S31: providing a first carrier board and a plurality of first chips, wherein each of the first chips includes a front surface and a back surface, and the front surface of the first chip has a solder pad, and the front surfaces of the plurality of first chips are fixed toward the first carrier board;

[0099] Step S32: forming a first plastic packaging layer to embed the plurality of first chips, and removing the first carrier to expose the solder pads of the first chips;

[0100] Step S33: forming a first redistribution layer on the bonding pad of the first chip, and forming a plurality of first metal bumps on a surface of the first redistribution layer facing away from the first chip to obtain a first semiconductor intermediate structure, and cutting the first semiconductor intermediate structure to form a plurality of first intermediate substructures;

[0101] Step S34: providing a second carrier board and a plurality of second chips, wherein each second chip includes a front surface and a back surface, and the front surface of the second chip has a solder pad, and the front surfaces of the plurality of second chips and the first metal bumps of the plurality of first intermediate substructures are fixed toward the second carrier board;

[0102] Step S35: forming a second plastic packaging layer to embed the plurality of second chips and the first intermediate substructure, and removing the second carrier to expose the bonding pads of the second chips and the surface of the first metal bumps facing away from the first chip;

[0103] Step S36: forming a second redistribution layer on the bonding pads of the second chip and the surface of the first metal bump facing away from the first chip;

[0104] Step S37: forming a plurality of second metal bumps on a surface of the second redistribution layer facing away from the second chip to obtain a second semiconductor intermediate structure;

[0105] Step S38: providing a plurality of fourth chips, each of the fourth chips including a front side and a back side, and having a bonding pad on the front side, and the front sides of the plurality of fourth chips being fixed on a surface of the second redistribution layer facing away from the second chip;

[0106] Step S39: forming a fourth plastic packaging layer to embed the plurality of fourth chips and the second semiconductor intermediate structure;

[0107] Step S310: thinning the fourth plastic packaging layer until the surface of the second metal bump facing away from the second chip is exposed;

[0108] Step S311 : forming a third solder ball on the surface of the second metal bump facing away from the second chip to obtain a third packaging structure.

[0109] In this embodiment, the specific process of steps S31 to S37 can refer to steps S21 to S27 to obtain the second semiconductor intermediate structure, which will not be described in detail here.

[0110] Referring to FIG. 18 , step S38 is performed to provide a plurality of fourth chips 401 and mount the plurality of fourth chips 401 on the second redistribution layer 204 of the second semiconductor intermediate structure. In this embodiment, the number of the fourth chips 401 can be two, three, all the chips after a wafer is diced, or even all the chips after multiple wafers are diced. This embodiment does not limit the number of fourth chips 401. The plurality of fourth chips 401 can be the same type of chip or different chips, that is, the structure and function of each fourth chip 401 can be the same or different. In this embodiment, the fourth chip 401 can be the same type of chip as the first chip 101, the second chip 201, and the third chip 301, or different chips, that is, the structure and function of the fourth chip 401 can be the same or different from the first chip 101, the second chip 201, and the third chip 301. Each of the fourth chips 401 includes a front surface 401a and a back surface 401b. The front surface 401a of each of the fourth chips 401 has a bonding pad (not shown in the figure), and the front surface 401a may also have a protective layer (not shown in the figure) covering the bonding pad. The protective layer may be made of an insulating resin material. The fourth chip 401 may include at least one of a bare chip and a packaged chip, but is not limited thereto.

[0111] In this embodiment, the fourth chip 401 can be mounted using surface mounting technology such as flip chip. One or more fourth chips 401 are mounted between the plurality of second metal bumps 206 of each second semiconductor intermediate structure, and the second metal bumps 206 are preferably higher than the thickness of the fourth chip 401.

[0112] In this embodiment, the front side 401a of the fourth chip 401 is attached to (e.g., surface-mounted on) the surface of the second redistribution layer 204 facing away from the second chip 201 using conductive bumps 402, such as solder bumps or stud bumps. The bonding pads of the fourth chip 401 are electrically connected to the conductive bumps 402, and the conductive bumps 402 can be formed of a material such as gold or solder. In other embodiments, the bonding pads of the fourth chip 401 can be directly connected to the surface of the second redistribution layer 204 facing away from the second chip 201. The fourth chip 401, the second chip 201, and the first chip 101 can be interconnected via the second redistribution layer 204, the first metal bumps 106, and the first redistribution layer 104.

[0113] Referring to FIG. 19 , step S39 is performed to form a fourth molding layer 403. The fourth molding layer 403 is formed on the second semiconductor intermediate structure to embed each fourth chip 401 and the second semiconductor intermediate structure. The material of the fourth molding layer 403 can be epoxy resin, polyimide resin, benzocyclobutene resin, polybenzoxazole resin, polybutylene terephthalate, polycarbonate, polyethylene terephthalate, polyethylene, polypropylene, polyolefin, polyurethane, polyolefin, polyethersulfone, polyamide, polyurethane, ethylene-vinyl acetate copolymer, or polyvinyl alcohol.

[0114] Referring to FIG. 20 , step S310 is performed to thin the fourth plastic encapsulation layer 403 until the surface of the second metal bumps 206 of the second semiconductor intermediate structure facing away from the second chip 201 is exposed. The fourth plastic encapsulation layer 403 is preferably thinned by a polishing process, such as, but not limited to, CMP (chemical mechanical polishing). After thinning, the surface of the fourth plastic encapsulation layer 403 facing away from the second chip 201 is coplanar with the surface of the second metal bumps 204 facing away from the second chip 201.

[0115] Referring to FIG. 21 , step S311 is performed to form a third solder ball 404 to obtain a third packaging structure. That is, in this embodiment, after thinning the fourth plastic encapsulation layer 403, subsequent ball planting is performed to form the third solder ball 404. The material of the third solder ball 404 can be tin, but is not limited thereto. The third packaging structure of this embodiment is a three-layer multi-chip flip-chip structure, that is, this embodiment packages a layer of multiple first chips 101, a layer of multiple second chips 201, and a layer of multiple fourth chips 401 to form a three-layer multi-chip flip-chip structure. After the step of forming the third solder ball 404, the preparation method of this embodiment further includes step S312: cutting the third packaging structure to form multiple third packaging sub-structures. Each of the third package substructures in this embodiment includes a first chip 101, a second chip 201, a fourth chip 401, a first plastic encapsulation layer 103, a second plastic encapsulation layer 203, a fourth plastic encapsulation layer 403, a first redistribution layer 104, a second redistribution layer 204, a first metal bump 106, a second metal bump 206, and a third solder ball 404. Furthermore, the first dielectric layer 105 and the second dielectric layer 205 may also be included. Preferably, the number of the first chip 101, the second chip 201, and the fourth chip 401 included in each of the third package substructures is plural.

[0116] In summary, the preparation method of the multi-layer chip packaging structure of the present invention can reduce the packaging size, and the multi-layer chip packaging structure prepared by this method is small in size, and more chips can be integrated in a smaller packaging structure, making the product more reliable, the material utilization rate higher, and the cost lower.

[0117] In addition, the present invention further provides a multi-layer chip packaging structure, which is formed by the above-mentioned steps S11 to S16. The multi-layer chip packaging structure may specifically include:

[0118] A plurality of first intermediate substructures 11, each of which includes a first chip 101, a first plastic encapsulation layer 103, a first redistribution layer 104, and first metal bumps 106, wherein the first chip 101 includes a front surface 101a and a back surface 101b, and has a solder pad 1011 on its front surface; the first plastic encapsulation layer 103 embeds the first chip 101 and exposes the front surface 101a of the first chip 101; the first redistribution layer 104 is located on the solder pad 1011 on the front surface of the first chip 101; and the first metal bumps 106 are located on a surface of the first redistribution layer 104 facing away from the first chip 101;

[0119] A plurality of second chips 201 , each of the second chips 201 including a front side 201 a and a back side 201 b , and having a bonding pad 2011 on the front side;

[0120] A second plastic encapsulation layer 203 , which embeds the plurality of second chips 201 and the first intermediate substructure 11 and exposes the surface of the first metal bump 106 facing away from the first chip 101 and the bonding pad 2011 of the second chip 201 ;

[0121] The second redistribution layer 204 is located on the bonding pads 2011 of the second chip and the surface of the first metal bumps 106 facing away from the first chip 101 .

[0122] In the multi-layer chip packaging structure, the front surface 201 a of the second chip 201 is coplanar with the surface of the first metal bump 106 facing away from the first chip 101 .

[0123] The multi-layer chip packaging structure may further include: a first dielectric layer 105 and a second dielectric layer 205, wherein the first dielectric layer 105 is located on the first plastic encapsulation layer 103 and covers the side of the first redistribution layer 104, exposing the surface of the first redistribution layer 104 facing away from the first chip 101; the second dielectric layer 205 is located on the second plastic encapsulation layer 203 and covers the side of the second redistribution layer 204, exposing the surface of the second redistribution layer 204 facing away from the second chip 201.

[0124] In one embodiment, the multi-layer chip package structure may further include: a first solder ball 207 located on a surface of the second redistribution layer 204 facing away from the second chip 201. This multi-layer chip package structure is a first package structure, specifically a double-layer chip package structure. In this embodiment, multiple first package substructures can be obtained by cutting the first package structure, which can be prepared by steps S11 to S18 described above.

[0125] In other embodiments, the multi-layer chip packaging structure may further include:

[0126] a plurality of second metal bumps 206 located on a surface of the second redistribution layer 204 facing away from the second chip 201; the plurality of second metal bumps 206, the plurality of first intermediate substructures 11, the plurality of second chips 201, the second plastic encapsulation layer 203, and the second redistribution layer 204 constitute a plurality of second intermediate substructures 21;

[0127] A plurality of third chips 301 , each of the third chips 301 including a front side 301 a and a back side 301 b , and having a bonding pad 3011 on the front side;

[0128] A third plastic encapsulation layer 303 , which embeds the plurality of third chips 301 and the second intermediate substructure 21 and exposes the bonding pads 3011 of the third chips and the second metal bumps 206 on the surface facing away from the second chip 201 ;

[0129] a third redistribution layer 304 , which is located on the bonding pad 3011 of the third chip and the surface of the second metal bump 206 facing away from the second chip 201 ;

[0130] The second solder balls 307 are located on a surface of the third redistribution layer 304 facing away from the third chip 301 .

[0131] Each of the second intermediate substructures 21 includes the second metal bumps 206 , the first intermediate substructure 11 , the second chip 201 , the second plastic encapsulation layer 203 and the second redistribution layer 204 .

[0132] The multi-layer chip packaging structure may further include: a third dielectric layer 305 , which is located on the third plastic packaging layer 303 and covers the side surface of the third redistribution layer 304 , exposing the surface of the third redistribution layer 304 facing away from the third chip 301 .

[0133] The multi-layer chip packaging structure is a second packaging structure, specifically a three-layer chip packaging structure. In this embodiment, multiple second packaging sub-structures can be obtained by cutting the second packaging structure, which can be prepared by the above steps S21 to S212.

[0134] In other embodiments, the multi-layer chip packaging structure may further include:

[0135] A second metal bump 206 is located on a surface of the second redistribution layer 204 facing away from the second chip 201;

[0136] a plurality of fourth chips 401, each of the fourth chips 401 including a front side 401a and a back side 401b, wherein the front side 401a has a bonding pad, and the front side 401a of the fourth chip is located on a surface of the second redistribution layer 204 facing away from the second chip 201;

[0137] a fourth plastic packaging layer 403 burying the fourth chip 401 on the second redistribution layer 204 and exposing the surface of the second metal bumps 206 facing away from the second chip 201 ;

[0138] The third solder ball 404 is located on the surface of the second metal bump 206 facing away from the second chip 201 .

[0139] The multi-layer chip packaging structure is a third packaging structure, specifically a three-layer chip flip-chip structure. In this embodiment, multiple third packaging sub-structures can be obtained by cutting the third packaging structure, which can be prepared by the above steps S31 to S312.

[0140] In summary, the method for preparing a multi-layer chip package structure provided by the present invention can produce a double-layer chip package structure, a triple-layer chip package structure, and a triple-layer flip-chip chip structure. Compared to chip package structures prepared by existing methods, the multi-layer chip package structure prepared by the preparation method of the present invention has a smaller size, better product reliability, higher material utilization, and lower cost.

[0141] In addition, it is understood that although the present invention has been disclosed above with reference to preferred embodiments, the above embodiments are not intended to limit the present invention. For any person skilled in the art, without departing from the scope of the technical solution of the present invention, the technical content disclosed above can be used to make many possible changes and modifications to the technical solution of the present invention, or to modify it into an equivalent embodiment with equivalent changes. Therefore, any simple modification, equivalent change, and modification made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention are still within the scope of protection of the technical solution of the present invention.

[0142] It should also be understood that the present invention is not limited to the specific methods, compounds, materials, manufacturing techniques, uses, and applications described herein, which may vary. It should also be understood that the terminology described herein is used only to describe specific embodiments and is not intended to limit the scope of the present invention. It should be noted that the singular forms "a," "an," and "the" as used herein and in the appended claims include plural references unless the context clearly indicates otherwise. Thus, for example, a reference to "a step" means a reference to one or more steps, and may include secondary steps. All conjunctions used should be understood in their broadest sense. Thus, the word "or" should be understood to have the definition of a logical "or," not a logical "exclusive or," unless the context clearly indicates otherwise. Structures described herein are to be understood to also refer to functional equivalents of that structure. Language that can be interpreted as approximating should be so interpreted unless the context clearly indicates otherwise.

Claims

1. A method for preparing a multi-layer chip packaging structure, characterized in that: The following steps are involved: Providing a first carrier board and a plurality of first chips, each of the first chips comprising a front side and a back side, and having a solder pad on the front side, and the front sides of the plurality of first chips are fixed toward the first carrier board; forming a first plastic packaging layer for embedding the plurality of first chips, and removing the first carrier to expose the solder pads of the first chips; forming a first rewiring layer on the bonding pad of the first chip, and forming a plurality of first metal bumps on a surface of the first rewiring layer facing away from the first chip to obtain a first semiconductor intermediate structure, and cutting the first semiconductor intermediate structure to form a plurality of first intermediate substructures; Providing a second carrier and a plurality of second chips, each of the second chips comprising a front side and a back side, and having a solder pad on the front side, and the front sides of the plurality of second chips and the first metal bumps of the plurality of first intermediate substructures are fixed toward the second carrier; Forming a second plastic encapsulation layer to embed the plurality of second chips and the first intermediate substructure, and removing the second carrier to expose the bonding pads of the second chip and the surface of the first metal bump facing away from the first chip; A second redistribution layer is formed on the bonding pads of the second chip and the surface of the first metal bumps facing away from the first chip.

2. The method for preparing a multi-layer chip packaging structure according to claim 1, characterized in that: The second chip is located between the plurality of first metal bumps of the first intermediate substructure, and the front surface of the second chip is coplanar with the surface of the first metal bumps facing away from the first chip.

3. The method for preparing a multi-layer chip packaging structure according to claim 1, characterized in that: After the step of forming the second redistribution layer, the preparation method further includes: forming a first solder ball on a surface of the second redistribution layer facing away from the second chip to obtain a first packaging structure.

4. The method for preparing a multi-layer chip packaging structure according to claim 3, characterized in that: After the step of obtaining the first packaging structure, the preparation method further includes: cutting the first packaging structure to form a plurality of packaging sub-structures.

5. The method for preparing a multi-layer chip packaging structure according to claim 1, characterized in that: After the step of forming the second rewiring layer, the preparation method further comprises: forming a plurality of second metal bumps on a surface of the second rewiring layer facing away from the second chip to obtain a second semiconductor intermediate structure.

6. The method for preparing a multi-layer chip packaging structure according to claim 5, characterized in that: After the step of obtaining the second semiconductor intermediate structure, the preparation method further comprises: cutting the second semiconductor intermediate structure to form a plurality of second intermediate substructures; Providing a third carrier board and a plurality of third chips, each of the third chips comprising a front side and a back side, and having a solder pad on the front side, and the front sides of the plurality of third chips and the second metal bumps of the plurality of second intermediate substructures are fixed toward the third carrier board; forming a third sealing layer to embed the plurality of third chips and the second intermediate substructure, and removing the third carrier to expose the pads of the third chip and the surface of the second metal bump facing away from the second chip; A third redistribution layer is formed on the surface of the pads and second metal bumps of the third chip facing away from the second chip, and a second solder ball is formed on the surface of the third redistribution layer facing away from the third chip to obtain a second packaging structure.

7. The method for preparing a multi-layer chip packaging structure according to claim 6, characterized in that: The third chip is located between the plurality of second metal bumps of the second intermediate substructure, and the front surface of the third chip is coplanar with the surface of the second metal bumps facing away from the second chip.

8. The method for preparing a multi-layer chip packaging structure according to claim 5, characterized in that: After the step of obtaining the second semiconductor intermediate structure, the preparation method further comprises: Providing a plurality of fourth chips, each of the fourth chips comprising a front side and a back side, and having a pad on the front side, and the front sides of the plurality of fourth chips being fixed on a surface of the second redistribution layer facing away from the second chip; Forming a fourth plastic packaging layer that embeds the plurality of fourth chips and the second semiconductor intermediate structure; Thinning the fourth plastic sealing layer until the surface of the second metal bump facing away from the second chip is exposed; A third solder ball is formed on the surface of the second metal bump facing away from the second chip to obtain a third packaging structure.

9. A multi-layer chip packaging structure, characterized in that: include: A plurality of first intermediate substructures, each of which comprises a first chip, a first plastic encapsulation layer, a first rewiring layer and a first metal bump, wherein the first chip comprises a front side and a back side, and the front side has a soldering pad; the first plastic encapsulation layer embeds the first chip and exposes the front side of the first chip; the first rewiring layer is located on the soldering pad on the front side of the first chip; the first metal bump is located on the surface of the first rewiring layer facing away from the first chip; A plurality of second chips, each of the second chips comprises a front side and a back side, and the front side has a bonding pad; The second plastic encapsulation layer embeds the plurality of second chips and the first intermediate substructure and exposes the The first metal bump faces away from the surface of the first chip and the bonding pad of the second chip; The second redistribution layer is located on the bonding pads of the second chip and the surface of the first metal bumps facing away from the first chip.

10. The multi-layer chip packaging structure according to claim 9, characterized in that: The multi-layer chip packaging structure further includes: a first solder ball located on a surface of the second redistribution layer facing away from the second chip.

11. The multi-layer chip packaging structure according to claim 9, characterized in that: The multi-layer chip packaging structure further includes: A plurality of second metal bumps, which are located on a surface of the second rewiring layer facing away from the second chip, wherein the plurality of second metal bumps, the plurality of first intermediate substructures, the plurality of second chips, the second plastic encapsulation layer and the second rewiring layer constitute a plurality of second intermediate substructures; A plurality of third chips, each of the third chips comprising a front side and a back side, and a bonding pad on the front side; A third plastic encapsulation layer, which embeds the plurality of third chips and the second intermediate substructure and exposes the pads and the second metal bumps of the third chip facing away from the second chip; A third redistribution layer is located on the bonding pads of the third chip and the surface of the second metal bump facing away from the second chip; The second solder ball is located on a surface of the third redistribution layer facing away from the third chip.

12. The multi-layer chip packaging structure according to claim 9, characterized in that: The multi-layer chip packaging structure further includes: a second metal bump, located on a surface of the second redistribution layer facing away from the second chip; a plurality of fourth chips, each of the fourth chips comprising a front side and a back side, and having a pad on the front side, and the front side of the fourth chip being located on a surface of the second redistribution layer facing away from the second chip; a fourth plastic packaging layer, embedding the fourth chip on the second redistribution layer and exposing a surface of the second metal bump facing away from the second chip; The third solder ball is located on the surface of the second metal bump facing away from the second chip.

Images