Inspection processing device and semiconductor device manufacturing method

Abstract

Provided are: an inspection processing device capable of improving efficiency; and a semiconductor device manufacturing method. According to an embodiment, an inspection processing device includes a storage unit and a processing unit. The storage unit is capable of storing a feature value distribution that includes first and second feature value distribution regions pertaining to a target device. The processing unit is capable of performing a current first inspection pertaining to the target device on the basis of the first and second feature value distribution regions which are stored in the storage unit. The feature value distribution pertains to a first past inspection result of a past first inspection pertaining to the target device, and to a second past inspection result. The second past inspection result is acquired by means of a second inspection which is subsequent to past first processing and which is performed after the past first inspection. A first defect rate of the second past inspection result corresponding to the first feature value distribution region is higher than a second defect rate of the second past inspection result corresponding to the second feature value distribution region.

Description

Inspection processing device and semiconductor device manufacturing method

[0001] An embodiment of the present invention relates to an inspection processing apparatus and a method for manufacturing a semiconductor device.

[0002] For example, various inspections are performed in the manufacture of target devices such as semiconductor devices, and it is desirable to improve the efficiency of these inspections.

[0003] Special table 2019-525450 publication

[0004] The embodiments provide an inspection processing apparatus and a method for manufacturing a semiconductor device that can improve efficiency.

[0005] According to an embodiment, an inspection processing device includes a memory unit and a processing unit. The memory unit is capable of storing a feature distribution including a first feature distribution region for a target device and a second feature distribution region for the target device. The processing unit is capable of performing a current first inspection of the target device based on the first feature distribution region and the second feature distribution region stored in the memory unit. The feature distribution relates to a first past inspection result and a second past inspection result of a past first inspection of the target device. The second past inspection result is obtained by a past second inspection of the target device after the past first inspection. A first defect rate of the second past inspection result corresponding to the first feature distribution region is higher than a second defect rate of the second past inspection result corresponding to the second feature distribution region.

[0006] FIG. 1 is a flowchart illustrating the operation of the inspection processing apparatus according to the first embodiment. FIG. 2 is a block diagram illustrating the inspection processing apparatus according to the first embodiment. FIG. 3 is a schematic diagram illustrating characteristics used in the operation of the inspection processing apparatus according to the first embodiment. FIG. 4 is a schematic diagram illustrating characteristics used in the operation of the inspection processing apparatus according to the first embodiment. FIG. 5 is a schematic diagram illustrating a result of the operation of the inspection processing apparatus according to the first embodiment. FIG. 6 is a schematic diagram illustrating a result of the operation of the inspection processing apparatus according to the first embodiment. FIG. 7 is a flowchart illustrating the operation of the inspection processing apparatus according to the first embodiment.

[0007] Hereinafter, embodiments of the present invention will be described with reference to the drawings. In this specification and the drawings, elements similar to those described above with reference to the previous drawings are designated by the same reference numerals, and detailed descriptions thereof will be omitted as appropriate.

[0008] First Embodiment Fig. 1 is a flowchart illustrating the operation of an inspection processing apparatus according to a first embodiment. Fig. 2 is a block diagram illustrating the inspection processing apparatus according to the first embodiment. Figs. 3 and 4 are schematic diagrams illustrating characteristics used in the operation of the inspection processing apparatus according to the first embodiment.

[0009] 2, the inspection processing device 110 according to the embodiment includes a storage unit 76m and a processing unit 76p. The processing unit 76p may include, for example, a computing device (e.g., a computer). The storage unit 76m may include any memory (including a hard disk). The inspection processing device 110 may include, for example, an interface 76f, a display 76d, and an input device 76i. The input device 76i may include, for example, at least one of a keyboard, a touch panel, and a mouse.

[0010] In the inspection processing device 110, the storage unit 76m can store a feature distribution related to a target device to be inspected. The target device includes, for example, various electronic devices. In one example, the target device may include a semiconductor device.

[0011] The feature distribution includes multiple feature regions for the target device. In one example, the feature distribution includes a region with multiple dimensions. The multiple dimensional region is divided into, for example, multiple subregions. For example, the feature distribution includes a first feature distribution region for the target device and a second feature distribution region for the target device.

[0012] 4 illustrates an example of a feature distribution FD. In this example, the feature distribution FD is two-dimensional. In this example, the feature distribution FD is shown two-dimensionally including a first feature F1 and a second feature F2. The feature distribution FD is expressed by the first feature F1 and the second feature F2.

[0013] 4, the first feature distribution region FR1 is one region in two dimensions. The second feature distribution region FR2 is another region in two dimensions. In this way, the feature distribution FD is divided into multiple regions by multiple features.

[0014] The processing unit 76p is capable of performing a first inspection (current first inspection) on a target device (e.g., a semiconductor device) based on the first feature distribution region FR1 and the second feature distribution region FR2 stored in the memory unit 76m.

[0015] In one example, when the target device is a semiconductor device, the above-mentioned "current first inspection" is an inspection of crystal defects in a semiconductor included in the semiconductor device. For example, an image (such as a microscope image) showing the crystal defects is acquired. For example, feature quantities related to the shape of the crystal defects may be derived from the image showing the crystal defects. A first inspection of the target device (such as a semiconductor device) is performed based on the derived feature quantities. In one example, the feature quantities may be defined by a multi-dimensional vector (such as a 128-dimensional value group).

[0016] The feature distribution FD relates to a first past inspection result and a second past inspection result of a past first inspection of a target device (e.g., a semiconductor device). The second past inspection result is obtained by a second past inspection of the target device after a first past process (post-process) performed after the first past inspection. For example, the "first past inspection," "first past process," and "second past inspection" are performed in this order.

[0017] In one example, the "past first inspection" is an inspection of a semiconductor device wafer for crystal defects. In one example, in the "past first processing", various processes are performed on the wafer after the first inspection is completed. The various processes include, for example, forming a semiconductor layer, patterning, and forming an electrode. A semiconductor device is fabricated from the wafer by the "past first processing". After this, a "past second inspection" is performed. In the "past second inspection", for example, an inspection of the electrical characteristics of the semiconductor device is performed. In the "past second inspection", an appearance inspection of the semiconductor device may also be performed.

[0018] The results of the "second past test" may be related to the results of the "first past test." For example, the second past test result is linked to the first past test result. Such first past test result and second past test result are stored in the memory unit 76m.

[0019] FIG. 3 illustrates an example of a feature distribution FD. The feature distribution FD is based on the results of a "past first inspection" and a "past second inspection" for a target device (e.g., a semiconductor device). The horizontal axis of FIG. 3 represents the first feature F1. The vertical axis of FIG. 3 represents the second feature F2. The first feature F1 and the second feature F2 are based on the results of the first past inspection and the results of the second past inspection. In this example, the "past first inspection" is an inspection of crystal defects in a semiconductor device. The "past second inspection" is an inspection of electrical characteristics of the semiconductor device.

[0020] 3 indicate the first feature value F1 and the second feature value F2 of a defective result (e.g., a crystal defect) in the "past first inspection." The black circle RS1 corresponds to a defect (crystal defect) in the "past first inspection" and also a defect (abnormal electrical characteristics) in the "past second inspection." The white circle RS2 corresponds to a defect (crystal defect) in the "past first inspection" but a pass (normal electrical characteristics) in the "past second inspection."

[0021] As shown in FIG. 3 , the feature distribution FD has a region (first feature distribution region FR1) where the density of occurrence of black dots RS1 is high. In this region, if a defect is found in the first inspection, it is highly likely to be found in the second inspection. Defects (crystal defects) in the first inspection contained in this region are highly likely to cause defects in the second inspection. Defects in the first inspection contained in this region have high "killer characteristics." In the first feature distribution region FR1, there is a high correlation between the results of the first inspection and the results of the second inspection.

[0022] On the other hand, in the regions other than the first feature amount distribution region FR1, the correlation between the results of the first inspection and the results of the second inspection is low.

[0023] Based on the results of such past inspections, a feature distribution FD as shown in Fig. 4 is obtained. As shown in Fig. 4, the feature distribution FD includes a first feature distribution region FR1 and a second feature distribution region FR2. The second feature distribution region FR2 may be, for example, a region excluding the first feature distribution region FR1.

[0024] The first defect rate of the second past inspection result (second inspection result) corresponding to the first feature distribution region FR1 is higher than the second defect rate of the second past inspection result (second inspection result) corresponding to the second feature distribution region FR2. The feature corresponding to the first feature distribution region FR1 indicates a high probability of failure in the second inspection. The feature corresponding to the second feature distribution region FR2 indicates a relatively low probability of failure in the second inspection. In the embodiment, the "current first inspection" is performed based on such first feature distribution region FR1 and second feature distribution region FR2.

[0025] As shown in FIG. 1 , in this embodiment, for example, data of the "current first examination" is acquired (step S109). Feature quantities (e.g., first feature quantity F1 and second feature quantity F2) are derived from the data of the "current first examination" (step S110). The derived feature quantities are compared with a first feature quantity distribution region FR1 based on past data (step S111). At this time, information on the first feature quantity distribution region FR1 and the second feature quantity distribution region FR2 is read from the storage unit 76m and used. Steps S110 and S111 correspond to at least a part of the "current first examination."

[0026] If the derived feature falls within the first feature distribution region FR1, the product is determined to be defective (step S112). For example, data (flag) indicating "defective" is output. For example, data indicating "defective" may be recorded.

[0027] By such processing, the first inspection can be performed with high efficiency. According to the embodiment, it is possible to provide an inspection processing apparatus capable of improving efficiency. The first inspection can be performed with high accuracy.

[0028] As shown in FIG. 1 , in step S111, a first process is performed on a target device (e.g., a semiconductor device) (step S130). After this, a second test (e.g., an electrical characteristic test) is performed, and data from the second test is acquired (step S119). The data from the second test is compared with a predetermined standard, and the results of the second test are determined (step S120). If the results of the second test are bad, the device is determined to be bad (step S122). If the results of the second test are good, the device is determined to be good (step S123).

[0029] 5 and 6 are schematic diagrams illustrating the results of the operation of the inspection processing apparatus according to the first embodiment. FIG. 5 illustrates the results of the "current first inspection" for the first sample SPL1. FIG. 6 illustrates the results of the "current first inspection" for the second sample SPL2. In this example, as shown in FIG. 5, multiple feature quantities V1 are derived for the first sample SPL1. The multiple feature quantities V1 are not included in the first feature quantity distribution region FR1. The first sample SPL1 is determined to be good. As shown in FIG. 6, multiple feature quantities V1 are derived for the second sample SPL2. At least one of the multiple feature quantities V1 for the second sample SPL2 is included in the first feature quantity distribution region FR1. The second sample SPL2 is determined to be bad.

[0030] In the embodiment, for example, the processing unit 76p can output a determination result of "failure" when the result of the "current first inspection" corresponds to the first feature distribution region FR1, and the processing unit 76p can not output a determination result of "failure" when the result of the "current first inspection" corresponds to the second feature distribution region FR2.

[0031] The processing unit 76p may be capable of storing the above determination result in the storage unit 76m.

[0032] For example, the "current first inspection" and the "past first inspection" may include an image inspection of the target device. For example, the "past second inspection" may include an electrical property inspection of the target device.

[0033] In one example, the target device is a semiconductor device. The "current first inspection" and the "past first inspection" include an inspection of semiconductor crystal defects. The "past second inspection" may include at least one of an electrical property inspection of the target device (e.g., semiconductor device) and an appearance inspection of the target device (e.g., semiconductor device).

[0034] In one example, the semiconductor includes SiC. In a semiconductor device including SiC, crystal defects in SiC tend to affect electrical characteristics. When the embodiment is applied to a semiconductor device including SiC, higher efficiency is likely to be obtained.

[0035] For example, the inspection of the crystal defects may include deriving a crystal defect feature amount that indicates a feature of an image of the crystal defects contained in the semiconductor. For example, the crystal defect feature amount indicates a feature of the shape of the image of the crystal defects.

[0036] The semiconductor device to which the embodiment is applied may include a plurality of semiconductor chips provided on a wafer containing semiconductors. Inspection is performed in the wafer state. Inspection of crystal defects is performed on each of the plurality of semiconductor chips.

[0037] For example, the inspection of crystal defects may include deriving, using a deep neural network (DNN), a crystal defect feature amount that indicates the characteristics of an image of a crystal defect contained in a semiconductor.

[0038] For example, the processing unit 76p may further be capable of deriving a feature distribution FD based on the first past inspection result and the second past inspection result.

[0039] The processing unit 76p may be capable of storing the derived feature distribution FD in the storage unit 76m.

[0040] Deriving the feature distribution FD may include compressing the dimensions of at least one of the first past inspection result and the second past inspection result. Deriving the feature distribution FD may include, for example, deriving a first feature distribution region FR1 and a second feature distribution region FR2 from the first past inspection result and the second past inspection result by processing the first past inspection result and the second past inspection result based on at least one distance selected from the group consisting of Euclidean distance, standard Euclidean distance, Mahalanobis distance, Manhattan distance, Chebyshev distance, and Minkowski distance.

[0041] FIG. 7 is a flowchart illustrating the operation of the inspection processing apparatus according to the first embodiment. In the example of FIG. 7, the target device is a semiconductor device containing SiC. For example, in the first inspection, a wafer containing SiC is inspected. As shown in FIG. 7, alignment marks are formed on the wafer (step S101). For example, the position of a semiconductor chip within the wafer surface is set. For example, the wafer is inspected for crystal defects (step S102). For example, the crystal defects are linked to the position of the semiconductor chip.

[0042] For example, a feature is derived from an inspection image of crystal defects for each chip (e.g., step S110). The derived feature is compared with a feature distribution region (first feature distribution region FR1) (step S103). It is determined whether the derived feature is in a feature distribution region corresponding to a good result (second feature distribution region FR2) (step S111). If the derived feature is not in a feature distribution region corresponding to a good result (second feature distribution region FR2), the chip is determined to be defective (step S112).

[0043] In step S111, if the derived feature is in a feature distribution region corresponding to a good result (second feature distribution region FR2), the remaining process (first process) is performed (step S130). After the remaining process (first process) is performed, an inspection process (second inspection) is performed on the target device (semiconductor device) (step S119). The result of the inspection process (second inspection) is determined to be good or bad (step S120). In step S120, if the result is good, the chip is determined to be good (step S123). In step S120, if the result is negative, the chip is determined to be bad (step S122).

[0044] In the above steps S130 and S111, the feature distribution FD (first feature distribution region FR1 and second feature distribution region FR2) stored in the storage unit 76m is used.

[0045] 7 , for example, in step S230, a first feature distribution region FR1 and a second feature distribution region FR2 are defined. The first feature distribution region FR1 is a region of characteristics corresponding to a failure result of the second inspection. For example, the first feature distribution region FR1 is a region including a cluster with a high failure frequency in an electrical test.

[0046] For example, the second feature distribution region FR2 is a region of features corresponding to a good result of the second inspection, and includes clusters uncorrelated with the electrical test results.

[0047] As shown in FIG. 7 , a database is stored in, for example, the storage unit 76m. In the database, for example, crystal defect inspection results and electrical test results are linked and stored for each chip. For example, feature quantities of a group of crystal defect inspection images are derived (step S210). For example, the derived feature quantity distribution FD is divided into clusters (step S220). The feature quantity distribution FD is divided into multiple regions. This defines a first feature quantity distribution region FR1 and a second feature quantity distribution region FR2.

[0048] As shown in FIG. 7 , the crystal defect inspection results obtained in step S102 may be stored in the memory unit 76m. For example, step S210 may be performed periodically. The inspection results (results of the second inspection) obtained in step S119 may be stored in the memory unit 76m. (Second Embodiment) The second embodiment relates to a semiconductor device manufacturing method. The semiconductor device manufacturing method according to the embodiment performs a first inspection using, for example, the memory unit 76m and the processing unit 76p. The memory unit 76m can store a feature distribution FD. The feature distribution FD includes a first feature distribution region FR1 related to the semiconductor device and a second feature distribution region FR2 related to the semiconductor device. The processing unit 76p can perform a "current first inspection" on the semiconductor device based on the first feature distribution region FR1 and the second feature distribution region FR2 stored in the memory unit 76m.

[0049] The feature distribution FD relates to a first past inspection result of a past first inspection on the semiconductor device and a second past inspection result. The second past inspection result is obtained by a "second past inspection" of the semiconductor device after a "first past process" performed after the "first past inspection." The second past inspection result is linked to the first past inspection result. The first defect rate of the second past inspection result corresponding to the first feature distribution region FR1 is higher than the second defect rate of the second past inspection result corresponding to the second feature distribution region FR2. In the embodiment, semiconductor devices can be inspected with high efficiency.

[0050] In the second embodiment, the semiconductor device includes a semiconductor. The "current first inspection" and the "past first inspection" include an inspection of crystal defects in the semiconductor. The "past second inspection" includes at least one of an electrical characteristic inspection of the semiconductor device and an appearance inspection of the semiconductor device. The semiconductor includes, for example, SiC.

[0051] The method for manufacturing a semiconductor device according to the embodiment may further include performing a “current first process” on the semiconductor device after the “current first inspection.” The method for manufacturing a semiconductor device according to the embodiment may further include performing a “current second inspection” on the semiconductor device after the “current first process” has been performed.

[0052] The embodiments may include the following technical proposals: (Technical proposal 1) An inspection processing apparatus comprising: a storage unit capable of storing a feature distribution including a first feature distribution region for a target device and a second feature distribution region for the target device; and a processing unit capable of performing a current first inspection for the target device based on the first feature distribution region and the second feature distribution region stored in the storage unit, wherein the feature distribution relates to a first past inspection result and a second past inspection result of a past first inspection for the target device, the second past inspection result being acquired by a past second inspection of the target device after the past first inspection, and a first defect rate of the second past inspection result corresponding to the first feature distribution region is higher than a second defect rate of the second past inspection result corresponding to the second feature distribution region.

[0053] (Technical proposal 2) An inspection processing device as described in Technical proposal 1, wherein the processing unit is capable of outputting a defective judgment result when the current result of the first inspection corresponds to the first feature distribution region, and the processing unit is capable of not outputting the defective judgment result when the current result of the first inspection corresponds to the second feature distribution region.

[0054] (Technical Solution 3) The inspection processing apparatus according to Technical Solution 1 or 2, wherein a past first process is performed between the past first inspection and the past second inspection.

[0055] (Technical proposal 4) An inspection processing device described in any one of Technical proposals 1 to 3, wherein the current first inspection and the past first inspection include an image inspection of the target device, and the past second inspection includes an electrical characteristic inspection of the target device.

[0056] (Technical proposal 5) An inspection processing device described in any one of technical proposals 1 to 3, wherein the target device is a semiconductor device including a semiconductor, the current first inspection and the past first inspection include an inspection of crystal defects in the semiconductor, and the past second inspection includes at least one of an electrical characteristic inspection of the target device and an appearance inspection of the target device.

[0057] (Technical Solution 6) The inspection processing apparatus according to Technical Solution 5, wherein the semiconductor includes SiC.

[0058] (Technical Solution 7) The inspection processing apparatus according to Technical Solution 5, wherein the inspection of the crystal defects includes deriving crystal defect feature amounts that indicate features of an image of the crystal defects included in the semiconductor.

[0059] (Technical Solution 8) The inspection processing apparatus according to Technical Solution 7, wherein the crystal defect feature amount indicates a feature of the shape of the image of the crystal defect.

[0060] (Technical proposal 9) An inspection processing apparatus according to any one of Technical proposals 5 to 8, wherein the semiconductor device includes a plurality of semiconductor chips provided on a wafer including the semiconductor, and the inspection of the crystal defects is performed on each of the plurality of semiconductor chips.

[0061] (Technical proposal 10) The inspection processing device described in Technical proposal 5, wherein the inspection of the crystal defects includes deriving crystal defect feature quantities that indicate characteristics of images of the crystal defects contained in the semiconductor using a DNN (Deep Neural Network).

[0062] (Technical Solution 11) The inspection processing apparatus according to any one of Technical Solutions 7 to 10, wherein the feature distribution is two-dimensional.

[0063] (Technical proposal 12) An inspection processing device described in any one of Technical proposals 7 to 10, wherein the feature distribution is two-dimensional including a first feature and a second feature, the first feature distribution region is one region in the two dimensions, and the second feature distribution region is another region in the two dimensions.

[0064] (Technical proposal 13) The inspection processing device described in any one of Technical proposals 1 to 12, wherein the processing unit is further capable of deriving the feature distribution based on the first past inspection result and the second past inspection result.

[0065] (Technical Solution 14) The inspection processing apparatus according to Technical Solution 13, wherein the processing unit is capable of storing the derived feature amount distribution in the storage unit.

[0066] (Technical Solution 15) The inspection processing device according to Technical Solution 13 or 14, wherein the deriving of the feature distribution includes compressing a dimension of at least one of the first past inspection result and the second past inspection result.

[0067] (Technical Proposal 16) The inspection processing device described in any one of Technical Proposals 13 to 15, wherein the deriving of the feature distribution includes deriving the first feature distribution region and the second feature distribution region by processing the first past inspection result and the second past inspection result based on at least one distance selected from the group consisting of Euclidean distance, standard Euclidean distance, Mahalanobis distance, Manhattan distance, Chebyshev distance, and Minkowski distance.

[0068] (Technical Proposal 17) A method for manufacturing a semiconductor device, comprising: a memory unit capable of storing a feature distribution including a first feature distribution region for a semiconductor device and a second feature distribution region for the semiconductor device; and a processing unit capable of performing a current first inspection for the semiconductor device based on the first feature distribution region and the second feature distribution region stored in the memory unit, wherein the first inspection is performed using the above; wherein the feature distribution relates to a first past inspection result and a second past inspection result of a past first inspection for the semiconductor device, the second past inspection result being obtained by a past second inspection of the semiconductor device after the past first inspection, and a first defect rate of the second past inspection result corresponding to the first feature distribution region is higher than a second defect rate of the second past inspection result corresponding to the second feature distribution region.

[0069] (Technical proposal 18) The semiconductor device includes a semiconductor, the current first inspection and the past first inspection include an inspection of crystal defects in the semiconductor, and the past second inspection includes at least one of an electrical characteristic inspection of the semiconductor device and an appearance inspection of the semiconductor device, in accordance with the method for manufacturing a semiconductor device described in Technical proposal 17.

[0070] (Technical Solution 19) The method for manufacturing a semiconductor device according to Technical Solution 18, wherein the semiconductor includes SiC.

[0071] (Technical proposal 20) A method for manufacturing a semiconductor device described in Technical proposal 17 or 18, further performing a current first process on the semiconductor device after the current first inspection, and further performing a current second inspection on the semiconductor device after the current first process has been performed.

[0072] According to the embodiment, it is possible to provide an inspection processing apparatus and a method for manufacturing a semiconductor device that can improve efficiency.

[0073] The embodiments of the present invention have been described above with reference to specific examples. However, the present invention is not limited to these specific examples. For example, the specific configurations of the elements, such as the memory unit and the processing unit, included in the inspection processing device are within the scope of the present invention as long as a person skilled in the art can implement the present invention in a similar manner and obtain similar effects by appropriately selecting them from known ranges.

[0074] Furthermore, any combination of two or more elements of each specific example within the scope of technical feasibility is also included within the scope of the present invention as long as it includes the gist of the present invention.

[0075] In addition, all inspection processing devices and semiconductor device manufacturing methods that can be implemented by a person skilled in the art by making appropriate design modifications based on the inspection processing device and semiconductor device manufacturing method described above as embodiments of the present invention also fall within the scope of the present invention, as long as they include the gist of the present invention.

[0076] In addition, within the scope of the concept of the present invention, a person skilled in the art may come up with various modifications and alterations, and it will be understood that these modifications and alterations also fall within the scope of the present invention.

[0077] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be embodied in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, and are also included in the scope of the invention and its equivalents as defined in the claims.

[0078] 76d: Display, 76f: Interface, 76i: Input device, 76m: Storage unit, 76p: Processing unit, 110: Inspection processing device, F1, F2: First and second feature amounts, FD: Feature amount distribution, FR1, FR2: First and second feature amount distribution areas, RS1: Black circle, RS2: White circle, SPL1, SPL2: First and second samples, V1: Feature amount

Claims

1. An inspection processing device comprising: a memory unit capable of storing a feature distribution including a first feature distribution region for a target device and a second feature distribution region for the target device; and a processing unit capable of performing a current first inspection for the target device based on the first feature distribution region and the second feature distribution region stored in the memory unit, wherein the feature distribution relates to a first past inspection result and a second past inspection result of a past first inspection for the target device, the second past inspection result being obtained by a past second inspection of the target device after the past first inspection, and a first defect rate of the second past inspection result corresponding to the first feature distribution region is higher than a second defect rate of the second past inspection result corresponding to the second feature distribution region.

2. The inspection processing device according to claim 1, wherein the processing unit is capable of outputting a defective judgment result when the current result of the first inspection corresponds to the first feature distribution region, and the processing unit is capable of not outputting the defective judgment result when the current result of the first inspection corresponds to the second feature distribution region.

3. The inspection processing apparatus according to claim 1, wherein a past first process is performed between the past first inspection and the past second inspection.

4. The inspection processing device according to claim 1, wherein the current first inspection and the past first inspection include an image inspection of the target device, and the past second inspection includes an electrical characteristic inspection of the target device.

5. An inspection processing apparatus according to any one of claims 1 to 3, wherein the target device is a semiconductor device including a semiconductor, the current first inspection and the past first inspection include an inspection of crystal defects in the semiconductor, and the past second inspection includes at least one of an inspection of electrical characteristics of the target device and an appearance inspection of the target device.

6. The inspection processing apparatus according to claim 5, wherein the inspection of the crystal defect includes deriving a crystal defect feature quantity indicating an image feature of the crystal defect contained in the semiconductor.

7. The inspection processing apparatus according to claim 5, wherein the semiconductor device includes a plurality of semiconductor chips provided on a wafer including the semiconductor, and the inspection for crystal defects is performed for each of the plurality of semiconductor chips.

8. The inspection processing device described in claim 6, wherein the feature distribution is two-dimensional including a first feature and a second feature, the first feature distribution region is one region in the two dimensions, and the second feature distribution region is another region in the two dimensions.

9. A method for manufacturing a semiconductor device, comprising: a memory unit capable of storing a feature distribution including a first feature distribution region for a semiconductor device and a second feature distribution region for the semiconductor device; and a processing unit capable of performing a current first inspection for the semiconductor device based on the first feature distribution region and the second feature distribution region stored in the memory unit, wherein the first inspection is performed using the above; the feature distribution relates to a first past inspection result and a second past inspection result of the past first inspection for the semiconductor device, the second past inspection result being obtained by a past second inspection of the semiconductor device after the past first inspection, and a first defect rate of the second past inspection result corresponding to the first feature distribution region is higher than a second defect rate of the second past inspection result corresponding to the second feature distribution region.

10. The method for manufacturing a semiconductor device according to claim 9, wherein the semiconductor device includes a semiconductor, the current first inspection and the past first inspection include an inspection of crystal defects in the semiconductor, and the past second inspection includes at least one of an electrical characteristic inspection of the semiconductor device and an appearance inspection of the semiconductor device.

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