Semiconductor device

Abstract

This semiconductor device (1) comprises a semiconductor layer (40) and a first vertical MOS transistor (10) and a second vertical MOS transistor (20) formed on the semiconductor layer (40). In plan view of the semiconductor layer (40), the full length of one side among the outer peripheral sides of a first gate electrode region (G1) and the full length of one side among the outer peripheral sides of a first resistance element region (R1) match a portion of a side which is orthogonal to a boundary line (90) and from which the distance to a first gate pad (119) is the shortest, among the outer peripheral sides of the semiconductor layer (40). In plan view of the semiconductor layer (40), the outer peripheral sides of the first resistance element region (R1) include only one corner among the four corners on the outer periphery of the first gate electrode region (G1), the only one corner being the corner where the distance to the boundary line (90) is the shortest and the distance to the side orthogonal to the boundary line (90) among the outer peripheral sides of the semiconductor layer (40) is the shortest.

Description

Semiconductor Devices

[0001] The present disclosure relates to a semiconductor device, and more particularly to a chip-size package type semiconductor device.

[0002] Dual-configuration vertical MOS transistors that can control bidirectional conduction with a single chip are required to have reduced conduction resistance and be smaller in size. For dual-configuration vertical MOS transistors, a four-pad configuration with only the minimum number of pads required has been disclosed.

[0003] Japanese Patent Application Laid-Open No. 2008-53623A

[0004] In a semiconductor device having a vertical MOS transistor formed therein, a resistive element may be provided in the semiconductor device to improve the resistance to ESD (Electrostatic Discharge). However, the provision of the resistive element reduces the area of ​​the region that contributes to the conduction of the vertical MOS transistor, making it difficult to reduce the conduction resistance.

[0005] In order to solve the above-described problems, a semiconductor device according to one aspect of the present disclosure is a chip-size package type semiconductor device that can be mounted face-down, and includes: a semiconductor layer including a semiconductor substrate; a first vertical MOS transistor entirely formed in a first region of the semiconductor layer on an upper surface side of the semiconductor layer; a second vertical MOS transistor entirely formed in a second region adjacent to the first region in a plan view of the semiconductor layer; and a metal layer formed in contact with the semiconductor substrate on a lower surface side of the semiconductor layer, a common drain region of a first vertical MOS transistor and the second vertical MOS transistor, the semiconductor layer having a square shape in the plan view, the first region and the second region aligned in a first direction in the plan view, a boundary line between the first region and the second region perpendicular to the first direction, dividing the semiconductor layer into two equal parts in area, and a straight line passing through the center of the semiconductor layer, and a pad provided in the first region in the plan view is one first solenoid connected to a first source electrode of the first vertical MOS transistor; and one first gate pad connected to a first gate electrode of the first vertical MOS transistor, and the first vertical MOS transistor includes a first gate resistor element connected to the first gate electrode, a first gate electrode region which is a rectangular region containing the first gate pad in the plan view and has the largest area within a range that does not include both the first source electrode and the first gate resistor element, and a first gate electrode region which is a rectangular region containing the first gate resistor element in the plan view and has the largest area within a range that does not include both the first source electrode and the first gate resistor element. and a first resistor element region having a maximum area within a range excluding both the first gate electrode region and the first gate pad, wherein, in the plan view, the total length of one side of the periphery of the first gate electrode region and the total length of one side of the periphery of the first resistor element region coincide with a part of a side of the periphery of the semiconductor layer that is perpendicular to the boundary line and has the shortest distance from the first gate pad, and, in the plan view, the periphery of the first resistor element region includes a corner that is the shortest distance from the boundary line among four corners of the periphery of the first gate electrode region, andOnly one corner where the distance between the boundary line and the perpendicular side is the shortest is included.

[0006] According to a semiconductor device according to an aspect of the present disclosure, a small-sized dual-configuration vertical MOS transistor can reduce conduction resistance while improving ESD resistance.

[0007] FIG. 1 is a cross-sectional view schematically illustrating an example of a structure of a semiconductor device according to an embodiment. FIG. 2 is a plan view schematically illustrating an example of a pad arrangement of a semiconductor device according to an embodiment. FIG. 3 is a plan view schematically illustrating an example of the shape and arrangement of components of a semiconductor device according to an embodiment. FIG. 4 is a circuit diagram illustrating an equivalent circuit of a semiconductor device according to an embodiment. FIG. 5A is a plan view schematically illustrating a schematic unit configuration of a first transistor according to an embodiment. FIG. 5B is a perspective view schematically illustrating a schematic unit configuration of a first transistor according to an embodiment. FIG. 6 is a plan view schematically illustrating an example of the shape and arrangement of components of a semiconductor device according to an embodiment. FIG. 7A is a plan view schematically illustrating the shape and arrangement of components of a semiconductor device according to Comparative Example 1. FIG. 7B is a plan view schematically illustrating the shape and arrangement of components of a semiconductor device according to Comparative Example 1. FIG. 8 is a plan view schematically illustrating an example of the shape and arrangement of components of a semiconductor device according to an embodiment. FIG. 9A is a plan view schematically illustrating the arrangement of components of a semiconductor device according to Comparative Example 2. FIG. 9B is a plan view schematically illustrating the arrangement of components of a semiconductor device according to Comparative Example 3. FIG. 9C is a plan view schematically illustrating the arrangement of components of a semiconductor device according to Comparative Example 4. 9D is a plan view schematic diagram showing the arrangement of components of a semiconductor device according to Comparative Example 5. FIG. 9E is a plan view schematic diagram showing the arrangement of components of a semiconductor device according to Comparative Example 6. FIG. 10 is a plan view schematic diagram showing an example of the shape and arrangement of components of a semiconductor device according to an embodiment. FIG. 11 is a plan view schematic diagram showing an example of the shape and arrangement of components of a semiconductor device according to an embodiment. FIG. 12 is a plan view schematic diagram showing an example of the shape and arrangement of components of a semiconductor device according to an embodiment. FIG. 13 is a plan view schematic diagram showing an example of the shape and arrangement of components of a semiconductor device according to an embodiment. FIG. 14 is a plan view schematic diagram showing an example of the shape and arrangement of components of a semiconductor device according to an embodiment.

[0008] The embodiments described below each illustrate a specific example of the present disclosure. The numerical values, shapes, materials, components, arrangement positions and connection forms of the components shown in the following embodiments are merely examples and are not intended to limit the present disclosure.

[0009] In the present disclosure, "A and B are electrically connected" includes a case where A and B are directly connected via wiring, a case where A and B are directly connected without wiring, and a case where A and B are indirectly connected via a resistance component (resistance element, resistance wiring).

[0010] (Embodiments) [1. Structure of Semiconductor Device] Hereinafter, the structure of a semiconductor device according to an embodiment will be described.

[0011] The semiconductor device according to the embodiment is a chip size package (CSP) type semiconductor device that can be mounted face down and has two vertical MOS (Metal Oxide Semiconductor) transistors formed on a semiconductor substrate. The two vertical MOS transistors are power transistors, so-called trench MOS field effect transistors (FETs).

[0012] Fig. 1 is a schematic cross-sectional view showing an example of the structure of a semiconductor device 1 according to an embodiment. Fig. 2 is a schematic plan view showing an example of the arrangement of pads of the semiconductor device 1. Fig. 1 is a cross-section taken along line II in Fig. 2.

[0013] As shown in FIGS. 1 and 2 , the semiconductor device 1 includes a semiconductor layer 40, a metal layer 30, a first vertical MOS transistor 10 (hereinafter also referred to as transistor 10) entirely formed in a first region A1 of the semiconductor layer 40, and a second vertical MOS transistor 20 (hereinafter also referred to as transistor 20) entirely formed in a second region A2 of the semiconductor layer 40.

[0014] The transistor 10 formed entirely within the first region A1 means that, in a plan view, all of the elements constituting the transistor 10 are contained within the first region A1 and not contained within the second region A2. Similarly, the transistor 20 formed entirely within the second region A2 means that, in a plan view, all of the elements constituting the transistor 20 are contained within the second region A2 and not contained within the first region A1.

[0015] In the present disclosure, the semiconductor substrate 32 and the low-concentration impurity layer 33 are collectively referred to as the semiconductor layer 40. The semiconductor substrate 32 is disposed on the lower surface side (also referred to as the back surface side) of the semiconductor layer 40, and is made of silicon containing impurities of the first conductivity type.

[0016] The low-concentration impurity layer 33 is disposed on the upper surface side (also referred to as the front surface side) of the semiconductor layer 40, is formed in contact with the semiconductor substrate 32, and is an impurity layer of the first conductivity type that contains impurities of the first conductivity type at a concentration lower than the concentration of impurities of the first conductivity type in the semiconductor substrate 32. The low-concentration impurity layer 33 may be formed on the semiconductor substrate 32 by, for example, epitaxial growth.

[0017] The metal layer 30 is formed in contact with the back surface of the semiconductor layer 40, i.e., the back surface of the semiconductor substrate 32, and is made of silver (Ag) or copper (Cu). Note that the metal layer 30 may contain trace amounts of elements other than metals that are mixed in as impurities during the manufacturing process of the metal material. Furthermore, the metal layer 30 does not have to be formed over the entire back surface of the semiconductor layer 40.

[0018] 1, a first body region 18 of a second conductivity type containing impurities of a second conductivity type different from the first conductivity type is formed in the first region A1 of the low-concentration impurity layer 33. A first source region 14 of the first conductivity type containing impurities of the first conductivity type is formed in the first body region 18.

[0019] Also, in the first region A1, a plurality of first gate trenches 17 are formed, each extending from the upper surface of the semiconductor layer 40 through the first source region 14 and the first body region 18 to a depth reaching a part of the low-concentration impurity layer 33, and a first gate conductor 15 is formed on the first gate insulating film 16 inside the first gate trench 17. The first gate conductor 15 is a buried gate electrode buried inside the semiconductor layer 40, and is electrically connected to the first gate pad 119.

[0020] The first source electrode 11 is composed of a portion 12 and a portion 13 , and the portion 12 is connected to the first source region 14 and the first body region 18 via the portion 13 .

[0021] Portion 12 of first source electrode 11 is a layer that is joined with solder during reflow soldering in face-down mounting, and may be made of a metal material including, but not limited to, one or more of nickel, titanium, tungsten, and palladium. The surface of portion 12 may be plated with gold or the like.

[0022] Portion 13 of first source electrode 11 is a layer that connects portion 12 and semiconductor layer 40, and may be made of a metal material including, by way of non-limiting example, any one or more of aluminum, copper, gold, and silver.

[0023] A second body region 28 of the second conductivity type containing impurities of the second conductivity type is formed in the second region A2 of the low-concentration impurity layer 33. A second source region 24 of the first conductivity type containing impurities of the first conductivity type is formed in the second body region 28.

[0024] In addition, in the second region A2, a plurality of second gate trenches 27 are formed, each extending from the upper surface of the semiconductor layer 40 through the second source region 24 and the second body region 28 to a depth reaching a part of the low-concentration impurity layer 33. Furthermore, a second gate conductor 25 is formed on the second gate insulating film 26 inside the second gate trench 27. The second gate conductor 25 is a buried gate electrode buried inside the semiconductor layer 40, and is electrically connected to the second gate pad 129.

[0025] The second source electrode 21 is composed of a portion 22 and a portion 23 , and the portion 22 is connected to the second source region 24 and the second body region 28 via the portion 23 .

[0026] Portion 22 of second source electrode 21 is a layer that is joined with solder during reflow soldering in face-down mounting, and may be made of a metal material including, but not limited to, one or more of nickel, titanium, tungsten, and palladium. The surface of portion 22 may be plated with gold or the like.

[0027] Portion 23 of second source electrode 21 is a layer that connects portion 22 and semiconductor layer 40, and may be made of a metal material including, by way of non-limiting example, any one or more of aluminum, copper, gold, and silver.

[0028] With the above-described configuration of transistor 10 and transistor 20, the semiconductor substrate 32 and the area of ​​low-concentration impurity layer 33 immediately above and adjacent to semiconductor substrate 32 form a common drain region in which the first drain region of transistor 10 and the second drain region of transistor 20 are shared. The metal layer 30 forms a common drain electrode in which the first drain electrode of transistor 10 and the second drain electrode of transistor 20 are shared.

[0029] 1 , the first body region 18 is covered with an interlayer insulating layer 34 having an opening, and a portion 13 of the first source electrode 11 connected to the first source region 14 is provided through the opening in the interlayer insulating layer 34. The interlayer insulating layer 34 and the portion 13 of the first source electrode 11 are covered with a passivation layer 35 having an opening, and a portion 12 connected to the portion 13 of the first source electrode 11 is provided through the opening in the passivation layer 35.

[0030] The second body region 28 is covered with an interlayer insulating layer 34 having an opening, and a portion 23 of the second source electrode 21 connected to the second source region 24 is provided through the opening in the interlayer insulating layer 34. The interlayer insulating layer 34 and the portion 23 of the second source electrode 21 are covered with a passivation layer 35 having an opening, and a portion 22 connected to the portion 23 of the second source electrode 21 is provided through the opening in the passivation layer 35.

[0031] Therefore, the first source pad 111 and the second source pad 121 respectively refer to regions where the first source electrode 11 and the second source electrode 21 are partially exposed on the surface of the semiconductor device 1, that is, so-called terminal portions. Similarly, the first gate pad 119 and the second gate pad 129 respectively refer to regions where the first gate electrode 19 (not shown in FIGS. 1 and 2) and the second gate electrode 29 (not shown in FIGS. 1 and 2) are partially exposed on the surface of the semiconductor device 1, that is, so-called terminal portions.

[0032] The material forming the first gate electrode 19 and the second gate electrode 29 may be the same as the material forming the first source electrode 11 and the second source electrode 21 .

[0033] As an example of the thickness of each structure in the semiconductor device 1, the semiconductor layer 40 is 10-90 μm thick, the metal layer 30 is 10-90 μm thick, and the sum of the thicknesses of the interlayer insulating layer 34 and the passivation layer 35 is 3-13 μm.

[0034] 1 and 2, the transistor 10 has a first source pad 111 and a first gate pad 119 on the surface of the semiconductor layer 40, which are bonded to a mounting substrate via a bonding material when mounted face-down. The transistor 20 has a second source pad 121 and a second gate pad 129 on the surface of the semiconductor layer 40, which are bonded to a mounting substrate via a bonding material when mounted face-down.

[0035] As shown in FIG. 2, the semiconductor layer 40 has a square shape in plan view.

[0036] 2, a virtual boundary line 90 that distinguishes the first region A1 from the second region A2 of the semiconductor layer 40 is shown by a dashed line. The boundary line 90 between the first region A1 and the second region A2 may be considered to be a virtual line that traces the center position of the gap between the portion 13 of the first source electrode 11 and the portion 23 of the second source electrode 21. Alternatively, it may be considered to be the gap itself, although it has a finite width. Even in the case of the gap, it can be recognized as a line by the naked eye or when viewed at low magnification.

[0037] In a plan view, the boundary line 90 is a straight imaginary line that is perpendicular to the first direction, bisects the area of ​​the semiconductor layer 40 in the first direction, and passes through the center of the semiconductor layer 40. The center of the semiconductor layer 40 is the intersection of two diagonals of the semiconductor layer 40 in a plan view.

[0038] The first direction is a direction parallel to the outer periphery of the semiconductor device 1 in plan view, in which the first region A1 and the second region A2 are aligned.

[0039] 2, the first region A1 and the second region A2 are adjacent to each other in a plan view, and are rectangular regions that halve the area of ​​the semiconductor layer 40. In a plan view, there is no part of the semiconductor layer 40 that is not included in either the first region A1 or the second region A2.

[0040] The outer periphery refers to the sides that form the outline of the shape, and in the case of a square shape such as the semiconductor layer 40 or a rectangular shape such as the first region A1, it refers to the four sides that form the respective shapes. In addition, in the case of a non-rectangular shape, it refers to the multiple sides that form the periphery of the shape.

[0041] As shown in FIG. 2, in the present disclosure, in a plan view, of the two sides of the outer periphery of the semiconductor layer 40 that are parallel to the boundary line 90, one side that is the shortest distance from the first gate pad 119 is designated as the first side S1, and the other side that is the shortest distance from the second gate pad 129 and faces the first side S1 is designated as the second side S2.

[0042] Similarly, in a planar view, of the two sides of the outer periphery of the semiconductor layer 40 that are perpendicular to the boundary line 90, one side that is the shortest distance from the first gate pad 119 is designated as the third side S3, and the other side that is the shortest distance from the first source pad 111 and faces the third side S3 is designated as the fourth side S4.

[0043] In addition, since the semiconductor layer 40 has a square shape in a plan view, the length of the first side S1, the length of the second side S2, the length of the third side S3, and the length of the fourth side S4 are the same.

[0044] The number of first source pads 111 of transistor 10 and the number of second source pads 121 of transistor 20 are each one, as shown in Figure 2. Also, the number of first gate pads 119 of transistor 10 and the number of second gate pads 129 of transistor 20 are each one, as shown in Figure 2.

[0045] That is, the semiconductor device 1 in the present disclosure is a dual-configuration vertical MOS transistor having a common drain electrode and including two vertical MOS transistors in one semiconductor device, and is a four-pad configuration semiconductor device having one pad corresponding to each of the source electrode and gate electrode of each vertical MOS transistor.

[0046] The shape, size, and arrangement of the pads in a plan view shown in FIG. 2 are one example, but it is preferable that the shapes and sizes of the four pads (first source pad 111, first gate pad 119, second source pad 121, and second gate pad 129) are uniform, and it is further desirable that they be circular with the same diameter.

[0047] 3 is a schematic plan view showing an example of the shapes and arrangement of the components of the semiconductor device 1. In FIG. 3, the passivation layer 35 and the interlayer insulating layer 34 are omitted as if they were transparent so that the structure of the upper surface of the semiconductor layer 40, which is not actually visible, can be clearly shown. The pads shown with dotted lines are shown to make it easier to understand the correspondence with FIG. 2.

[0048] 3 , in a plan view, the shapes and arrangement of the components provided in the first region A1 and the shapes and arrangement of the components provided in the second region A2 that correspond to the first region A1 on a 1:1 basis are arranged in a line-symmetric relationship with the boundary line 90 as the axis of symmetry. The components that correspond to the first region A1 on a 1:1 basis include, for example, the first gate electrode 19 and the second gate electrode 29, the first source pad 111 and the second source pad 121, and the first gate resistor element 41 and the second gate resistor element 51 described below. The same is true for the first control region C1 and the second control region C2 described below. These are arranged in a line-symmetric relationship with the boundary line 90 as the axis of symmetry in a plan view.

[0049] As shown in FIG. 3, a first gate resistance element 41 connected to the first gate electrode 19 is formed in the first region A1 of the semiconductor device 1, and a second gate resistance element 51 connected to the second gate electrode 29 is formed in the second region A2 of the semiconductor device 1.

[0050] As a non-limiting example, the first gate resistance element 41 and the second gate resistance element 51 are made of polysilicon into which impurities of the first conductivity type or the second conductivity type have been implanted, and each gate resistance element is made of a material having a higher resistance value than the metal material that constitutes the source electrode, etc.

[0051] The first gate resistance element 41 and the second gate resistance element 51 are provided for the purpose of preventing the transistor 10 and the transistor 20 from being destroyed when an excessive voltage is applied to the gate electrode or a surge current flows. In other words, the first gate resistance element 41 and the second gate resistance element 51 are elements provided to increase the ESD resistance of the semiconductor device 1.

[0052] 3, the first region A1 of the semiconductor device 1 is provided with a first gate wiring 42 that is connected to the first gate electrode 19 via a first gate resistance element 41 and that is arranged to surround the first source electrode 11. Similarly, the second region A2 of the semiconductor device 1 is provided with a second gate wiring 52 that is connected to the second gate electrode 29 via a second gate resistance element 51 and that is arranged to surround the second source electrode 21.

[0053] The first gate wiring 42 and the second gate wiring 52 are formed, as a non-limiting example, from polysilicon doped with impurities of the first or second conductivity type or from the same metal species as the first gate electrode 19 and the second gate electrode 29, and the first gate wiring 42 and the second gate wiring 52 are connected to the first gate conductor 15 and the second gate conductor 25, respectively.

[0054] 3 , in plan view, the first region A1 is provided with a first Zener diode 43 connected to the first source electrode 11 and the first gate electrode 19 and disposed around the first gate electrode 19. Similarly, the second region A2 is provided with a second Zener diode 53 connected to the second source electrode 21 and the second gate electrode 29 and disposed around the second gate electrode 29.

[0055] As a non-limiting example, the first Zener diode 43 and the second Zener diode 53 may be bidirectional Zener diodes having one or more PN junctions and made of polysilicon doped with impurities of the first conductivity type or the second conductivity type.

[0056] The first Zener diode 43 and the second Zener diode 53 are provided for the purpose of preventing the transistor 10 and the transistor 20 from being destroyed when an excessive voltage is applied to the gate electrode or the source electrode or when a surge current flows. In other words, the first Zener diode 43 and the second Zener diode 53 are elements provided to enhance the ESD resistance of the semiconductor device 1.

[0057] Although not shown in FIG. 3, the first region A1 is provided with a first connection region where the first Zener diode 43 and the first source electrode 11 are connected, and the second region A2 is provided with a second connection region where the second Zener diode 53 and the second source electrode 21 are connected (see FIG. 14).

[0058] The first connection region and the second connection region are made of the same metal type as the portion 13 of the first source electrode 11 and the portion 23 of the second source electrode 21, and in a planar view, the first gate trench 17 and the second gate trench 27 are not located directly below them.

[0059] 3, a first EQR (Equi potential Ring) 44 electrically connected to the semiconductor substrate 32, which is a common drain region, may be provided on the periphery of the first region A1 in plan view. Similarly, a second EQR 54 electrically connected to the semiconductor substrate 32, which is a common drain region, may be provided on the periphery of the second region A2 in plan view. The first EQR 44 and the second EQR 54 may be shared in a portion where the transistor 10 and the transistor 20 are adjacent and facing each other in plan view.

[0060] The first EQR 44 and the second EQR 54 may be made common, and the portion perpendicular to the first direction may be regarded as the boundary line 90 .

[0061] The first EQR 44 is provided for the transistor 10 in the hope of preventing leakage current from flowing between the outside and the first body region 18. The second EQR 54 is provided for the transistor 20 in the hope of preventing leakage current from flowing between the outside and the second body region 28.

[0062] The first EQR 44 and the second EQR 54 may be made of a metal material including, by way of example and not limitation, any one or more of aluminum, copper, gold, and silver, and may be electrically connected to the metal layer 30 via the semiconductor substrate 32, which is a common drain region.

[0063] As shown in FIG. 3, in the first region A1, in a plan view, a rectangular region that includes the first gate pad 119 and has the largest area within the range that does not include both the first source electrode 11 and the first gate resistance element 41 is called the first gate electrode region G1.

[0064] Similarly, as shown in FIG. 3, in the second region A2, in a plan view, a rectangular region that includes the second gate pad 129 and has the largest area within the range that does not include both the second source electrode 21 and the second gate resistance element 51 is called the second gate electrode region G2.

[0065] As shown in FIG. 3, in the first region A1, in a plan view, a rectangular region that contains the first gate resistor element 41 and has the largest area within the range that does not include both the first source electrode 11 and the first gate electrode region G1 is called the first resistor element region R1.

[0066] Similarly, as shown in FIG. 3, in the second region A2, in a plan view, a rectangular region that contains the second gate resistance element 51 and has the largest area within the range that does not include both the second source electrode 21 and the second gate electrode region G2 is called the second resistance element region R2.

[0067] In plan view, the first gate electrode region G1 and the first resistor region R1 do not overlap due to the definitions that determine the range of each region, although the outer peripheries of each region may overlap in some parts in plan view.

[0068] Similarly, in plan view, the second gate electrode region G2 and the second resistor region R2 do not overlap due to the definitions that determine the range of each region, although the outer peripheries of each region may overlap in some parts in plan view.

[0069] In this disclosure, when it is stated that the outer perimeter of one region coincides with the outer perimeter of another region in a planar view, this may be understood to mean that the respective outer perimeters overlap or are common.

[0070] As shown in FIG. 3, in a plan view, at least one side of the periphery of the first gate electrode region G1 and at least one side of the periphery of the first resistor region R1 both coincide with part of the third side S3 of the semiconductor layer 40.

[0071] Similarly, as shown in FIG. 3, in a plan view, at least one side of the outer periphery of the second gate electrode region G2 and at least one side of the outer periphery of the second resistor region R2 both coincide with a portion of the third side S3 of the semiconductor layer 40.

[0072] Also, as shown in Figure 3, in a planar view, the outer periphery of the first resistor region R1 includes only one corner (also called the first corner P1) of the four corners on the outer periphery of the first gate electrode region G1 that has the shortest distance from the boundary line 90 and the shortest distance from the third side S3 of the semiconductor layer 40, and does not include the other corners.

[0073] Similarly, as shown in FIG. 3, in a plan view, the outer periphery of the second resistor region R2 includes only one corner (also referred to as the second corner P2) of the four corners on the outer periphery of the second gate electrode region G2 that has the shortest distance from the boundary line 90 and the shortest distance from the third side S3 of the semiconductor layer 40, and does not include the other corners.

[0074] 3, in a plan view, the region in the first region A1 that combines the first gate electrode region G1 and the first resistor region R1 is referred to as a first control region C1. Similarly, in a plan view, the region in the second region A2 that combines the second gate electrode region G2 and the second resistor region R2 is referred to as a second control region C2.

[0075] As shown in Figure 3, in a planar view of the semiconductor device 1, at least one side of the outer periphery of the first control region C1 and at least one side of the outer periphery of the second control region C2 both coincide with a portion of the third side S3 of the semiconductor layer 40, and the outer periphery of the first control region C1 and the outer periphery of the second control region C2 do not have a portion that coincides with the fourth side S4 of the semiconductor layer 40.

[0076] Furthermore, as shown in Figure 3, in a planar view, the length of the portion where the outer periphery of the first control region C1 coincides with the outer periphery of the semiconductor layer 40 is the longest at the portion where the outer periphery of the first control region C1 coincides with the third side S3 of the semiconductor layer 40.

[0077] Similarly, as shown in Figure 3, in a planar view, the length of the portion where the outer periphery of the second control region C2 coincides with the outer periphery of the semiconductor layer 40 is longest at the portion where the outer periphery of the second control region C2 coincides with the third side S3 of the semiconductor layer 40.

[0078] 3 shows an example in which, in a plan view, the outer periphery of the first control region C1 and the outer periphery of the second control region C2 respectively coincide with part of the first side S1 and part of the second side S2 of the semiconductor layer 40. However, in the semiconductor device 1 according to the present embodiment, the outer periphery of the first control region C1 and the outer periphery of the second control region C2 do not need to have parts which coincide with part of the first side S1 and part of the second side S2 of the semiconductor layer 40 respectively in a plan view.

[0079] 3 also shows an example in which, in a plan view, the outer periphery of the first control region C1 and the outer periphery of the second control region C2 each coincide with part of the boundary line 90. However, in the semiconductor device 1 according to this embodiment, the outer periphery of the first control region C1 and the outer periphery of the second control region C2 do not need to have a part that coincides with part of the boundary line 90 in a plan view.

[0080] FIG. 4 is a circuit diagram showing an equivalent circuit of the semiconductor device 1 according to the present embodiment.

[0081] As shown in FIG. 4, in the transistor 10, the first gate resistor element 41 and the first Zener diode 43 are connected in parallel between the first gate pad 119 and the first source pad 111, respectively.

[0082] Of these, the path through which current flows between the first gate pad 119 and the first source pad 111 via the first Zener diode 43 becomes conductive when an excessive voltage is applied to the first gate pad 119 or the first source pad 111 or a surge current flows due to the function of the first Zener diode 43.

[0083] Generally, breakdown of the gate insulating film is a breakdown mode of a vertical MOS transistor caused by the application of excessive voltage or the flow of surge current. By providing the first Zener diode 43 in the transistor 10, the surge current can be shunted and the load on the first gate insulating film 16 can be reduced. This prevents breakdown of the first gate insulating film 16, thereby improving the ESD resistance of the transistor 10.

[0084] Furthermore, by providing the first gate resistor element 41 in parallel with the first Zener diode 43, the surge current flowing through the first gate insulating film 16 can be further significantly reduced, thereby further improving the ESD resistance of the transistor 10.

[0085] The above description has been given taking as an example a case where an excessive voltage is applied or a surge current flows to the first gate pad 119 or the first source pad 111 of the transistor 10. The same applies to a case where an excessive voltage is applied or a surge current flows to the second gate pad 129 or the second source pad 121 of the transistor 20. Providing the second Zener diode 53 and the second gate resistor element 51 in the transistor 20 can prevent the second gate insulating film 26 from being destroyed, thereby improving the ESD resistance of the transistor 20.

[0086] 5A and 5B are a plan view and a perspective view, respectively, of a general unit configuration of transistor 10 or transistor 20 repeatedly formed in the X direction and the Y direction of semiconductor device 1. For ease of understanding, semiconductor substrate 32 and metal layer 30, passivation layer 35 and first source electrode 11 or second source electrode 21, and interlayer insulating layer 34 are not shown in FIGS.

[0087] The Y direction is parallel to the upper surface of the semiconductor layer 40 and is the direction in which the first gate trench 17 extends. The X direction is parallel to the upper surface of the semiconductor layer 40 and is perpendicular to the Y direction. The Z direction is perpendicular to both the X direction and the Y direction and is the direction indicating the height direction of the semiconductor device 1.

[0088] 5A and 5B , the transistor 10 includes a first connection portion 18a that electrically connects the first body region 18 and the first source electrode 11. The first connection portion 18a is a region of the first body region 18 in which the first source region 14 is not formed, and contains the same second conductivity type impurity as the first body region 18. The first source regions 14 and the first connection portion 18a are alternately and periodically arranged in the Y direction. The same applies to the transistor 20.

[0089] In the semiconductor device 1, for example, the first conductivity type may be N-type and the second conductivity type may be P-type, and the first source region 14, the second source region 24, the semiconductor substrate 32, and the low-concentration impurity layer 33 may be N-type semiconductors, and the first body region 18, the first connection portion 18a, the second body region 28, and the second connection portion 28a may be P-type semiconductors.

[0090] Furthermore, in the semiconductor device 1, for example, the first conductivity type may be P-type and the second conductivity type may be N-type, with the first source region 14, the second source region 24, the semiconductor substrate 32, and the low-concentration impurity layer 33 being P-type semiconductors, and the first body region 18, the first connection portion 18 a, the second body region 28, and the second connection portion 28 a being N-type semiconductors.

[0091] In the following description, the bidirectional conduction paths of the semiconductor device 1 will be described assuming that the transistors 10 and 20 are so-called N-channel transistors, with the first conductivity type being N-type and the second conductivity type being P-type.

[0092] In the semiconductor device 1, when a high voltage is applied to the first source electrode 11 and a low voltage is applied to the second source electrode 21, and a voltage equal to or greater than the threshold is applied to the second gate electrode 29 (second gate conductor 25) with the second source electrode 21 as the reference, a conduction channel is formed near the second gate insulating film 26 in the second body region 28. As a result, a current flows through the path of the first source electrode 11-first connection portion 18a-first body region 18-low-concentration impurity layer 33-semiconductor substrate 32-metal layer 30-semiconductor substrate 32-low-concentration impurity layer 33-conductive channel formed in the second body region 28-second source region 24-second source electrode 21, bringing the semiconductor device 1 into a conductive state. In this conduction path, a PN junction is formed at the contact surface between the first body region 18 and the low-concentration impurity layer 33, which functions as a body diode.

[0093] Similarly, in the semiconductor device 1, when a high voltage is applied to the second source electrode 21 and a low voltage is applied to the first source electrode 11, and a voltage equal to or greater than the threshold is applied to the first gate electrode 19 (first gate conductor 15) with the first source electrode 11 as the reference, a conductive channel is formed near the first gate insulating film 16 in the first body region 18. As a result, a current flows through the path of the second source electrode 21, the second connection portion 28a, the second body region 28, the low-concentration impurity layer 33, the semiconductor substrate 32, the metal layer 30, the semiconductor substrate 32, the low-concentration impurity layer 33, the conductive channel formed in the first body region 18, the first source region 14, and the first source electrode 11, bringing the semiconductor device 1 into a conductive state. A PN junction is present at the contact surface between the second body region 28 and the low-concentration impurity layer 33 along this conductive path, and functions as a body diode.

[0094] Furthermore, in the semiconductor device 1, a voltage equal to or higher than the threshold value may be applied to the first gate electrode 19 to form a conduction channel in the first body region 18 near the first gate insulating film 16, and simultaneously a voltage equal to or higher than the threshold value may be applied to the second gate electrode 29 to form a conduction channel in the second body region 28 near the second gate insulating film 26. As a result, a current may flow through a path from the first source electrode 11 to the first source region 14, the conduction channel formed in the first body region 18, the low-concentration impurity layer 33, the semiconductor substrate 32, the metal layer 30, the semiconductor substrate 32, the low-concentration impurity layer 33, the conduction channel formed in the second body region 28, the second source region 24, and the second source electrode 21, or through the reverse path, thereby making the semiconductor device 1 conductive.

[0095] 6 is a schematic plan view showing an example of the shapes and arrangements, in a plan view, of the first body region 18, the second body region 28, the first active region 112, and the second active region 122, among the components of the semiconductor device 1. In FIG. 6, the passivation layer 35, the first source electrode 11, the first gate electrode 19, the second source electrode 21, the second gate electrode 29, and the interlayer insulating layer 34 are omitted to make them appear transparent, so as to clearly show the structure of the upper surface of the semiconductor layer 40, which is not actually visible. The first source region 14 and the second source region 24 are also omitted. The pads indicated by dotted lines are shown to facilitate understanding of the correspondence with FIGS. 2 and 3 .

[0096] The first active region 112 refers to the smallest area that includes all of the portions where a conduction channel is formed when a voltage equal to or greater than the threshold voltage is applied to the first gate electrode 19 (first gate conductor 15) of the transistor 10. The portions where a conduction channel is formed are portions where each of the multiple first gate trenches 17 is adjacent to the first source region 14. As shown in FIG. 6 , in a plan view of the semiconductor layer 40, the first active region 112 is included in the first body region 18.

[0097] The second active region 122 refers to the smallest range that includes all of the portions where a conductive channel is formed when a voltage equal to or greater than the threshold voltage is applied to the second gate electrode 29 (second gate conductor 25) of the transistor 20. The portions where a conductive channel is formed are portions where each of the multiple second gate trenches 27 is adjacent to the second source region 24. As shown in FIG. 6 , the second active region 122 is included in the second body region 28 in a plan view of the semiconductor layer 40.

[0098] In order to reduce the conduction resistance of the semiconductor device 1, it is necessary to ensure that the first active region 112 and the second active region 122 are as large as possible. If the area of ​​the first active region 112 and the area of ​​the second active region 122 are large, the conduction path of the semiconductor device 1 is expanded, and therefore the conduction resistance of the semiconductor device 1 is reduced.

[0099] 3, the first control region C1 and the second control region C2 are regions in which the first active region 112 and the second active region 122 are not formed, and are regions that do not contribute to the conduction of the semiconductor device 1. In other words, the first control region C1 and the second control region C2 are regions that are necessary for the semiconductor device 1 to function, but on the other hand, they are regions that should be reduced as much as possible in order to reduce the conduction resistance of the semiconductor device 1 within the limited device area.

[0100] [3. Consideration] The semiconductor device 1 according to the present disclosure described above has the following features.

[0101] A semiconductor device 1 according to one aspect of the present disclosure is a chip-size package type semiconductor device 1 that can be mounted face-down, and includes a semiconductor layer 40 including a semiconductor substrate 32, a first vertical MOS transistor 10 entirely formed in a first region A1 of the semiconductor layer 40 on the upper surface side of the semiconductor layer 40, a second vertical MOS transistor 20 entirely formed in a second region A2 adjacent to the first region A1 in a plan view of the semiconductor layer 40, and a metal layer 30 formed in contact with the semiconductor substrate 32 on the lower surface side of the semiconductor layer 40, and the semiconductor substrate 32 is The semiconductor layer 40 has a square shape in plan view, the first region A1 and the second region A2 are aligned in a first direction in plan view, a boundary line 90 between the first region A1 and the second region A2 is perpendicular to the first direction, divides the semiconductor layer 40 into two equal parts in area, and is a straight line passing through the center of the semiconductor layer 40, and the pads provided in the first region A1 in plan view are one first source pad 1 connected to a first source electrode 11 of the first vertical MOS transistor 10. 11 and one first gate pad 119 connected to a first gate electrode 19 of the first vertical MOS transistor 10, and the first vertical MOS transistor 10 includes a first gate resistor element 41 connected to the first gate electrode 19, a first gate electrode region G1 which is a rectangular region containing the first gate pad 119 in a plan view and has the largest area within a range that does not include both the first source electrode 11 and the first gate resistor element 41, and a first gate electrode region G2 which is a rectangular region containing the first gate resistor element 41 in a plan view and has the largest area within a range that does not include both the first source electrode 11 and the first gate resistor element 41. and a first resistor region R1 having the largest area within a range not including both the first gate electrode region G1 and the first gate pad 119, and in plan view, the total length of one side of the outer periphery of the first gate electrode region G1 and the total length of one side of the outer periphery of the first resistor region R1 coincide with a part of a side of the outer periphery of the semiconductor layer 40 that is perpendicular to the boundary line 90 and has the shortest distance from the boundary line 90, and in plan view, the outer periphery of the first resistor region R1 includes a corner of the outer periphery of the first gate electrode region G1 that is the shortest distance from the boundary line 90, andThe semiconductor device 1 includes only one corner (first corner P1) where the distance between the boundary line 90 and the side perpendicular to the boundary line 90 is the shortest.

[0102] 8, 10, 11, 12, 13, and 14 are plan schematic diagrams showing examples of the shapes and arrangements of the components of the semiconductor device 1 according to this embodiment that satisfy the above conditions. In FIGS. 8, 10, 11, 12, 13, and 14, the passivation layer 35 and the interlayer insulating layer 34 are omitted as if they were transparent, in order to make it easier to understand the structure of the upper surface of the semiconductor layer 40, which is not actually visible. The pads indicated by dotted lines would normally be invisible if the passivation layer 35 were omitted, but are shown as they are for clarity.

[0103] Before describing the features and effects of the shapes and arrangements of the components shown in Figure 8 and subsequent figures, a semiconductor device 2 according to a comparative example 1 of this embodiment will first be described with reference to Figures 7A and 7B. As components of the semiconductor device 2 according to the comparative example 1 are already described, they are assigned the same reference numerals and detailed description thereof will be omitted, and the description will focus on the differences from the semiconductor device 1.

[0104] It has been explained that providing a gate resistor element in a semiconductor device improves the ESD resistance of the semiconductor device. However, using a semiconductor device 2 according to Comparative Example 1, it will be explained that, depending on the positions at which the gate electrode and gate resistor element are arranged in a plan view of the semiconductor layer, there may be areas that have a low contribution to conduction despite being active regions.

[0105] 7A is a schematic plan view showing the shapes and arrangement of the components of the semiconductor device 2 in a plan view of the semiconductor layer 40. In order to make it easier to understand the structure of the upper surface of the semiconductor layer 40, which is not actually visible, the passivation layer 35 and the interlayer insulating layer 34 are omitted in Fig. 7A as if they were transparent. The pads indicated by dotted lines would actually become invisible if the passivation layer 35 were omitted, but are shown as they are for ease of understanding.

[0106] 7B is a schematic plan view showing the shapes and arrangements, in a plan view, of the first body region 18, the second body region 28, the first active region 112, and the second active region 122, among the components of the semiconductor device 2. In addition to the omissions in FIG. 7A, the first source electrode 11, the first gate electrode 19, the second source electrode 21, and the second gate electrode 29 are also omitted from FIG. 7B. The first source region 14 and the second source region 24 are also omitted from the illustration.

[0107] The semiconductor layer 40 of the semiconductor device 2 according to the first comparative example has the same shape and area as the semiconductor layer 40 of the semiconductor device 1 according to the embodiment in plan view.

[0108] 7A , in a plan view, a first control region C1, which combines a first gate electrode region G1 and a first resistor region R1, is formed in a first region A1 of the semiconductor device 2. A second control region C2, which combines a second gate electrode region G2 and a second resistor region R2, is formed in a second region A2. In a plan view, the areas of the first control region C1 and the second control region C2 are the same in the semiconductor device 1 according to the embodiment and the semiconductor device 2 according to the comparative example 1 (see FIG. 3 ).

[0109] 7A , in a plan view, one side of the outer periphery of the first resistor region R1 coincides with part of the third side S3 of the semiconductor layer 40. However, the outer periphery of the first gate electrode region G1 does not have a portion that coincides with the outer periphery of the semiconductor layer 40. Furthermore, the outer periphery of the first resistor region R1 does not include the first corner P1, among the four corners on the periphery of the first gate electrode region G1. Note that, as defined in the semiconductor device 1 according to the embodiment, the first corner P1 is the corner that is shortest in plan view among the four corners on the periphery of the first gate electrode region G1 and that is also shortest in distance from the boundary line 90 to the side of the outer periphery of the semiconductor layer 40 that is perpendicular to the boundary line 90.

[0110] Similarly, in a plan view, one side of the outer periphery of the second resistor region R2 coincides with part of the third side S3 of the semiconductor layer 40. However, the outer periphery of the second gate electrode region G2 does not have a portion that coincides with the outer periphery of the semiconductor layer 40. Furthermore, the outer periphery of the second resistor region R2 does not include the second corner P2 of the four corners on the outer periphery of the second gate electrode region G2. Note that, as defined in the semiconductor device 1 according to the embodiment, the second corner P2 is the corner that is shortest in plan view among the four corners on the outer periphery of the second gate electrode region G2 in terms of distance from the boundary line 90 and that is shortest in terms of distance from the side of the outer periphery of the semiconductor layer 40 that is perpendicular to the boundary line 90.

[0111] The area of ​​the first active region 112 and the area of ​​the second active region 122 in the planar view of the semiconductor device 2 shown in Figure 7B are the same as the area of ​​the first active region 112 and the area of ​​the second active region 122 in the planar view of the semiconductor device 1 according to the embodiment (see Figure 6).

[0112] 7B , in plan view, the first active region 112 of the semiconductor device 2 has a relatively narrow region between the first gate electrode region G1 and the boundary line 90 or between the first gate electrode region G1 and the first side S1 of the semiconductor layer 40. The relatively narrow region between the first gate electrode region G1 and the boundary line 90 or between the first gate electrode region G1 and the first side S1 of the semiconductor layer 40 is called a first narrow path region N1.

[0113] Similarly, in a plan view, the second active region 122 of the semiconductor device 2 has a relatively narrow region between the second gate electrode region G2 and the boundary line 90 or between the second gate electrode region G2 and the second side S2 of the semiconductor layer 40. The relatively narrow region between the second gate electrode region G2 and the boundary line 90 or between the second gate electrode region G2 and the second side S2 of the semiconductor layer 40 is called a second narrow path region N2.

[0114] 7B , in plan view, the first active region 112 of the semiconductor device 2 has a region that cannot be reached without passing through the first narrowing region N1 when viewed from the first source pad 111. This is called a first dead end region D1.

[0115] Similarly, in a plan view, the second active region 122 of the semiconductor device 2 has a region that cannot be reached without passing through the second narrowing region N2 when viewed from the second source pad 121. This is called a second dead end region D2.

[0116] When current flows in from the first source pad 111, the portion of the first source electrode 11 formed near the first source pad 111 is sufficiently wide so that the conduction resistance is low and the region can be effectively utilized for conduction.

[0117] In contrast, current cannot reach the portion of the first source electrode 11 formed in the first dead end region D1 without passing through the first constriction region N1 as viewed from the first source pad 111. However, the portion of the first source electrode 11 formed in the first constriction region N1 has a narrow width in a plan view, so the conduction resistance when current passes through this portion is relatively high. For this reason, current does not easily flow through the portion of the first source electrode 11 formed in the first constriction region N1, and furthermore, current does not easily reach the portion of the first source electrode 11 formed in the first dead end region D1 beyond the first constriction region N1.

[0118] That is, although the first narrowing region N1 and the first dead end region D1 are both part of the first active region 112 and have mechanisms that can contribute to conduction, the current density does not increase and they remain in regions that are relatively unlikely to contribute to conduction. The same applies to the second narrowing region N2 and the second dead end region D2.

[0119] Therefore, in plan view, the semiconductor device 2 according to Comparative Example 1 does not have an arrangement that can effectively utilize the remaining limited area after the first control region C1 and the second control region C2 are provided, in order to reduce the conduction resistance. In order to reduce the conduction resistance, it is preferable to use an arrangement that minimizes the occurrence of the first narrowing region N1 and the second narrowing region N2, and the first dead end region D1 and the second dead end region D2, which relatively reduce the contribution to conduction.

[0120] As shown in FIG. 3, in the semiconductor device 1 according to the present disclosure, in a plan view, the first gate electrode region G1 and the first resistor region R1 are arranged so that the entire length of one side of the outer periphery of each of the first gate electrode region G1 and the first resistor region R1 coincides with a portion of the third side S3 of the semiconductor layer 40, and therefore a first dead end region D1 does not occur.

[0121] Similarly, in the semiconductor device 1 according to the present disclosure, in a planar view, the second gate electrode region G2 and the second resistor region R2 are arranged so that the total length of one side of the outer periphery of each of the second gate electrode region G2 and the second resistor region R2 coincides with a portion of the third side S3 of the semiconductor layer 40, and therefore a second dead end region D2 does not occur.

[0122] Therefore, in the semiconductor device 1, while having the same area of ​​the active region, the area that contributes relatively more to conduction can be expanded compared to the semiconductor device 2 according to the comparative example 1. In other words, this is an arrangement that can effectively utilize the limited area of ​​the semiconductor device 1, and can reduce the conduction resistance.

[0123] However, when mounting the semiconductor device 1 face-down on a mounting board, if the distance between the pads on the semiconductor device 1 is short in a plan view, there is a risk that the solder connecting the semiconductor device 1 to the mounting board may come into contact with each other. For this reason, it is necessary to maintain a constant distance between the pads on the semiconductor device 1. As a non-limiting example, the constant distance is the same as the diameter of the pads on the semiconductor device 1.

[0124] 8 , in the semiconductor device 1, the first resistor region R1 is desirably disposed between the boundary line 90 and a side of the periphery of the first gate electrode region G1 that is the shortest distance from the boundary line 90, in a plan view of the semiconductor layer 40. More desirably, the first resistor region R1 is disposed so that the entire length of one side of the periphery of the first gate electrode region G1 coincides with part of the side of the periphery of the first gate electrode region G1 that is the shortest distance from the boundary line 90.

[0125] Similarly, it is desirable to arrange the second resistor region R2 between the boundary line 90 and a side of the periphery of the second gate electrode region G2 that is the shortest distance from the boundary line 90. It is more desirable to arrange the second resistor region R2 so that the entire length of one side of the periphery of the second resistor region R2 coincides with a part of the side of the periphery of the second gate electrode region G2 that is the shortest distance from the boundary line 90.

[0126] By arranging them in this manner, the area between the first gate pad 119 and the second gate pad 129, which is provided to prevent mounting problems due to contact between solders, can be used efficiently as an area for arranging the first gate resistance element 41 and the second gate resistance element 51.

[0127] The above advantages will now be described in more detail.

[0128] 8, areas where the area can be reduced are shown on both sides in the X direction. These are areas where the area can be reduced reasonably if further miniaturization of the semiconductor device 1 is required. As explained above, a certain width must be secured in the area between the first gate pad 119 and the second gate pad 129 to prevent the solder from contacting each other, and excessive reduction is not advisable.

[0129] 8 , the end of the semiconductor device 1 in the X direction of the first active region 112 (or the first source electrode 11) in plan view is a region where the area can be easily reduced. In the first region A1 in plan view, the end is a strip-shaped region in the Y direction that is located between the first side S1 of the semiconductor layer 40 and the side of the periphery of the first gate electrode region G1 that is the shortest distance from the first side S1 of the semiconductor layer 40.

[0130] Similarly, the area of ​​the second active region 122 (or the second source electrode 21) in the X direction of the semiconductor device 1 can be easily reduced in plan view. In plan view, the second region A2 is a strip-shaped region in the Y direction that is located between the second side S2 of the semiconductor layer 40 and the side of the periphery of the second gate electrode region G2 that is the shortest distance from the second side S2 of the semiconductor layer 40.

[0131] That is, in the semiconductor device 1 according to this embodiment shown in FIG. 8, the first resistor region R1 and the second resistor region R2 are arranged so as to be sandwiched between the region between the first gate electrode region G1 and the second gate electrode region G2, which makes it possible to further reduce the area of ​​the semiconductor layer 40, i.e., to meet the demand for miniaturization of the semiconductor device 1.

[0132] 9A to 9E, semiconductor devices 3 to 7 according to comparative examples 2 to 6 of the present embodiment will be described. Regarding semiconductor devices 3 to 7 according to comparative examples 2 to 6, components similar to those of semiconductor device 1 will be assigned the same reference numerals as those already described, and detailed description thereof will be omitted. The description will focus on the differences from semiconductor device 1.

[0133] By showing comparative examples 2 to 6 in Figures 9A to 9E, the advantage of the semiconductor device 1 of this embodiment, in which the outer periphery of the first resistor region R1 and the outer periphery of the second resistor region R2 each include only the first corner P1 on the outer periphery of the first gate electrode region G1 and the second corner P2 on the outer periphery of the second gate electrode region G2, respectively, is explained.

[0134] 9A to 9E are schematic plan views showing the shapes and arrangements of the components of semiconductor devices 3 to 7, respectively, in a plan view of semiconductor layer 40. For ease of understanding, FIGS. 9A to 9E separate and extract only the first region A1 of semiconductor layer 40 from the components of semiconductor devices 3 to 7, and further show only the first source electrode 11, the first source pad 111, the first gate pad 119, the first gate electrode region G1, and the first resistor region R1, while omitting other components. The shape and arrangement of each component in the second region A2 of semiconductor layer 40 in a plan view can be considered to be in a line-symmetric relationship with the shape and arrangement of each component in the first region A1 in a one-to-one correspondence, with respect to boundary line 90 as the axis of symmetry.

[0135] In semiconductor devices 3 to 7 according to comparative examples 2 to 6, the first region A1 of the semiconductor layer 40 has the same shape and area as the first region A1 of the semiconductor layer 40 of the semiconductor device 1 according to the embodiment in plan view. The first gate electrode region G1, the first resistor region R1, the first active region 112, the first source pad 111, etc. also have the same area.

[0136] As shown in Figures 9A to 9E, semiconductor devices 3 to 7 according to comparative examples 2 to 6 have in common that the total length of one side of the outer periphery of the first gate electrode region G1 coincides with a portion of the third side S3 of the semiconductor layer 40.

[0137] 9A is a schematic plan view of a semiconductor device 3 according to Comparative Example 2. In the semiconductor device 3, the outer periphery of the first resistor region R1 in plan view includes only one of the four corners on the periphery of the first gate electrode region G1, which has the shortest distance from the boundary line 90 but is not the shortest distance from the third side S3 of the semiconductor layer 40 (i.e., the shortest distance from the fourth side S4 of the semiconductor layer 40). Furthermore, in the semiconductor device 3, the first resistor region R1 is disposed in the region between the first gate electrode region G1 and the boundary line 90 in plan view.

[0138] 9A results in a first dead end region D1 in the semiconductor device 3. Therefore, compared to the semiconductor device 1 (FIG. 8) according to the embodiment, this arrangement makes it difficult to reduce the conduction resistance even if the area of ​​the first active region 112 is the same.

[0139] 9B is a schematic plan view of the semiconductor device 4 according to Comparative Example 3. In the semiconductor device 4, the outer periphery of the first resistor region R1 in plan view includes only one corner of the four corners on the outer periphery of the first gate electrode region G1, which has the shortest distance from the boundary line 90 but is not the shortest distance from the third side S3 of the semiconductor layer 40 (i.e., the shortest distance from the fourth side S4 of the semiconductor layer 40).

[0140] 9C is a schematic plan view of the semiconductor device 5 according to Comparative Example 4. In the semiconductor device 5, the outer periphery of the first resistor region R1 in plan view includes only one corner, of the four corners on the outer periphery of the first gate electrode region G1, that is the corner that is the shortest in distance to the first side S1 of the semiconductor layer 40 and that is the shortest in distance to the fourth side S4 of the semiconductor layer 40.

[0141] Furthermore, in the semiconductor device 4 and the semiconductor device 5, the first resistor region R1 is disposed in the region between the first gate electrode region G1 and the first source pad 111 in plan view.

[0142] 9B and 9C, a part of the region near first source pad 111, which contributes relatively more to conduction, is replaced with first resistor region R1, which does not contribute to conduction. Therefore, compared to semiconductor device 1 (FIG. 8) according to the embodiment, this arrangement makes it difficult to reduce the conduction resistance even if the area of ​​first active region 112 is the same.

[0143] 9D is a schematic plan view of a semiconductor device 6 according to Comparative Example 5. In the semiconductor device 6, the outer periphery of the first resistor region R1 in plan view includes only one corner, of the four corners on the outer periphery of the first gate electrode region G1, that is the corner that is the shortest in distance to the first side S1 of the semiconductor layer 40 and that is the shortest in distance to the fourth side S4 of the semiconductor layer 40.

[0144] 9E is a schematic plan view of the semiconductor device 7 according to Comparative Example 6. In the semiconductor device 7, the outer periphery of the first resistor region R1 in plan view includes only one corner, out of the four corners on the outer periphery of the first gate electrode region G1, which has the shortest distance to the third side S3 of the semiconductor layer 40 but is not the shortest distance to the boundary line 90 (i.e., the shortest distance to the first side S1 of the semiconductor layer 40).

[0145] Furthermore, in the semiconductor devices 6 and 7, the first resistor region R1 is disposed in the region between the first gate electrode region G1 and the first side S1 of the semiconductor layer 40 in plan view.

[0146] Therefore, the arrangement of semiconductor device 6 shown in FIG. 9D and the arrangement of semiconductor device 7 shown in FIG. 9E cannot accommodate the demand for reducing the area of ​​semiconductor layer 40 (reducing the size of semiconductor device 1), as described above with reference to FIG. 8.

[0147] 9D , a first dead end region D1 occurs in the semiconductor device 6. Therefore, compared to the semiconductor device 1 ( FIG. 8 ) according to the embodiment, this arrangement makes it difficult to reduce the conduction resistance even if the area of ​​the first active region 112 is the same.

[0148] As described above, as in the semiconductor device 1 according to this embodiment shown in FIG. 3 or FIG. 8, it is most desirable that, in a plan view, the outer periphery of the first resistor region R1 includes only one corner (first corner P1) among the four corners on the outer periphery of the first gate electrode region G1, which has the shortest distance from the boundary line 90 and the shortest distance from the third side S3 of the semiconductor layer 40.

[0149] Similarly, in a planar view, it is most desirable that the outer periphery of the second resistor region R2 includes only one corner (second corner P2) of the four corners on the outer periphery of the second gate electrode region G2 that has the shortest distance from the boundary line 90 and the shortest distance from the third side S3 of the semiconductor layer 40.

[0150] By adopting the above-described arrangement, the semiconductor device 1 according to this embodiment can ensure ESD resistance by providing a gate resistor, while increasing the rate at which the limited area of ​​the active region can be utilized to the maximum extent possible, thereby reducing the conduction resistance. Furthermore, it is possible to provide room for meeting the demand for miniaturization of the semiconductor device 1.

[0151] 8 , in the semiconductor device 1 according to the present embodiment, the transistors 10 and 20 are arranged in line symmetry with respect to the boundary line 90 in a plan view of the semiconductor layer 40. Therefore, there is almost no imbalance in the electrical characteristics and heat dissipation of the bidirectional conduction between the transistors 10 and 20.

[0152] Therefore, in the semiconductor device 1, it is preferable that the transistors 10 and 20 are arranged in line symmetry with the boundary line 90 as the axis of symmetry, as in the above configuration. This makes it less likely that deviations in electrical characteristics and heat dissipation will occur due to differences in the current direction. For example, if a protection circuit using the semiconductor device 1 is configured for a lithium-ion battery pack for a smartphone, tablet, or the like, there is no need to make any special differences in the direction of conduction in the semiconductor device 1 during either charging or discharging.

[0153] That is, in a plan view, the pads provided in the second region A2 are only one second source pad 121 connected to the second source electrode 21 of the second vertical MOS transistor 20 and one second gate pad 129 connected to the second gate electrode 29 of the second vertical MOS transistor 20. The second vertical MOS transistor 20 has a second gate resistance element 51 connected to the second gate electrode 29, a second gate electrode region G2 which is a rectangular region containing the second gate pad 129 in a plan view and has the largest area within a range that does not include both the second source electrode 21 and the second gate resistance element 51, and a second resistance element region R2 which is a rectangular region containing the second gate resistance element 51 in a plan view and has the largest area within a range that does not include both the second source electrode 21 and the second gate electrode region G2. The total length of one side and the total length of one side of the outer periphery of the second resistor region R2 coincide with a part of the side of the outer periphery of the semiconductor layer 40 that is perpendicular to the boundary line 90 and has the shortest distance from the second gate pad 129, and in a planar view, the outer periphery of the second resistor region R2 includes only one corner (first corner P1) of the four corners on the outer periphery of the second gate electrode region G2 that is shortest in distance to the boundary line 90 and that is shortest in distance from the side of the outer periphery of the semiconductor layer 40 that is perpendicular to the boundary line 90, and it is desirable that in a planar view, the second source pad 121, the second gate pad 129, the second gate electrode region G2, and the second resistor region R2 are arranged in a linearly symmetrical relationship with the first source pad 111, the first gate pad 119, the first gate electrode region G1, and the first resistor region R1, respectively, with the boundary line 90 as the axis of symmetry.

[0154] As shown in Figure 10, in a planar view of the semiconductor layer 40, the entire length of one side of the outer periphery of the first resistor element region R1 may be arranged so as to coincide with part of the boundary line 90, and the entire length of one side of the outer periphery of the second resistor element region R2 may be arranged so as to coincide with part of the boundary line 90.

[0155] 7A , the semiconductor device 1 does not have the first dead end region D1 and the second dead end region D2, and the areas of the first narrowing region N1 and the second narrowing region N2 can be reduced. This expands the area that can effectively contribute to the conduction of the semiconductor device 1, thereby reducing the conduction resistance of the semiconductor device 1.

[0156] As shown in FIG. 11 , in a plan view of the semiconductor layer 40, the entire length of one side of the outer periphery of the first gate electrode region G1 may be arranged to coincide with a part of a first side S1 of the outer periphery of the semiconductor layer 40 that is parallel to the boundary line 90, and the entire length of one side of the outer periphery of the second gate electrode region G2 may be arranged to coincide with a part of a second side S2 of the outer periphery of the semiconductor layer 40 that is parallel to the boundary line 90.

[0157] 7A , the semiconductor device 1 does not have the first dead end region D1 and the second dead end region D2, and the areas of the first narrowing region N1 and the second narrowing region N2 can be reduced. This expands the area that can effectively contribute to the conduction of the semiconductor device 1, thereby reducing the conduction resistance of the semiconductor device 1.

[0158] 11 from the arrangement shown in Fig. 10, in plan view, the width in the X direction of both the first active region 112 (or the first source electrode 11) and the second active region 122 (or the second source electrode 21) on the side closer to the boundary line 90 is expanded. Furthermore, excluding the installation margin, the first active region 112 (or the first source electrode 11) and the second active region 122 (or the second source electrode 21) occupy the entire length of the boundary line 90 in the Y direction.

[0159] The opposing region where the first region A1 and the second region A2 face each other across the boundary line 90 has the highest current density, so it is desirable to use the entire length of the opposing region along the Y direction for conduction. That is, it is desirable for the opposing region to be occupied by the first active region 112 (or the first source electrode 11) and the second active region 122 (or the second source electrode 21). In the arrangement shown in Figure 11, the entire length of the opposing region along the Y direction can be effectively used for conduction, which particularly benefits from reduced conduction resistance.

[0160] It is desirable to effectively utilize as long an area of ​​the opposing region as possible in the Y direction, even if it is not the entire length in the Y direction. For this reason, it is desirable that the outer periphery of the first source electrode 11 be longest at the portion closest to the boundary line 90 in a plan view. It is desirable that the length of the portion of the outer periphery of the first source electrode 11 closest to the boundary line 90 be longer than the length of the portion of the outer periphery of the first source electrode 11 closest to the first side S1 of the semiconductor layer 40 in a plan view.

[0161] Similarly, in a plan view, it is desirable that the length of the outer periphery of the second source electrode 21 be the longest at the portion closest to the boundary line 90. At least in a plan view, it is desirable that the length of the portion closest to the boundary line 90 at the outer periphery of the second source electrode 21 be longer than the length of the portion closest to the second side S2 of the semiconductor layer 40 at the outer periphery of the second source electrode 21.

[0162] The above-described configuration can be realized by an arrangement such as that shown in Fig. 3 or Fig. 11. In particular, in the arrangement shown in Fig. 11, the first source electrode 11 and the second source electrode 21 each occupy the entire length in the Y direction along the boundary line 90, excluding the installation margin, and therefore, the effect of reducing the conduction resistance can be particularly enjoyed.

[0163] As shown in Figure 3, the first control region C1 may be arranged so that the entire length of one side of the outer periphery coincides with half of the third side S3 of the semiconductor layer 40, and the second control region C2 may be arranged so that the entire length of one side of the outer periphery coincides with half of the third side S3 of the semiconductor layer 40.

[0164] In other words, the sum of the length over which the outer periphery of the first control region C1 coincides with a portion of the third side S3 of the semiconductor layer 40 and the length over which the outer periphery of the second control region C2 coincides with a portion of the third side S3 of the semiconductor layer 40 is the same as the length of one side of the outer periphery of the semiconductor layer 40 (the length of the third side S3).

[0165] Furthermore, in a planar view, the length of the portion where the outer periphery of the first control region C1 coincides with the outer periphery of the semiconductor layer 40 is longest at the portion where the outer periphery of the first control region C1 coincides with the third side S3 of the semiconductor layer 40, and the length of the portion where the outer periphery of the second control region C2 coincides with the outer periphery of the semiconductor layer 40 is longest at the portion where the outer periphery of the second control region C2 coincides with the third side S3 of the semiconductor layer 40.

[0166] According to the above configuration, compared to the semiconductor device 2 according to Comparative Example 1 shown in Figures 7A and 7B, the semiconductor device 1 does not form the first dead end region D1 and the second dead end region D2, and the areas of the first narrowing region N1 and the second narrowing region N2 can be reduced to the maximum extent possible compared to the examples shown in Figures 8 and 10. As a result, the region of the semiconductor device 1 that contributes highly to conduction is expanded to the maximum extent possible, and the conduction resistance of the semiconductor device 1 can be significantly reduced.

[0167] 12, 13, and 14, a portion of the first gate trench 17 and a portion of the second gate trench 27 are schematically shown by a straight line with circles at both ends. The straight line is the gate trench, and the extension direction of the straight line is the extension direction of the gate trench. The circles at both ends represent the points where the gate conductor embedded inside each trench is connected to the gate wiring.

[0168] 12 , in plan view, the first gate trench 17 and the second gate trench 27 extend in a direction perpendicular to the boundary line 90. In this case, the first gate wiring 42 and the second gate wiring 52 may be disposed so as to surround the first source electrode 11 and the second source electrode 21, respectively, except for the portions closest to the fourth side S4 of the semiconductor layer 40.

[0169] In plan view, to connect the first gate electrode 19 and the first gate conductor 15, it is sufficient to provide the first gate wiring 42 on an extension line of the first gate trench 17. Similarly, to connect the second gate electrode 29 and the second gate conductor 25, it is sufficient to provide the second gate wiring 52 on an extension line of the second gate trench 27. Therefore, when the first gate trench 17 and the second gate trench 27 extend in a direction perpendicular to the boundary line 90, no inconvenience occurs even if the first gate wiring 42 and the second gate wiring 52 are not provided in the portions of the semiconductor layer 40 closest to the fourth side S4.

[0170] According to the above configuration, the first gate wiring 42 and the second gate wiring 52 are not installed in the portion closest to the fourth side S4 of the semiconductor layer 40, and therefore the first active region 112 and the second active region 122 can be enlarged, thereby reducing the conduction resistance of the semiconductor device 1.

[0171] 13 , the first gate trench 17 extends in a direction parallel to the boundary line 90 in a plan view. In this case, the first gate wiring 42 may be provided so as to surround the first source electrode 11 except for the portion closest to the first side S1 of the semiconductor layer 40. Similarly, in the arrangement shown in FIG. 13 , the second gate trench 27 extends in a direction parallel to the boundary line 90 in a plan view. In this case, the second gate wiring 52 may be provided so as to surround the second source electrode 21 except for the portion closest to the second side S2 of the semiconductor layer 40.

[0172] According to the above configuration, the first gate wiring 42 and the second gate wiring 52 are not installed in the portion closest to the first side S1 of the semiconductor layer 40 and the portion closest to the second side S2 of the semiconductor layer 40, respectively, and therefore the first active region 112 and the second active region 122 can be enlarged, thereby reducing the conduction resistance of the semiconductor device 1.

[0173] As shown in FIG. 14 , in the semiconductor device 1, in a plan view, the first connection region connecting the first Zener diode 43 and the first source electrode 11 may be disposed in a portion of the outer periphery of the first gate electrode region G1 where the first gate electrode region G1 and the first source electrode 11 face each other and further overlap only with a side parallel to the direction in which the first gate trench 17 extends.

[0174] Similarly, in a plan view, the second connection region connecting the second Zener diode 53 and the second source electrode 21 may be arranged so that the second gate electrode region G2 faces the second source electrode 21 on the outer periphery of the second gate electrode region G2 and further has a portion that overlaps only with the side parallel to the direction in which the second gate trench 27 extends.

[0175] According to the above configuration, the first Zener diode 43 can be connected to the first source electrode 11 without interfering with the region where the first gate wiring 42 and the first gate conductor 15 are connected in a plan view of the semiconductor layer 40. Similarly, the second Zener diode 53 can be connected to the second source electrode 21 without interfering with the region where the second gate wiring 52 and the second gate conductor 25 are connected.

[0176] Therefore, in plan view, it is possible to prevent the area of ​​the first active region 112 and the area of ​​the second active region 122 from being reduced, and therefore the conduction resistance of the semiconductor device 1 can be reduced.

[0177] Although the semiconductor device according to one aspect of the present disclosure has been described above based on the embodiment and comparative examples 1 to 6, the present disclosure is not limited to the embodiment. As long as it does not deviate from the spirit of the present disclosure, various modifications that a person skilled in the art can make to these embodiments, or configurations constructed by combining components in different embodiments and modifications, may also be included within the scope of one or more aspects of the present disclosure.

[0178] A semiconductor device including a vertical MOS transistor according to the present invention can be widely used as a device for controlling the conduction state of a current path.

[0179] 1, 2, 3, 4, 5, 6, 7 Semiconductor device 10 Transistor (first vertical MOS transistor) 11 First source electrode 12, 13, 22, 23 Portion 14 First source region 15 First gate conductor 16 First gate insulating film 17 First gate trench 18 First body region 18a First connecting portion 19 First gate electrode 20 Transistor (second vertical MOS transistor) 21 Second source electrode 24 Second source region 25 Second gate conductor 26 Second gate insulating film 27 Second gate trench 28 Second body region 28a Second connecting portion 29 Second gate electrode 30 Metal layer 32 Semiconductor substrate 33 Lightly doped impurity layer 34 Interlayer insulating layer 35 Passivation layer 40 Semiconductor layer 41 First gate resistor element 42 First gate wiring 43 First Zener diode 44 First EQR 51 Second gate resistor 52 Second gate wiring 53 Second Zener diode 54 Second EQR 90 Boundary line 111 First source pad 112 First active region 119 First gate pad 121 Second source pad 122 Second active region 129 Second gate pad A1 First region A2 Second region C1 First control region C2 Second control region G1 First gate electrode region G2 Second gate electrode region R1 First resistor region R2 Second resistor region P1 First corner P2 Second corner N1 First narrowing region N2 Second narrowing region D1 First dead end region D2 Second dead end region S1 First side S2 Second side S3 Third side S4 Fourth side

Claims

1. A chip-size package type semiconductor device capable of face-down mounting, comprising: a semiconductor layer including a semiconductor substrate; a first vertical MOS transistor entirely formed in a first region of the semiconductor layer on an upper surface side of the semiconductor layer; a second vertical MOS transistor entirely formed in a second region adjacent to the first region in a plan view of the semiconductor layer; and a metal layer formed in contact with the semiconductor substrate on a lower surface side of the semiconductor layer, wherein the semiconductor substrate is a common drain region of the first vertical MOS transistor and the second vertical MOS transistor, wherein the semiconductor layer is square in the plan view, the first region and the second region are aligned in a first direction in the plan view, and a boundary line between the first region and the second region is perpendicular to the first direction, bisects the semiconductor layer in terms of area, and is a straight line passing through the center of the semiconductor layer, in the plan view, pads provided in the first region are only one first source pad connected to a first source electrode of the first vertical MOS transistor and one first gate pad connected to a first gate electrode of the first vertical MOS transistor, the first vertical MOS transistor having: a first gate resistance element connected to the first gate electrode; a first gate electrode region which is a rectangular region containing the first gate pad in the plan view and has a maximum area within a range not including the first source electrode and the first gate resistance element; and a first resistance element region which is a rectangular region containing the first gate resistance element in the plan view and has a maximum area within a range not including the first source electrode and the first gate electrode region, in the plan view, a total length of one side of the periphery of the first gate electrode region and a total length of one side of the periphery of the first resistance element region coincide with a part of a side of the periphery of the semiconductor layer which is perpendicular to the boundary line and has a shortest distance from the first gate pad,a semiconductor device in which, in the planar view, the outer periphery of the first resistance element region includes only one corner of four corners in the outer periphery of the first gate electrode region that has the shortest distance from the boundary line and that has the shortest distance from a side perpendicular to the boundary line to the outer periphery of the semiconductor layer.

2. In the plan view, the pads provided in the second region are only one second source pad connected to a second source electrode of the second vertical MOS transistor and one second gate pad connected to a second gate electrode of the second vertical MOS transistor, and the second vertical MOS transistor has: a second gate resistance element connected to the second gate electrode; a second gate electrode region which is a rectangular region containing the second gate pad in the plan view and has a maximum area within a range not including the second source electrode and the second gate resistance element; and a second resistance element region which is a rectangular region containing the second gate resistance element in the plan view and has a maximum area within a range not including the second source electrode and the second gate electrode region, 2. The semiconductor device according to claim 1 , wherein, in the plan view, a total length of one side of the outer periphery of the second gate electrode region and a total length of one side of the outer periphery of the second resistance element region coincide with a part of a side of the outer periphery of the semiconductor layer that is perpendicular to the boundary line and has the shortest distance from the second gate pad; in the plan view, the outer periphery of the second resistance element region includes only one corner of four corners on the outer periphery of the second gate electrode region that is shortest in distance from the boundary line and that is shortest in distance from a side of the outer periphery of the semiconductor layer that is perpendicular to the boundary line; and in the plan view, the second source pad, the second gate pad, the second gate electrode region, and the second resistance element region are arranged in a linear symmetrical relationship with the first source pad, the first gate pad, the first gate electrode region, and the first resistance element region, respectively, with the boundary line as an axis of symmetry.

3. The semiconductor device according to claim 2, wherein, in the plan view, a total length of one side of the outer periphery of the first resistive element region coincides with a part of the boundary line.

4. The semiconductor device according to claim 2, wherein, in the plan view, the total length of one side of the periphery of the first gate electrode region coincides with a part of a side of the periphery of the semiconductor layer that is parallel to the boundary line.

5. The semiconductor device according to claim 3 or 4, wherein, in the plan view, the first gate electrode region and the first resistive element region together form a first control region, and, in the plan view, of two sides of the periphery of the semiconductor layer parallel to the boundary line, one side which is the shortest distance from the first gate pad is designated as a first side, and the other side opposite to the first side is designated as a second side, and, in the plan view, of two sides of the periphery of the semiconductor layer perpendicular to the boundary line, one side which is the shortest distance from the first gate pad is designated as a third side, and the other side opposite to the third side is designated as a fourth side, and, in the plan view, a length of a portion where the periphery of the first control region and the third side coincide is half the length of the third side, and, in the plan view, a length of a portion where the periphery of the first control region and the periphery of the semiconductor layer coincide is longest.

6. The semiconductor device according to claim 4, wherein, in the plan view, the outer periphery of the first source electrode is longest at a portion closest to the boundary line.

7. The semiconductor device according to claim 5, wherein, in the plan view, the first region includes a first gate trench formed to a depth from an upper surface of the semiconductor layer to a portion of the semiconductor layer, and a first gate wiring connected to the first gate electrode, the first gate trench extends in a direction perpendicular to the boundary line, and the first gate wiring is arranged to surround the first source electrode except for a portion closest to the fourth side.

8. The semiconductor device according to claim 5, wherein, in the plan view, the first region includes a first gate trench formed to a depth from an upper surface of the semiconductor layer to a portion of the semiconductor layer, and a first gate wiring connected to the first gate electrode, the first gate trench extends in a direction parallel to the boundary line, and the first gate wiring is arranged to surround the first source electrode except for a portion closest to the first side.

9. The semiconductor device according to claim 5, wherein, in the plan view, the first region includes a first gate trench formed to a depth from an upper surface of the semiconductor layer to a portion of the semiconductor layer, and a first Zener diode connected to the first gate electrode and the first source electrode, and in the plan view, a first connection region connecting the first Zener diode and the first source electrode faces the first source electrode among the outer periphery of the first gate electrode region and overlaps only with a side parallel to the extension direction of the first gate trench.

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