Current detection amplifier and current detection semiconductor device

Abstract

The present invention provides a current detection amplifier for amplifying a detection signal of a current flowing to a current detection resistor and then outputting the amplified signal to an AD converter. The current detection amplifier includes: a first noise removal filter connected to one end of the current detection resistor and configured to have a first capacitance and a first resistance; and a first capacitance connection switch provided between the first capacitance of the first noise removal filter and a first sampling capacitance of the AD converter.

Description

Current detection amplifier and current detection semiconductor device

[0001] The present invention relates to a current detection amplifier and a semiconductor device for current detection.

[0002] Conventionally, when detecting current using a current detection resistor, a low resistance current detection resistor is required to suppress power loss due to the current detection resistor. However, when the resistance of the current detection resistor is reduced, the detection signal becomes smaller and the S / N ratio deteriorates, so noise reduction is required. Techniques for noise reduction include, for example, chopping to suppress 1 / f noise and incorporating a noise reduction filter.

[0003] For example, Patent Document 1 listed below discloses a technology for a ΔΣ type AD converter that includes a detection resistor and a ΔΣ modulator that converts an analog signal detected by the detection resistor into a digital signal, in which an anti-aliasing filter is provided between the detection resistor and the ΔΣ modulator to remove high-frequency components of the signal input to the ΔΣ modulator.

[0004] Japanese Patent Application Laid-Open No. 2009-260605

[0005] However, in the technology of Patent Document 1, charge redistribution occurs from the capacitance of the anti-aliasing filter to the ΔΣ modulator when sampling to the ΔΣ modulator, so the capacitance of the anti-aliasing filter needs to be increased.

[0006] Furthermore, in the technology of Patent Document 1, if the signal input to the ΔΣ modulator is configured to be chopped (polarity inverted) by a current detection amplifier, chopping noise occurs when the polarity is inverted. In order to suppress this chopping noise, the capacitance of the anti-aliasing filter must be increased, and it was not possible to implement the capacitance of the anti-aliasing filter in the same semiconductor integrated circuit as the current detection amplifier.

[0007] A current detection amplifier according to one embodiment amplifies a detection signal of a current flowing through a current detection resistor and then outputs the amplified signal to an AD converter. The current detection amplifier includes: a first noise removal filter connected to one end of the current detection resistor and including a first capacitance and a first resistance; and a first capacitance connection switch provided between the first capacitance of the first noise removal filter and a first sampling capacitance of the AD converter.

[0008] According to one embodiment of the current detection amplifier, when sampling to the AD converter, the first capacitance connection switch is turned off to disconnect the first capacitance of the first noise removal filter from the AD converter, thereby preventing charge redistribution from the first capacitance and allowing the first capacitance to be reduced in size.

[0009] Furthermore, according to one embodiment of the current detection amplifier, when the signal input to the AD converter is configured to be chopped (polarity inverted) by the current detection amplifier, the first capacitance connection switch and the second capacitance connection switch are turned off during chopping to disconnect the first capacitance and the second capacitance from the AD converter, thereby preventing noise generated during polarity inversion from being superimposed on the first capacitance and the second capacitance, thereby making it possible to reduce the capacitance of the first capacitance and the second capacitance.

[0010] FIG. 1 shows a circuit configuration of a current detection device according to an embodiment. A timing chart showing timings of each part in a current detection device according to an embodiment. FIG. 2 shows a modified circuit configuration of a current detection device according to an embodiment. A timing chart showing an example of output when the capacitance of an anti-aliasing filter is connected at a constant cycle when starting up a current detection amplifier according to an embodiment. A timing chart showing an example of output when the capacitance of an anti-aliasing filter is kept connected when starting up a current detection amplifier according to an embodiment.

[0011] Hereinafter, an embodiment will be described with reference to the drawings.

[0012] (Circuit Configuration of Current Detection Device 100) FIG. 1 is a diagram showing the circuit configuration of a current detection device 100 according to one embodiment. The current detection device 100 shown in FIG. 1 detects a current flowing through a wiring L1 to be detected, amplifies and AD-converts the detected current signal, and then outputs the AD-converted digital signal. The current detection device 100 can be used, for example, in a battery fuel gauge. However, the use of the current detection device 100 is not limited to this, and the current detection device 100 can be applied to any low-noise application that can detect low voltages.

[0013] As shown in FIG. 1 , the current detection device 100 includes a current detection resistor R1 , a current detection amplifier 110 , and a ΔΣ AD converter 120 .

[0014] The current detection resistor R1 is provided on the wiring L1 that is the target of current detection. The potential difference across the current detection resistor R1 changes depending on the current flowing through the current detection resistor R1.

[0015] The current detection amplifier 110 is connected to both ends of the current detection resistor R1, and amplifies a detection signal of the potential difference between both ends of the current detection resistor R1.

[0016] The current detection amplifier 110 includes a resistor R21, a resistor R22, a resistor R23, and a resistor R24.

[0017] One end of the resistor R21 is connected to one end of the current detection resistor R1. The other end of the resistor R22 is connected to the current detection resistor R21. That is, the resistors R21 and R22 are connected in series with each other.

[0018] One end of the resistor R23 is connected to the other end of the current detection resistor R1. The resistor R24 ​​is connected to the other end of the current detection resistor R23. That is, the resistors R23 and R24 are connected in series with each other.

[0019] The gain of the current detection amplifier 110 is R22 / R21=R24 / R23. That is, the resistors R21, R22, R23, and R24 are examples of “gain-determining resistors” that determine the gain of the current detection amplifier 110.

[0020] The current detection amplifier 110 includes a differential operational amplifier 111. The differential operational amplifier 111 amplifies the differential voltage between the negative input terminal and the positive input terminal, and outputs the amplified voltage from the negative output terminal and the positive output terminal.

[0021] The negative input terminal of the differential operational amplifier 111 is connected between resistors R21 and R22 via a chopping switch SW11, and the negative input terminal of the differential operational amplifier 111 is connected between resistors R23 and R24 via a chopping switch SW21.

[0022] The positive input terminal of the differential operational amplifier 111 is connected between resistors R21 and R22 via a chopping switch SW22, and the positive input terminal of the differential operational amplifier 111 is connected between resistors R23 and R24 via a chopping switch SW12.

[0023] The positive output terminal of the differential operational amplifier 111 is connected to a first input terminal Vin+ of the ΔΣ AD converter 120 via a chopping switch SW13. In addition, the positive output terminal of the differential operational amplifier 111 is connected to a second input terminal Vin− of the ΔΣ AD converter 120 via a chopping switch SW23.

[0024] The negative output terminal of the differential operational amplifier 111 is connected to a first input terminal Vin+ of the ΔΣ AD converter 120 via a chopping switch SW24. In addition, the negative output terminal of the differential operational amplifier 111 is connected to a second input terminal Vin− of the ΔΣ AD converter 120 via a chopping switch SW14.

[0025] As a result, the current detection amplifier 110 can chop (i.e., invert the polarity of) the signal Vamp input from the differential operational amplifier 111 to the ΔΣ AD converter 120 by switching the chopping switches SW11 to SW14 and SW21 to SW24.

[0026] Specifically, by simultaneously switching on the chopping switches SW11 to SW14 and simultaneously switching off the chopping switches SW21 to SW24, the current detection amplifier 110 can input the positive polarity signal Vamp output from the differential operational amplifier 111 to the first input terminal Vin+ of the ΔΣ AD converter 120, and can input the negative polarity signal Vamp output from the differential operational amplifier 111 to the second input terminal Vin− of the ΔΣ AD converter 120.

[0027] Conversely, by simultaneously switching off the chopping switches SW11 to SW14 and simultaneously switching on the chopping switches SW21 to SW24, the current detection amplifier 110 can input the negative polarity signal Vamp output from the differential operational amplifier 111 to the first input terminal Vin+ of the ΔΣ AD converter 120, and input the positive polarity signal Vamp output from the differential operational amplifier 111 to the second input terminal Vin− of the ΔΣ AD converter 120.

[0028] The current detection amplifier 110 can suppress 1 / f noise in the signal Vamp by chopping the signal Vamp input to the ΔΣ AD converter 120. The chopping switches SW11 to SW14 and SW21 to SW24 are an example of a “first chopping unit” that chops the signal Vamp input to the ΔΣ AD converter 120.

[0029] The current detection amplifier 110 also includes a first anti-aliasing filter 112, a second anti-aliasing filter 113, a first capacitor connection switch SW1, and a second capacitor connection switch SW2.

[0030] The first anti-aliasing filter 112 is configured to include the above-mentioned resistor R22 (an example of a "first resistor") and a first capacitance C1. The first capacitance C1 is connected in parallel with the resistor R22. The first capacitance C1 is also connected to the first input terminal Vin+ of the ΔΣ AD converter 120. The first anti-aliasing filter 112 is a noise removal filter (i.e., a low-pass filter) that removes high-frequency components from the detection signal Vout that is input to the first input terminal Vin+ of the ΔΣ AD converter 120 when sampling is performed on the ΔΣ AD converter 120.

[0031] The second anti-aliasing filter 113 is configured to include the above-mentioned resistor R24 ​​(an example of a "second resistor") and a second capacitor C2. The second capacitor C2 is connected in parallel with the resistor R24. The second capacitor C2 is also connected to the second input terminal Vin- of the ΔΣ AD converter 120. The second anti-aliasing filter 113 is a noise removal filter (i.e., a low-pass filter) that removes high-frequency components from the detection signal Vout (i.e., a detection signal Vout having a polarity different from that of the detection signal Vout input to the first input terminal Vin+) input to the second input terminal Vin- of the ΔΣ AD converter 120 when sampling is performed on the ΔΣ AD converter 120.

[0032] The first capacitance connection switch SW1 is provided between the first capacitance C1 of the first anti-aliasing filter 112 and the first input terminal Vin+ of the ΔΣ AD converter 120. The first capacitance connection switch SW1 can switch the first capacitance C1 of the first anti-aliasing filter 112 between a state where it is connected to the first input terminal Vin+ of the ΔΣ AD converter 120 and a state where it is disconnected from the first input terminal Vin+ of the ΔΣ AD converter 120.

[0033] The second capacitance connection switch SW2 is provided between the second capacitance C2 of the second anti-aliasing filter 113 and the second input terminal Vin− of the ΔΣ AD converter 120. The second capacitance connection switch SW2 can switch the second capacitance C2 of the second anti-aliasing filter 113 between a state where it is connected to the second input terminal Vin− of the ΔΣ AD converter 120 and a state where it is disconnected from the second input terminal Vin− of the ΔΣ AD converter 120.

[0034] The ΔΣ AD converter 120 is provided at the subsequent stage of the current detection amplifier 110, and performs AD conversion on the detection signal Vout (analog signal) output from the current detection amplifier 110 into a digital signal.

[0035] For example, the ΔΣ AD converter 120 is composed of a ΔΣ modulator that performs AD conversion on the detection signal Vout (analog signal) output from the current detection amplifier 110, and a digital filter that performs filtering processing on the detection signal that has been AD converted by the ΔΣ modulator.

[0036] 1 illustrates a portion (input section) of the ΔΣ AD converter 120. As shown in Fig. 1, the portion (input section) of the ΔΣ AD converter 120 includes a first input terminal Vin+, a second input terminal Vin-, a first sampling capacitor C31 connected to the first input terminal Vin+, and a second sampling capacitor C32 connected to the second input terminal Vin-.

[0037] In addition, a part (input section) of the ΔΣ AD converter 120 includes a differential operational amplifier 121 connected to a first sampling capacitor C31 and a second sampling capacitor C32, a first integrating capacitor C35 provided between the negative input terminal and the positive output terminal of the differential operational amplifier 121, a second integrating capacitor C36 provided between the positive input terminal and the negative output terminal of the differential operational amplifier 121, sampling switches SW51 to SW56, and integrating switches SW61 to SW64.

[0038] By switching the sampling switches SW51 to SW56 and the integration switches SW61 to SW64, the ΔΣ AD converter 120 can switch between a state in which the detection signal Vout output from the current detection amplifier 110 is sampled in the first sampling capacitor C31 and the second sampling capacitor C32, and a state in which the charges sampled in the first sampling capacitor C31 and the second sampling capacitor C32 are integrated in the first integration capacitor C35 and the second integration capacitor C36.

[0039] Specifically, the ΔΣ AD converter 120 can switch the detection signal Vout output from the current detection amplifier 110 to a state in which it is sampled by the first sampling capacitor C31 and the second sampling capacitor C32 by simultaneously switching on the sampling switches SW51 to SW56 and simultaneously switching off the integration switches SW61 to SW64.

[0040] Conversely, the ΔΣ AD converter 120 can switch to a state in which the charges sampled in the first sampling capacitor C31 and the second sampling capacitor C32 are integrated in the first integrating capacitor C35 and the second integrating capacitor C36 by simultaneously switching off the sampling switches SW51 to SW56 and simultaneously switching on the integrating switches SW61 to SW64.

[0041] This embodiment includes a ΔΣ AD converter 120. Here, a ΔΣ AD converter is used as an example, but any type of AD converter can be applied as long as it has a sampling capacitor.

[0042] The current detection device 100 of this embodiment is an example of a "current detection semiconductor device," and the current detection amplifier 110 and the ΔΣ AD converter 120 are implemented on a single semiconductor integrated circuit. In particular, the current detection device 100 of this embodiment can reduce the capacitance of the first capacitance C1 and the second capacitance C2 for removing high-frequency components, so that the first capacitance C1 and the second capacitance C2 can be implemented on the current detection amplifier 110, and the current detection amplifier 110 and the ΔΣ AD converter 120 can be implemented on a single semiconductor integrated circuit.

[0043] (Timing of Signals in Current Detector 100) FIG. 2 is a timing chart showing timings of various parts in the current detector 100 according to one embodiment.

[0044] The timing chart shown in Figure 2 shows, from top to bottom, the switching timing of the capacitance connection switches SW1 and SW2 provided in the current detection amplifier 110, the switching timing of the sampling switches SW51 to SW56 provided in the ΔΣ AD converter 120, the switching timing of the integration switches SW61 to SW64 provided in the ΔΣ AD converter 120, the switching timing of the chopping switches SW11 to SW14 provided in the current detection amplifier 110, the switching timing of the chopping switches SW21 to SW24 provided in the current detection amplifier 110, and the voltage level of the signal Vamp output from the differential operational amplifier 111.

[0045] In the timing chart shown in FIG. 2, timings T1 and T4 indicate the timings at which chopping is performed on the signal Vamp output from the differential operational amplifier 111.

[0046] In the timing chart shown in FIG. 2, timings T2 and T5 indicate the timings at which sampling is started for the first sampling capacitor C31 and the second sampling capacitor C32 included in the ΔΣ AD converter 120.

[0047] Also, in the timing chart shown in Figure 2, timings T3 and T6 indicate the timings at which the capacitances C1 and C2 of the anti-aliasing filters 112 and 113 are connected to the first sampling capacitance C31 and the second sampling capacitance C32 provided in the ΔΣ AD converter 120 and sampled by the first sampling capacitance C31 and the second sampling capacitance C32.

[0048] As shown in FIG. 2, the current detection amplifier 110 switches between chopping switches SW11 to SW14 and chopping switches SW21 to SW24 at regular intervals, thereby chopping the signal Vamp.

[0049] Also, as shown in Figure 2, in the ΔΣ AD converter 120, by switching the sampling switches SW51 to SW56 and the integrating switches SW61 to SW64 at a constant period, the state alternates between a state in which the detection signal Vout output from the current detection amplifier 110 is sampled by the first sampling capacitor C31 and the second sampling capacitor C32, and a state in which the charges sampled by the first sampling capacitor C31 and the second sampling capacitor C32 are integrated by the first integrating capacitor C35 and the second integrating capacitor C36.

[0050] Furthermore, as shown in FIG. 2, the current detection amplifier 110 can sample the capacitances C1 and C2 of the anti-aliasing filters 112 and 113 to the first sampling capacitance C31 and the second sampling capacitance C32 by switching on the capacitance connection switches SW1 and SW2 at regular intervals.

[0051] 2, the capacitance-connecting switches SW1 and SW2 are turned off at the timings T1 and T4 when chopping is performed, i.e., the capacitances C1 and C2 of the anti-aliasing filters 112 and 113 are not connected at the timings T1 and T4 when chopping is performed.

[0052] As a result, the current detection amplifier 110 according to one embodiment can prevent noise generated in the detection signal Vout when the polarity of the signal Vamp is inverted from being superimposed on the capacitances C1 and C2, thereby enabling the capacitances C1 and C2 to be reduced.

[0053] 2, the capacitor connection switches SW1 and SW2 are also turned off at times T2 and T5 when sampling is started for the first sampling capacitor C31 and the second sampling capacitor C32. That is, the capacitors C1 and C2 of the anti-aliasing filters 112 and 113 are not connected at times T2 and T5 when sampling is started.

[0054] As a result, in one embodiment of the current detection amplifier 110, the charge redistribution that occurs at the start of sampling is performed from the differential operational amplifier 111, and charge redistribution is not performed from the capacitances C1 and C2, so that the capacitances C1 and C2 can be made smaller.

[0055] 2 , after sampling starts, at times T3 and T6 immediately before the sampling switches SW51 to SW56 are switched off, the capacitance-connecting switches SW1 and SW2 are switched on, and the capacitances C1 and C2 of the anti-aliasing filters 112 and 113 are connected to the first sampling capacitance C31 and the second sampling capacitance C32. As a result, the current detection device 100 according to one embodiment can cause the ΔΣ AD converter 120 to sample the signal from which high-frequency noise has been removed by the anti-aliasing filters 112 and 113.

[0056] In this way, the current detection amplifier 110 according to one embodiment can prevent noise during chopping from being superimposed on the capacitances C1 and C2, and can also prevent charge redistribution from the capacitances C1 and C2, thereby enabling the capacitances C1 and C2 to be made extremely small. As a result, the current detection amplifier 110 according to one embodiment can implement the capacitances C1 and C2 on a single semiconductor integrated circuit.

[0057] For example, in the configuration of Patent Document 1, the capacitance of the anti-aliasing filter required was 0.01 to 0.1 μF, but in the present invention, the capacitance of the anti-aliasing filter can be set to 100 pF or less, making it possible to incorporate the anti-aliasing filter into a semiconductor integrated circuit.

[0058] (Modification of Circuit Configuration of Current Detection Device 100) FIG. 3 is a diagram showing a modification of the circuit configuration of the current detection device 100 according to one embodiment.

[0059] The current detection device 100-2 shown in FIG. 3 differs from the current detection device 100 shown in FIG. 1 in that it includes a current detection amplifier 110-2 instead of the current detection amplifier 110.

[0060] The current detection amplifier 110-2 includes resistor chopping switches SW31, SW32, SW33, and SW34 between the current detection resistor R1 and resistors R21 and R23.

[0061] The resistor chopping switch SW31 is provided between one end of the current detection resistor R1 and the resistor R21. The resistor chopping switch SW32 is provided between one end of the current detection resistor R1 and the resistor R23. The resistor chopping switch SW33 is provided between the other end of the current detection resistor R1 and the resistor R21. The resistor chopping switch SW34 is provided between the other end of the current detection resistor R1 and the resistor R23.

[0062] This allows the current detection amplifier 110-2 to chop (i.e., invert the polarity of) the detection signal input from the current detection resistor R1 to the resistors R21 and R23 by switching the resistor chopping switches SW31 to SW34.

[0063] 3, polysilicon resistors are used for the resistors R21 to R24 (gain-determining resistors), which may cause 1 / f noise in the resistors R21 to R24.

[0064] Therefore, the current detection amplifier 110-2 chops the detection signals input to the resistors R21 and R23. Specifically, the current detection amplifier 110-2 switches the resistor chopping switches SW31 and SW34 on and off at the same timing as the switching timings of SW11 to SW14 shown in FIG. 2, and switches the resistor chopping switches SW32 and SW33 on and off at the same timing as the switching timings of SW21 to SW24 shown in FIG.

[0065] This allows the current detection amplifier 110-2 to chop the detection signal input to resistors R21 and R23, and therefore suppresses the 1 / f noise generated in resistors R21 to R24 and the 1 / f noise generated in the differential operational amplifier 111.

[0066] The resistor chopping switches SW31 to SW34 are an example of a "second chopping unit" that chops the signal input to the gain detection resistor.

[0067] 4 is a timing chart showing an example of an output when the capacitances C1 and C2 of the anti-aliasing filters 112 and 113 are connected at regular intervals during startup of the current detection amplifier 110 according to an embodiment. FIG. 5 is a timing chart showing an example of an output when the capacitances C1 and C2 of the anti-aliasing filters 112 and 113 are kept connected during startup of the current detection amplifier 110 according to an embodiment.

[0068] The timing charts shown in Figures 4 and 5 show, from top to bottom, the switching timing of the activation signal (Enable signal) of the current detection device 100, the switching timing of the capacitance connection switches SW1 and SW2 provided in the current detection amplifier 110, the switching timing of the sampling switches SW51 to SW56 provided in the ΔΣ AD converter 120, the switching timing of the integration switches SW61 to SW64 provided in the ΔΣ AD converter 120, the switching timing of the chopping switches SW11 to SW14 provided in the current detection amplifier 110, the switching timing of the chopping switches SW21 to SW24 provided in the current detection amplifier 110, and the amount of charge on the capacitances C1 and C2 of the anti-aliasing filters 112 and 113.

[0069] As shown in Figure 5, the current detection amplifier 110 of one embodiment may switch on the capacitance connection switches SW1 and SW2 at startup (i.e., when the startup signal (Enable signal) of the current detection device 100 is switched on) to connect the capacitances C1 and C2 of the anti-aliasing filters 112 and 113 to the sampling capacitances C31 and C32 of the ΔΣ AD converter 120 until a predetermined time has elapsed or until the amount of charge on the capacitances C1 and C2 of the anti-aliasing filters 112 and 113 reaches a predetermined threshold.

[0070] As a result, in one embodiment of the current detection amplifier 110, the charging time required for the charge amount of the capacitances C1 and C2 of the anti-aliasing filters 112 and 113 to reach a certain amount at startup can be shortened compared to when the capacitances C1 and C2 of the anti-aliasing filters 112 and 113 are connected to the sampling capacitances C31 and C32 of the ΔΣ AD converter 120 at a constant period at startup (see Figure 4), thereby shortening the startup time.

[0071] Although one embodiment of the present invention has been described in detail above, the present invention is not limited to these embodiments, and various modifications and changes are possible within the scope of the gist of the present invention described in the claims.

[0072] For example, the present invention is applicable not only to differential current detection amplifiers but also to single-ended current detection amplifiers.

[0073] This international application claims priority based on Japanese Patent Application No. 2023-141640, filed on August 31, 2023, the entire contents of which are incorporated herein by reference.

[0074] 100, 100-2 Current detection device (current detection semiconductor device) 110, 110-2 Current detection amplifier 111 Differential operational amplifier 112 First anti-aliasing filter (first noise removal filter) 113 Second anti-aliasing filter (second noise removal filter) 120 ΔΣ AD converter (AD converter) 121 Differential operational amplifier L1 Wiring R1 Current detection resistor R21 to R24 Resistors (gain determination resistors) SW11 to SW14, SW21 to SW24 Chopping switches (first chopping section) C1 First capacitance C2 Second capacitance C31 First sampling capacitance C32 Second sampling capacitance C35 First integrating capacitance C36 Second integrating capacitance SW1 First capacitance connection switch SW2 Second capacitance connection switch SW31 to SW34 Resistor chopping switches (second chopping section) SW51 to SW56 Sampling switches SW61 to SW64 Integration switches Vin+ First input terminal Vin- Second input terminal

Claims

1. A current detection amplifier which amplifies a detection signal of a current flowing through a current detection resistor and then outputs it to an AD converter, comprising: a first noise elimination filter connected to one end of the current detection resistor and comprising a first capacitance and a first resistance; and a first capacitance connection switch provided between the first capacitance of the first noise elimination filter and a first sampling capacitance of the AD converter.

2. The current detection amplifier according to claim 1, characterized in that, when sampling of the detection signal output from the current detection amplifier is started to the first sampling capacitance of the AD converter, the first capacitance connection switch is turned off so that the first capacitance of the first noise removal filter is not connected to the first sampling capacitance of the AD converter.

3. The current detection amplifier according to claim 2, characterized in that after starting sampling of the detection signal output from the current detection amplifier to the first sampling capacitance of the AD converter, the first capacitance connection switch is turned on to connect the first capacitance of the first noise removal filter to the first sampling capacitance of the AD converter.

4. A current detection amplifier as described in claim 3, further comprising a first chopping unit that chops the detection signal input from the current detection amplifier to the AD converter, and when the first chopping unit chops the detection signal, the first capacitance connection switch is turned off so that the first capacitance of the first noise removal filter is not connected to the first sampling capacitance of the AD converter.

5. The current detection amplifier according to claim 4, further comprising: a second noise elimination filter connected to the other end of the current detection resistor and comprising a second capacitance and a second resistance; and a second capacitance connection switch provided between the second capacitance of the second noise elimination filter and a second sampling capacitance of the AD converter, wherein the second capacitance connection switch is turned off to not connect the second capacitance of the second noise elimination filter to the second sampling capacitance of the AD converter, and the second capacitance connection switch is turned on to connect the second capacitance of the second noise elimination filter to the second sampling capacitance of the AD converter.

6. The current detection amplifier according to claim 5, further comprising: a gain determining resistor that determines a gain of the detection signal by the current detection amplifier; and a second chopping section that chops the detection signal input from the current detection resistor to the gain determining resistor.

7. The current detection amplifier of claim 2, characterized in that, at startup, the first capacitance is connected to the first sampling capacitance until a predetermined time has elapsed or until the amount of charge on the first sampling capacitance reaches a predetermined threshold.

8. A current detection semiconductor device comprising: a current detection amplifier according to any one of claims 1 to 7; and the AD converter in a single semiconductor integrated circuit.

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