Function chain implementation method, function chaining system, and data holding device

Abstract

A function chain implementation method according to the present invention includes: adding a buffer function to a function chain on the basis of a difference in processing delay between functions in the function chain; for each group obtained by grouping the functions including the buffer function, selecting data processing devices for implementing the functions; and determining the data processing device for implementing the functions on the basis of a score calculated on the basis of an implementation cost corresponding to the operation rate of each data processing device and communication delays between the data processing devices.

Description

Function chain implementation method, function chaining system, and data retention device

[0001] The present invention relates to a function chaining system that provides services to users by using a service function chaining technique.

[0002] Service Function Chaining (SFC) is being studied to provide end-to-end services flexibly (see, for example, Non-Patent Document 1). SFC is a technology that allows for the free combination of service functions (SFs) scattered across a network, and by using SFC, it is possible to combine any service functions to build a service function chain that meets the user's purpose.

[0003] In SFC, a classifier installed at the entrance attaches a tag to a packet, and a service function forwarder (SFF) refers to the tag and forwards the packet to the appropriate function, as shown in Fig. 17. In SFC, different function combinations can be realized by changing the tag attached to a packet, so different services according to user objectives can be provided within a single network.

[0004] A typical SFC aims to provide network services by combining network functions virtualized using NFV (Network Function Virtualization) technology, but SFC is also an effective technology for more advanced cloud services.

[0005] For example, Non-Patent Document 2 considers an image processing service using SFC and aims to provide a highly accurate object detection service by selecting a feature extraction function appropriate for the scene. Non-Patent Document 2 proposes a low-latency architecture using a hardware accelerator because image processing services cannot be provided with low latency when using a general-purpose server with low processing performance. For such advanced cloud services, functions may be implemented not only on a general-purpose server but also on a hardware accelerator, as shown in Figure 18.

[0006] RFC 7665 - Service Function Chaining (SFC) Architecture, Internet Engineering Task Force (IETF), October 2015, <https: / / datatracker.ietf.org / doc / html / rfc7665> Yuta UKON, Koji YAMAZAKI, Koyo NITTA, “Real-Time Image Processing Based on Service Function Chaining Using CPU-FPGA Architecture”, IEICE Transactions on Communications, Vol.E103-B, No.1, pp.11-19, 2020, <https: / / search.ieice.org / bin / summary.php?id=e103-b_1_11>

[0007] 18, if there is a difference in processing delay among the functions that make up the function chain, and the processing delay of a later function is greater than that of a previous function, there is a possibility that data will be lost if the next data is input before the processing of the later function is completed. This data loss can be prevented by providing an input buffer in some of the functions.

[0008] In a typical SFC, data transfer between functions is performed via memory, which acts as a buffer. Therefore, even if the processing delay in a subsequent function becomes large and the processing delay is reversed, the difference in processing delay between the functions is absorbed in the memory, so the problem of data loss does not occur.

[0009] On the other hand, in SFC-compatible cloud services that use hardware accelerators to prioritize data processing speed, the communication memory of the hardware accelerator may be small or may not exist. This is because the memory resources of the hardware accelerator are limited. In such cases, the difference in processing delay between functions cannot be absorbed in the downstream function, and data may be lost, making it impossible to provide the service normally.

[0010] To solve the above problem, in SFC-compatible cloud services, it is necessary to add a buffer function in addition to the service function that performs the specified processing on the function chain, taking into account the processing delay difference between functions; however, an implementation algorithm for a function chain that can accommodate the addition of a buffer function has not yet been realized.

[0011] The present invention has been made to solve the above-mentioned problems, and aims to provide a function chain implementation method that can accommodate the addition of buffer functions by taking into account the processing delay differences between functions in the function chain.

[0012] In order to solve the above problems, the function chain implementation method of the present invention is a function chain implementation method executed in a function chaining system having a function chain in which a plurality of functions are combined, the function chaining system comprising a data processing device that performs data processing of the function on data contained in a received packet, and a control device that implements the function in the data processing device, the control device adding a buffer function to the function chain based on the difference in processing delay between the functions, selecting the data processing device in which to implement the function for each of a plurality of groups of the function, and determining the data processing device in which to implement the function based on an implementation cost corresponding to the availability rate of the data processing device for the function and a score calculated based on the communication delay between the data processing devices.

[0013] In order to solve the above problems, the function chaining system of the present invention is a function chaining system having a function chain in which a plurality of functions are combined, and comprises a data processing device that performs data processing of the function on data contained in a received packet, and a control device that implements the function in the data processing device, and the control device is configured to add a buffer function to the function chain based on the difference in processing delay between the functions, select the data processing device that implements the function for each of a plurality of groups of the function, and determine the data processing device that implements the function based on a score calculated based on the implementation cost of the function in the data processing device and the communication delay between the data processing devices.

[0014] According to the present invention, it is possible to provide a function chain implementation method that can accommodate the addition of buffer functions by taking into account the difference in processing delay between functions in the function chain.

[0015] FIG. 1 shows an example of the configuration of a function chaining system according to an embodiment of the present invention. FIG. 2 shows an example of the configuration of a function chain according to an embodiment of the present invention. FIG. 3 shows an example of the configuration of a function chain to which a buffer function has been added according to an embodiment of the present invention. FIG. 4 shows an example of the configuration of a timing chart of a function chain according to an embodiment of the present invention. FIG. 5 shows an example of the configuration of a function chain according to an embodiment of the present invention. FIG. 6 shows an example of the configuration of a function chain to which a buffer function has been added according to an embodiment of the present invention. FIG. 7 shows an example of the configuration of a timing chart of a function chain according to an embodiment of the present invention. FIG. 8 shows an example of the configuration of a function chain to which a buffer function has been added according to an embodiment of the present invention. FIG. 9 shows an example of the configuration of a timing chart of a function chain according to an embodiment of the present invention. FIG. 10 shows an example of a method for implementing a function chain according to an embodiment of the present invention. FIG. 11 shows an example of the configuration of a data retention device according to an embodiment of the present invention. FIG. 12 shows an example of the configuration of a data retention device according to an embodiment of the present invention. FIG. 13 shows an operation flowchart of the method for implementing a function chain according to an embodiment of the present invention. FIG. 14 shows an operation flowchart of the method for adding a buffer function according to an embodiment of the present invention. FIG. 15 shows an operation flowchart of the method for adding a buffer function according to an embodiment of the present invention. Fig. 16 is a flowchart showing the operation of a method for adding a buffer function according to an embodiment of the present invention. Fig. 17 shows an example of the configuration of a conventional function chaining system. Fig. 18 shows an example of the configuration of a conventional function chaining system.

[0016] Hereinafter, embodiments of the present invention will be described with reference to the drawings. However, the present invention can be embodied in many different forms and should not be construed as being limited to the embodiments of the present invention described below.

[0017] 1 is a block diagram showing an example of the configuration of a service function chaining system (SFCS) 1 according to an embodiment of the present invention. The SFCS includes a tagging device 10 that adds tags indicating function chains to input packets, data transfer devices (20-1 to 20-3) that refer to the tags and transfer the packets to data processing devices in which functions are implemented or to other data transfer devices, data processing devices (30-1 to 30-4) that process received data according to the implemented functions, an external transmission device 50 that transmits the processed data to a destination, and a control device 40 that implements functions in the data processing devices and registers function chains in the tagging devices, data transfer devices, and external transmission devices.

[0018] The input packet is tagged by the tagging device 10 with a tag containing the identification information of the desired function chain, and is then transferred to several data processing devices (30-1 to 30-4) via data transfer devices (20-1 to 20-3). The data processing devices (30-1 to 30-4) process the data according to the implemented functions.

[0019] The processed packet is sent to the external transmitting device 50, where the tag is removed and the packet is output to the outside of the SFCS as a packet with a TCP / IP header. Data transfer using tags can be realized by using the NSH (Network Service Header) defined in RFC8300.

[0020] The data processing devices (30-1 to 30-4) are specifically general-purpose servers or hardware accelerators, and can perform data processing using a CPU, GPU, FPGA (Field-Programmable Gate Array), and ASIC (Application Specific Integrated Circuit).

[0021] The control device 40 creates a function chain having multiple functions based on a user's service usage request. It also generates tags according to the created function chain and registers the tags and routing information in the tagging device 10 and data transfer devices (20-1 to 20-3). In an SFCS targeted at cloud services, the data processing devices (30-1 to 30-4) may not have input buffers, so the control device 40 must modify the initial function chain taking into account differences in processing delays between functions in order to prevent data loss in the data processing devices (30-1 to 30-4).

[0022] The control device 40 can perform the above control using a CPU, a GPU, a field-programmable gate array (FPGA), and an application-specific integrated circuit (ASIC).

[0023] <Example of Function Chain Configuration> Figure 2 shows an example of a function chain for realizing a service requested by a user. The function chain in Figure 2 has four functions (F1 to F4) (60-1 to 60-4) connected in series, and each function generates its own processing delay (value in parentheses). Note that the processing delay of each function is known information that is determined during the function development stage.

[0024] Because users generally specify the service (function chain) they want to use, the initial function chain in Figure 2 does not take into account differences in processing delay between functions. As a result, a situation may occur in which the processing delay of a later function is greater than the processing delay of an earlier function, i.e., a processing delay reversal may occur, resulting in data loss in some functions. In the example in Figure 2, processing delay reversals occur in the section between function F1 (60-1) and function F2 (60-2) and the section between function F3 (60-3) and function F4 (60-4).

[0025] <Timing chart of function chain> Figure 3 shows a function chain that takes into account differences in processing delay between functions. Figure 4 is a timing chart of the function chain of Figure 3. In the initial function chain shown in Figure 2, when data is continuously input, a reversal of the processing delay may cause data loss in function F2 (60-2) and function F4 (60-4). In this embodiment, a buffer function B1 (70-1) is placed at the beginning of the function chain, and the data output interval of buffer function B1 is set to be equal to or greater than the maximum processing delay (=7) of the function chain.

[0026] 4, by providing buffer function B1 (70-1), subsequent functions can complete their processing before the next input arrives from the preceding function, preventing data loss. For example, processes P4 and P5 of function F2 (60-2) are completed before processes P2 and P3 of function F1 (60-1) are completed, respectively, and processes P10 and P11 of function F4 (60-4) are completed when processes P8 and P9 of function F3 (60-3) are completed, respectively.

[0027] When the function chain is connected in series, the buffer can be added at the beginning of the function. By setting a sufficient output interval when inputting data at the beginning of the function chain, subsequent functions can complete processing with ample time to spare. The buffer size of buffer function B1 (70-1) can be calculated by the difference between the amount of data sent from the user at one time and the amount of data sent to function F1 (60-1). However, the user must not continuously send data that exceeds the sending rate of buffer function B1 (70-1). This is to prevent data loss in buffer function B1 (70-1).

[0028] In this way, even if there is a section within the function chain where the processing delay of the functions is reversed, by adding a buffer function to the beginning of the function chain, it is possible to create a function chain that does not lose data even when data is received continuously for a certain period of time.

[0029] <Example of Function Chain Configuration> Figure 5 shows a function chain that includes a section (first section) where the processing delays of the functions are reversed, as well as a section (second section) where a data path branches and the branched data paths merge. This function chain is composed of five functions (F1 to F5) (60-1 to 60-5). In Figure 5, function F3 (60-3) and function F4 (60-4) are connected in parallel, and function F5 (60-5) performs processing using the outputs of both function F3 (60-3) and function F4 (60-4). Each function generates its own processing delay (value in parentheses).

[0030] 5, a reversal of the processing delay occurs in the section between function F1 (60-1) and function F2 (60-2) and the section between function F2 (60-2) and function F4 (60-4).Furthermore, there is a possibility that data loss will occur in function F5 (60-5) due to waiting for input data.

[0031] Figure 6 shows a function chain in which buffer functions have been added to account for differences in processing delay between functions. In Figure 6, two buffer functions B1 and B2 (70-1 and 70-2) have been added to the function chain to avoid the aforementioned data loss. Buffer function B1 (70-1) has been added to the beginning of the function chain to deal with the reversal of processing delay.

[0032] The data output interval of the buffer function B1 (70-1) is set to be equal to or greater than the maximum processing delay of the function chain (=5), so that all functions in the function chain can complete processing before the next data is input.

[0033] The buffer function B2 (70-2) is used to synchronize the data merging timing in the branching and merging sections of the data paths. The data output interval of the buffer function B2 (70-2) is set so that the processing delay in each branched data path is equal. In Figure 6, the data output interval of the buffer function B2 (70-2) is set to the difference (=3) between the processing delay of function F3 (=2) and the processing delay of function F4 (=5).

[0034] Since the buffer function B1 (70-1) at the head of the function chain manages the data input interval, the size of the buffer function B2 (70-2) can be set to the amount of data received at one time.

[0035] Furthermore, the buffer function B2 (70-2) can be added at any position between where the data paths branch and where they merge. Because the position of the buffer function B2 (70-2) can be changed, it is possible to implement the function chain in fewer data processing devices.

[0036] <Timing Chart of Function Chain> Figure 7 is a timing chart of the function chain in Figure 6. Buffer function B1 (70-1) allows functions F2, F4, and F5 (60-2 to 60-5) to perform processes P4 to P6, P10 to P12, and P13 to P15 at the minimum intervals. Buffer function B2 (70-2) also allows functions F3 and F4 (60-3, 60-4) to synchronize the completion timing of processes P7 and P10, P8 and P11, and P9 and P12.

[0037] In this way, even if there is a section within the function chain where the processing delay of the function is reversed as well as a branching and merging section of the data path, by adding a buffer function to the beginning of the function chain and the branching and merging section of the data path, it is possible to create a function chain that does not lose data even when data is received continuously for a certain period of time.

[0038] <Example of Function Chain Configuration> Fig. 8 shows another example of a function chain configuration that takes into account the difference in processing delay between functions in the function chain of Fig. 2. In the function chain of Fig. 8, buffer functions B1 and B2 (70-1, 70-2) are added not to the beginning of the function chain but to the section where the processing delay of the functions is reversed.

[0039] <Timing chart of function chain> Figure 9 is a timing chart of the function chain in Figure 8. When the processes P2 and P3 are completed in the function F1 (60-1), the process P4 in the function F2 (60-2) has not yet finished, so the results of the processes P2 and P3 are stored in the buffer function B1 (70-1) and the function F2 (60-2) waits for the process P4 to be completed.

[0040] Similarly, when the processes P8 and P9 of function F3 (60-3) are completed, the processes P10 and P11 of function F4 (60-4) have not yet been completed, so the results of the processes P8 and P9 are stored in buffer function B2 (70-2) and the function F4 waits for the completion of the process of function F3.

[0041] The buffer size of buffer functions B1 and B2 (70-1 and 70-2) can be calculated from the amount of data sent by the preceding function at one time, the amount of data that the succeeding function can receive at one time, and the processing delay within the buffer. However, the buffer's reception rate must not exceed its transmission rate. This is to prevent data loss in buffer functions B1 and B2 (70-1 and 70-2).

[0042] In this way, even if there is a section within the function chain where the processing delay of the function is reversed, by adding a buffer function to the section where the processing delay of the function is reversed, it is possible to create a function chain that does not lose data even when data is received continuously for a certain period of time.

[0043] <Method of implementing a function chain in a data processing device> The SFCS according to the embodiment of the present invention transfers data between functions via network communication, so functions can be implemented in any data processing device. However, when data processing devices are involved, communication delays between the data processing devices may occur, increasing data transmission delays in the function chain. Furthermore, randomly selecting a data processing device may result in a decrease in the availability of data processing devices throughout the system.

[0044] In this embodiment, when implementing a function chain in a data processing device, the data processing device in which the function chain is implemented is determined taking into consideration (1) the availability of the data processing device and (2) the communication delay between the data processing devices.

[0045] 10 is a diagram for explaining a method of implementing a function chain in a data processing device, and shows an example of a configuration in which the function chain in FIG.

[0046] 10, buffer function B1 (70-1) is implemented in data processing device 1 (30-1), function F1 (60-1) and function F3 (60-3) are implemented in data processing device 2 (30-2), and function F2 (60-2) and function F4 (60-4) are implemented in data processing device 3 (30-3). In Fig. 10, e1, e2, e3, and e4 are data transfer delays between buffer function B1 (70-1) and function F1 (60-1), between function F1 (60-1) and function F2 (60-2), between function F2 (60-2) and function F3 (60-3), and between function F3 (60-3) and function F4 (60-4), respectively.

[0047] In this embodiment, the group consisting of the combination of functions to be implemented in one data processing device is changed, and the group of functions and the data processing device that implements the functions are searched for based on a score calculated based on the implementation cost corresponding to the availability rate of the data processing device and the communication delay between the data processing devices, and the optimal group of functions and the data processing device that implements the functions are determined.

[0048] In this embodiment, the implementation cost is estimated to be higher for data processing devices with lower availability rates. This reduces the possibility that unused data processing devices will be used, and makes it possible to select groups of functions and the data processing devices that implement them so as to reduce the number of data processing devices operating in the entire system.

[0049] On the other hand, for communication delays between data processing devices, for example, the total value of the communication delays between the data processing devices is used as a constraint when selecting a data processing device to implement a function. In the example of Figure 10, the data transfer delay in the function chain is the total value of the data transfer delays e1, e2, e3, and e4 between the above-mentioned functions, and if this data transfer delay is below a predetermined reference value, the group of functions and the data processing device to implement it can be selected.

[0050] In this way, by selecting a data processing device to implement a function based on the implementation cost corresponding to the operating rate of the data processing device and the communication delay between the data processing devices, it is possible to provide a function chaining system that realizes low-latency services while operating the data processing device with high efficiency.

[0051] <Configuration of Data Holding Device Implementing Buffer Function> The configuration of a data holding device implementing a buffer function will be described using Figures 11 and 12. Figure 11 is a block diagram showing an example configuration of a data holding device. A data holding device 80 is made up of an input unit 81 that receives packets, a data acquisition unit 82 that acquires the data portion from the packet, a data holding control unit 83 that controls the input and output of data to and from a storage unit 85, a storage unit 85 that temporarily stores data, a timer unit 84 that notifies the timing of retrieving data from the storage unit 85, a packet generation unit 86 that adds a header to the data retrieved from the storage unit 85 to packetize it, and an output unit 87 that transmits the packets.

[0052] When the data retention control unit 83 stores the data in the memory unit 85, the timer unit 84 counts a fixed time (data output interval). This counting is repeated as long as data exists in the memory unit 85. Each time this fixed time elapses, the data retention control unit retrieves the data from the memory unit 85 in accordance with a timing signal sent from the timer unit 84 and transfers it to the packet generation unit 86.

[0053] If the data retention control unit 83 receives the next data a certain time after the last data was retrieved from the storage unit 85, the data may be transferred directly to the packet generation unit 86 without being stored in the storage unit 85. The data output interval can be changed by setting, so the data retention device 80 can function as a buffer function that outputs data at a predetermined data output interval.

[0054] The packet generator 86 rewrites the tag information, which is the identification information of the function chain, to the next destination, and then packetizes the data. The configuration of the data holding device 80 supports data transfer using tags, and the control device 40 of the function chaining system can handle the data holding device 80 as a single function, in the same way as other service functions.

[0055] If the required buffer size cannot be secured with one data holding device 80, it is possible to increase the buffer size by arranging multiple data holding devices 80 in parallel and sending packets to each device using a method such as round robin.

[0056] The data holding device may be a separate device or may be implemented in the data processing device in the same way as other functions.

[0057] 12 is a block diagram showing another example of the configuration of a data holding device. In addition to the configuration of FIG. 11, this data holding device includes a packet analysis unit 88 that acquires tag information of received packets, and a plurality of storage units 85.

[0058] 12, the packet analysis unit 88 acquires a tag from a received packet, and the data retention control unit 83 stores the data in the memory unit 85 associated with the tag, thereby enabling a single data retention device 80 to implement multiple buffer functions. In this case, the timer unit 84 needs to count the data output interval for each memory unit 85.

[0059] The memory unit 85 may be divided into banks, or the logical address space may be divided into multiple blocks. The former is advantageous in terms of performance because it is physically divided, but it does not necessarily allow the optimal memory size to be set. On the other hand, the latter is more resource efficient because it allows the required memory size to be allocated.

[0060] In the above description, the data retention device 80 deletes headers from received packets, extracts the data, stores the data in a storage unit, and then adds a header to the data to packetize it when the data is extracted from the storage unit and transmitted. It is also possible to store the packets as they are in the storage unit without deleting their headers, and extract and transmit the packets from the storage unit at predetermined output intervals. In this case, the data acquisition unit and packet generation unit in Figures 11 and 12 are unnecessary. Furthermore, although the above description is of a case where tags are rewritten in the packet generation unit, it is also possible to configure the device so that this tag rewriting process is not performed.

[0061] <Flowchart of function chain implementation method> Fig. 13 is a flowchart of a function chain implementation method. When a user requests the use of a service, if the service requested by the user cannot be provided by the currently running services, the control device 40 of the function chaining system starts the function chain implementation process.

[0062] In the flow of FIG. 13, first, the initial function chain is analyzed, and buffer functions are added based on the difference in processing delay between functions (S1-1).

[0063] A buffer function is added to a function chain when the processing delay between functions is reversed, when timing adjustment is required due to branching and merging of data paths between functions, etc. Details of how to add a buffer function will be explained later with reference to Figures 14 to 16.

[0064] Next, the functions including the added buffer function are grouped and divided into a plurality of groups (S1-2).

[0065] As a grouping method, the first grouping may be selected randomly or according to the remaining resources of the implementation site, and the second and subsequent groupings may be selected using a local optimization algorithm that searches for a local optimum solution, such as hill climbing, simulated annealing, or a genetic algorithm.

[0066] After grouping the functions into a plurality of groups, a data processing device for implementing the functions of each of the plurality of groups is selected (S1-3).

[0067] If there is a data processing device capable of implementing the functions of each group (S1-4: YES), a data processing device that implements the functions is searched for among the data processing devices capable of implementing the functions so that the implementation cost is low and the communication delay is small, based on a score calculated based on the implementation cost corresponding to the availability rate of the data processing device and the communication delay between the data processing devices (S1-5, S1-6).If there is no data processing device capable of implementing the functions of each group (S1-4: NO), the functions are grouped again.

[0068] The calculation of the score involves first allocating a cost to the selected data processing device according to its availability, and then calculating the implementation cost of the selected data processing device. Specifically, the implementation cost is calculated to be higher for data processing devices with lower availability, and lower for data processing devices with higher availability. By calculating the implementation cost in this way, the possibility of using unused data processing devices is reduced, thereby improving the availability of data processing devices throughout the system.

[0069] Next, the total communication delay (data transfer delay) between the data processing devices when the functions of the group are assigned to the data processing devices that can implement them is calculated, thereby making it possible to select a combination of data processing devices that will have the smallest data transmission delay in the function chain.

[0070] Finally, a score is calculated by calculating a weighted average of the calculated implementation cost and communication delay. The data processing device that implements the group's functions is changed so that this score is minimized, and the score calculation is repeated. This process of searching for a local optimum solution can be realized using a local optimization algorithm.

[0071] If an implementation location for the group with the smallest score is found (S1-5: YES), the obtained score is compared with the previous best score, and if the obtained score is smaller than the best score, the group, the data processing device to be implemented, and the score are retained (S1-6).

[0072] If the search termination conditions are met (S1-7: YES), such as when the best score is not updated a certain number of times, when the score update range falls below a reference value, or when the updated best score falls below a reference value, the search is terminated and the function is implemented in the data processing device according to the retained group and implementation destination (S1-8). If the search termination conditions are not met (S1-7: NO), the process returns to S1-2 and starts again from grouping the functions.

[0073] <Flowchart of a method for adding a buffer function> Figure 14 is an operational flowchart of a method for adding a buffer function according to an embodiment of the present invention. Figure 14 is an operational flowchart for adding a buffer function in the function chains described with reference to Figures 3 and 8. In Figure 14, first, it is detected whether there is a section in the initial function chain where the processing delay is reversed (S2-1). If no such section is found, there is no need to add a buffer, and the process ends immediately.

[0074] If a reverse section of the processing delay exists, a buffer function is added to the beginning of the initial function chain, or a buffer function is added to the reverse section of the processing delay (S2-2).

[0075] When adding a buffer function to the beginning of the initial function chain, the data output interval of the buffer function is set to be equal to or greater than the maximum processing delay of the function chain.

[0076] After adding the buffer functions, the buffer size required for each buffer is calculated (S2-3).

[0077] When adding a buffer function to the processing delay reversal section, the buffer size of the buffer function can be calculated from the amount of data sent by the preceding function at one time, the amount of data that the subsequent function can receive at one time, and the processing interval.

[0078] 15 is a flowchart illustrating an operation of a method for adding a buffer function according to an embodiment of the present invention, in which a buffer function is added when there is a section where the data paths branch and merge in the function chain described in FIG.

[0079] In FIG. 15, first, a branching and joining section of a data path is detected in the function chain (S3-1), and if such a section cannot be detected, there is no need to add a buffer, so the process ends immediately.

[0080] On the other hand, if the function chain has a section where data paths branch and merge, it is checked whether timing adjustment is necessary at the data path junction (S3-2). If there is a difference in the processing delay of the functions in each branching data path, timing adjustment is necessary. If timing adjustment is necessary (S3-2: YES), a buffer function is added to the branch and merge section, and the data output interval is set to an appropriate value (S3-3), and the buffer size of the buffer function is set to an appropriate value (S3-4).

[0081] 16 is a flowchart showing the operation of a method for adding a buffer function according to an embodiment of the present invention, in which a buffer function is added to the function chain described in FIG.

[0082] 16, first, a section where the processing delay in the initial function chain is reversed is detected (S4-1). If no such section exists (S4-1: NO), there is no need to add a buffer, and the process ends.

[0083] On the other hand, if a reverse interval of the processing delay exists (S4-1: YES), a buffer function is added to the beginning of the initial function chain, and the data output interval is set to be equal to or greater than the maximum processing delay of the function chain (S4-2).

[0084] Next, the section where the data paths in the function chain branch and merge is detected (S4-3), and it is confirmed whether timing adjustment is necessary at the data path junction (S4-5). If timing adjustment is necessary (S4-5: YES), a buffer is added to the section where the data paths branch and merge, and the data output interval is set to an appropriate value (S4-6).

[0085] When there are no more unsearched branching and merging sections (S4-3: NO), the buffer size required for each buffer function is calculated (S4-4). If one data holding device is not enough, the configuration can be changed to one in which multiple data holding devices are connected in parallel.

[0086] As described above, according to this embodiment, in cases where there are sections within a function chain where the processing delay of functions is reversed or where data paths branch and merge, and data loss occurs due to differences in processing delay between functions, by adding a buffer function to an appropriate section depending on the location of the section, it is possible to create a function chain that does not lose data, even when data is received continuously for a certain period of time.

[0087] In addition, by selecting a data processing device to implement a function based on the implementation cost corresponding to the operating rate of the data processing device and the communication delay between the data processing devices, it is possible to provide a function chaining system that realizes low-latency services while operating the data processing device with high efficiency.

[0088] [Extending the Embodiments] The present invention has been described above with reference to the embodiments, but the present invention is not limited to the above embodiments. Various modifications that can be understood by those skilled in the art can be made to the configuration and details of the present invention within the scope of the present invention. Furthermore, the embodiments can be implemented in any combination within a consistent range.

[0089] Some or all of the above-described embodiments can be described as, but are not limited to, the following supplementary notes.

[0090] [Supplementary Note 1] A function chain implementation method executed in a function chaining system having a function chain in which a plurality of functions are combined, the function chaining system comprising: a data processing device that performs data processing of the function on data contained in a received packet; and a control device that implements the function in the data processing device, the control device adding a buffer function to the function chain based on a difference in processing delay between the functions, selecting the data processing device in which to implement the function for each of a plurality of groups of the function, and determining the data processing device in which to implement the function based on a score calculated based on an implementation cost corresponding to the availability rate of the data processing device for the function and a communication delay between the data processing devices. [Supplementary Note 2] The control device detects a first section between the functions in the function chain in which the processing delay of the subsequent function is larger than the processing delay of the previous function, and when the first section is detected, adds the buffer function, whose data output interval is set to a predetermined value, to the first section or to the beginning of the function chain, and detects a second section between the functions in the function chain in which a data path branches and the branched data paths merge, and adds the buffer function, whose data output interval is set to a predetermined value, to the second section so that the processing delay in each of the branched data paths is equal. [Supplementary Note 3] The function chain implementation method according to Supplementary Note 2, in which the control device adds the buffer function, whose data output interval is set to a value equal to or greater than the maximum processing delay in the function chain, to the beginning of the function chain when the first section is detected.and a data processing device that performs data processing of the function on data included in a received packet, the data processing device being configured to: add a buffer function to the function chain based on a difference in processing delay between the functions, select the data processing device that will implement the function for each of a plurality of groups of the function, and determine the data processing device that will implement the function based on a score calculated based on an implementation cost corresponding to the operation rate of the data processing device for the function and the communication delay between the data processing devices.[Supplementary Note 6] The control device detects a first section between the functions in the function chain where the processing delay of a later function is greater than the processing delay of a previous function, and when the first section is detected, adds the buffer function, whose data output interval is set to a predetermined value, to the first section or the beginning of the function chain, detects a second section between the functions in the function chain where a data path branches and the branched data paths merge, and adds the buffer function, whose data output interval is set to a predetermined value, to the second section so that the processing delay in each of the branched data paths is equal. This is the function chaining system described in Supplementary Note 5. [Supplementary Note 7] The function chaining system according to Supplementary Note 5, wherein the control device calculates an implementation cost according to an availability rate of the data processing devices, calculates the implementation cost when the function of the group is assigned to an implementable data processing device, calculates a communication delay between the data processing devices, calculates a score based on the implementation cost and the communication delay, and determines the data processing device that implements the function by changing the data processing device that implements the function of the group and searching for a local optimum solution of the score. [Supplementary Note 8] A data holding device that implements the buffer function in the function chain in the function chain system according to Supplementary Note 5, comprising: a packet analysis unit that analyzes received packets and acquires tag information including identification information of the function chain, at least one memory unit that holds the packets or data of the packets, and a data holding control unit that stores the packets or data of the packets in the memory unit associated with the tag information, and retrieves the packets or data of the packets from the memory unit in accordance with a timing signal from a timer unit.

[0091] The present invention can be applied to service function chaining technology.

[0092] 1... function chaining system, 10... tagging device, 20-1 to 20-3... data transfer devices, 30-1 to 30-4... data processing devices, 40... control device, 50... external transmission device

Claims

1. A function chain implementation method executed in a function chaining system having a function chain combining a plurality of functions, the function chaining system comprising: a data processing device that performs data processing of the function on data contained in a received packet; and a control device that implements the function in the data processing device, the control device adding a buffer function to the function chain based on a difference in processing delay between the functions, selecting the data processing device in which to implement the function for each of a plurality of groups of the function, and determining the data processing device in which to implement the function based on a score calculated based on an implementation cost corresponding to the operation rate of the data processing device for the function and a communication delay between the data processing devices.

2. The function chain implementation method of claim 1, wherein the control device detects a first section between the functions in the function chain in which the processing delay of a later function is greater than the processing delay of a previous function, and when the first section is detected, adds the buffer function, the data output interval of which is set to a predetermined value, to the first section or to the beginning of the function chain, detects a second section between the functions in the function chain in which a data path branches and the branched data paths merge, and adds the buffer function, the data output interval of which is set to a predetermined value, in the second section so that the processing delay in each of the branched data paths is equal.

3. A function chain implementation method as described in claim 2, wherein the control device, when detecting the first section, adds to the beginning of the function chain the buffer function, the data output interval of which is set to a value equal to or greater than the maximum processing delay in the function chain.

4. The function chain implementation method of claim 1, wherein the control device calculates an implementation cost based on the availability rate of the data processing devices, calculates the implementation cost when the functions of the group are assigned to the data processing devices capable of implementing the functions, calculates a communication delay between the data processing devices, calculates a score based on the implementation cost and the communication delay, and determines the data processing device that implements the functions of the group by changing the data processing device that implements the functions of the group and searching for a local optimum solution of the score.

5. A function chaining system having a function chain combining a plurality of functions, comprising: a data processing device that performs data processing of the function on data contained in a received packet; and a control device that implements the function in the data processing device, wherein the control device is configured to: add a buffer function to the function chain based on a difference in processing delay between the functions; select the data processing device in which to implement the function for each of a plurality of groups of the functions; and determine the data processing device in which to implement the function based on a score calculated based on an implementation cost corresponding to the operation rate of the data processing device for the function and a communication delay between the data processing devices.

6. The function chaining system of claim 5, wherein the control device detects a first section between the functions in the function chain in which the processing delay of a subsequent function is greater than the processing delay of a previous function, and when the first section is detected, adds the buffer function, the data output interval of which is set to a predetermined value, to the first section or to the beginning of the function chain, detects a second section between the functions in the function chain in which a data path branches and the branched data paths merge, and adds the buffer function, the data output interval of which is set to a predetermined value, in the second section so that the processing delay in each of the branched data paths is equal.

7. The function chaining system of claim 5, wherein the control device calculates an implementation cost according to the availability rate of the data processing devices, calculates the implementation cost when the functions of the group are assigned to the data processing devices capable of implementing the functions, calculates a communication delay between the data processing devices, calculates a score based on the implementation cost and the communication delay, and determines the data processing device that implements the functions by changing the data processing device that implements the functions of the group and searching for a local optimum solution of the score.

8. A data holding device which implements the buffer function within the function chain in the function chaining system described in claim 5, comprising: a packet analysis unit which analyzes a received packet and obtains tag information including identification information of the function chain; at least one memory unit which holds the packet or the packet data; and a data holding control unit which stores the packet or the packet data in the memory unit associated with the tag information and retrieves the packet or the packet data from the memory unit in accordance with a timing signal from a timer unit.

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