Temporal kernel device, temporal kernel computing system, and method for operating device and system

Abstract

Disclosed are a temporal kernel device, a temporal kernel computing system comprising same, and a method for operating the device and system. The disclosed temporal kernel device may comprise one or more temporal kernel cell structures, wherein each of the temporal kernel cell structures may comprise a first nonvolatile memristor, and a second nonvolatile memristor and a capacitor connected in parallel to each other, wherein the second nonvolatile memristor and the capacitor connected in parallel to each other may be connected in series to the first nonvolatile memristor. The temporal kernel device may comprise a first electrode, a second electrode, an intermediate electrode, and a third electrode, the capacitor may be disposed between the first electrode and the intermediate electrode, the second nonvolatile memristor may be disposed between the second electrode and the intermediate electrode, and the first nonvolatile memristor may be disposed between the intermediate electrode and the third electrode.

Description

Time kernel elements, time kernel computing systems, and their operating methods

[0001] The present invention relates to a kernel-related device and system, and more particularly, to a time kernel element, a time kernel computing system including the same, and an operating method thereof.

[0002] In computer science, a kernel is a computer program that serves as the core of a computer operating system. It controls the entire system and provides various services necessary for application execution. In the recently burgeoning field of artificial intelligence, kernels can preprocess signals input to artificial neural networks. In particular, a temporal kernel refers to a kernel capable of processing data in a time-series fashion.

[0003] Existing time-dependent kernel components include reservoir computing components. Reservoir computing components incorporate a single volatile memristor in their unit cell structure and utilize the volatile properties of the memristor to process time-dependent input signals. However, existing memristor-based reservoir computing systems face controllability issues due to the inherent fixed relaxation dynamics of a given material. In other words, time-dependent kernels based on volatile memristors have limitations in that they cannot control the rate of relaxation of the memristor's conductance state, as the relaxation is dependent on the material's properties, and they cannot implement dynamics other than relaxation. Consequently, it is difficult to control the temporal characteristics of the reservoir.

[0004] Furthermore, existing memristive resistor-capacitor (RC) systems have inherent limitations in implementing higher-dimensional reservoirs due to their architecture, in which one input signal is mapped to one memristor. To enhance the diversity of reservoir states in physical reservoir computing systems, two approaches can be used: device-to-device variation (D2D variation) and virtual nodes. However, D2D variation is nearly uncontrollable and has limitations in effectively enhancing reservoir richness. This problem arises because D2D variation-based reservoirs generate highly correlated dimensions, which increase training parameters without significantly improving reservoir performance. On the other hand, the virtual node method may have good performance, but it has the problem that it requires buffer memory to store temporal results because it performs sequential operations.

[0005] The technical problem to be solved by the present invention is to provide a temporal kernel device capable of achieving high dimensional data mapping and tunable dynamics.

[0006] In addition, the technical problem to be achieved by the present invention is to provide a temporal kernel device that can improve the diversity of reservoir states and perform efficient and accurate data processing with high dimensionality and tunable dynamics without unnecessarily increasing training parameters or relying on sequential operations.

[0007] In addition, a technical problem to be achieved by the present invention is to provide a time kernel computing system including the above-described time kernel element.

[0008] In addition, the technical problem to be achieved by the present invention is to provide an operating method of the time kernel element and the time kernel computing system.

[0009] The problems to be solved by the present invention are not limited to the problems mentioned above, and other problems not mentioned can be understood by those skilled in the art from the description below.

[0010] According to one embodiment of the present invention, a temporal kernel device is provided, comprising one or more temporal kernel cell structures, each of the temporal kernel cell structures comprising a first nonvolatile memristor; and a second nonvolatile memristor and a capacitor connected in parallel with each other, wherein the second nonvolatile memristor and the capacitor connected in parallel with each other are connected in series with the first nonvolatile memristor.

[0011] The time kernel element may include a first electrode, a second electrode, a middle electrode, and a third electrode, the capacitor may be disposed between the first electrode and the middle electrode, the second non-volatile memristor may be disposed between the second electrode and the middle electrode, and the first non-volatile memristor may be disposed between the middle electrode and the third electrode.

[0012] An electrical signal corresponding to a time-series input signal can be applied to the third electrode while the first and second electrodes are grounded.

[0013] A plurality of the above time kernel cell structures may be arranged to form an array, wherein the time kernel elements may include first and second electrodes extending in a first direction while being spaced apart from each other, a plurality of third electrodes extending in a second direction while being spaced apart from the first and second electrodes and intersecting the first and second electrodes, and a plurality of intermediate electrodes arranged between the electrode groups composed of the first and second electrodes and the plurality of third electrodes to correspond to the plurality of third electrodes, respectively, and wherein the plurality of time kernel cell structures may be arranged between the electrode groups composed of the first and second electrodes and the plurality of third electrodes, and each of the time kernel cell structures may include the capacitor arranged between the first electrode and the intermediate electrode, the second nonvolatile memristor arranged between the second electrode and the intermediate electrode, and the first nonvolatile memristor arranged between the intermediate electrode and the third electrode.

[0014] The first non-volatile memristor and the second non-volatile memristor may be arranged on the same vertical axis, and the capacitor may be arranged horizontally spaced from the second non-volatile memristor.

[0015] The first and second non-volatile memristors may be configured to store different information for the same input signal.

[0016] The time kernel element may be configured to store information in the first and second non-volatile memristors, and input the information stored in the first and second non-volatile memristors into an artificial neural network.

[0017] According to another embodiment of the present invention, a temporal kernel computing system is provided, including the aforementioned temporal kernel element; and an artificial neural network connected to the temporal kernel element and receiving information processed by the temporal kernel element.

[0018] According to another embodiment of the present invention, there is provided a method of operating a temporal kernel device comprising one or more temporal kernel cell structures, each of the temporal kernel cell structures comprising a first nonvolatile memristor and a second nonvolatile memristor and a capacitor connected in parallel with each other, wherein the second nonvolatile memristor and the capacitor are connected in series with the first nonvolatile memristor, the method comprising: applying a time-series input signal to the temporal kernel cell structure to store information in the first and second nonvolatile memristors; and reading the information stored in the first and second nonvolatile memristors.

[0019] The time kernel element may include a first electrode, a second electrode, a middle electrode, and a third electrode, the capacitor may be disposed between the first electrode and the middle electrode, the second non-volatile memristor may be disposed between the second electrode and the middle electrode, and the first non-volatile memristor may be disposed between the middle electrode and the third electrode.

[0020] The step of storing information in the first and second non-volatile memristors may include the step of applying an electrical signal corresponding to the time-series input signal to the third electrode while the first and second electrodes are grounded.

[0021] The step of reading information stored in the first and second non-volatile memristors may include a step of applying an electrical signal for reading information stored in the first non-volatile memristor between the third electrode and the middle electrode, and a step of applying an electrical signal for reading information stored in the second non-volatile memristor between the middle electrode and the second electrode.

[0022] A plurality of the above time kernel cell structures may be arranged to form an array, wherein the time kernel elements may include first and second electrodes extending in a first direction while being spaced apart from each other, a plurality of third electrodes extending in a second direction while being spaced apart from the first and second electrodes and intersecting the first and second electrodes, and a plurality of intermediate electrodes arranged between the electrode groups composed of the first and second electrodes and the plurality of third electrodes to correspond to the plurality of third electrodes, respectively, and wherein the plurality of time kernel cell structures may be arranged between the electrode groups composed of the first and second electrodes and the plurality of third electrodes, and each of the time kernel cell structures may include the capacitor arranged between the first electrode and the intermediate electrode, the second nonvolatile memristor arranged between the second electrode and the intermediate electrode, and the first nonvolatile memristor arranged between the intermediate electrode and the third electrode.

[0023] According to embodiments of the present invention, a temporal kernel device capable of achieving high dimensional data mapping and tunable dynamics can be implemented by using a 2M (memristor) - 1C (capacitor) temporal kernel cell structure including two nonvolatile memristors and one capacitor. According to embodiments of the present invention, there is provided a temporal kernel device capable of improving the diversity of reservoir states and performing efficient and accurate data processing with high dimensionality and tunable dynamics without unnecessarily increasing training parameters or relying on sequential operations.

[0024] In particular, according to embodiments of the present invention, since two non-volatile memristors can perform uncorrelated, individualized dimension data mapping for the same input signal, the dimensionality of data mapping can be increased, and the accuracy and efficiency of data processing can be improved. In addition, the time constant can be easily adjusted by adjusting the size of the capacitor or the initial resistance value of the two non-volatile memristors as needed. In addition, since the mapping signal can be varied by adjusting the pulse shape of the input signal, the freedom of use of the device can be improved.

[0025] For example, the complementary features projected onto each memristor reflect the characteristics of the binary pattern of the input signal, and can exhibit an accuracy of about 94.3% or higher and about 86.4% or higher in the 8-bit and 28-bit cases, respectively, in the Modified National Institute of Standards and Technology (MNIST) classification task. In addition, for example, for Mackey-Glass nonlinear timeseries patterns, the time kernel element can exhibit an NRMSE (normalized root mean square error) of 0.04 at the minimum network size (20×1), which can be said to have verified excellent prediction performance.

[0026] By applying the temporal kernel elements according to the above-described embodiments, a temporal kernel computing system having excellent performance and applicable to various fields can be implemented.

[0027] However, the effects of the present invention are not limited to the above effects, and can be expanded in various ways without departing from the technical spirit and scope of the present invention.

[0028] FIG. 1 is a diagram exemplarily showing a temporal kernel device and a temporal kernel computing system including the same according to one embodiment of the present invention.

[0029] FIG. 2 is a diagram showing changes in voltage applied to first and second non-volatile memristors and changes in conductance of each memristor according to application of a temporal signal to a time kernel cell structure of a time kernel element according to one embodiment of the present invention.

[0030] FIG. 3 is a circuit diagram for explaining the operating principle of a time kernel element according to one embodiment of the present invention.

[0031] FIG. 4 is a diagram showing the overall operation method of a temporal kernel computing system including a temporal kernel element according to one embodiment of the present invention.

[0032] FIG. 5 is a diagram showing an optical microscope image (left image) of a time kernel device according to one embodiment of the present invention and a cross-sectional SEM (scanning electron microscope) image (right image) of a time kernel cell structure.

[0033] FIG. 7 is a diagram showing energy dispersive spectrometer (EDS) line profiles of a first nonvolatile memristor, a second nonvolatile memristor, and a capacitor that can be applied to a time kernel element according to one embodiment of the present invention.

[0034] FIG. 8 is a graph exemplarily showing voltage-current characteristics of first and second non-volatile memristors that can be applied to a time kernel element according to one embodiment of the present invention.

[0035] FIG. 9 is a graph showing the results of measuring the final conductance after applying ten voltage pulses to the first and second non-volatile memristors that can be applied to a time kernel element according to one embodiment of the present invention.

[0036] FIG. 10 is a graph showing a capacitance value in a predetermined voltage range according to a feature size (F) of a capacitor that can be applied to a time kernel element according to one embodiment of the present invention.

[0037] FIGS. 11 to 13 are diagrams showing changes in voltage applied to first and second non-volatile memristors and changes in conductance of each memristor according to application of an input signal to a time kernel element according to one embodiment of the present invention.

[0038] FIG. 14 is a diagram showing final conductance states measured in a first nonvolatile memristor and a second nonvolatile memristor for 16 cases of 4-bit patterns from '0000' to '1111' according to one embodiment of the present invention.

[0039] FIG. 15 is a schematic diagram exemplarily showing an image inference process using a time kernel computing system including a time kernel element according to one embodiment of the present invention.

[0040] FIG. 16 is a graph showing the maximum accuracy achieved under the conditions of each input sequence and the input network size when performing image inference using a time kernel computing system including a time kernel element according to one embodiment of the present invention.

[0041] Fig. 17 is a graph showing the results of performing initialization and prediction using only the conductance vector of the first non-volatile memristor in Mackey-Glass time series prediction according to a comparative example.

[0042] Fig. 18 is a graph showing the results of performing initialization and prediction using only the conductance vector of the second non-volatile memristor in Mackey-Glass time series prediction according to a comparative example.

[0043] FIG. 19 is a graph showing the results of performing initialization and prediction using both the conductance vector of the first nonvolatile memristor and the conductance vector of the second nonvolatile memristor in Mackey-Glass time series prediction according to one embodiment of the present invention.

[0044] FIG. 20 is a diagram showing the results of evaluating conductance values ​​for four types of time series patterns to analyze information extracted from the time series of a first nonvolatile memristor and a second nonvolatile memristor according to an embodiment of the present invention.

[0045] Hereinafter, embodiments of the present invention will be described in detail with reference to the attached drawings.

[0046] The embodiments of the present invention described below are provided to more clearly explain the present invention to a person having ordinary skill in the art, and the scope of the present invention is not limited by the following embodiments, and the following embodiments can be modified in various other forms.

[0047] The terminology used herein is used to describe particular embodiments and is not intended to limit the present invention. The singular forms used herein may include the plural forms unless the context clearly dictates otherwise. In addition, the terms "comprise" and / or "comprising" used herein specify the presence of a stated feature, step, number, operation, element, element, and / or group thereof, but do not exclude the presence or addition of one or more other features, steps, numbers, operations, elements, elements, and / or groups thereof. In addition, the term "connected" used herein not only means that certain elements are directly connected, but also includes a concept that indirectly connects elements by interposing another element between them.

[0048] In addition, when it is said in this specification that a certain element is located "on" another element, this includes not only cases where a certain element is in contact with another element, but also cases where another element exists between the two elements. The term "and / or" as used in this specification includes any one of the listed items and any and all combinations of one or more of them. In addition, terms of degree such as "about", "substantially", etc. as used in this specification are used to mean a range of or close to the numerical value or degree, taking into account inherent manufacturing and material tolerances, and are used to prevent infringers from unfairly using the disclosure that mentions exact or absolute numbers provided to help the understanding of this specification.

[0049] Hereinafter, embodiments of the present invention will be described in detail with reference to the attached drawings. The sizes and thicknesses of areas or parts illustrated in the attached drawings may be somewhat exaggerated for clarity and convenience of explanation. Like reference numbers designate like components throughout the detailed description.

[0050] FIG. 1 is a diagram exemplarily showing a temporal kernel device and a temporal kernel computing system including the same according to one embodiment of the present invention. The temporal kernel device may be referred to as a hardware temporal kernel device.

[0051] Referring to FIG. 1, a time kernel device (100) according to an embodiment of the present invention may include one or more temporal kernel cell structures (CL1). The time kernel cell structure (CL1) may include a first nonvolatile memristor (11) and a second nonvolatile memristor (12) and a capacitor (20) connected in parallel with each other, wherein the second nonvolatile memristor (12) and the capacitor (20) connected in parallel with each other may be connected in series with the first nonvolatile memristor (11). The time kernel cell structure (CL1) may be said to have a 2M-1C configuration. Here, M represents nonvolatile memristors (11, 12), and C represents a capacitor (20). The time kernel device (100) may be an integrated temporal kernel device having a 2M-1C cell configuration.

[0052] Each of the first and second non-volatile memristors (11, 12) may include two electrodes (e.g., a lower electrode and an upper electrode) and a resistance-variable material layer (resistance-variable memory layer) disposed therebetween. For example, each of the first and second non-volatile memristors (11, 12) may have a TiN / HfO2 / W structure, wherein TiN may correspond to the lower electrode (or upper electrode), W (tungsten) may correspond to the upper electrode (or lower electrode), and HfO2 may correspond to the resistance-variable material layer, respectively. However, this is merely exemplary, and the specific structure and constituent materials of the first and second non-volatile memristors (11, 12) may vary. The structure and materials of existing non-volatile memristors may be applied to the first and second non-volatile memristors (11, 12). The first and second non-volatile memristors (11, 12) may have the same laminated structure, but in some cases, they may have different laminated structures.

[0053] The capacitor (20) may include two electrodes (e.g., a lower electrode and an upper electrode) and a dielectric layer disposed therebetween. For example, the capacitor (20) may have a TiN / ZrO2 / Al2O3 / ZrO2 / TiN structure, wherein TiN may correspond to the lower electrode and the upper electrode, and ZrO2 / Al2O3 / ZrO2 may correspond to the dielectric layer, respectively. ZnO2 may play a role in increasing the permittivity, and Al2O3 may play a role in suppressing the leakage current. Therefore, by using a dielectric layer having a ZrO2 / Al2O3 / ZrO2 structure, a capacitor (20) having a high permittivity and a low leakage current can be manufactured. However, the specific structure and constituent materials of the capacitor (20) exemplified herein are merely exemplary and may be variously changed depending on the case. The structure and materials of existing capacitors can be applied to the capacitor (20).

[0054] Although the capacitor (20) is illustrated as a single capacitor element (capacitor element), it may, in some cases, include multiple capacitor elements. That is, the capacitor (20) may be understood to include either a single capacitor element or multiple capacitor elements. When the capacitor (20) includes the multiple capacitor elements, at least one of the multiple capacitor elements may be selectively used.

[0055] A time kernel element (100) may include a first electrode (E10), a second electrode (E20), a middle electrode (E25), and a third electrode (E30). A capacitor (20) may be disposed between the first electrode (E10) and the middle electrode (E25), and a second non-volatile memristor (12) may be disposed between the second electrode (E20) and the middle electrode (E25). A first non-volatile memristor (11) may be disposed between the middle electrode (E25) and the third electrode (E30). Accordingly, the first non-volatile memristor (11) and the second non-volatile memristor (12) may be connected in series through the middle electrode (E25), and similarly, the first non-volatile memristor (11) and the capacitor (20) may be connected in series through the middle electrode (E25). In addition, the second non-volatile memristor (12) and the capacitor (20) may be connected in parallel to the first non-volatile memristor (11) via the intermediate electrode (E25). The intermediate electrode (E25) may be referred to as a bridge electrode connecting the second non-volatile memristor (12) and the capacitor (20). The time kernel cell structure (CL1) may be considered to include the first non-volatile memristor (11), the second non-volatile memristor (12), the capacitor (20), and the intermediate electrode (E25), and the first and second electrodes (E10, E20) may be connected to one end of the time kernel cell structure (CL1), and the third electrode (E30) may be connected to the other end. In some cases, at least a portion of the first and second electrodes (E10, E20) and / or at least a portion of the third electrode (E30) may also be considered to be included in the time kernel cell structure (CL1).

[0056] A plurality of time kernel cell structures (CL1) can be arranged. In other words, a plurality of time kernel cell structures (CL1) can be arranged to form an array. At this time, the time kernel element (100) can include first and second electrodes (E10, E20) extending in a first direction while being spaced apart from each other (e.g., spaced apart horizontally), a plurality of third electrodes (E30) extending in a second direction while being spaced apart from the first and second electrodes (E10, E20) (e.g., spaced upwardly) and intersecting (e.g., vertically intersecting) the first and second electrodes (E10, E20), and a plurality of intermediate electrodes (E25) arranged between the electrode group composed of the first and second electrodes (E10, E20) and the plurality of third electrodes (E30) so as to correspond to each of the plurality of third electrodes (E30). A plurality of intermediate electrodes (E25) can extend in the second direction.

[0057] A plurality of time kernel cell structures (CL1) may be respectively arranged between the electrode group composed of the first and second electrodes (E10, E20) and the plurality of third electrodes (E30). The plurality of time kernel cell structures (CL1) may respectively be arranged at the intersections of the electrode group composed of the first and second electrodes (E10, E20) and the plurality of third electrodes (E30). Accordingly, a plurality of time kernel cell structures (CL1) spaced apart from each other in a direction parallel thereto may be arranged on the electrode group composed of the first and second electrodes (E10, E20), and a third electrode (E30) connected (in contact with) the same may be arranged on each time kernel cell structure (CL1). Each of the time kernel cell structures (CL1) may include a capacitor (20) disposed between a first electrode (E10) and a middle electrode (E25), a second non-volatile memristor (12) disposed between a second electrode (E20) and the middle electrode (E25), and a first non-volatile memristor (11) disposed between the middle electrode (E25) and a third electrode (E30). Here, a case where one first electrode (E10) and one second electrode (E20) are used is illustrated, but a plurality of electrode groups composed of the first and second electrodes (E10, E20) may be disposed, and a plurality of time kernel cell structures (CL1) and a plurality of third electrodes (E30) may be disposed on each of the electrode groups. In addition, the stack of elements from the electrode group consisting of the first and second electrodes (E10, E20) to the third electrode (E30) may be reversed in their vertical order. A part of the first electrode (E10) may be included in the capacitor (20), and a part of the intermediate electrode (E25) may also be included in the capacitor (20). A part of the second electrode (E20) may be included in the second non-volatile memristor (12), and a part of the intermediate electrode (E25) may also be included in the second non-volatile memristor (12).A portion of the middle electrode (E25) may be included in the first non-volatile memristor (11), and a portion of the third electrode (E30) may also be included in the first non-volatile memristor (11).

[0058] When inputting data into the time kernel element (100), an electrical signal corresponding to a time-series input signal (e.g., an input signal that changes over time) may be applied to the third electrode (E30) while the first and second electrodes (E10, E20) are grounded. In other words, when storing information in the first and second non-volatile memristors (11, 12) of the time kernel cell structure (CL1), an electrical signal corresponding to a time-series input signal may be applied to the third electrode (E30) while the first and second electrodes (E10, E20) are grounded. At this time, the middle electrode (E25) may be in a floating state. In the step for storing information in the time kernel element (100), the electrical signal may be applied to a plurality of third electrodes (E30) while the first and second electrodes (E10, E20) are grounded. Through this, information can be stored in the first and second non-volatile memristors (11, 12) of each of the multiple time kernel cell structures (CL1).

[0059] Meanwhile, in the step of reading information stored in the first and second non-volatile memristors (11, 12), an electrical signal for reading information stored in the first non-volatile memristor (11) can be applied between the third electrode (E30) and the middle electrode (E25), and further, an electrical signal for reading information stored in the second non-volatile memristor (12) can be applied between the middle electrode (E25) and the second electrode (E20). When applying an electrical signal for reading information stored in the first non-volatile memristor (11) between the third electrode (E30) and the middle electrode (E25), the second electrode (E20) can be floated. Similarly, when applying an electrical signal for reading information stored in the second non-volatile memristor (12) between the middle electrode (E25) and the second electrode (E20), the third electrode (E30) may be floated. In addition, in the step of reading information stored in the first and second non-volatile memristors (11, 12), the first electrode (E10) may be floated. By separately forming the first electrode (E10) and the second electrode (E20) connected to the capacitor (20) and the second non-volatile memristor (12) below them, the influence of the capacitor (20) can be eliminated during the reading. Therefore, problems such as RC delay can be prevented during the reading. The electrical signal for reading the above information may be, for example, a direct current (DC) voltage signal, and the information can be read by measuring (sensing) the size of the current flowing through the non-volatile memristor (11, 12) by applying the direct current (DC) voltage signal.

[0060] According to one embodiment, in the time kernel cell structure (CL1), the first non-volatile memristor (11) and the second non-volatile memristor (12) may be arranged on the same (or substantially the same) vertical axis, and the capacitor (20) may be arranged horizontally spaced apart from the second non-volatile memristor (12). The capacitor (20) may be arranged at the same level (height) or substantially the same level (height) as the second non-volatile memristor (12). In this case, the manufacturing of the time kernel element (100) may be easy, and may be advantageous in improving space efficiency and integration. However, the arrangement relationship between the first non-volatile memristor (11), the second non-volatile memristor (12), and the capacitor (20) in the time kernel cell structure (CL1) is not limited to the above-described one, and may vary depending on the case.

[0061] The time kernel element (100) according to an embodiment of the present invention may have a time kernel cell structure (CL1) having the above-described 2M-1C configuration, and in this time kernel cell structure (CL1), information stored in the first and second non-volatile memristors (11, 12) may be different due to the influence of the capacitor (20). That is, the first and second non-volatile memristors (11, 12) may store different information for the same input signal (time-series input signal). More specifically, when a high signal enters the time kernel cell structure (CL1) after the capacitor (20) is discharged by a low signal, a spike (voltage spike) signal may be generated in the first non-volatile memristor (11). Accordingly, it can be said that the first nonvolatile memristor (11) mainly reflects the number of transitions from a low signal to a high signal and the related characteristics in an input signal in which low signals and high signals are randomly repeated. On the other hand, the second nonvolatile memristor (12) can be said to reflect the number of high signals and the related characteristics in the input signal because it is mainly affected by the number of high signal inputs in a different way from the first nonvolatile memristor (11). Since the first and second nonvolatile memristors (11, 12) can perform uncorrelated, individualized dimension data mapping for the same input signal, the dimension of data mapping can be increased and the accuracy and efficiency of data processing can be improved.According to an embodiment of the present invention, a time kernel element can be implemented that can improve the diversity of reservoir states and perform efficient and accurate data processing with high dimensionality and tunable dynamics without unnecessarily increasing training parameters or relying on sequential operations.

[0062] In addition, according to an embodiment of the present invention, the time constant can be easily adjusted by adjusting the size of the capacitor (20) or the initial resistance values ​​of the two non-volatile memristors (11, 12) as needed. In addition, since the mapping signal can be varied by adjusting the pulse shape of the input signal, the degree of freedom in utilizing the time kernel element can be improved.

[0063] A time kernel element (100) according to an embodiment of the present invention may be configured to process a time-series input signal (input information) to store information in first and second non-volatile memristors (11, 12), and input the information stored in the first and second non-volatile memristors (11, 12) into an artificial neural network (200). In other words, information stored in the first and second non-volatile memristors (11, 12) and then read out may be input into the artificial neural network (200). The information stored in the first and second non-volatile memristors (11, 12) may be input into the artificial neural network (200) in the form of, for example, a memristor conductance vector (MCV), and it may be determined what information was first input into the time kernel element (100) through information (data) processing / recognition of the artificial neural network (200).

[0064] A temporal kernel computing system according to an embodiment of the present invention may include a temporal kernel element (100) described above and an artificial neural network (200) connected to the temporal kernel element (100) and receiving information processed by the temporal kernel element (100). The specific configuration and principles of the artificial neural network (200) may be the same as or similar to those well known in the art.

[0065] A brief and illustrative description of a method for manufacturing a time kernel element according to one embodiment of the present invention is as follows.

[0066] For example, when manufacturing a time kernel element, a capacitor, a second non-volatile memristor, and a first non-volatile memristor can be manufactured in this order. First, a SiO2 layer having a thickness of about 100 nm can be thermally formed on a Si substrate, and a TiN layer having a thickness of about 80 nm can be formed on the SiO2 layer at room temperature by a sputtering method. The TiN layer can be patterned in a line shape as a lower electrode of the capacitor. The lower electrode of the capacitor can have a width of, for example, about 5 to 500 μm, and can be patterned by a conventional photolithography and dry etching method. Then, at a substrate temperature of about 280° C., an ALD (atomic layer deposition) process can be used to sequentially deposit about 3 nm ZrO2, about 2.5 nm Al2O3, and about 3 nm ZrO2. That is, a ZAZ dielectric can be formed. About 60 nm TiN can be sputtered and deposited on the ZAZ dielectric, and the TiN and the ZAZ dielectric can be patterned to form a capacitor including an upper electrode patterned from the TiN. After the formation of the capacitor, a first passivation layer having a thickness of about 80 nm can be deposited using a plasma enhanced chemical vapor deposition (PECVD) process. The first passivation layer can be formed to cover the capacitor, and can be formed of, for example, SiO2. Then, about 60 nm thick TiN can be sputtered and patterned to form a second nonvolatile memristor lower electrode having a width of about 5 to 20 μm next to the capacitor. Then, a HfO2 film that serves as a resistance-variable memory layer for the second non-volatile memristor can be deposited to a thickness of about 2.5 nm using a PEALD (plasma enhanced atomic layer deposition) process at a substrate temperature of about 280°C.Then, W (tungsten) having a thickness of about 40 nm can be deposited by sputtering at room temperature, and the W and HfO2 film can be patterned to form a second non-volatile memristor. Next, a second passivation layer having a thickness of about 80 nm can be deposited. The second passivation layer can be formed to cover the capacitor and the second non-volatile memristor, and can be formed of, for example, SiO2. The second passivation layer and the first passivation layer can be wet-etched with a BOE (buffered oxide etchant) solution to expose the upper electrode of the capacitor and the upper electrode of the second non-volatile memristor. Then, TiN having a thickness of about 60 nm can be deposited by sputtering and patterned to form an intermediate electrode having a width of about 5 to 20 μm. A part of the above intermediate electrode can be used as a lower electrode of the first non-volatile memristor. Next, a HfO2 film, which serves as a resistance variable memory layer for the first non-volatile memristor, can be deposited to a thickness of about 2.5 nm using a PEALD process, and patterned. W (tungsten) to a thickness of about 40 nm can be sputtered and deposited on the patterned HfO2 film, and patterned to form an upper electrode of the first non-volatile memristor in a line shape. However, the specific materials, device structures, process conditions, etc. mentioned in the method for manufacturing the time kernel device according to the above-described embodiment are merely exemplary and may be variously changed.

[0067] FIG. 2 is a diagram showing changes in voltages applied to first and second non-volatile memristors (M1, M2) and changes in conductance of each memristor (M1, M2) according to application of a temporal signal to a time kernel cell structure of a time kernel element according to one embodiment of the present invention. FIG. 2 shows changes in voltages applied to each memristor (M1, M2) and conductance of each memristor (M1, M2) when an input signal (low signal '0', high signal '1') corresponding to '1101' is applied to the time kernel cell structure as a pulse stream according to time (t1 to t4).

[0068] Referring to Fig. 2, the input voltage can be distributed to the first nonvolatile memristor (M1) and the second nonvolatile memristor (M2) according to the dynamic relationship of the first and second nonvolatile memristors (M1, M2). Here, V(M1) represents the voltage applied to the first nonvolatile memristor (M1), and V(M2) represents the voltage applied to the second nonvolatile memristor (M2). V, which is the voltage of the capacitor (C), C can be equal to V(M2). Due to the memristive resistance with the capacitive element, there may be a delay in the charging and discharging of the capacitor (C). This behavior causes a 'peak and relaxation' voltage pattern for M1 and an 'increase and saturation' pattern for M2 at high signals (see upper graph), which may result in different conductance evolutions of M1 and M2 (see lower graph).

[0069] In the case of M1, when a high signal ('1') is input while the capacitor (C) is discharged, a spike (voltage spike) signal may be applied, and at this time, a large increase in conductance may occur. The capacitor (C) may be initially in a discharged state, and may also be discharged when a low signal ('0') is input. Therefore, when a high signal is input to the time kernel cell structure after the capacitor (C) is discharged by the low signal, a spike (voltage spike) signal may be generated in M1. Therefore, it can be said that M1 mainly reflects the number of transitions from a low signal to a high signal and related characteristics.

[0070] Meanwhile, in the case of M2, since a voltage similar to the input signal is applied, an increase in conductance may mainly appear when a high signal is input, and may be mainly affected by the number of high signal inputs. Unlike M1, M2 is mainly affected by the number of high signal inputs, so it can be said to reflect the number of high signals and related characteristics in the input signal. Therefore, M1 and M2 can perform uncorrelated, individualized dimension data mapping for the same input signal. In this regard, the dimensionality of data mapping can be increased, and the accuracy and efficiency of data processing can be improved.

[0071] FIG. 3 is a circuit diagram for explaining the operating principle of a time kernel element according to one embodiment of the present invention.

[0072] Referring to Fig. 3, the drawing (A) shows a circuit diagram of a time kernel cell structure. Here, a pulse generator (PG) can supply an input voltage stream to the device using the lower electrodes of M2 (a second non-volatile memristor) and C (a capacitor), which are grounded. When a high signal is supplied while C is discharged, V(M1) may rapidly increase and then decrease to saturate, and V(M2) may gradually increase to saturate as C is gradually charged with the high signal. Subsequently, when a low signal is applied, C may return to its original discharged state. As can be seen in drawings (B) and (C) of FIG. 3, when temporal data is cascaded through a time kernel cell structure, high and low signals are repeated and charge / discharge RC delays occur, resulting in distinct voltage patterns for M1 (a first non-volatile memristor) and M2 (a second non-volatile memristor). The input voltage can be distributed to M1 and M2, and a voltage spike can occur in M1 due to the RC delay, and a gradually increasing voltage can be applied to M2.

[0073] The voltage spike of M1 can only occur if C has previously discharged, making the voltage spike of M1 sensitive to a low signal ('0') preceding a high signal ('1'). Conversely, V(M2) can depend on the high signal ('1') itself, as it increases with the charging of C. C can be discharged through M1 and M2, as shown in drawing (C) of Fig. 3. However, the current flowing through M1 and M2 can be different due to their different conductances, voltage-current nonlinearity, and bias polarity dependence. This feature can also contribute to the high performance of the time-kernel system by enriching the final conductance states of M1 and M2. Therefore, M1 and M2 in the time-kernel cell structure can extract and map complementary information for the same input, providing a unique approach to time-kernel computing.

[0074] FIG. 4 is a diagram showing the overall operation method of a temporal kernel computing system including a temporal kernel element according to one embodiment of the present invention.

[0075] Referring to FIG. 4, in a method of operating a time kernel computing system including a time kernel element according to an embodiment of the present invention, an input signal is input to the time kernel element, and dual mapping is performed by two non-volatile memristors (M1, M2), so that it can be projected into two distinct conductance vectors. Then, combination and inference can be performed in a subsequent readout layer. The performance of the time kernel computing system can be verified through applications in, for example, image recognition and nonlinear time series prediction tasks. This will be described in more detail later.

[0076] The method of operating a time kernel device according to an embodiment of the present invention is summarized as follows. According to an embodiment of the present invention, there is provided a method of operating a temporal kernel device including one or more temporal kernel cell structures, each of the temporal kernel cell structures including a first nonvolatile memristor and a second nonvolatile memristor and a capacitor connected in parallel with each other, and the second nonvolatile memristors connected in parallel with each other and the capacitor are connected in series with the first nonvolatile memristor, the method comprising the steps of applying a time-series input signal to the temporal kernel cell structure to store information in the first and second nonvolatile memristors, and reading the information stored in the first and second nonvolatile memristors.

[0077] Here, the time kernel element may be as described with reference to FIG. 1. Accordingly, the time kernel element may include a first electrode, a second electrode, a middle electrode, and a third electrode. The capacitor may be disposed between the first electrode and the middle electrode, the second non-volatile memristor may be disposed between the second electrode and the middle electrode, and the first non-volatile memristor may be disposed between the middle electrode and the third electrode.

[0078] The step of storing information in the first and second non-volatile memristors may include a step of applying an electrical signal corresponding to the time-series input signal to the third electrode while the first and second electrodes are grounded. The step of reading the information stored in the first and second non-volatile memristors may include a step of applying an electrical signal for reading the information stored in the first non-volatile memristor between the third electrode and the middle electrode, and a step of applying an electrical signal for reading the information stored in the second non-volatile memristor between the middle electrode and the second electrode.

[0079] Additionally, a plurality of the time kernel cell structures may be arranged to form an array. The time kernel elements may include first and second electrodes extending in a first direction while being spaced apart from each other, a plurality of third electrodes extending in a second direction while being spaced apart from the first and second electrodes and intersecting the first and second electrodes, and a plurality of intermediate electrodes disposed between the electrode groups composed of the first and second electrodes and the plurality of third electrodes to correspond to the plurality of third electrodes, respectively. The plurality of time kernel cell structures may be disposed between the electrode groups composed of the first and second electrodes and the plurality of third electrodes, respectively. Each of the time kernel cell structures may include the capacitor disposed between the first electrode and the intermediate electrode, the second nonvolatile memristor disposed between the second electrode and the intermediate electrode, and the first nonvolatile memristor disposed between the intermediate electrode and the third electrode.

[0080] In addition, the method of operation of the temporal kernel element can be understood based on the configuration and operating characteristics of the temporal kernel element described with reference to FIGS. 1 to 4. In addition, the method of operation of a temporal kernel computing system to which a temporal kernel element according to an embodiment is applied can also be easily understood.

[0081] FIG. 5 is a diagram showing an optical microscope image (left image) of a time kernel device according to one embodiment of the present invention and a cross-sectional SEM (scanning electron microscope) image (right image) of a time kernel cell structure.

[0082] Referring to Fig. 5, the structural connectivity of the time kernel array elements with a size of 10×1 and the time kernel cells having a 2M-1C structure can be confirmed. M1 and M2 can be vertically stacked, and M2 and C can be horizontally spaced apart. Here, the M1 TE pad represents the upper electrode pad of M1, the Bridge pad represents the middle electrode pad, the M2 BE pad represents the lower electrode pad of M2, and the C BE pad represents the lower electrode pad of C. In addition, the Bridge represents the middle electrode.

[0083] FIG. 6 is a diagram showing cross-sectional TEM (transmission electron microscope) images of a first nonvolatile memristor (M1), a second nonvolatile memristor (M2), and a capacitor (C) that can be applied to a time kernel element according to one embodiment of the present invention. Drawing (A) of FIG. 6 is a TEM image of M1, drawing (B) is a TEM image of M2, and drawing (C) is a TEM image of C. In drawing (C) of FIG. 6, ZAZ represents a ZrO2 / Al2O3 / ZrO2 stacked structure.

[0084] FIG. 7 is a diagram showing energy dispersive spectrometer (EDS) line profiles of a first nonvolatile memristor (M1), a second nonvolatile memristor (M2), and a capacitor (C) that can be applied to a time kernel element according to one embodiment of the present invention. Here, the lines may correspond to the dotted lines of FIG. 6. Drawing (A) of FIG. 7 is for M1, drawing (B) is for M2, and drawing (C) is for C. However, the specific configurations and materials of M1, M2, and C disclosed in FIGS. 6 and 7 are merely exemplary, and may be varied in various ways.

[0085] Fig. 8 is a graph exemplarily showing voltage-current characteristics of first and second nonvolatile memristors (M1, M2) that can be applied to a time kernel element according to one embodiment of the present invention. Here, the first and second nonvolatile memristors (M1, M2) have a TiN / HfO2 / W structure and have a size of 6 μm × 6 μm. Fig. 8 shows the results of evaluating sweep characteristics using a direct current (DC) voltage. In addition, Fig. 8 shows the evaluation results for each of the first and second nonvolatile memristors (M1, M2).

[0086] Referring to FIG. 8, the first and second nonvolatile memristors (M1, M2) applicable to the time kernel element according to an embodiment of the present invention may exhibit voltage-current characteristics as illustrated according to a voltage sweep. When the voltage is swept in a positive (+) direction, a set switching may occur as the current increases due to an increase in conductance. On the other hand, when the voltage is swept in a negative (-) direction, a reset switching may occur as the current decreases due to a decrease in conductance. The first and second nonvolatile memristors (M1, M2) may exhibit almost similar voltage-current characteristics. In addition, the first and second nonvolatile memristors (M1, M2) may have a wider memory window in a negative (-) voltage region, and a read voltage for conductance data, for example, approximately -0.5 V, may be selected. However, the characteristics of the first and second non-volatile memristors (M1, M2) illustrated in FIG. 8 are exemplary and may vary.

[0087] Fig. 9 is a graph showing the results of measuring the final conductance after applying ten voltage pulses to first and second non-volatile memristors (M1, M2) applicable to a time kernel element according to one embodiment of the present invention. The dependence of the voltage pulse size on the voltage pulse size was confirmed by gradually increasing the size (height) of the voltage pulse. Fig. 9 shows the evaluation results for each of the first and second non-volatile memristors (M1, M2).

[0088] Referring to FIG. 9, it can be seen that the conductance of the first and second non-volatile memristors (M1, M2) in a time kernel element according to one embodiment of the present invention increases nonlinearly as the magnitude of the voltage pulse increases. This nonlinear characteristic can further improve the responses and dimensionality of the kernel element.

[0089] Fig. 10 is a graph showing capacitance values ​​in a given voltage range according to the feature size (F) of a capacitor (C) that can be applied to a time kernel element according to one embodiment of the present invention. Here, the feature size (F) of the capacitor (C) was 10, 20, 100, and 500 μm.

[0090] Referring to Fig. 10, it can be confirmed that the capacitor (C) has a stable capacitance value over a wide voltage range suitable for kernel operation. When the feature size (F) of the capacitor (C) is 10 μm to 500 μm, a capacitance range of pF to nF can be obtained. A wide capacitance range with low leakage may be a desirable characteristic of a capacitor for a time kernel element.

[0091] Figures 11 to 13 are diagrams showing changes in voltages applied to first and second non-volatile memristors (M1, M2) and changes in conductance of each memristor (M1, M2) according to application of an input signal to a time kernel element according to one embodiment of the present invention. Figures 11 to 13 show kernel responses to three different 8-bit binary input signals, namely '10101010' (case 1), '11001100' (case 2), and '10001000' (case 3). Each binary input signal was input in the form of a voltage pulse stream. V(M1) represents the voltage applied to the first nonvolatile memristor (M1), V(M2) represents the voltage applied to the second nonvolatile memristor (M2), G(M1) represents the conductance of the first nonvolatile memristor (M1), and G(M2) represents the conductance of the second nonvolatile memristor (M2). Figures 11 to 13 also include conductance data [G_sim(M1), G_sim(M2)] measured by simulation. G_sim(M1) is for the first nonvolatile memristor (M1), and G_sim(M2) is for the second nonvolatile memristor (M2). In the measurements of Figures 11 to 13, the capacitance of the capacitor (C) was set to 150 pF.

[0092] Referring to FIGS. 11 to 13, as described above, V(M1) can exhibit a 'peak and relaxation' pattern only when C (capacitor) is pre-discharged, and V(M2) can exhibit a 'rise and saturation' pattern for signal '1'. For example, in the '11001100' input pattern of FIG. 12, it can be confirmed that there is no peak in V(M1) for the second and fourth '1'. Both V(M1) and V(M2) have a saturation region during signal '1', but due to the nonlinear conductance change of M1 and M2 with respect to voltage as described in FIG. 9, M1 may be more sensitive to the 'peak (spike)' region. Due to these unique voltage distributions and nonlinear dependency characteristics, M1 may be more sensitive to the signal '0' preceding the consecutive '1' (and relatively insensitive to repeated '1'), while M2 may be more sensitive to the signal '1' itself.

[0093] As can be seen in the conductance data (lower graphs), M1 showed the highest final conductance in Case 1, which generated a total of four spikes due to the repeated signal '0' between signal '1's. Cases 2 and 3 only generate two spikes, so the conductance of M1 becomes lower than that of Case 1. On the other hand, M2 shows a high value in Cases 1 and 2 because four '1's are given, but its conductance value becomes lower in Case 3 because two '1's are given. Therefore, M1 and M2 can extract complementary information from the input signal, which achieves the separability of each pattern (input pattern) that cannot be achieved with a single memristive element.

[0094] FIG. 14 is a diagram showing the final conductance states measured in a first nonvolatile memristor (M1) and a second nonvolatile memristor (M2) for 16 cases of a 4-bit pattern from '0000' to '1111' according to one embodiment of the present invention. Drawing (A) of FIG. 14 shows the results for the first nonvolatile memristor (M1), and drawing (B) shows the results for the second nonvolatile memristor (M2). The pulse conditions were 5 V high and 50 μs wide, and the capacitance was 150 pF. For temporal separation, a reference '1' signal was provided at the end of each sequence (otherwise the results for '0101' and '1010' inputs are identical). That is, a reference '1' signal is added at the end of all sequences in (A) and (B) of Fig. 14. The reference signal '1' is not indicated in Fig. 14.

[0095] Referring to Figure 14, for M1, '0000', '0001', '0011', '0111', and '1111' belonged to the group with low conductance with one spike throughout the sequence, and the '1010' pattern showed the highest conductance value with three spikes. Meanwhile, M2 showed higher conductance as the number of signal '1' increased.

[0096] To further investigate the kernel characteristics, we tested various capacitances and signal voltages that could affect the temporal dynamics and nonlinearities of the integrated system. For a 4-bit input case, we evaluated the final conductance values ​​of M1 and M2 as C varied from 20 pF, 150 pF, and 1000 pF, respectively. Increasing the capacitance increases the conductance values ​​of both M1 and M2. This may be because a larger capacitance leads to a longer spike relaxation time in M1, which extends the duration in the higher voltage region. The increased conductance value for M1 at the peak can consequently lower V(M1) in the subsequent saturation region. This can then increase V(M2), which in turn can increase the conductance of M2. However, the delayed discharge of C with a higher capacitance value can lower the spike amplitude for the next '1' depending on the number of '0's. Due to this complex relationship, the characteristics of M1 connected to 1000 pF C can vary not only depending on the number of spikes but also on the interval between signal '1's. If the interval between signal '1's is long, C may be completely discharged, resulting in a higher second spike. On the other hand, if the capacitance of C is too small (approximately 20 pF), the voltage spike that increases the conductance of M1 may not be effectively generated. This may be because the capacitor (C) is momentarily charged at the beginning of the signal '1'.

[0097] Additionally, the voltage dependence (at 4, 5, and 6 V) of the M1 and M2 mapping characteristics was evaluated. For M1, increasing the voltage resulted in a more rapid, nonlinear increase, allowing for better discrimination between inputs with different peak counts. Lowering the voltage resulted in a similar effect of spike and saturation voltages, which may somewhat reduce the differences between the M1 and M2 mapping schemes. Therefore, appropriate selection of operating conditions and device features is necessary to achieve the desired mapping. Nevertheless, the tunable dynamics of the time kernel element according to the embodiment can enhance the dimensionality of feature extraction ability.

[0098] FIG. 15 is a schematic diagram exemplarily showing an image inference process using a time kernel computing system including a time kernel element according to one embodiment of the present invention.

[0099] Referring to Figure 15, the raw data can be preprocessed and transferred to the temporal domain, projected by a 2M-1C temporal kernel element, and further trained and inferred in the final reading network. The raw MNIST image consisting of 784 pixels (28 × 28) can be binarized into '0' and '1'. Then, the binary pixels can be chopped into 8-bit sequences (784 / 8 = 98 units) and rearranged in the temporal domain to form an input pulse stream for feeding the kernel. This input stream can be fed to the kernel and estimated as the final conductances of M1 and M2. These values ​​can represent a higher dimensional space in a more distilled and condensed form, while the actual volume of the data itself can be reduced. Next, the conductance vector consisting of 196 values ​​(M1 and M2 data from 98 units) can be input to the read inference layer (single layer). The cases of 10-, 14-, and 28-bit sequences are performed similarly, but with smaller units and input sizes for readout (78, 56, and 28 units, and 156, 112, and 56 readout input sizes, respectively). Only a single feedforward layer network can be used, which is directly connected to the inferred classes of '0' to '9', without burdening the entire training network. Since the MNIST dataset has 10 digit classes, only 1960, 1560, 1120, and 560 parameters need to be trained for the 8-, 10-, 14-, and 28-bit cases, respectively, which can be a surprisingly small (if not large) network parameter size.

[0100] FIG. 16 is a graph showing the maximum accuracy and input network size achieved under the conditions of each input sequence when performing image inference using a time kernel computing system including a time kernel element according to an embodiment of the present invention. FIG. 16 shows the maximum accuracy and input network size achieved under the given conditions (pulse 5 V / 50 μs, C = 150 pF for 8, 10, and 14-bit cases, C = 1000 pF for 28-bit case) for each inference case of 8-, 10-, 14-, and 28-bit input sequences. The result indicated as "Both" in FIG. 16 corresponds to an embodiment of the present invention, as it uses both data from M1 and M2. Meanwhile, the result indicated as "M1" corresponds to a case where inference was performed using only data from M1, and the result indicated as "M2" corresponds to a case where inference was performed using only data from M2. Therefore, the "M1" and "M2" cases correspond to comparative examples.

[0101] Referring to Figure 16, we can see that 94.3% and 86.4% accuracy were achieved for the 8-bit and 28-bit cases, respectively. Accuracy and unit bits may be a trade-off. Increasing the number of bits can result in decreased accuracy. Nevertheless, the 86.4% accuracy is a surprisingly high result for a very long 28-bit pattern, even with a small training parameter (560). Furthermore, using both M1 and M2 yielded the highest accuracy in all cases, compared to using only M1 or M2. The longer the pattern, the greater the complementarity between M1 and M2, leading to a greater accuracy increase when using both. Since combining random data alone is not expected to improve accuracy, the improved accuracy when using both M1 and M2 likely means that the features mapped by M1 and M2 are not linearly correlated but rather distinct from each other.

[0102] Figure 17 is a graph showing the results of performing initialization and prediction using only the conductance vector of the first non-volatile memristor (M1) in Mackey-Glass time series prediction according to a comparative example. Here, a 10×1 network was trained with data from steps 1 to 800, and prediction was performed without an update process for 200 steps.

[0103] Fig. 18 is a graph showing the results of initialization and prediction using only the conductance vector of the second non-volatile memristor (M2) in Mackey-Glass time series prediction according to a comparative example. Here, a 10×1 network was trained with data from steps 1 to 800, and prediction was performed without an update process for 200 steps. In Figs. 17 and 18, “Ground truth” represents actual data, and “Predicted” represents the predicted value. In addition, initialization means the learning step.

[0104] Referring to FIGS. 17 and 18, it can be seen that when learning and prediction are performed using only the conductance vector of the first non-volatile memristor (M1) or the conductance vector of the second non-volatile memristor (M2), the accuracy of the prediction is significantly reduced.

[0105] Fig. 19 is a graph showing the results of performing initialization and prediction using both the conductance vector of the first non-volatile memristor (M1) and the conductance vector of the second non-volatile memristor (M2) in Mackey-Glass time series prediction according to one embodiment of the present invention. After initialization up to 800 steps, prediction for 1200 steps was performed through 100-step prediction and 50-step update cycles.

[0106] Referring to Fig. 19, according to an embodiment of the present invention, successful learning and prediction can be achieved by using the MCV (memristor conductance vector) of M1 and M2 together. The initialization and prediction steps have a normalized root mean square error (NRMSE) of 0.023 (800 steps) and 0.026 to 0.06 (50 to 150 steps), respectively. Long-range prediction was also successful with a low NRMSE by updating 50 steps per 100 prediction steps. For Mackey-Glass time series prediction using the 2M-1C kernel, a very small single-layer readout network with dimensionality of 20×1, which is 50 to 100 times smaller than previous studies, was used. Here, in the 20×1 readout network, 20 may correspond to the total number of memristors (i.e., the total number of the first and second non-volatile memristors), and 1 may correspond to the number of neuron elements. This performance may be because the information mapped to memristors M1 and M2 are uncorrelated, so that a sufficiently wide feature space is secured with only two memristors.

[0107] FIG. 20 is a diagram showing the results of evaluating conductance values ​​for four types of time series patterns to analyze information extracted from the time series of a first non-volatile memristor (M1) and a second non-volatile memristor (M2), according to an embodiment of the present invention. The upper graphs of FIG. 20 correspond to a portion of FIG. 19. The lower mapping diagrams of FIG. 20 show conductance data mapped to M1 and M2 for each of the upper grades.

[0108] Referring to Figure 20, the conductance of M1 and M2 can vary depending on the amplitude and duration of each applied voltage, which are determined by the kernel conditions and time series pattern. Each time series of 50 time steps can be applied as an analog voltage to 10 kernels (kernel cells) at 5-time steps each. M1 and M2 can reflect the characteristics of the time series in different ways. Consequently, M1 and M2 can contribute to the kernel system's ability to identify the overall trend and local variations within the time series.

[0109] According to the embodiments of the present invention described above, a temporal kernel device capable of achieving high dimensional data mapping and tunable dynamics can be implemented by using a 2M (memristor) - 1C (capacitor) temporal kernel cell structure including two nonvolatile memristors and one capacitor. According to the embodiments of the present invention, there is provided a temporal kernel device capable of improving the diversity of reservoir states and performing efficient and accurate data processing with high dimensionality and tunable dynamics without unnecessarily increasing training parameters or relying on sequential operations.

[0110] In particular, according to embodiments of the present invention, since two non-volatile memristors can perform uncorrelated, individualized dimension data mapping for the same input signal, the dimensionality of data mapping can be increased, and the accuracy and efficiency of data processing can be improved. In addition, the time constant can be easily adjusted by adjusting the size of the capacitor or the initial resistance value of the two non-volatile memristors as needed. In addition, since the mapping signal can be varied by adjusting the pulse shape of the input signal, the freedom of use of the device can be improved.

[0111] For example, the complementary features projected onto each memristor reflect the characteristics of the binary pattern of the input signal, and can exhibit an accuracy of about 94.3% or higher and about 86.4% or higher in the 8-bit and 28-bit cases, respectively, in the Modified National Institute of Standards and Technology (MNIST) classification task. In addition, for example, for Mackey-Glass nonlinear timeseries patterns, the time kernel element can exhibit an NRMSE (normalized root mean square error) of 0.04 at the minimum network size (20×1), which can be said to have verified excellent prediction performance.

[0112] By applying the temporal kernel elements according to the above-described embodiments, a temporal kernel computing system having excellent performance and applicable to various fields can be implemented.

[0113] In this specification, preferred embodiments of the present invention have been disclosed, and although specific terms have been used, they have been used in a general sense only to easily explain the technical contents of the present invention and to help the understanding of the invention, and are not intended to limit the scope of the present invention. It will be apparent to those skilled in the art that other modifications based on the technical idea of ​​the present invention can be implemented in addition to the embodiments disclosed herein. Those skilled in the art will appreciate that the time kernel device and the time kernel computing system including the same and the operating method thereof according to the embodiments described with reference to FIGS. 1 to 16 and FIGS. 19 and 20 can be variously substituted, changed, and modified without departing from the technical idea of ​​the present invention. Therefore, the scope of the invention should not be defined by the described embodiments, but by the technical idea described in the claims.

[0114] Embodiments of the present invention can be applied to kernel-related devices and systems, and methods related thereto. Embodiments of the present invention can be applied to time kernel elements, time kernel computing systems including the same, and operating methods thereof.

Claims

1. Contains one or more temporal kernel cell structures, Each of the above time kernel cell structures is A first nonvolatile memristor; and comprising a second non-volatile memristor and a capacitor connected in parallel with each other, The second non-volatile memristor and the capacitor connected in parallel with each other are temporal kernel devices connected in series to the first non-volatile memristor.

2. In paragraph 1, The above time kernel element includes a first electrode, a second electrode, a middle electrode, and a third electrode, The capacitor is placed between the first electrode and the middle electrode, The second non-volatile memristor is disposed between the second electrode and the middle electrode, The first non-volatile memristor is a time kernel element disposed between the middle electrode and the third electrode.

3. In paragraph 2, A time kernel element configured so that an electrical signal corresponding to a time-series input signal is applied to the third electrode while the first and second electrodes are grounded.

4. In paragraph 1, A plurality of the above time kernel cell structures are arranged to form an array, The time kernel element comprises an electrode group comprising first and second electrodes extending in a first direction and spaced apart from each other, a plurality of third electrodes extending in a second direction intersecting the first and second electrodes and spaced apart from the first and second electrodes, and a plurality of intermediate electrodes arranged between the plurality of third electrodes to correspond to each of the plurality of third electrodes, The above plurality of time kernel cell structures are respectively arranged between the electrode group composed of the first and second electrodes and the plurality of third electrodes, A time kernel element, wherein each of the time kernel cell structures comprises the capacitor disposed between the first electrode and the middle electrode, the second non-volatile memristor disposed between the second electrode and the middle electrode, and the first non-volatile memristor disposed between the middle electrode and the third electrode.

5. In paragraph 1, The first non-volatile memristor and the second non-volatile memristor are arranged on the same vertical axis, The above capacitor is a time kernel element arranged horizontally apart from the second non-volatile memristor.

6. In paragraph 1, The first and second non-volatile memristors are time kernel elements configured to store different information for the same input signal.

7. In paragraph 1, The time kernel element is configured to store information in the first and second non-volatile memristors and input the information stored in the first and second non-volatile memristors into an artificial neural network.

8. A time kernel element as set forth in any one of claims 1 to 7; and A temporal kernel computing system including an artificial neural network connected to the temporal kernel element and receiving information processed by the temporal kernel element.

9. A method of operating a temporal kernel device comprising one or more temporal kernel cell structures, each of the temporal kernel cell structures comprising a first non-volatile memristor and a second non-volatile memristor and a capacitor connected in parallel with each other, wherein the second non-volatile memristor and the capacitor connected in parallel with each other are connected in series with the first non-volatile memristor, A step of storing information in the first and second non-volatile memristors by applying a time-series input signal to the time kernel cell structure; and A method of operating a time kernel element, comprising the step of reading information stored in the first and second non-volatile memristors.

10. In paragraph 9, A method of operating a time kernel element, wherein the time kernel element comprises a first electrode, a second electrode, a middle electrode, and a third electrode, the capacitor is disposed between the first electrode and the middle electrode, the second non-volatile memristor is disposed between the second electrode and the middle electrode, and the first non-volatile memristor is disposed between the middle electrode and the third electrode.

11. In paragraph 10, A method of operating a time kernel element, wherein the step of storing information in the first and second non-volatile memristors includes the step of applying an electrical signal corresponding to the time-series input signal to the third electrode while the first and second electrodes are grounded.

12. In paragraph 10, A method of operating a time kernel element, wherein the step of reading information stored in the first and second non-volatile memristors includes the step of applying an electrical signal for reading information stored in the first non-volatile memristor between the third electrode and the middle electrode, and the step of applying an electrical signal for reading information stored in the second non-volatile memristor between the middle electrode and the second electrode.

13. In paragraph 9, A plurality of the above time kernel cell structures are arranged to form an array, The time kernel element comprises an electrode group comprising first and second electrodes extending in a first direction and spaced apart from each other, a plurality of third electrodes extending in a second direction intersecting the first and second electrodes and spaced apart from the first and second electrodes, and a plurality of intermediate electrodes arranged between the plurality of third electrodes to correspond to each of the plurality of third electrodes, The above plurality of time kernel cell structures are respectively arranged between the electrode group composed of the first and second electrodes and the plurality of third electrodes, A method of operating a time kernel element, wherein each of the time kernel cell structures comprises the capacitor disposed between the first electrode and the middle electrode, the second nonvolatile memristor disposed between the second electrode and the middle electrode, and the first nonvolatile memristor disposed between the middle electrode and the third electrode.

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