Circuit design modeling for bonding integrated circuits

Abstract

A method includes receiving a first layout file for a first workpiece and a second layout file for a second workpiece. First layout file and second layout file are analyzed to identify contact points, which are grouped into bins. A contact point of a first bin is simulated using a simulation model. Contact point includes a first feature of the first workpiece and a second feature of the second workpiece. In response to determining that the contact point does not have desired properties, a first layout of the first feature and a second layout of the second feature are updated to determine an updated contact point. Updated contact point is simulated using the simulation model. In response to determining that the updated contact point has the desired properties, first layout file is updated to include updated first layout, and second layout file is updated to include updated second layout.

Description

CIRCUIT DESIGN MODELING FOR BONDING INTEGRATED CIRCUITSCROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application claimsthebenefitof U.S. Provisional Application No. 63 / 534,763, filed on August25, 2023 and U. S. Nonprovisional Application No. 18 / 615,365, filed on March 25, 2024, which are hereby incorporated herein by reference.TECHNICAL FIELD

[0002] The present disclosure relates generally to a system and method for microfabrication of integrated circuits, and, in particular embodiments, to a system and method for heterogeneous integration of integrated circuits.BACKGROUND

[0003] Transistors per unit area on a chip have been increasing in density over the decades. As two-dimensional (2D) space available for circuit elements begins to exhaust space available, chip fabrication moves to three-dimensional (3D) designs in which transistors and other circuit elements are stacked on top of each other. Monolithic integration includes forming transistors on top of each other on a single wafer (substrate). Heterogeneous integration includes bonding two or more wafers and / or dies together to form vertically stacked devices.SUMMARY

[0004] In accordance with an embodiment of the present disclosure, an apparatus includes a memory configuredto store a simulation model and process parameters of a bonding process. The apparatus further includes a processor communicatively coupled to the memory. The processor is configuredto receive a firstlayoutfile, first design rules, firstparametervariations, and first material parameters for a first workpiece. The processor is further configured to receive a second layout file, second design rules, second parameter variations, and second material parameters for a second workpiece. The processor is further configured to analyze the first layout file and the second layout file to identify a plurality of contact points. Each contact point includes a feature of the first workpiece and a feature of the second workpiece. The processor is further configured to determine types of the plurality of contact points based on the first layout file and the second layout file and group the plurality of contact points into aplurality of bins. Each bin includes a subset of the plurality of contact points having a same type. The processor is further configured to simulate a first contact point of a first bin of the plurality of bins using the simulation model. The first contact point includes a first feature of the first workpiece and a second feature of the second workpiece. The processor is further configured to determine whether the first contact point has desired properties and, in response to determining that the first contact point does not have the desired properties update a first layout of the first feature and a second layout of the second feature to determine an updated first contact point, simulate the updated first contact point using the simulation model, and determine whether the updated first contact point has the desired properties. In response to determining that the updated first contact point has the desired properties, the processor is further configured to update the first layout file to include the updated first layout of the first feature and update the second layout file to include the updated second layout of the second feature.

[0005] In accordance with an embodiment of the present disclosure, a method includes receiving a first layout file, first design rules, first parameter variations, and first material parameters for a first workpiece, and receivinga second lay out file, second design rules, second parameter variations, and second material parameters for a second workpiece. The method further includes analyzing the first layout file and the second layout file to identify a plurality of contact points. Each contact point includes a feature of the first workpiece and a feature of the second workpiece. The method further includes determiningtypes of the plurality of contact points based on the first layout file and the second layout file and grouping the plurality of contact points into a plurality of bins. Each bin includes a subset of the plurality of contact points having a same type. The method further includes simulating a first contact point of a first bin of the plurality of bins using a simulation model. The first contact point includes a first feature of the first workpiece and a second feature of the second workpiece. The method further includes determining whether the first contact point has desired properties. In response to determining that the first contact point does not have the desired properties, the method further includes updating a first layout of the first feature and a second layout of the second feature to determine an updated first contact point, simulating the updated first contact point using the simulation model, and determining whether the updated first contact point has the desired properties. In response to determining that the updated first contact point has the desired properties, the method further includes updating the first layout file to include the updated firstlayout of the first feature and updating the second layout file to include the updated second layout of the second feature.

[0006] In accordance with an embodiment of the present disclosure, a non-transitory computer-readablemedium storinginstructions that, when executed by one or more processors, cause the one or more processors to receive a first layout file, first design rules, first parameter variations, and first material parameters for a first workpiece, and receive a second layout file, second design rules, second parameter variations, and second material parameters for a second workpiece. The instructions, when executed by one or more processors, further cause the one or more processors to analyze the first layout file and the second layout file to identify a plurality of contact points. Each contact point includes a feature of the first workpiece and a feature of the second workpiece. The instructions, when executed by one or more processors, further cause the one or more processors to determine types of the plurality of contact points based on the first layout file and the second layout file, group the plurality of contact points into a plurality of bins, wherein each bin includes a subset of the plurality of contact points having a same type, and simulate a first contact point of a first bin of the plurality of bins using a simulation model. The first contact point includes a first feature of the first workpiece and a second feature of the second workpiece. The instructions, when executed by one or more processors, further cause the one or more processors to determine whether the first contact point has desired properties. In response to determining that the first contact point does not have the desired properties, the instructions, when executed by one or more processors, further cause the one or more processors to update a first layout of the first feature and a second layout of the second feature to determine an updated first contact point, simulate the updated first contactpointusingthe simulation model, and determine whether the updated first contact point has the desired properties. In response to determining that the updated first contact point has the desired properties, the instructions, when executed by one or more processors, further cause the one or more processors to update the first layout file to include the updated first layout of the first feature and update the second layout file to include the updated second layout of the second feature.BRIEF DESCRIPTION OF THE DRAWINGS

[0007] For a more complete understanding of the present disclosure, and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which:

[0008] Figure 1 A illustrates a schematic view of a bonding apparatus in accordance with various embodiments;

[0009] Figure IB illustrates a schematic view of a circuit design modeling system in accordance with various embodiments;

[0010] Figure 2A illustrates perspective views of workpieces to be bonded in accordance with various embodiments;

[0011] Figure 2B illustrates perspective views of workpieces to be bonded in accordance with various embodiments;

[0012] Figure 3 illustrates a cross-sectional view of a workpiece in accordance with various embodiments;

[0013] Figures 4A and 4B illustrate top and cross-sectional views of bonding structures in accordance with various embodiments;

[0014] Figures 5 A and 5B illustrate top and cross-sectional views of a bonding structure in accordance with various embodiments;

[0015] Figures 6A-6C illustrate cross-sectional views of a workpiece in accordance with various embodiments;

[0016] Figure 7 A illustrates a cross-sectional view of a workpiece stack in accordance with various embodiments;

[0017] Figure 7B illustrates a cross-sectional view of a workpiece stack in accordance with various embodiments;

[0018] Figure 7C illustrates a cross-sectional view of a workpiece stack in accordance with various embodiments;

[0019] Figure 8 illustrates a cross-sectional view of a workpiece stack in accordance with various embodiments;

[0020] Figures 9 A and 9B illustrate a process flow diagram of a method for circuit design modeling of workpieces to be bonded in accordance with various embodiments; and

[0021] Figures 10A and 10B illustrate a process flow diagram of a method for bonding workpieces in accordance with various embodiments.DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

[0022] The making and using of various embodiments are discussed in detail below. It should be appreciated, however, that the various embodiments described herein are applicable in a wide variety of specific contexts. The specific embodiments discussed are merely illustrative of specific way s to make and use various embodiments, and shouldnotbe constmed in a limited scope.

[0023] Because of the microscopic scale of circuit features, there are challenges with heterogeneous integration. For example, challenges include alignment and bonding of workpieces (e.g., wafers and / or dies). That is, correctly aligning bonding structures from one workpiece with corresponding bonding structures from another workpiece, and then making a reliable bond with opposing bonding structures in physical contact with each other.

[0024] Techniques disclosed hereininclude methodsand systems for optimizingthe design and process for heterogeneousintegration (HI) bonding. Methods include software applications dedicated to optimizingthe design and process for HI bonding. Such software application may include a physical model and an artificial intelligence (Al) model. The physical model includes thermal modeling (e.g., thermal expansion modelling, thermal conductivity modeling, thermal stress modeling, etc.), specifically targeting the bonding of top and bottom workpieces using bonding structures (e.g., copper vias), while considering metal layouts adjacent the bonding structures. The physical model considers various critical factors for a bonding structure, including a metal volume, insulation volume, metal isolation, metal density, insulation type, metal type, underlying metal line connected to the bonding structure, underlying via connected to the bonding structure, liner metal in the via, material type ofthe bonding structure, and shape of the bonding structure.

[0025] The physical model includes calculating a volume change of a metal of the bonding structure caused by thermal expansion during bonding. The physical model may predict the joining of bonding structures and identify any potential voids thatmay arise afterthe bonding process. The physical model further generates outputs indicating which bonding structures might encounter bonding issues during workpiece -to-workpiece bonding under specific bonding conditions, such as a bonding temperature, bonding time, and recess of bonding structure from an adjacent insulating film. For example, the physical model analyzes thermal stresses, identifying potential fracture or cracking risks of bonding structures, and predicts electrical and mechanical properties of the workpiece stack.

[0026] The software application may further include a chemical model. The chemical model may include analyzing interface effects, grain growth, and diffusion of copper into the surrounding insulator. By integrating these chemical analyses, the software application generates results enabling a more holistic understanding of the bonding process, leading to improved design decisions and optimization strategies.

[0027] The Al model may perform design checks, considering the 3D geometry and dimensions of the bonding structures involved. Should any problems be detected during the design check, the Al model can propose effective solutions to rectify the identified issues, ensuring an optimized and reliable workpiece-to-workpiece (e.g., die-to-wafer or wafer-to- wafer) bonding process.

[0028] The techniques described herein provide a simulation model that takes into consideration circuit architecture in combination with material specific properties, thermodynamic phenomena and process conditions to propose alternate architecture and process conditions to optimize heterogeneous integration processes. The model includes a physical model that determines if the different contact points between the first workpiece and the second workpiece will have desired properties with the given process inputs. When the contact point fails then the Al model reworks the layout for both the first workpiece and the second workpiece, then reruns the physical model. The Al model may also change process conditions of the bonding process as need if no layout solution can be obtained.

[0029] Figure 1 A illustrates a schematic view of a bonding apparatus 100 in accordance with various embodiments. The bonding apparatus 100 is configured to perform a bonding process to bond a first workpiece HOAto a second workpiece HOB. In some embodiments, the first workpiece 110A and the second workpiece HOB may be wafers as described below with reference to Figure 2A. In such embodiments, the bonding apparatus 100 is configured to perform a wafer-to-wafer bonding process. In other embodiments, the first workpiece 110A may be a wafer and the second workpiece 110B may be a die as described below with reference to Figure 2B. In such embodiments, the bonding apparatus 100 is configured to perform a die- to-wafer or chip-to-wafer bonding process.

[0030] The bonding apparatus 100 comprises a vacuum chamber 104 coupled to a pump 106. The pump 106 is configured to maintain a desired vacuum level within the vacuum chamber 104. In some embodiments, a first chuck 108A and a second chuck 108B is disposed in the vacuum chamber 104. The first chuck 108 A is configured to hold the first workpiece110A and the second chuck 108B is configured to hold the second workpiece HOB during the bonding process. The first chuck 108A and the second chuck 108B may comprise mechanical chucks, vacuum chucks, electrostatic chucks, or the like.

[0031] In some embodiments, the first chuck 108 A is configured to move the first workpiece 110A toward the second workpiece 110B. The first chuck 108 A may comprise a heating element 112. The heating element 112 is configured to heat the first workpiece 110A and the second workpiece HOB during the bonding process. The heating element 112 may be a resistive heating element, a hot plate, or the like. In some embodiments, the second chuck 108B is configured to move the second workpiece 110B toward the first workpiece 110 A. The second chuck 108B may be an annular structure having an opening 114 therein. The opening 114 may be disposed at the center of the second chuck 108B. The second chuck 108B may further comprise a pin 116 within the opening 114. The pin 116 may be configured to extend into the opening 114 toward the second workpiece 110B, physically contact the second workpiece 110B, and bend the second workpiece 110B.

[0032] In some embodiments, the bonding apparatus 100 may comprise a circuit design modeling system 102. The circuitdesign modelingsystem 102maybein signal communication with various components of the bonding apparatus 100. The circuit design modeling system 102 may exchange signals 118 with various components of the bonding apparatus 100. In some embodiments, the circuit design modeling system 102 may be configured to analyze layouts of the first workpiece 110A and the second workpiece 110B and update layouts of the first workpiece l lOA andthe second workpiece 110B such that a workpiece stack (e.g., comprising the first workpiece 110A and the second workpiece 110B) has desired properties . In other embodiments, the circuit design modeling system 102 may be configured to control operations of the bonding apparatus 100. In other embodiments, the circuit design modeling system 102 may be an external system separate from the bonding apparatus 100.

[0033] In operation, the bonding apparatus 100 is configured to move the first workpiece 110 A toward the second workpiece 110B . After a desired distance between the first workpiece 110A and the second workpiece 110B is achieved, the pin 116 is extended toward the second workpiece 110B to bend the second workpiece 110B such that the second workpiece HOB makes a physical contact with the first workpiece 110A initiating a bonding process. After initiating the bonding process, the second workpiece 110B is released from the second chuck 108B to complete the bonding process to form workpiece stack comprising the first workpiece110A and the second workpiece HOB. In some embodiments, after releasing the second workpiece HOB from the second chuck 108B, a bonding wave propagates from the centers of the first workpiece 110A and the second workpiece 110B toward edges of the first workpiece 110A and the second workpiece 110B.

[0034] Figure IB illustrates a schematic view of the circuit design modeling system 102 in accordance with various embodiments. The circuit design modeling system 102 may comprise a processor 120 communicatively (or operably) coupled to a memory 122. The processor 120 may comprise one or more microprocessors having integrated circuits. The memory 122 may comprise a non-transitory computer-readable medium that is configured to store software instructions 124 and / or any other data. The software instructions 124, when executed by the processor 120, cause the processor 120 to perform various functions of the circuit design modeling system 102 described herein. The memory 122 may further store a simulation model 126. The simulation model 126 may comprise a physical model 126 A and an Al model 126B. The physical model 126A, when executed by the processor 120, causes the processor 120 to simulate a bonding process of workpieces (e.g., first workpiece 110A and second workpiece 110B of Figure 1A). The Al model 126B, when executed by the processor 120, causes the processor 120 to analyze results of the physical model 126 A and generate updated layouts of the workpieces (e.g., first workpiece 110 A and second workpiece 110B of Figure 1 A). In some embodiments, the circuit design modeling system 102 is configured to perform a method 900 for circuit design modeling of workpieces (e.g., first workpiece 110 A and second workpiece 110B of Figure 1 A) to be bonded as described below with reference to Figures 9 A and 9B. In other embodiments, the circuit design modeling system 102 may perform one or more operations of a method 1000 for bonding workpieces (e.g., first workpiece 110A and second workpiece 110B of Figure 1A) as described below with reference to Figures 10A and 10B.

[0035] Figure 2A illustrates perspective views of workpieces (e.g., workpieces 200A and 200B) to be bonded by the bonding apparatus 100 (see Figure 1 A) in accordance with various embodiments. For example, the workpiece 200A may be implemented as the first workpiece 110A and the workpiece 200B may be implemented as the second workpiece 110B. In the illustrated embodiment, the workpieces 200A and 200B are wafers. Each of the workpieces 200A and 200B may comprise a substrate. In some embodiments, the substrate may comprise a plurality of device regions. In such embodiments, the substrate may include isolation regions such as shallow trench isolation (STI) regions, diffusion regions, as well as other regions formed therein.

[0036] The substrate may comprise layers of semiconductors suitable for various microelectronics. In one or more embodiments, the substrate may be a silicon wafer, or a silicon-on-insulator (SOI) wafer. In certain embodiments, the substrate may comprise a silicon germanium wafer, silicon carbidewafer, gallium arsenide wafer, gallium nitride wafer, or other compound semiconductors. In other embodiments, the substrate may comprise heterogeneous layers such as silicon germanium on silicon, gallium nitride on silicon, silicon carbon on silicon, or layers of silicon on a silicon or SOI substrate.

[0037] Each of the workpieces 200A and 200B may further comprise an interconnect structure on a front side of the substrate. The interconnect structure may comprise one or more dielectric layers and one or more metallization layers within the one or more dielectric layers. In some embodiments, the one or more dielectric layers may comprise one or more suitable dielectric materials such as silicon oxide, low-k dielectric materials, or the like. The one or more metallization layers may comprise a plurality of conductive lines and a plurality of conductive vias electrically coupling adjacent metallization layers. The metallization layers may comprise a suitable conductive material such as copper (Cu), for example. The metallization layers may be formed by a damascene process, a dual damascene process, or the like.

[0038] Each of the workpieces 200A and 200B may further comprise one or more bonding structures. In some embodiments, the one or more bonding structures may be formed on the front side of the substrate over the interconnect structure. In some embodiments, portions of the topmost metallization layer of the interconnect structure act as bonding structure. In other embodiments, the one or more bonding structures may be formed on the backside of the substrate. In yet other embodiments, the one or more bonding structures may be formed both on the front side and the backside of the substrate. The one or more bonding structures may be configured to electrically and mechanically couple the bonded workpieces. The one or more bonding structures may comprise a suitable conductive material such as copper (Cu), for example. In some embodiments, the workpieces 200A and 200B may have similar structures and be formed using similar process steps. In other embodiments, the workpiece 200A may be different from the workpiece 200B, such that they may comprise different structures and may be formed using different process steps.

[0039] Figure 2B illustrates perspective views of workpieces (e.g., workpieces 202A and 202B) to be bonded by the bonding apparatus 100 (see Figure 1 A) in accordance with variousembodiments. For example, the workpiece 202A may be implemented as the first workpiece 110A and the workpiece 202B may be implemented as the second workpiece HOB. In the illustrated embodiment, the workpiece 202 A is a wafer and the workpiece 202B is a die. The workpiece 202 A may be similar to the workpiece 200A (see Figure 2A) and the description is not repeated herein. The workpiece 202B may be formed as a wafer and subsequently diced into a plurality of dies. The wafer may be similar to the workpiece 200 A (see Figure 2A) and the description is not repeated herein.

[0040] Figure 3 illustrates a cross-sectional view of a workpiece 300 in accordance with various embodiments. The workpiece 300 may be implemented as the first workpiece 110A or the second workpiece HOB (see Figure 1 A). The workpiece 300 comprises a substrate 302. The substrate 302 may be similar to the substrate of the workpiece 200A (see Figure 2A) and the description is not repeated herein. The workpiece 300 may further comprise an interconnect structure (not shown) on a front side of the substrate 302. The interconnect structure may comprise one or more dielectric layers and one or more metallization layers within the one or more dielectric layers. In some embodiments, the one or more dielectric layers may comprise one or more suitable dielectric materials such as silicon oxide, low-k dielectric materials, or the like. The one or more metallization layers may comprise a plurality of conductive lines and a plurality of conductive vias electrically coupling adjacent metallization layers. The metallization layers may comprise a suitable conductive material such as copper (Cu), for example. The metallization layers may be formed by a damascene process, a dual damascene process, or the like.

[0041] The workpiece 300 may further comprise a bonding layer 304 over the interconnect structure. The bondinglayer 304 may comprise a dielectric layer 306 and a plurality of bonding structures 308 in the dielectric layer 306. The dielectric layer 306 may comprise a suitable dielectric material such as silicon oxide, for example. The bonding structures 308 may comprise a suitable conductive material such as copper (Cu), for example. In some embodiments, the bonding structures 308 have different dimensions and pitches within the dielectric layer 306. A chemical mechanical polishing (CMP) process may be performed on the workpiece 300 to planarize the bonding layer 304 and expose the bonding structures 308. The CMP process may cause erosion of the dielectric layer 306 and dishing of the bonding structures 308. Due to variations of dimensions and pitches of the bonding structures 308, amounts of erosion and dishing also vary along the workpiece 300. For example, isolatedbonding structures 308A are subject to a greater dishing than densely -spaced bonding structures 308B.

[0042] Figures 4A and 4B illustrate top and cross-sectional views of bonding structures 308B (see Figure 3) in accordance with various embodiments. In particular, Figure 4A illustrates a top view andFigure 4B illustrates a cross-sectional viewalongaloneBB’ ofFigure 4A. In the illustrated embodiment, the bonding structures 308B are densely-spaced bonding structures. Due to dishing, the bonding structures 308B are recessed below a top surface of the workpiece 300 (seeFigure 3). In some embodiments, recesses 402 over the bonding structures 308B may have a depth Di in a range from 0 nm to 20 nm. In other embodiments, the depth Di may be in a range from 3 nm to 8 nm.

[0043] Figures 5 A and 5B illustrate top and cross-sectional views of the bonding structure 308A (see Figure 3) in accordance with various embodiments. In particular, Figure 5A illustrates a top view and Figure 5B illustrates a cross-sectional viewalongaloneBB’ ofFigure 5 A. In the illustrated embodiment, thebonding structure 308Ais an isolated bonding structure. Due to dishing, the bonding structure 308 A is recessed below the top surface of the workpiece 300 (see Figure 3). In some embodiments, a recess 502 over the bonding structure 308A may have a depth D2 in a range from 0 nm to 20 nm. In other embodiments, the depth D2 may be in a range from 3 nm to 8 nm. In the illustrated embodiment, the depth D2is greater than the depth Di.

[0044] Figure 6A illustrates a cross-sectional view of a portion of a workpiece 600 in accordance with various embodiments. In particular, Figure 6 A illustrates a metallization layer 602 and abondinglayer604 of the workpiece 600 atafirsttemperature. In some embodiments, the first temperature may be less than a bonding temperature. In some embodiments, the workpiece 600 is similar to the workpiece 200A (see Figure 2A) and the description is not repeated herein. In some embodiments, the metallization layer 602 may be a topmost metallization layer of the workpiece 600. The metallization layer 602 may comprise a suitable conductive material such as copper (Cu), for example. The bonding layer 604 may comprise a dielectric layer 608 and a bonding structure 610 in the dielectric layer 608. The dielectric layer 608 may comprise a suitable dielectric material such as silicon oxide, for example. Thebonding structure 610 may be in physical and electrical contact with a metal line 606 of the metallization layer 602. The bonding structure 610 may comprise a suitable conductive material such as copper (Cu), for example. The bonding structure 610 may be recessed below a top surface ofthe workpiece 600 due to dishing, for example. In some embodiments, the recess 612 has a depth D3in a range from 0 nm to 20 nm. In other embodiments, the depth D3may be in a range from 3 nm to 8 nm.

[0045] In some embodiments, the circuit design modeling system 102 (see Figure IB) may implementthe physical model 126Ato simulate thermal processes (e.g., thermal expansion, thermal conductively, thermal stress, etc.) of the workpiece 600. For example, the physical model 126 A may analyze thermal expansions of the bonding structure 610 and the metal line 606 to determine whether a material of the bonding structure 610 and the metal line 606 fills the recess 612. In the illustrated embodiment, the physical model 126A may determine that the material of the bonding structure 610 and the metal line 606 dose not fill the recess 612 at the first temperature.

[0046] Figure 6B illustrates a cross-sectional view of a portion of the workpiece 600 in accordance with various embodiments. In particular, Figure 6B illustrates the metallization layer 602 and the bonding layer 604 of the workpiece 600 at a second temperature greater than the first temperature. The second temperature may equal to a bonding temperature. In some embodiments, the circuit design modeling system 102 (see Figure IB) may implement the physical model 126 A to simulate thermal processes (e.g., thermal expansion, thermal conductively, thermal stress, etc.) of the workpiece 600. For example, the physical model 126A may analyze thermal expansions of the bonding structure 610 and the metal line 606 to determine whether a material of the bonding structure 610 and the metal line 606 fills the recess 612. In the illustrated embodiment, the physical model 126 A may determine that the material of the bonding structure 610 and the metal line 606 fills the recess 612 (see Figure 6A) at the second temperature.

[0047] Figure 6C illustrates a cross-sectional view of a portion of the workpiece 600 in accordance with various embodiments. In particular, Figure 6B illustrates the metallization layer 602 and the bonding layer 604 of the workpiece 600 at a third temperature greater than the first temperature and the second temperature. The third temperature may equal to a bonding temperature. In some embodiments, the circuit design modeling system 102 (see Figure IB) may implement the physical model 126 A to simulate thermal processes (e.g., thermal expansion, thermal conductively, thermal stress, etc.) of the workpiece 600. For example, the physical model 126 A may analyze thermal expansions of the bonding structure 610 and the metal line 606 to determine whether a material of the bonding structure 610 and the metal line606 fills the recess 612. In the illustrated embodiment, the physical model 126A may determine that the material of the bonding structure 610 and the metal line 606 overfills the recess 612 (see Figure 6A) at the second temperature.

[0048] Figure 7 A illustrates a cross-sectional view of a workpiece stack 700 A in accordance with various embodiments. The workpiece stack 700 A comprises a first workpiece 600Abondedto a second workpiece600B. The first workpiece600Aand the second workpiece 600B may be similar to the workpiece 600 (see Figure 6 A), with similar features being labeled by similar numerical references, and descriptions of similar features are not repeated herein. In some embodiments, the circuit design modeling system 102 (see Figure IB) may implement the physical model 126A to simulate thermal processes (e.g., thermal expansion, thermal conductively, thermal stress, etc.) of the workpiece stack 700A during the bonding process at a firstbondingtemperature. In the illustrated embodiment, the firstbondingtemperature equals to the first temperature of the workpiece 600 shown in Figure 6 A. The physical model 126A may analyze thermal expansions of the bonding structures 610 A and 610B and the metal lines 606 A and 606B to determine whether a material of the bonding structures 610 A and 610B and the metal lines 606A and 606B fills the recesses formed due to dishing. In the illustrated embodiment, the physical model 126 A may determinethatthe material of the bonding structure 610A and 610B and the metal lines 606 A and 606B does notfill the recesses atthe firstbonding temperature.

[0049] The physical model 126 A may determine that the bonding layer 604 A of the first workpiece 600Ais bonded to the bonding layer 604B of the second workpiece 600B such that the dielectric layer 608 A is bonded to the dielectric layer 608B, with a bonding interface 702 indicated by a dashed line. The physical model 126 A may further determine that the bonding structures 610 A and 610B do not fill respective recesses at the first bonding temperature and are not bonded to each other. Accordingly, the bonding structures 610A and 610B fail to electrically couple the metal line 606 A of the metallization layer 602A of the first workpiece 600A to a metalline 606B of a metallization layer 602B of the second workpiece 600B. In such embodiments, the workpiece stack 700A comprises a void 704 at the bonding interface 702. The bonded structure of the bonding structures 610A and 610B may be also referred to as a contact point. In the illustrated embodiments, the contact point fails to electrically couple the first workpiece 600 A to the second workpiece 600B. In some embodiments, the Al model 126B may generate updated layouts (e.g., comprisingupdated widths, lengths, and / or heights) forthebonding structures 610A and 61 OB and / or the metal lines 606 A and 606B, such that the formation of the void 704 is avoided.

[0050] Figure 7B illustrates a cross-sectional view of a workpiece stack 700B in accordance with various embodiments. The workpiece stack 700B comprises a first workpiece 600Abondedto a second workpiece600B. The first workpiece600Aand the second workpiece 600B may be similar to the workpiece 600 (see Figure 6 A), with similar features being labeled by similar numerical references, and descriptions of similar features are not repeated herein. In some embodiments, the circuit design modeling system 102 (see Figure IB) may implement the physical model 126A to simulate thermal processes (e.g., thermal expansion, thermal conductively, thermal stress, etc.) of the workpiece stack 700B during the bonding process at a second bonding temperature. In the illustrated embodiment, the second bonding temperature equals to the second temperature of the workpiece 600 shown in Figure 6B. The physical model 126A may analyze thermal expansions of the bonding structures 610A and 610B and the metal lines 606A and 606B to determine whether a material of the bonding structures 610A and 610B and the metal lines 606A and 606B fills the recesses formed due to dishing. In the illustrated embodiment, the physical model 126 A may determine that the material of the bonding structure 610 A and 610B and the metal lines 606 A and 606B fills the recesses at the second bonding temperature.

[0051] The physical model 126 A may determine that the bonding layer 604 A of the first workpiece 600Ais bonded to the bonding layer 604B of the second workpiece 600B such that the dielectric layer 608 A is bonded to the dielectric layer 608B, with a bonding interface 702 indicated by a dashed line. The physical model 126 A may further determine that the bonding structures 610A and 610B fill respective recesses at the second bonding temperature and are bonded to each other. Accordingly, the bonding structures 610Aand 610B electrically couple the metal line 606 A of the metallization layer 602 A of the first workpiece 600 A to the metal line 606B of the metallization layer 602B of the second workpiece 600B. The bonded structure of the bonding structures 610A and 610B may be also referred to as a contact point. Accordingly, the contact point (comprisingthe bonding structures 610 A and 610B) electrically couples the metal line 606 A of the metallization layer 602A of the first workpiece 600A to the metal line 606B of the metallization layer 602B of the second workpiece 600B. In some embodiments, the Al model 126B may determinethatlayoutupdatesforthe bonding structures 610A and 610B and / or the metal lines 606 A and 606B are not needed.

[0052] Figure 7C illustrates a cross-sectional view of a workpiece stack 700C in accordance with various embodiments. The workpiece stack 700C comprises a first workpiece 600Abondedto a second workpiece600B. The first workpiece600Aand the second workpiece 600B may be similar to the workpiece 600 (see Figure 6 A), with similar features being labeled by similar numerical references, and descriptions of similar features are not repeated herein. In some embodiments, the circuit design modeling system 102 (see Figure IB) may implement the physical model 126A to simulate thermal processes (e.g., thermal expansion, thermal conductively, thermal stress, etc.) of the workpiece stack 700C during the bonding process at a third bonding temperature. In the illustrated embodiment, the third bonding temperature equals to the third temperature of the workpiece 600 shown in Figure 6C. The physical model 126A may analyze thermal expansions of the bonding structures 610A and 610B and the metal lines 606 A and 606B to determine whether a material of the bonding structures 610 A and 610B and the metal lines 606A and 606B fills the recesses formed due to dishing. In the illustrated embodiment, the physical model 126 A may determinethatthe material of the bonding structure 610 A and 610B and the metal lines 606 A and 606B over fills the recesses at the third bonding temperature.

[0053] The physical model 126 A may determine that the bonding layer 604 A of the first workpiece 600Ais bonded to the bonding layer 604B of the second workpiece 600B such that the dielectric layer 608 A is bonded to the dielectric layer 608B, with a bonding interface 702 indicated by a dashed line. The physical model 126 A may further determine that the bonding structures 610A and 610B overfill respective recesses at the third bonding temperature such that the material of the bonding structures 610A and 610B extends along the bonding interface 702. The bonded structure of the bonding structures 610A and 610B may be also referred to as a contact point. Accordingly, the contact point (comprising the bonding structures 610A and 610B) electrically couples the metal line 606A of the metallization layer 602 A of the first workpiece 600 A to the metal line 606B of the metallizationlayer 602B of the second workpiece 600B. In some embodiments, the material of the bonding structures 610A and 610B that extends along the bonding interface 702 adversely affects properties of the contact point. In some embodiments, the Al model 126B may generate updated layouts (e.g., comprising updated widths, lengths, and / or heights) for the bonding structures 6 lOAand 610B and / or the metal lines 606 A and 606B, such that the material of the bonding structures 610A and 610B does not extends along the bonding interface 702 at the third bonding temperature.

[0054] Figure 8 illustrates a cross-sectional view of a workpiece stack 800 in accordance with various embodiments. The workpiece stack 800 comprises a first workpiece 800 A bonded to a second workpiece 800B. In the illustrated embodiment, a front side of the first workpiece 800A is bonded to a back side of the second workpiece 800B. The first workpiece 800A comprises a substrate 802 A and an interconnect structure on a front side of the substrate 802A. In some embodiments, the substrate 802 A may be similar to the substrate of the workpiece 200A (see Figure 2A) and the description is not repeated herein. The interconnect structure may comprise one or more dielectric layers 804A and one or more metallization layers (e.g., metallization layers 806A and 808A) within the one or more dielectric layers 804A. In some embodiments, the one or more dielectric layers 804A may comprise one or more suitable dielectric materials such as silicon oxide, low-k dielectric materials, or the like. The one or more metallization layers (e.g., metallization layers 806A and 808 A) may comprise a plurality of conductive lines and a plurality of conductive vias electrically coupling adjacent metallization layers. The metallization layers may comprise a suitable conductive material such as copper (Cu), for example. The metallization layers may be formed by a damascene process, a dual damascene process, or the like. In some embodiments, portions of the topmost metallization layer (e.g., metallization layer 808A) may act as a bonding structure 816A.

[0055] The second workpiece 800B comprises a substrate 802B and an interconnect structure on a front side of the substrate 802B. In some embodiments, the substrate 802B may be similar to the substrate of the workpiece 200A (see Figure 2A) and the description is not repeated herein. The interconnect structure may comprise one or more dielectric layers 804B and one or more metallization layers (e.g., metallization layers 806B and 808B) within the one or more dielectric layers 804B. In some embodiments, the one or more dielectric layers 804B may comprise one or more suitable dielectric materials such as silicon oxide, low-k dielectric materials, or the like. The one or more metallization layers (e.g., metallization layers 806B and 808B) may comprise a plurality of conductive lines and a plurality of conductive vias electrically coupling adjacent metallization layers. The metallization layers may comprise a suitable conductive material such as copper (Cu), for example. The metallization layers may be formed by a damascene process, a dual damascene process, or the like.

[0056] In some embodiments, the second workpiece 800B further comprises a through- silicon via (TSV) 816B extending through the substrate 802B and in physical and electrical contact with metallization layer 808B. The TSV 816B may comprises a conductive material 814 and a dielectric liner 812 isolating the conductive material 814 from the substrate 802B.The conductive material 814 may comprise a suitable metallic material such as copper (Cu), for example. The dielectric liner 812 may comprise a suitable dielectric material such as silicon oxide, silicon nitride, a combination thereof, or the like. In some embodiments, TSV816B may act as a bonding structure. In some embodiments, the second workpiece 800B may further comprise a dielectric layer 810 on the back side of the substrate 802B. The dielectric layer 810 may comprise a suitable dielectric material such as silicon oxide, silicon nitride, a combination thereof, or the like.

[0057] In some embodiments, the circuit design modeling system 102 (see Figure IB) may implement the physical model 126 A to simulate thermal processes (e.g., thermal expansion, thermal conductively, thermal stress, etc.) of the workpiece stack 800 during the bonding process. The physical model 126A may analyze the bonding structure 816A and the TSV 816B to determine if a contact point formed after bonding the bonding structure 816A to the TSV 816B has desired properties. In some embodiments, the Al model 126B may analyze results of the physical model 126A to determine whether updated layouts (e.g., comprising updated widths, lengths, and / or heights) for the bonding structure 816A and the TSV 816B are needed. In some embodiments, the first workpiece 800A and the second workpiece 800B may be bonded using the bonding apparatus 100 (see Figure 1A) such that a topmost dielectric layer of the one or more dielectric layers 804A is bonded to the dielectric layer 810 andthe bonding structure 816A is bonded to the TSV 816B.

[0058] Figures 9A and 9B illustrate a process flow diagram of a method 900 for circuit design modeling of workpieces to be bonded in accordance with various embodiments. The method 900 maybe implemented by the circuit design modeling system 102 ofFigure IB. The method 900 may be implemented, atleastin part, in the form of executable code (e.g., software instructions 124 and simulation model 126 of Figure IB) stored on non-transitory, tangible, computer-readable medium (e.g., memory 122 of Figure IB) that when executed by one or more processors (e.g., processor 120 of Figure IB) may cause the one or more processors to perform one or more of the operations 902-938.

[0059] Method 900 starts with operation 902. In operation 902, a processor 120 of the circuit design modeling system 102 (see Figure IB) receives a first layout file (e.g., first layout file 130A of Figure IB), first design rules (e.g., first design rules 132A of Figure IB), first parameter variations (e.g., first parameter variations 134A of Figure IB), and first material parameters (e.g., first material parameters 136A ofFigure IB) for a first workpiece (e.g., firstworkpiece 110A of Figure 1A). In operation 904, the processor 120 of the circuit design modeling system 102 receives a second layoutfile (e.g., second layout file 130B ofFigure IB), second design rules (e.g., second design rules 132B ofFigure IB), second parameter variations (e.g., second parameter variations 134B of Figure IB), and second material parameters (e.g, second material parameters 136B ofFigure lB)fora second workpiece (e.g., second workpiece 11 OB of Figure 1 A).

[0060] The first layout file (e.g., first layout file 130 A ofFigure IB) and the second layout file (e.g., second layout file 130B of Figure IB) may include geometries and dimensions of bonding structures of the first workpiece (e.g., first workpiece 110A of Figure 1A) and the second workpiece (e.g., second workpiece HOB of Figure 1 A), respectively. The first layout file (e.g., first layout file 130A ofFigure IB) and the second layout file (e.g., second layout file 130B of Figure IB) may further include geometries and dimensions of metallization layers adjacent to the bonding structures. The first design rules (e.g., first design rules 132A ofFigure IB) and the second design rules (e.g., second design rules 132B of Figure IB) include design rules forthefirstworkpiece (e.g., first workpiece 110A ofFigure 1A) and the second workpiece (e.g., second workpiece HOB ofFigure 1 A), respectively. The first material parameters (e.g, first material parameters 136A ofFigure IB) and the second material parameters (e.g., second material parameters 136B of Figure IB) include information about the materials used, along with their thermal, mechanical, and electrical properties for the first workpiece (e.g., first workpiece 110A of Figure 1 A) and the second workpiece (e.g., second workpiece 110B of Figure 1 A), respectively. The first parameter variations (e.g., first parameter variations 134A of Figure IB) and second parameter variations (e.g., second parameter variations 134B of Figure IB) include ranges of dimensions of various structures (e.g., widths, lengths, and recess depths of bonding structures) due to process variations while forming the first workpiece (e.g, first workpiece 110A of Figure 1A) and the second workpiece (e.g., second workpiece HOB of Figure 1A), respectively.

[0061] In operation 906, the processor 120 of the circuit design modeling system 102 analysis the first layout file (e.g., first layout file 130A ofFigure lB) andthe second layout file (e.g., second layoutfile 130B ofFigure IB) to identify a plurality of contactpoints (e.g., contact points 138 of Figure IB). Each contact point (e.g., each of contactpoints 138 of Figure IB) comprises a bonding structure (e.g., bonding structure 144A of Figure IB) of the first workpiece (e.g., first workpiece 110A of Figure 1 A) and a bonding structure (e.g., bondingstructure 144B of Figure IB) of the second workpiece (e.g., second workpiece HOB of Figure 1A).

[0062] In operation 908, the processor 120 of the circuit design modeling system 102 determines types (e.g., types 140 of Figure IB) of the plurality of contact points (e.g., contact points 138 of Figure IB) based on the first layout file (e.g., first layout file 130A of Figure IB) and the second layout file (e.g., second layout file 130B of Figure IB). The types (e.g., types 140 of Figure IB) of the plurality of contact points (e.g., contact points 138 of Figure IB) may include types based on dimensions, geometry, and pitch of the bonding structures, as well as dimensions and geometry of adjacent metallization features.

[0063] In operation 910, the processor 120 of the circuit design modeling system 102 groups the plurality of contact points (e.g., contact points 138 of Figure IB) into a plurality of bins (e.g., bins 142 of Figure IB). Each bin (e.g., each of bins 142 of Figure IB) includes a subset of the plurality of contactpoints (e.g., contactpoints 138 of Figure IB) having a same type (e.g., respective on types 140 of Figure IB).

[0064] In operation 912, the processor 120 of the circuit design modeling system 102 selects a bin (e.g., respective one of bins 142 of Figure IB). In operation 914, the processor 120 of the circuit design modeling system 102 simulates a contact point (e.g., respective one of contact points 138 of Figure IB) of the selected bin (e.g., respective one of bins 142 of Figure IB) using a physical model (e.g., physical model 126A of Figure IB) of a simulation model (e.g., simulation model 126 of Figure IB). The contact point (e.g., respective one of contact points 138 of Figure IB) comprises a first bonding structure (e.g., respective one of first bonding structures 144A of Figure IB) and a second bonding structure (e.g., respective one of second bonding structures 144B of Figure IB).

[0065] In operation 916, the processor 120 of the circuit design modeling system 102 determines whether the contact point (e.g., respective one of contact points 138 of Figure IB) has desired properties. In some embodiments, the processor 120 of the circuit design modeling system 102 may determine whether the contact point (e.g., respective one of contact points 138 of Figure IB) has one or more voids, whether the contact point (e.g., respective one of contact points 138 ofFigure IB) has a desired resistance, and / orwhetheramaterial of thefirstbonding structure (e.g., respective one of first bonding structures 144A ofFigure IB) and the second bonding structure (e.g., respective one of second bonding structures 144B of Figure IB)extends along an interface between the first workpiece (e.g., first workpiece 110A of FigureIA) and the second workpiece (e.g., second workpiece HOB of Figure 1A).

[0066] In response to determining at operation 916 that the contact point (e.g., respective one of contact points 138 of Figure IB) has desired properties, method 900 proceeds to operation 918. In operation 918, the processor 120 of the circuit design modeling system 102 determines whether all bins (e.g., bins 142 of Figure IB) have been selected. In response to determining at operation 918 that all bins have not been selected, method 900 proceeds to operation 920. In operation 920, the processor 120 of the circuit design modeling system 102 selects a newbin (e.g., respective of bins 142 of Figure IB). After performing operation 920, method 900 proceeds back to operation 914.

[0067] In response to determining at operation 916 that the contact point (e.g., respective one of contact points 138 of Figure IB) does not have desired properties, method 900 proceeds to operation 922. In operation 922, the processor 120 of the circuit design modeling system 102 executes an Al model (e.g., Al model 126B of Figure IB) of the simulation model (e.g., simulation model 126 of Figure IB) to update a first layout (e.g., first layout 146A of Figure lB) ofthefirstbonding structure (e.g., respectiveone of firstbonding structures 144AofFigureIB) and a second layout (e.g., second layout 146B of Figure IB) of the second bonding structure (e.g., respective one of second bonding structures 144B of Figure IB) to determine an updated first layout (e.g., updated firstlayout 148A of Figure IB) and an updated second layout (e.g., updated second layout 148B of Figure IB), respectively. The updated first layout (e.g., updated first layout 148A of Figure IB) and the updated second layout (e.g., updated second layout 148B of Figure IB) defines an updated contact point.

[0068] In operation 924, the processor 120 of the circuit design modeling system 102 simulates the updated contact point using the physical model (e.g., physical model 126A of Figure IB) of the simulation model (e.g., simulation model 126 of Figure IB). In operation 926, the processor 120 of the circuit design modeling system 102 determines whether the updated contact point has the desired properties. In response to determining at operation 926 that the updated contact point has the desired properties, method 900 proceeds back to operation 918.

[0069] In response to determining at operation 926 that the updated contact point does not have the desired properties, method 900 proceeds to operation 928. In operation 928, the processor 120 of the circuit design modeling system 102 executes the Al model (e.g., Al model126B of Figure IB) of the simulation model (e.g., simulation model 126 of Figure IB) to update process parameters (e.g., process parameters 128 of Figure IB) of a bonding process. In some embodiments, the processor 120 of the circuit design modeling system 102 updates a temperature of the bonding process. After performing operation 928, method 900 proceeds back to operation 912.

[0070] In response to determining at op eration 918 that all bins have been selected, method900 proceeds to operation 930. In operation 930, the processor 120 of the circuit design modeling system 102 executes the Al model (e.g., Al model 126B of Figure IB) of the simulation model (e.g., simulation model 126 of Figure IB) to update the first lay out file (e.g, first lay out file 130A ofFigure IB) and the second layout file (e.g., second lay out file I30B of Figure IB) and generate an updated first layout file (e.g., updated first layout file 150A of Figure IB) and an updated second lay out file (e.g., updated second layout file 150B ofFigure IB), respectively. In some embodiments, the updated first layout file (e.g., updated first layout file 150A of Figure IB) comprises updated first layouts (e.g., updated first layouts 148A of Figure IB) of the firstbonding structures (e.g., first bonding structures 144A ofFigure IB) and the updated second layout file (e.g., updated second layout file 150B ofFigure IB) comprises updated secondlayouts (e.g., updated secondlayouts 148B ofFigure IB) of the second bonding structures (e.g., second bonding structures 144B of Figure IB).

[0071] In operation 932, theprocessor 120ofthe circuitdesign modelingsystem 102 sends the updated firstlay outfile (e.g., updated firstlayoutfile 150 A ofFigure IB) to a manufacturer of the first workpiece (e.g., first workpiece 1 lOAof Figure 1 A) and the updated second layout file (e.g., updated second layout file 150B of Figure IB) to a manufacturer of the second workpiece (e.g., second workpiece 110B ofFigure 1 A). In operation 934, the processor 120 of the circuit design modeling system 102 sends the updated process parameters (e.g., updated process parameters 152 ofFigure IB) to the bonding apparatus (e.g., bonding apparatus 100 of Figure 1A).

[0072] In operation 936, the processor 120 of the circuit design modeling system 102 receives test results (e.g., test results 154 ofFigure IB) obtainedby testing a test chip. In some embodiments, the testchip may compriseone ormore updated contactpoints. In operation 938, theprocessor 120 of the circuit design modeling system 102 updates the simulation model (e.g, simulation model 126 ofFigure IB) based on the test results to generate an updated simulation model (e.g., updated simulation model 156 ofFigure IB). In some embodiments, theprocessor120 of the circuit design modeling system 102 updates the physical model (e.g., physical model 126A of Figure IB) and / or the Al model (e.g., Al model 126B of Figure IB) of the simulation model (e.g., simulation model 126 of Figure IB).

[0073] Figures 10A and 10B illustrate a process flow diagram of a method 1000 for bonding workpieces in accordance with various embodiments. The method 1000 may be implemented, at least in part, in the form of executable code (e.g., software instructions 124 and simulation model 126) stored on non -transitory, tangible, computer-readable medium (e.g, memory 122) that when executed by one or more processors (e.g., processor 120) may cause the one or more processors to perform one or more of the operations 1002 -1032.

[0074] Method 1000 starts with operation 1002. In operation 1002, a processor 120 of the circuit design modeling system 102 (see Figure IB) receives a notification (e.g., notification 158 of Figure lB) from a bonding apparatus (e.g., bonding apparatus 100 ofFigure lA) that a first workpiece (e.g., first workpiece 110A ofFigure 1A) and a second workpiece (e.g., second workpiece HOB of Figure 1 A) are to be bonded. In operation 1004, the processor 120 of the circuit design modeling system 102 (see Figure IB) receives a first layout file (e.g., first layout file 130A of Figure IB), first design rules (e.g., first design rules 132A of Figure IB), first parameter variations (e.g., first parameter variations 134A of Figure IB), and first material parameters (e.g., first material parameters 136A ofFigure IB) for a first workpiece (e.g., first workpiece 110A of Figure 1A). In operation 1006, the processor 120 of the circuit design modeling system 102 receives a second layoutfile (e.g., second layout file 130B ofFigure IB), second design rules (e.g., second design rules 132B ofFigure IB), second parameter variations (e.g., second parameter variations 134B of Figure IB), and second material parameters (e.g, second material parameters 136B ofFigure lB)fora second workpiece (e.g., second workpiece HOB ofFigure 1 A). In operation 1008, the processor 120 of the circuit design modeling system 102 receives process parameters (e.g., process parameters 128 of Figure IB) of a bonding process to be performed by the bonding apparatus (e.g., bonding apparatus 100 ofFigure 1 A).

[0075] In operation 1010, the processor 120 of the circuit design modeling system 102 analysis the first layout file (e.g., first layout file 130A ofFigure lB) andthe second layout file (e.g., second lay outfile 130B ofFigure IB) to identify a plurality of contactpoints (e.g., contact points 138 of Figure IB). Each contact point (e.g., each of contact points 138 of Figure IB) comprises a bonding structure (e.g., bonding structure 144A of Figure IB) of the first workpiece (e.g., first workpiece 110A of Figure 1 A) and a bonding structure (e.g., bondingstructure 144B of Figure IB) of the second workpiece (e.g., second workpiece 110B of Figure 1A).

[0076] In operation 1012, the processor 120 of the circuit design modeling system 102 determines types (e.g., types 140 of Figure IB) of the plurality of contact points (e.g., contact points 138 of Figure IB) based on the first layout file (e.g., first layout file 130A ofFigure IB) and the second layout file (e.g., second layout file 130B of Figure IB). The types (e.g., types 140 of Figure IB) of the plurality of contact points (e.g., contact points 138 ofFigure IB) may include types based on dimensions, geometry, and pitch of the bonding structures, as well as dimensions and geometry of adjacent metallization features.

[0077] In operation 1014, the processor 120 of the circuit design modeling system 102 groups the plurality of contact points (e.g., contact points 138 ofFigure IB) into a plurality of bins (e.g., bins 142 of Figure IB). Each bin (e.g., each of bins 142 of Figure IB) includes a sub set of the plurality of contact points (e.g., contact points 138 of Figure IB) having a same type (e.g., respective on types 140 of Figure IB).

[0078] In operation 1016, the processor 120 of the circuit design modeling system 102 selects a bin (e.g., respective one of bins 142 of Figure IB). In operation 1018, the processor 120 of the circuit design modeling system 102 simulates a contact point (e.g., respective one of contact points 138 of Figure IB) of the selected bin (e.g., respective one of bins 142 of Figure IB) using a physical model (e.g., physical model 126A of Figure IB) of a simulation model (e.g., simulation model 126 of Figure IB). The contact point (e.g., respective one of contact points 138 of Figure IB) comprises a first bonding structure (e.g., respective one of first bonding structures 144A of Figure IB) and a second bonding structure (e.g., respective one of second bonding structures 144B of Figure IB).

[0079] In operation 1020, the processor 120 of the circuit design modeling system 102 determines whether the contact point (e.g., respective one of contact points 138 of Figure IB) has desired properties. In some embodiments, the processor 120 of the circuit design modeling system 102 may determine whether the contact point (e.g., respective one of contact points 138 of Figure IB) has one or more voids, whether the contact point (e.g., respective one of contact points 138 ofFigure IB) has a desired resistance, and / orwhetheramaterial ofthe firstbonding structure (e.g., respective one of first bonding structures 144A ofFigure IB) and the second bonding structure (e.g., respective one of second bonding structures 144B of Figure IB)extends along an interface between the first workpiece (e.g., first workpiece 110A of Figure 1A) and the second workpiece (e.g., second workpiece HOB of Figure 1A).

[0080] In response to determining at operation 1020 that the contact point (e.g., respective one of contact points 138 of Figure IB) has desired properties, method 1000 proceeds to operation 1022. In operation 1022, the processor 120ofthe circuitdesign modelingsystem 102 determines whether all bins (e.g., bins 142 of Figure IB) have been selected. In response to determining at operation 1022 that all bins have not been selected, method 1000 proceeds to operation 1024. In operation 1024, the processor 120ofthe circuitdesign modelingsystem 102 selects a new bin (e.g., respective of bins 142 of Figure IB). After performing operation 1024, method 1000 proceeds back to operation 2018.

[0081] In response to determining at operation 1020 that the contact point (e.g., respective one of contactpoints 138ofFigure lB)doesnothave desired properties, method lOOO proceeds to operation 1026. In operation 1026, the processor 120 of the circuit design modeling system 102 updates process parameters (e.g., process parameters 128 of Figure IB) of the bonding process to determine updated process parameters (e.g., updated process parameters 152 of Figure IB). After performing operation 1026, method 1000 proceeds backto operation 1016.

[0082] In response to determining at operation 1022 that all bins have been selected, method 1000 proceedsto operation 1028. In operation 1028, the processor 120 of the circuit design modeling system 102 determines whether the process parameters (e.g., process parameters 128 of Figure IB) have been updated. In response to determining at operation 1028 that the process parameters (e.g., process parameters 128 of Figure IB) have been updated, method 1000 proceedsto operation 1030. In operation 1030, the processor 120 of the circuit design modeling system 102 sends the updated process parameters (e.g., updated process parameters 152 of Figure IB) of the bonding process to the bonding apparatus (e.g., bonding apparatus of Figure 1A).

[0083] In response to determining at operation 1028 that the process parameters (e.g., process parameters 128 of Figure IB) have not been updated or after performing operation 1030, method 1000 proceeds to operation 1032. In operation 1032, the processor 120 of the circuit design modeling system 102 sends an instruction (e.g., instruction 160 of Figure IB) to the bonding apparatus (e.g., bonding apparatus of Figure 1 A) to perform the bonding process between thefirstworkpiece(e.g., firstworkpiece 1 lOA ofFigure 1A) and the second workpiece (e.g., second workpiece HOB of Figure 1A). After performing operation 1032, method 1000proceedsto end. Uponreceivingtheinstruction (e.g., instruction 160 ofFigure IB), the bonding apparatus (e.g., bonding apparatus of Figure 1A) performs the bonding process between the first workpiece (e.g., first workpiece 110A of Figure 1A) and the second workpiece (e.g, second workpiece HOB of Figure 1A).

[0084] Example embodiments of the disclosure are described below. Other embodiments can also be understood from the entirety of the specification as well as the claims filed herein.

[0085] Example 1 . An apparatus includes a memory configuredto store a simulation model and process parameters of a bonding process. The apparatus further includes a processor communicatively coupled to the memory. The processor is configured to receive a first layout file, first design rules, first parameter variations, and first material parameters for a first workpiece. The processor is further configured to receive a second layout file, second design rules, second parameter variations, and second material parameters for a second workpiece. The processor is further configured to analyze the first layout file and the second layout file to identify a plurality of contact points. Each contactpoint includes a feature ofthe first workpiece and a feature of the second workpiece. The processor is further configured to determine types of the plurality of contact points based on the first layout file and the second layout file and group the plurality of contact points into a plurality of bins. Each bin includes a subset of the plurality of contact points having a same type . The processor is further configured to simulate a first contact point of a first bin of the plurality of bins using the simulation model . The first contact point includes a first feature of the first workpiece and a second feature of the second workpiece. The processor is further configured to determine whether the first contact point has desired properties and, in response to determining that the first contact point does not have the desired properties update a first layout of the first feature and a second layout of the second feature to determine an updated first contact point, simulate the updated first contact point using the simulation model, and determine whether the updated first contact point has the desired properties. In response to determiningthattheupdatedfirstcontactpointhas the desired properties, the processor is further configured to update the first layout file to include the updated first layout of the first feature and update the second layout file to include the updated second layout of the second feature.

[0086] Example 2. The apparatus of example 1 , where the processor is further configured to, in response to determining that the updated first contact point does not have the desired properties, update the process parameters of the bonding process.

[0087] Example s . The apparatus of oneof examples 1 and 2, where the processor is further configured to send the updated process parameters of the bonding process to a bonding apparatus.

[0088] Example 4. The apparatus of one of examples 1 to 3, where the processor is further configured to receive test results, the test results being obtained from testing a test chip including the updated first contact point, and update the simulation model based on the test results.

[0089] Example 5. The apparatus of one of examples 1 to 4, where the processor is further configured to, in response to determining that the updated first contact point has the desired properties simulate a second contact point of a second bin of the plurality of bins using the simulation model. The second contact point includes a third feature of the first workpiece and a fourth feature of the second workpiece. The processor is further configured to determine whether the second contact point has desired properties. In response to determining that the second contact point does not have the desired properties, the processor is further configured to update a third layout of the third feature and a fourth layout ofthe fourth featureto determine an updated second contact point, simulate the updated second contact point using the simulation model, and determine whether the updated second contact point has the desired properties. In response to determining that the updated second contact point has the desired properties, the processor is further configured to update the first layout file to include the updated third layout of the third feature and update the second layout file to include the updated fourth layout of the fourth feature.

[0090] Example 6. The apparatus of one of examples 1 to 5, where the first contact point and the second contact point are simulated in parallel.

[0091] Example 7. The apparatus of one of examples 1 to 6, where the simulation model simulates the bonding process between the first workpiece and the second workpiece.

[0092] Example 8. A method includes receiving a first layout file, first design rules, first parameter variations, and firstmaterial parameters for a first workpiece, and receiving a second layout file, second design rules, second parameter variations, and second material parameters for a second workpiece. The method further includes analyzing the first layout file and the second layout file to identify a plurality of contact points. Each contact point includes a feature of the first workpiece and a feature of the second workpiece. The method further includes determining types of the plurality of contact points based on the first layout file and the secondlayoutfile and groupingthe plurality of contactpoints into a plurality of bins. Each bin includes a subset of the plurality of contact points having a same type. The method further includes simulating a first contact point of a first bin of the plurality of bins using a simulation model. The first contact point includes a first feature of the first workpiece and a second feature of the second workpiece. The method further includes determining whether the first contact point has desired properties. In response to determining that the first contact point does not have the desired properties, the method further includes updating a first layout of the first feature and a second layout of the second feature to determine an updated first contact point, simulating the updated first contact point using the simulation model, and determining whether the updated first contact point has the desired properties. In response to determining that the updated first contact point has the desired properties, the method further includes updating the first layout file to include the updated first layout of the first feature and updating the second layout file to include the updated second layout of the second feature.

[0093] Example 9. The method of example 8, further including, in response to determining that the updated first contact point does not have the desired properties, updating process parameters of a bonding process.

[0094] Example 10. The method of one of examples 8 and 9, further including sending the updated process parameters of the bonding process to a bonding apparatus.

[0095] Example 11. The method of one of examples 8 to 10, further including receiving test results, the test results being obtained from testing a test chip including the updated first contact point, and updating the simulation model based on the test results.

[0096] Example 12. The method of one of examples 8 to 11, further including, in response to determiningthatthe updated first contact point has the desiredproperties simulating a second contact point of a second bin of the plurality of bins using the simulation model . The second contact point includes a third feature of the first workpiece and a fourth feature of the second workpiece. The method further includes determining whether the second contact point has desired properties. In response to determiningthatthe second contact point does not have the desired properties, the method further includes updating a third layout of the third feature and a fourth layout of the fourth feature to determine an updated second contact point, simulating the updated second contact point using the simulation model, and determining whether the updated second contact point has the desired properties. In response to determining that the updated second contact point has the desired properties, the method further includes updatingthe first layout file to include the updated third layout of the third feature and updating the second layout file to include the updated fourth layout of the fourth feature.

[0097] Example 13. The method of one of examples 8 to 12, where the first contact point and the second contact point are simulated in parallel.

[0098] Example 14. The method of one of examples 8 to 13, where the simulation model simulates a bonding process between the first workpiece and the second workpiece.

[0099] Example 15. A non-transitory computer-readable medium storing instructions that, when executed by one or more processors, cause the one or more processors to receive a first layout file, first design rules, first parameter variations, and first material parameters for a first workpiece, and receive a second layout file, second design rules, second parameter variations, and second material parameters for a second workpiece. The instructions, when executed by one or more processors, further cause the one or more processors to analyze the first layout file and the second layout file to identify a plurality of contact points . Each contact point includes a feature of the first workpiece and a feature of the second workpiece. The instructions, when executed by one or more processors, further cause the one or more processors to determine types of the plurality of contact points based on the first layout file and the second layout file, group the plurality of contact points into a plurality of bins, wherein each bin includes a subset of the plurality of contact points having a same type, and simulate a first contact point of a first bin of the plurality of bins using a simulation model. The first contact point includes a first feature of the first workpiece and a second feature of the second workpiece. The instructions, when executed by one or more processors, further cause the one or more processors to determine whether the first contactpointhas desired properties. In response to determiningthat the first contact point does not have the desired properties, the instructions, when executed by one or more processors, further cause the one or more processors to update a first layout of the first feature and a second layout of the second feature to determine an updated first contact point, simulate the updated first contact point using the simulation model, and determine whether the updated first contact point has the desired properties . In response to determining that the updated first contact point has the desired properties, the instructions, when executed by one or more processors, further cause the one or more processors to update the first layout file to include the updated first layout of the first feature and update the second layout file to include the updated second layout of the second feature.

[0100] Example 16. The non-transitory computer-readable medium of example 15, where the instructions, when executed by the one or more processors, further cause the one or more processors to, in response to determining that the updated first contact point does not have the desired properties, update process parameters of a bonding process.

[0101] Example 17. The non-transitory computer-readable medium of one of examples 15 and 16, where the instructions, when executed by the one or more processors, further cause the one or more processors to send the updated process parameters of the bonding process to a bonding apparatus.

[0102] Example 18. The non-transitory computer-readable medium of one of examples 15 to 17, where the instructions, when executed by the one or more processors, further cause the one or more processors to receive test results, the test results being obtained from testing a test chip including the updated first contact point, and update the simulation model based on the test results.

[0103] Example 19. The non-transitory computer-readable medium of one of examples 15 to 18, where the instructions, when executed by the one or more processors, further cause the one or more processors to, in response to determining that the updated first contact point has the desired properties simulate a second contact point of a second bin of the plurality of bins using the simulation model. The second contact point includes a third feature of the first workpiece and a fourth feature of the second workpiece. The instructions, when executed by the one or more processors, further cause the one or more processors to determine whether the second contact point has desired properties. In response to determining that the second contact point does not have the desired properties, the instructions, when executed by the one or more processors, further cause the one or more processors to update a third layout of the third f eature and a fourth layout of the fourth feature to determine an updated second contact point, simulate the updated second contact point using the simulation model, and determine whether the updated second contact point has the desired properties. In response to determining that the updated second contact point has the desired properties, the instructions, when executed by the one or more processors, further cause the one or more processors to update the first layout file to include the updated third layout of the third feature and update the second layout file to include the updated fourth layout of the fourth feature.

[0104] Example 20. The non-transitory computer-readable medium of one of examples 15 to 19, where the first contact point and the second contact point are simulated in parallel.

[0105] While this invention has been described with reference to illustrative embodiments, this description is not intended to be construed in a limiting sense. Various modifications and combinations of the illustrative embodiments, as well as other embodiments of the invention, will be apparent to persons skilled in the art upon reference to the description. It is therefore intended that the appended claims encompass any such modifications or embodiments.

Claims

WHAT IS CLAIMED IS:1 . A system comprising: a memory configured to store: a simulation model; and process parameters of a bonding process; and a processor communicatively coupled to the memory, wherein the processor is configured to: receive a first layout file, first design rules, first parameter variations, and first material parameters for a first workpiece; receive a second layout file, second design rules, second parameter variations, and second material parameters for a second workpiece; analyze the first layout file and the second layout file to identify a plurality of contact points, wherein each contact point comprises a feature of the first workpiece and a feature of the second workpiece; determine types of the plurality of contact points based on the first layout file and the second layout file; group the plurality of contact points into a plurality of bins, wherein each bin includes a subset of the plurality of contact points having a same type; simulate a first contact point of a first bin of the plurality of bins using the simulation model, wherein the first contact point comprises a first feature of the first workpiece and a second feature of the second workpiece; determine whether the first contact point has desired properties; and in response to determining that the first contact point does not have the desired properties: update a first layout of the first feature and a second layout of the second feature to determine an updated first contact point; simulate the updated first contact point using the simulation model; determine whether the updated first contact point has the desired properties; and in response to determining that the updated first contact point has the desired properties: update the first layout file to include the updated first layout of the first feature; andupdate the second layout file to include the updated second layout of the second feature.

2. The system of claim 1, wherein the processor is further configured to, in response to determining that the updated first contact point does not have the desired properties, update the process parameters of the bonding process.

3. The system of claim 2, wherein the processor is further configured to send the updated process parameters of the bonding process to a bonding apparatus.

4. The system of claim 1, wherein the processor is further configured to: receive test results, the test results being obtained from testing a test chip comprising the updated first contact point; and update the simulation model based on the test results.

5. The system of claim 1, wherein the processor is further configured to, in response to determining that the updated first contact point has the desired properties : simulate a second contact point of a second bin of the plurality of bins using the simulation model, wherein the second contact point comprises a third feature of the first workpiece and a fourth feature of the second workpiece; determine whether the second contact point has desired properties; and in response to determining that the second contact point does not have the desired properties: update a third layout of the third feature and a fourth layout of the fourth feature to determine an updated second contact point; simulate the updated second contact point using the simulation model; determine whether the updated second contact point has the desired properties; and in response to determining that the updated second contact point has the desired properties: update the first layout file to include the updated third layout of the third feature; and update the second layout file to include the updated fourth layout of the fourth feature.

6. The system of claim 5, wherein the first contact point and the second contact point are simulated in parallel.

7. The system of claim 1, wherein the simulation model simulates the bonding process between the first workpiece and the second workpiece.

8. A method comprising: receiving a first layout file, first design rules, first parameter variations, and first material parameters for a first workpiece; receiving a second layout file, second design rules, second parameter variations, and second material parameters for a second workpiece; analyzing the first layout file and the second layout file to identify a plurality of contact points, wherein each contact point comprises a feature of the first workpiece and a feature of the second workpiece; determining types of the plurality of contact points based on the first layout file and the second layout file; grouping the plurality of contact points into a plurality of bins, wherein each bin includes a subset of the plurality of contact points having a same type; simulating a first contact point of a first bin of the plurality of bins using a simulation model, wherein the first contact point comprises a first feature of the first workpiece and a second feature of the second workpiece; determining whether the first contact point has desired properties; and in response to determining that the first contact point does not have the desired properties: updating a first layout of the first feature and a second layout of the second feature to determine an updated first contact point; simulating the updated first contact point using the simulation model; determining whether the updated first contact point has the desired properties; and in response to determining that the updated first contact point has the desired properties: updating the first layout file to include the updated first layout of the first feature; and updating the second layout file to include the updated second layout of the second feature.

9. The method of claim 8, further comprising, in response to determining that the updated first contact point does not have the desired properties, updating process parameters of a bonding process.

10. The method of claim 9, further comprising sending the updated process parameters of the bonding process to a bonding apparatus.11 . The method of claim 8, further comprising: receiving test results, the test results being obtained from testing a test chip comprising the updated first contact point; and updating the simulation model based on the test results.

12. The method of claim 8, further comprising, in response to determining that the updated first contact point has the desired properties: simulating a second contact point of a second bin of the plurality of bins using the simulation model, wherein the second contact point comprises a third feature of the first workpiece and a fourth feature of the second workpiece; determining whether the second contact point has desired properties; and in response to determining that the second contact point does not have the desired properties: updating a third layout of the third feature and a fourth layout of the fourth feature to determine an updated second contact point; simulating the updated second contact point using the simulation model; determining whether the updated second contact point has the desired properties; and in response to determining that the updated second contact point has the desired properties: updating the first layout file to include the updated third layout of the third feature; and updating the second layout file to include the updated fourth layout of the fourth feature.

13. The method of claim 12, wherein the first contact point and the second contact point are simulated in parallel.

14. The method of claim 8, wherein the simulation model simulates a bonding process between the first workpiece and the second workpiece.

15. A non-transitory computer-readable medium storing instructions that, when executed by one or more processors, cause the one or more processors to: receive a first layout file, first design rules, first parameter variations, and first material parameters for a first workpiece; receive a second layout file, second design rules, second parameter variations, and second material parameters for a second workpiece; analyze the first layout file and the second layout file to identify a plurality of contact points, wherein each contact point comprises a feature of the first workpiece and a feature of the second workpiece; determine types of the plurality of contact points based on the first layout file and the second layout file; group the plurality of contact points into a plurality of bins, wherein each bin includes a subset of the plurality of contact points having a same type; simulate a first contact point of a first bin of the plurality of bins using a simulation model, wherein the first contact point comprises a first feature of the first workpiece and a second feature of the second workpiece; determine whether the first contact point has desired properties; and in response to determining that the first contact point does not have the desired properties: update a first layout of the first feature and a second layout of the second feature to determine an updated first contact point; simulate the updated first contact point using the simulation model; determine whether the updated first contact point has the desired properties; and in response to determining that the updated first contact point has the desired properties: update the first layout file to include the updated first layout of the first feature; and update the second layout file to include the updated second layout of the second feature.

16. The non-transitory computer-readable medium of claim 15, wherein the instructions, when executed by the one or more processors, further cause the one or more processors to, in response to determining that the updated first contact point does not have the desired properties, update process parameters of a bonding process.

17. The non-transitory computer-readable medium of claim 16, wherein the instructions, when executed by the one or more processors, further cause the one or more processors to send the updated process parameters of the bonding process to a bonding apparatus.

18. The non-transitory computer-readable medium of claim 15, wherein the instructions, when executed by the one or more processors, further cause the one or more processors to : receive test results, the test results being obtained from testing a test chip comprising the updated first contact point; and update the simulation model based on the test results.

19. The non-transitory computer-readable medium of claim 15, wherein the instructions, when executed by the one or more processors, further cause the one or more processors to , in response to determining that the updated first contact point has the desired properties: simulate a second contact point of a second bin of the plurality of bins using the simulation model, wherein the second contact point comprises a third feature of the first workpiece and a fourth feature of the second workpiece; determine whether the second contact point has desired properties; and in response to determining that the second contact point does not have the desired properties: update a third layout of the third feature and a fourth layout of the fourth feature to determine an updated second contact point; simulate the updated second contact point using the simulation model; determine whether the updated second contact point has the desired properties; and in response to determining that the updated second contact point has the desired properties: update the first layout file to include the updated third layout of the third feature; andupdate the second layout file to include the updated fourth layout of the fourth feature.

20. The non-transitory computer-readable medium of claim 19, wherein the first contact point and the second contact point are simulated in parallel.

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