Micro LED with apertured current flow

Abstract

Described are light emitting diode (LED) arrays comprising a plurality of mesas defining pixels having sidewalls, each of the mesas comprising an epitaxial stack on a substrate. The epitaxial stack includes a first n-type layer on the substrate, a second n-type layer on the first n-type layer, an n-type confinement layer on the second n-type layer, an active region having an active region width on the n-type confinement layer, a p-type confinement layer on the active region, a second p-type layer on the p-type confinement layer. The n-type confinement layer and the p-type confinement layer independently have a width less than the active region.

Description

MICRO LED WITH APERTURED CURRENT FLOWTECHNICAL FIELD

[0001] Embodiments of the disclosure generally relate to arrays of light emitting diode (LED) devices and methods of manufacturing the same. More particularly, embodiments are directed to light emitting diode devices having a decreased Shockley-Read-Hall (RSH) non-radiative recombination on the mesa sidewalls.BACKGROUND

[0002] A light emitting diode (LED) is a semiconductor light source that emits visible light when current flows through it. LEDs combine a P-type semiconductor with an N-type semiconductor. LEDs commonly use a lll-group compound semiconductor. A lll-group compound semiconductor provides stable operation at a higher temperature than devices that use other semiconductors. The lll-group compound is typically formed on a substrate formed of sapphire or silicon carbide (SiC).

[0003] Aluminum indium gallium phosphorus (AllnGaP) quaternary compound semiconductors are promising candidates for micro-LED red emission and may provide advantages over Ill-nitride material systems. AllnGaP micro-LED have high external quantum efficiency (EQE), low voltage, narrow peak, wavelength with small full width half maximum (FWHM), good reliability, and wider color gamut coverage. AllnGaP micro-LED has a wide range of applications with mesa sizes from one micron to tens of microns.

[0004] AllnGaP, however, can have a minority carrier diffusion length of up to several microns, which is much longer than Ill-nitride and therefore has more significant mesa size effects. Due to a higher surface-to volume ratio, a smaller LED size can lead to a high Shockley-Read-Hall (SRH) non-radiative recombination at sidewall defect sites, which is caused by plasma dry etching. The high SRH non- radiative recombination at the sidewall defect sites also degrades reliability performance for smaller mesa micro-LEDs.

[0005] A desirable micro-LED AllnGaP device architecture has the least SRH non- radiative recombination on mesa sidewalls. Accordingly, there is a need for improved LED devices. More specifically, there is a need to improve LED devices havingreduced sidewall damage and constrained carrier flow away from sidewall damage sites in the active region, especially as device size decreases.SUMMARY

[0006] Embodiments of the disclosure are directed to LED devices and methods for manufacturing LED devices. In one or more embodiments, a light emitting diode (LED) device comprises: an epitaxial stack on a substrate, the epitaxial stack comprising at least one n-type layer, at least one p-type layer, a first confinement layer, a second confinement layer, and an active region having an active region width, wherein the first confinement layer and the second confinement layer independently have a width less than the active region width; a p-type contact on the epitaxial stack; and an n-type contact adjacent to the at least one n-type layer.

[0007] Further embodiments of the disclosure are directed to a light emitting diode (LED) array. In one or more embodiments, a light emitting diode (LED) array comprises: a plurality of mesas defining pixels having sidewalls, each of the mesas comprising: an epitaxial stack on a substrate, the epitaxial stack comprising a first n- type layer on the substrate, a second n-type layer on the first n-type layer, an n-type confinement layer on the second n-type layer, an active region having an active region width on the n-type confinement layer, a p-type confinement layer on the active region, a second p-type layer on the p-type confinement layer, wherein the n-type confinement layer and the p-type confinement layer independently have a width less than the active region width; a p-type contact on the epitaxial stack; and an n-type contact adjacent to the second n-type layer on the first n-type layer.

[0008] Additional embodiments of the disclosure are directed to methods of manufacturing a light emitting diode (LED) devices. In one or more embodiments, a method of manufacturing a light emitting diode (LED) device comprises: growing a plurality of epitaxial layers including at least one n-type layer, an active region having an active region width, and at least one p-type layer on a substrate to form a mesa having sidewalls; treating the sidewalls of the mesa to form an n-type confinement layer and a p-type confinement layer, wherein the n-type confinement layer and the p- type confinement layer independently have a width less than the active region width;forming a p-contact on the at least one p-type layer; and forming an n-contact adjacent to the at least one n-type layer.BRIEF DESCRIPTION OF THE DRAWINGS

[0009] So that the manner in which the above recited features of the present disclosure can be understood in detail, a more particular description of the disclosure, briefly summarized above, may be had by reference to embodiments, some of which are illustrated in the appended drawings. It is to be noted, however, that the appended drawings illustrate only typical embodiments of this disclosure and are therefore not to be considered limiting of its scope, for the disclosure may admit to other equally effective embodiments. The embodiments as described herein are illustrated by way of example and not limitation in the figures of the accompanying drawings in which like references indicate similar elements.

[0010] FIG. 1 illustrates a process flow diagram for a method of forming a LED die according to one or more embodiments;

[0011] FIG. 2 illustrates a cross-section schematic of an epitaxy configuration according to one or more embodiments;

[0012] FIG. 3A illustrates a cross-section schematic of an epitaxy configuration according to one or more embodiments;

[0013] FIG. 3B illustrates an isometric view of an epitaxy configuration according to one or more embodiments;

[0014] FIG. 4 illustrates an example of a general device in accordance with some embodiments;

[0015] FIG. 5 illustrates an example lighting system, according to some embodiments;

[0016] FIG. 6 illustrates an example hardware arrangement for implementing the above disclosed subject matter, according to some embodiments;

[0017] FIG. 7 shows a block diagram of an example of a system, according to some embodiments; and

[0018] FIG. 8 illustrates an example method of fabricating an illumination device, according to some embodiments.

[0019] To facilitate understanding, identical reference numerals have been used, where possible, to designate identical elements that are common to the figures. The figures are not drawn to scale. For example, the heights and widths of the mesas are not drawn to scale.DETAILED DESCRIPTION

[0020] Before describing several exemplary embodiments of the disclosure, it is to be understood that the disclosure is not limited to the details of construction or process steps set forth in the following description. The disclosure is capable of other embodiments and of being practiced or being carried out in various ways.

[0021] The term "substrate" as used herein according to one or more embodiments refers to a structure, intermediate or final, having a surface, or portion of a surface, upon which a process acts. In addition, reference to a substrate in some embodiments also refers to only a portion of the substrate, unless the context clearly indicates otherwise. Further, reference to depositing on a substrate according to some embodiments includes depositing on a bare substrate or on a substrate with one or more layers, films, features, or materials deposited or formed thereon.

[0022] In one or more embodiments, the "substrate" means any substrate or material surface formed on a substrate upon which film processing is performed during a fabrication process. In exemplary embodiments, a substrate surface on which processing is performed includes materials such as silicon, silicon oxide, silicon on insulator (SOI), strained silicon, amorphous silicon, doped silicon, carbon doped silicon oxides, germanium, gallium arsenide, glass, sapphire, and any other suitable materials such as metals, metal nitrides, Ill-nitrides (e.g., GaN, AIN, InN, and other alloys), metal alloys, and other conductive materials, depending on the application. Substrates include, without limitation, light emitting diode (LED) devices. Substrates in some embodiments are exposed to a pretreatment process to polish, etch, reduce, oxidize, hydroxylate, anneal, UV cure, e-beam cure and / or bake the substrate surface. In addition to film processing directly on the surface of the substrate itself, in some embodiments, any of the film processing steps disclosed is also performed on an underlayer formed on the substrate, and the term "substrate surface" is intended to include such underlayer as the context indicates. Thus, for example, where afilm / layer or partial film / layer has been deposited onto a substrate surface, the exposed surface of the newly deposited film / layer becomes the substrate surface.

[0023] The term "wafer" and "substrate" will be used interchangeably in the instant disclosure. Thus, as used herein, a wafer serves as the substrate for the formation of the LED devices described herein.

[0024] Examples of different light illumination systems and / or light emitting diode (LED) implementations will be described more fully hereinafter with reference to the accompanying drawings. These examples are not mutually exclusive, and features found in one example may be combined with features found in one or more other examples to achieve additional implementations. Accordingly, it will be understood that the examples shown in the accompanying drawings are provided for illustrative purposes only and they are not intended to limit the disclosure in any way. Like numbers refer to like elements throughout.

[0025] Semiconductor light emitting devices or optical power emitting devices, such as devices that emit ultraviolet (UV) or infrared (IR) optical power, are among the most efficient light sources currently available. These devices may include light emitting diodes, resonant cavity light emitting diodes, vertical cavity laser diodes, edge emitting lasers, or the like (hereinafter referred to as "LEDs"). Due to their compact size and lower power requirements, for example, LEDs may be attractive candidates for many different applications. For example, they may be used as light sources (e.g., flashlights and camera flashes) for hand-held battery-powered devices, such as cameras and cell phones. They may also be used, for example, for automotive lighting, heads up display (HUD) lighting, horticultural lighting, street lighting, torch for video, general illumination (e.g., home, shop, office and studio lighting, theater / stage lighting and architectural lighting), augmented reality (AR) lighting, virtual reality (VR) lighting, as back lights for displays, and IR spectroscopy. A single LED may provide light that is less bright than an incandescent light source, and, therefore, multi-junction devices or arrays of LEDs (such as monolithic LED arrays, micro-LED arrays, etc.) may be used for applications where more brightness is desired or required.

[0026] The present disclosure generally relates to the manufacture of red light sources for applications in high power general illumination systems. Embodiments described herein describe LED devices and methods for forming LED devices. Inparticular, the present disclosure describes LED devices and methods to produce LED devices which reduce SRH non-radiative recombination at the sidewall defect sites and, therefore, advantageously improve AllnGaP micro LED performance. The LED devices of one or more embodiments improve micro LED reliability performance and reduce size-dependent effects of AllnGaP micro LEDs.

[0027] One or more embodiments of the disclosure are described with reference to the Figures. In one or more embodiments, to improve AllnGaP microLED EQE the injection current is kept away from the mesa sidewalls at the active region, where there could be extensive defects generated by the mesa fabrication process, such as dry etch.

[0028] FIG. 1 illustrates a process flow diagram of a method according to one or more embodiments. FIG. 2 illustrates a cross-section view of an LED device according to one or more embodiments. FIG. 3A illustrates a cross-section view of an LED device according to one or more embodiments. FIG. 3B illustrates an isometric view of the LED device of one or more embodiments.

[0029] An aspect of the disclosure pertains to a method of manufacturing a LED array. Referring first to FIG. 1 , an LED device is manufactured by, at operation 12, forming a mesa stack on a substrate. At operation 14, the mesa is then treated to form confinement layers. At operation 16, contacts are formed on the mesa to form the LED device.

[0030] Referring to FIG. 2, in one or more embodiments, a semiconductor mesa structure 100 is fabricated to build a light emitting diode (LED). The mesa dimension could be from sub microns to hundreds of microns. The mesa could be circular or square or any other shape. In one or more embodiments, a plurality of epitaxial layers 103 are formed on a substrate 102. The substrate 102 may be any substrate known to one of skill in the art which is configured for use in the formation of LED devices. In one or more embodiments, the substrate 102 comprises one or more of sapphire, silicon carbide, silicon (Si), quartz, magnesium oxide (MgO), zinc oxide (ZnO), spinel, gallium phosphide (GaP), and the like. In one or more embodiments, the substrate 102 is a transparent substrate. In specific embodiments, the substrate 102 comprises sapphire. In one or more embodiments, the substrate 102 is not patterned prior to formation of the LEDs. Thus, in some embodiments, the substrate is 102 notpatterned and can be considered to be flat or substantially flat. In other embodiments, the substrate 102 is a patterned substrate.

[0031] In one or more embodiments, the plurality of epitaxial layers 103 include a first n-type layer 104 formed on the substrate 102, a second n-type layer 106 formed on the first n-type epitaxial layer 104, a third n-type layer 108 formed on the second n- type layer 106, an active region 110 formed on the third n-type layer 108, a first p-type layer 112 formed on the top surface of the active region 110, and a second p-type layer 114 formed on the first p-type layer 112.

[0032] In one or more embodiments, the first n-type layer 104, the second n-type layer 106, and the third n-type layer 108 may comprise any Group lll-V semiconductor material, including binary, ternary, and quaternary alloys of gallium (Ga), aluminum (Al), indium (In), nitrogen (N), and phosphorus (P). Thus, in some embodiments, the first n-type layer 104, the second n-type layer 106, and the third n-type layer 108 comprise aluminum indium gallium phosphide (AllnGaP). Aluminum indium gallium phosphide (AllnGaP) is a semiconductor material that provides a platform for the manufacture of light-emitting diodes of high-brightness red, orange, green and yellow color. AllnGaP may be grown by any suitable means known to the skilled artisan. In some embodiments, AllnGaP may be grown by heteroepitaxy. In one or more embodiments, the first n-type layer 104, the second n-type layer 106, and the third n- type layer 108 are independently doped with n-type dopants, such as silicon (Si) or tellurium (Te). In one or more embodiments, the dopant concentration is in a range of from 1 e17 to 2e19 cm3. In one or more embodiments, the first n-type layer 104 may have a thickness in the range of from 1 pm to 3 pm to ensure a wide process margin for a subsequent etching step used to contact this layer.

[0033] In one or more embodiments, the first p-type layer 112 and the second p- type layer 114. may comprise any Group lll-V semiconductor material, including binary, ternary, and quaternary alloys of gallium (Ga), aluminum (Al), indium (In), nitrogen (N), and phosphorus (P). Thus, in some embodiments, the first p-type layer 112 and the second p-type layer 114 comprise aluminum indium gallium phosphide (AllnGaP). In one or more embodiments, the first p-type layer 112 and the second p- type layer 114 may be independently doped with any suitable p-type dopant known tothe skilled artisan. In one or more embodiments, the first p-type layer 112 and the second p-type layer 114 may independently be doped with magnesium (Mg).

[0034] In one or more embodiments, the layers of material that make up the plurality of epitaxial layers 103, or the mesa, may be deposited by one or more of metalorganic chemical vapor deposition (MOCVD), physical vapor deposition (PVD), organic metal vapor phase epitaxy (OMVPE), liquid phase epitaxy (LPE), hydride vapor phase epitaxy (HVPE), and molecular beam epitaxy (MBE).

[0035] As used herein according to some embodiments, "chemical vapor deposition" refers to a process in which films of materials are deposited from the vapor phase by decomposition of chemicals on a substrate surface. In CVD, a substrate surface is exposed to precursors and / or co-reagents simultaneously or substantially simultaneously. A particular subset of CVD processes commonly used in LED manufacturing use metalorganic precursor chemical and are referred to as MOCVD or metalorganic vapor phase epitaxy (MOVPE). As used herein, "substantially simultaneously" refers to either co-flow or where there is overlap for a majority of exposures of the precursors.

[0036] In one or more embodiments, pLED array 100 is manufactured by placing the substrate in a metalorganic vapor-phase epitaxy (MOVPE) reactor, or an MBE reactor, or a LPE reactor, or a HVPE reactor so that the pLED array layers are grown epitaxially.

[0037] In one or more embodiments, a mesa in FIG. 3A was formed by photolithography patterning on the stack of FIG. 2 and subsequently etch process. First a photo sensitive resist (make more general and add other patterning masking like hardmask) covers the wafer with the epitaxial stack. Secondly, the photo sensitive resist is exposed under UV light or laser using a photo mask or direct writing followed by photo resist developer chemicals to selectively remove photo resist from unwanted areas. A photo resist baking process is used to remove moisture from the remaining photo resist. Finally, an etching process is used to form mesa shape. The etch process could be a dry plasma etch process or a wet etch process.

[0038] Referring to FIG. 1 , and FIGS. 3A and 3B, at operation 14, in one or more embodiments, a mesa sidewall treatment after mesa dry etch is used to reduce damage using processes such as wet etch and low power plasma treatment. In one ormore embodiments, a mesa structure 150 is advantageously fabricated that has semiconductor confinement layers 108B, 1 12B above and below the active region 1 10 with smaller outer dimensions than that of the active region 110 layer itself.

[0039] In one or more embodiments, the third n-type layer 108 is treated to etch the sidewalls 152 such that the n-type confinement layer 108B has an outer dimension that is in a range of from 0.1 pm to 2.0 pm smaller than the active region 110. In one or more embodiments, the treatment on layer 108 could be wet etch or low power plasma treatment.

[0040] In one or more embodiments, the first p-type layer 1 12 is treated to etch the sidewalls 152 such that the p-type confinement layer 112B has an outer dimension that is in a range of from 0.1 pm to 2.0 pm smaller than the active region 110. In one or more embodiments, the treatment on layer 1 12 could be wet etch or low power plasma treatment.

[0041] In one or more embodiments, in the active region layer 1 10, the carrier current flow may be restricted from the mesa sidewalls 152 where non-radiative emission defects reside. The dimension difference between the confinement layers 108B, 112B and the active region layer 1 10 could be from sub-micron to microns, depending on LED epitaxy layers 103 materials and designs.

[0042] In one or more embodiments, after the mesa sidewall treatment, a passivation layer (not illustrated), may be deposited on mesa sidewall using processes including, but not limited to, atomic layer deposition (ALD) with thermal or plasma processes, PECVD, spin-on-glass (SOG). The passivation layer may comprise any suitable material known to the skilled artisan. In one or more embodiments, the passivation layer is selected from one or more of aluminum oxide (AI2O3), silicon oxide (SiC ), aluminum nitride (AIN), titanium oxide (TiC ), and silicon nitride (Si3N4).

[0043] Referring to FIG. 1 and FIGS. 3A through 3B, at operation 16, contacts are formed on the mesa 150. In one or more embodiments, a P-contact layout design is used to maximize spacing between mesa sidewall 152 and P-contact 1 16 edges. In one or more embodiments, any chip size can be used. In specific embodiments, the LED is most effective for microLEDs having a mesa size less than 50 pm. In one or more embodiments, the p-contact 1 16 may comprise any suitable contact materialknown to the skilled artisan. In some embodiments, the p-contact 116 comprises one or more of aluminum (Al), gold (Au), zinc (Zn), platinum (Pt), silver (Ag), zinc oxide (ZnO), indium tin oxide (ITO), and the like.

[0044] In one or more embodiments, an n-contact 118 is formed adjacent to the second n-type layer 106. The n-contact 118 may comprise any suitable material known to the skilled artisan. In some embodiments, the n-contact 118 comprises one or more of copper (Cu), aluminum (Al), palladium (Pd), gold (Au), germanium (Ge), nickel (Ni), titanium (Ti) and the like.

[0045] FIG. 4 illustrates an example of a general device in accordance with some embodiments. The device 600 may be a mobile device such as a laptop computer (PC), a tablet PC, a smart phone, or an augmented reality (AR) / virtual reality (VR), or an automotive device, for example. Various elements may be provided on the backplane indicated above, while other elements may be local or remote. Examples, as described herein, may include, or may operate on, logic or a number of components, modules, or mechanisms.

[0046] Modules and components are tangible entities (e.g., hardware) capable of performing specified operations and may be configured or arranged in a certain manner. In an example, circuits may be arranged (e.g., internally or with respect to external entities such as other circuits) in a specified manner as a module. In an example, the whole or part of one or more computer systems (e.g., a standalone, client or server computer system) or one or more hardware processors may be configured by firmware or software (e.g., instructions, an application portion, or an application) as a module that operates to perform specified operations. In an example, the software may reside on a machine readable medium. In an example, the software, when executed by the underlying hardware of the module, causes the hardware to perform the specified operations.

[0047] Accordingly, the term “module” (and “component”) is understood to encompass a tangible entity, be that an entity that is physically constructed, specifically configured (e.g., hardwired), or temporarily (e.g., transitorily) configured (e.g., programmed) to operate in a specified manner or to perform part or all of any operation described herein. Considering examples in which modules are temporarily configured, each of the modules need not be instantiated at any one moment intime. For example, where the modules comprise a general-purpose hardware processor configured using software, the general-purpose hardware processor may be configured as respective different modules at different times. Software may accordingly configure a hardware processor, for example, to constitute a particular module at one instance of time and to constitute a different module at a different instance of time.

[0048] The electronic device 600 may include a hardware processor (or equivalently processing circuitry) 602 (e.g., a central processing unit (CPU), a GPU, a hardware processor core, or any combination thereof), a memory 604 (which may include main and static memory), some or all of which may communicate with each other via an interlink (e.g., bus) 608. The memory 604 may contain any or all removable storage and non-removable storage, volatile memory, or non-volatile memory. The electronic device 600 may further include a display / light source 610 such as the LEDs described above, or a video display, an alphanumeric input device 612 (e.g., a keyboard), and a user interface (Ul) navigation device 614 (e.g., a mouse). In an example, the display / light source 610, input device 612 and Ul navigation device 614 may be a touch screen display. The electronic device 600 may additionally include a storage device (e.g., drive unit) 616, a signal generation device 618 (e.g., a speaker), a network interface device 620, one or more cameras 628, and one or more sensors 630, such as a global positioning system (GPS) sensor, compass, accelerometer, or other sensor such as those described herein. The electronic device 600 may further include an output controller, such as a serial (e.g., universal serial bus (USB), parallel, or other wired or wireless (e.g., infrared (IR), near field communication (NFC), etc.) connection to communicate or control one or more peripheral devices (e.g., a printer, card reader, etc.).

[0049] The storage device 616 may include a non-transitory machine readable medium 622 (hereinafter simply referred to as machine readable medium) on which is stored one or more sets of data structures or instructions 624 (e.g., software) embodying or utilized by any one or more of the techniques or functions described herein. The instructions 624 may also reside, completely or at least partially, within the memory 604 and / or within the hardware processor 602 during execution thereof by the electronic device 600. While the machine readable medium 622 is illustratedas a single medium, the term "machine readable medium" may include a single medium or multiple media (e.g., a centralized or distributed database, and / or associated caches and servers) configured to store the one or more instructions 624.

[0050] The term “machine readable medium” may include any medium that is capable of storing, encoding, or carrying instructions for execution by the electronic device 600 and that cause the electronic device 600 to perform any one or more of the techniques of the present disclosure, or that is capable of storing, encoding, or carrying data structures used by or associated with such instructions. Non-limiting machine-readable medium examples may include solid-state memories, and optical and magnetic media. Specific examples of machine-readable media may include nonvolatile memory, such as semiconductor memory devices (e.g., Electrically Programmable Read-Only Memory (EPROM), Electrically Erasable Programmable Read-Only Memory (EEPROM)) and flash memory devices; magnetic disks, such as internal hard disks and removable disks; magneto-optical disks; Random Access Memory (RAM); and CD-ROM and DVD-ROM disks.

[0051] The instructions 624 may further be transmitted or received over a communications network using a transmission medium 626 via the network interface device 620 utilizing any one of a number of wireless local area network (WLAN) transfer protocols or a SPI or CAN bus. Example communication networks may include a local area network (LAN), a wide area network (WAN), a packet data network (e.g., the Internet), mobile telephone networks (e.g., cellular networks), Plain Old Telephone (POTS) networks, and wireless data networks. Communications over the networks may include one or more different protocols, such as Institute of Electrical and Electronics Engineers (IEEE) 802.11 family of standards known as WiFi, IEEE 802.16 family of standards known as WiMax, IEEE 802.16.4 family of standards, a Long Term Evolution (LTE) family of standards, a Universal Mobile Telecommunications System (UMTS) family of standards, peer-to-peer (P2P) networks, a next generation (NG) / 6thgeneration (6G) standards among others. In an example, the network interface device 620 may include one or more physical jacks (e.g., Ethernet, coaxial, or phone jacks) or one or more antennas to connect to the transmission medium 626.

[0052] Note that the term “circuitry” as used herein refers to, is part of, or includes hardware components such as an electronic circuit, a logic circuit, a processor (shared, dedicated, or group) and / or memory (shared, dedicated, or group), an Application Specific Integrated Circuit (ASIC), a field-programmable device (FPD) (e.g., a field-programmable gate array (FPGA), a programmable logic device (PLD), a complex PLD (CPLD), a high-capacity PLD (HCPLD), a structured ASIC, or a programmable SoC), digital signal processors (DSPs), etc., that are configured to provide the described functionality. In some embodiments, the circuitry may execute one or more software or firmware programs to provide at least some of the described functionality. The term “circuitry” may also refer to a combination of one or more hardware elements (or a combination of circuits used in an electrical or electronic system) with the program code used to carry out the functionality of that program code. In these embodiments, the combination of hardware elements and program code may be referred to as a particular type of circuitry.

[0053] The term “processor circuitry” or “processor” as used herein thus refers to, is part of, or includes circuitry capable of sequentially and automatically carrying out a sequence of arithmetic or logical operations, or recording, storing, and / or transferring digital data. The term “processor circuitry” or “processor” may refer to one or more application processors, one or more baseband processors, a physical central processing unit (CPU), a single- or multi-core processor, and / or any other device capable of executing or otherwise operating computer-executable instructions, such as program code, software modules, and / or functional processes.

[0054] The camera 628 may sense light at least the wavelength or wavelengths emitted by the LEDs. The camera 628 may include optics (e.g., at least one camera lens) that are able to collect reflected light of illumination that is reflected from and / or emitted by an illuminated region. The camera lens may direct the reflected light onto a multi-pixel sensor (also referred to as a light sensor) to form an image of on the multi-pixel sensor.

[0055] The processor 602 may control and drive the LEDs via one or more drivers. For example, the processor 602 may optionally control one or more LEDs in LED arrays independent of another one or more LEDs in the LED arrays, so as to illuminate an area in a specified manner.

[0056] In addition, the sensors 630 may be incorporated in the camera 628 and / or the light source 610. The sensors 630 may sense visible and / or infrared light and may further sense the ambient light and / or variations / flicker in the ambient light in addition to reception of the reflected light from the LEDs. The sensors may have one or more segments (that are able to sense the same wavelength / range of wavelengths or different wavelength / range of wavelengths), similar to the LED arrays.

[0057] FIG. 5 illustrates an example lighting system, according to some embodiments. As above, some of the elements shown in the lighting system 700 may not be present, while other additional elements may be disposed in the lighting system 700. The lighting system 700 may include a controller 702 that controls illumination using a pixel array 710 that contains multiple individual pixels 712.

[0058] In some embodiments, some or all of the components described as the controller 702 may be disposed on a backplane such as, for example, a complementary metal oxide semiconductor (CMOS) backplane. The controller 702 may be coupled to or include one or more processors 704. The processor 704 may receive image data (in frames) via an interface and may process the image data to control a generator 706a, for example, controlling analog signals or PWM duty cycles and / or turn-on times for causing the lighting system 700 to produce the images indicated by the image data.

[0059] The controller 702 may further include a frame buffer 708. The frame buffer 708 may store one or more images prior to the one or more processors 704 and store the indications for implementation by the one or more processors 704.

[0060] The generator 706a may be controlled by the processor 704 and may produce driving signals in accordance with the indications. The generator 706a may be connected to a driver 706b to drive the pixel array 710 so that the pixels 712 provide desired intensities of light.

[0061] Each pixel 712 may include one or more LEDs 714. The LEDs 714 may be different colors and may be controlled individually or in groups. As shown, the pixel 712 may include, for each pixel 712 or LED 714, a PWM switch, and a current source. The pixel 712 may be driven by the driver 706b. The signal from the generator 706a may cause the switch to open and close in accordance with the value of the signal. The signal corresponding to the intensities of light may cause the current source toproduce a current flow to cause the pixels 712 to produce the corresponding intensities of light.

[0062] The lighting system 700 may further include a power supply 720. In some embodiments, the power supply 720 may be a battery that produces power for the controller 702.

[0063] FIG. 6 illustrates an example hardware arrangement for implementing the above disclosed subject matter, according to some embodiments. In particular, the hardware arrangement 800 may include an LED die 802 that contains the LED array(s) and a backplane, such as a CMOS backplane 804. The LED die 802 may be coupled to the CMOS backplane 804 by one or more interconnects 810, where the interconnects 810 may provide for transmission of signals between the LED die 802 and the CMOS backplane 804. The interconnects 810 may comprise one or more solder bump joints, one or more copper pillar bump joints, other types of interconnects known in the art, or some combination thereof.

[0064] The LED die 802 may include circuitry to implement the LED array described above. In particular, the LED die 802 may include a plurality of LEDs. The LED die 802 may include a shared active layer and a shared substrate for the LED array, and thereby the LED array may be a monolithic LED array. Each LED of the LED array may include an individual segmented active layer and / or substrate. In some embodiments, the LED die 802 may further include switches and current sources to drive the LED array as described above. In other embodiments, the switches and the current sources may be included in the CMOS backplane 804. The LEDs may be micro-LEDs or LEDs larger than micro-LEDs.

[0065] The CMOS backplane 804 may include circuitry to implement the control module. The CMOS backplane 804 may utilize the interconnects 810 to provide the LED array with the driving signals and the signals for the intensity for causing the LED array to produce light in accordance with the signals and the intensity.

[0066] The hardware arrangement 800 may further include a PCB 806. The PCB 806 may include circuitry to implement various functionality described herein. The PCB 806 may be coupled to the CMOS backplane 804. For example, the PCB 806 may be coupled to the CMOS backplane 804 via one or more wire bonds 812. ThePCB 806 and the CMOS backplane 804 may exchange image data, power, and / or feedback via the coupling, among other signals.

[0067] As shown, the LEDs and circuitry supporting the LED array can be packaged and include a submount or printed circuit board for powering and controlling light production by the LEDs. The PCB supporting the LED array may include electrical vias, heat sinks, ground planes, electrical traces, and flip chip or other mounting systems. The submount or PCB may be formed of any suitable material, such as ceramic, silicon, aluminum, etc. If the submount material is conductive, an insulating layer may be formed over the substrate material, and a metal electrode pattern formed over the insulating layer for contact with the micro-LED array. The submount can act as a mechanical support, providing an electrical interface between electrodes on the LED array and a power supply, and also provide heat sink functionality.

[0068] In general, a variety of applications may be supported by LED arrays. Such applications may include stand-alone applications to provide general illumination (e.g., within or external to a room or vehicle) or to provide specific images. In addition to devices such as a luminaire, projector, mobile device, the system may be used to provide AR and VR-based applications. Visualization systems, such as VR and AR systems, are becoming increasingly more common across numerous fields such as entertainment, education, medicine, and business. Various types of devices may be used to provide AR / VR to users, including headsets, glasses, and projectors. Such an AR / VR system may include components similar to those described above: the micro- LED array, a display or screen (which may include touchscreen elements), a micro- LED array controller, sensors, and a controller, among others. The AR / VR components can be disposed in a single structure, or one or more of the components shown can be mounted separately and connected via wired or wireless communication. Power and user data may be provided to the controller. The user data input can include information provided by audio instructions, haptic feedback, eye or pupil positioning, or connected keyboard, mouse, or game controller. The sensors may include cameras, depth sensors, audio sensors, accelerometers, two or three axis gyroscopes and other types of motion and / or environmental / wearer sensors that provide the user input data. Other sensors can include but are not limited to airpressure, stress sensors, temperature sensors, or any other suitable sensors for local or remote environmental monitoring. In some embodiments, the control input can include detected touch or taps, gestural input, or control based on headset or display position. As another example, based on the one or more measurement signals from one or more gyroscope or position sensors that measure translation or rotational movement, an estimated position of the AR / VR system relative to an initial position can be determined.

[0069] In some embodiments, the controller may control individual micro-LEDs or one or more groups of LEDs to display content (AR / VR and / or non-AR / VR) to the user while controlling other LEDs and sensors used in eye tracking to adjust the content displayed. Content display LEDs may be designed to emit light within the visible band (approximately 400 nm to 780 nm) while LEDs used for tracking may be designed to emit light in the IR band (approximately 780 nm to 2,200 nm). In some embodiments, the tracking LEDs and content LEDs may be simultaneously active. In some embodiments, the tracking LEDs may be controlled to emit tracking light during a time period that content LEDs are deactivated and are thus not displaying content to the user. The AR / VR system can incorporate optics, such as those described above, and / or an AR / VR display, for example to couple light emitted by LED array onto the AR / VR display.

[0070] In some embodiments, the AR / VR controller may use data from the sensors to integrate measurement signals received from the accelerometers over time to estimate a velocity vector and integrate the velocity vector over time to determine an estimated position of a reference point for the AR / VR system. In other embodiments, the reference point used to describe the position of the AR / VR system can be based on depth sensor, camera positioning views, or optical field flow. Based on changes in position, orientation, or movement of the AR / VR system, the system controller can send images or instructions to the light emitting array controller. Changes or modifications to the images or instructions can also be made by user data input, or automated data input.

[0071] In general, in a VR system, a display can present to a user a view of a scene, such as a three-dimensional scene. The user can move within the scene, such as by repositioning the user’s head or by walking. The VR system can detect theuser’s movement and alter the view of the scene to account for the movement. For example, as a user rotates the user’s head, the system can present views of the scene that vary in view directions to match the user’s gaze. In this manner, the VR system can simulate a user’s presence in a three-dimensional scene. Further, a VR system can receive tactile sensory input, such as from wearable position sensors, and can optionally provide tactile feedback to the user.

[0072] In an AR system, on the other hand, the display can incorporate elements from the user’s surroundings into the view of the scene. For example, the AR system can add textual captions and / or visual elements to a view of the user’s surroundings. For example, a retailer can use an AR system to show a user what a piece of furniture would look like in a room of the user’s home, by incorporating a visualization of the piece of furniture over a captured image of the user’s surroundings. As the user moves around the user’s room, the visualization accounts for the user’s motion and alters the visualization of the furniture in a manner consistent with the motion. For example, the AR system can position a virtual chair in a room. The user can stand in the room on a front side of the virtual chair location to view the front side of the chair. The user can move in the room to an area behind the virtual chair location to view a back side of the chair. In this manner, the AR system can add elements to a dynamic view of the user’s surroundings.

[0073] FIG. 7 shows a block diagram of an example of a system, according to some embodiments. The system 900 may provide AR / VR functionality using microLEDs. The system 900 can include a wearable housing 912, such as a headset or goggles. The housing 912 can mechanically support and house the elements detailed below. In some examples, one or more of the elements detailed below can be included in one or more additional housings that can be separate from the wearable housing 912 and couplable to the wearable housing 912 wirelessly and / or via a wired connection. For example, a separate housing can reduce the weight of wearable goggles, such as by including batteries, radios, and other elements. The housing 912 can include one or more batteries 914, which can electrically power any or all of the elements detailed below. The housing 912 can include circuitry that can electrically couple to an external power supply, such as a wall outlet, to recharge thebatteries 914. The housing 912 can include one or more radios 916 to communicate wirelessly with a server or network via a suitable protocol, such as WiFi.

[0074] The system 900 can include one or more sensors 918, such as optical sensors, audio sensors, tactile sensors, thermal sensors, gyroscopic sensors, time-of- flight sensors, triangulation-based sensors, and others. In some examples, one or more of the sensors can sense a location, a position, and / or an orientation of a user. In some examples, one or more of the sensors 918 can produce a sensor signal in response to the sensed location, position, and / or orientation. The sensor signal can include sensor data that corresponds to a sensed location, position, and / or orientation. For example, the sensor data can include a depth map of the surroundings. In some examples, such as for an AR system, one or more of the sensors 918 can capture a real-time video image of the surroundings proximate a user.

[0075] The system 900 can include one or more video generation processors 920. The one or more video generation processors 920 can receive scene data that represents a three-dimensional scene, such as a set of position coordinates for objects in the scene or a depth map of the scene. This data may be received from a server and / or a storage medium. The one or more video generation processors 920 can receive one or more sensor signals from the one or more sensors 918. In response to the scene data, which represents the surroundings, and at least one sensor signal, which represents the location and / or orientation of the user with respect to the surroundings, the one or more video generation processors 920 can generate at least one video signal that corresponds to a view of the scene. In some examples, the one or more video generation processors 920 can generate two video signals, one for each eye of the user, that represent a view of the scene from a point of view of the left eye and the right eye of the user, respectively. In some examples, the one or more video generation processors 920 can generate more than two video signals and combine the video signals to provide one video signal for both eyes, two video signals for the two eyes, or other combinations.

[0076] The system 900 can include one or more light sources 922 that can provide light for a display of the system 900. Suitable light sources 922 can include the microLEDs above, for example. The one or more light sources 922 can include lightproducing elements having different colors or wavelengths. For example, a lightsource can include a red light-emitting diode that can emit red light, a green lightemitting diode that can emit green light, and a blue light-emitting diode that can emit blue right. The red, green, and blue light combine in specified ratios to produce any suitable color that is visually perceptible in a visible portion of the electromagnetic spectrum.

[0077] The system 900 can include one or more modulators 924. The modulators 924 can be implemented in one of at least two configurations. In a first configuration, the modulators 924 can include circuitry that can modulate the light sources 922 directly. For example, the light sources 922 can include an array of light-emitting diodes, and the modulators 924 can directly modulate the electrical power, electrical voltage, and / or electrical current directed to each light-emitting diode in the array to form modulated light. The modulation can be performed in an analog manner and / or a digital manner. In some examples, the light sources 922 can include an array of red light-emitting diodes, an array of green light-emitting diodes, and an array of blue lightemitting diodes, and the modulators 924 can directly modulate the red light-emitting diodes, the green light-emitting diodes, and the blue light-emitting diodes to form the modulated light to produce a specified image.

[0078] In a second configuration, the modulators 924 can include a modulation panel, such as a liquid crystal panel. The light sources 922 can produce uniform illumination, or nearly uniform illumination, to illuminate the modulation panel. The modulation panel can include pixels. Each pixel can selectively attenuate a respective portion of the modulation panel area in response to an electrical modulation signal to form the modulated light. In some examples, the modulators 924 can include multiple modulation panels that can modulate different colors of light. For example, the modulators 924 can include a red modulation panel that can attenuate red light from a red light source such as a red light-emitting diode, a green modulation panel that can attenuate green light from a green light source such as a green light-emitting diode, and a blue modulation panel that can attenuate blue light from a blue light source such as a blue light-emitting diode.

[0079] In some examples of the second configuration, the modulators 924 can receive uniform white light or nearly uniform white light from a white light source, such as a white-light light-emitting diode. The modulation panel can include wavelength-selective filters on each pixel of the modulation panel. The panel pixels can be arranged in groups (such as groups of three or four), where each group can form a pixel of a color image. For example, each group can include a panel pixel with a red color filter, a panel pixel with a green color filter, and a panel pixel with a blue color filter. Other suitable configurations can also be used.

[0080] The system 900 can include one or more modulation processors 926, which can receive a video signal, such as from the one or more video generation processors 920, and, in response, can produce an electrical modulation signal. For configurations in which the modulators 924 directly modulate the light sources 922, the electrical modulation signal can drive the modulators 924. For configurations in which the modulators 924 include a modulation panel, the electrical modulation signal can drive the modulation panel.

[0081] The system 900 can include one or more beam combiners 928 (also known as beam splitters), which can combine light beams of different colors to form a single multi-color beam. For configurations in which the light sources 922 can include multiple light-emitting diodes of different colors, the system 900 can include one or more wavelength-sensitive (e.g., dichroic) beam combiners 928 that can combine the light of different colors to form a single multi-color beam.

[0082] The system 900 can direct the modulated light toward the eyes of the viewer in one of at least two configurations. In a first configuration, the system 900 can function as a projector, and can include suitable projection optics 930 that can project the modulated light onto one or more screens 932. The screens 932 can be located a suitable distance from an eye of the user. The system 900 can optionally include one or more lenses 934 that can locate a virtual image of a screen 932 at a suitable distance from the eye, such as a close-focus distance, such as 500 mm, 750 mm, or another suitable distance. In some examples, the system 900 can include a single screen 932, such that the modulated light can be directed toward both eyes of the user. In some examples, the system 900 can include two screens 932, such that the modulated light from each screen 932 can be directed toward a respective eye of the user. In some examples, the system 900 can include more than two screens 932. In a second configuration, the system 900 can direct the modulated light directly into one or both eyes of a viewer. For example, the projection optics 930 can form animage on a retina of an eye of the user, or an image on each retina of the two eyes of the user.

[0083] For some configurations of AR systems, the system 900 can include at least a partially transparent display, such that a user can view the user’s surroundings through the display. For such configurations, the AR system can produce modulated light that corresponds to the augmentation of the surroundings, rather than the surroundings itself. For example, in the example of a retailer showing a chair, the AR system can direct modulated light, corresponding to the chair but not the rest of the room, toward a screen or toward an eye of a user.

[0084] FIG. 8 illustrates an example method of fabricating an illumination device, according to some embodiments. Not all of the operations may be undertaken in the method 1000, and / or additional operations may be present. The operations may occur in a different order from that indicated in FIG. 12.

[0085] At operation 1002, a temporary substrate is attached to an initial structure that includes a substrate and epitaxial layer (including n-type semiconductor layer, p- type semiconductor layer and active region). If a TCO layer may have been deposited on the initial structure, the temporary substrate is attached to the TCO layer.

[0086] At operation 1004, the substrate is etched or otherwise removed, and the n- type semiconductor layer is etched such that the remaining epitaxial layer has a thickness significantly less than the thickness of the initial structure.

[0087] At operation 1006, the epitaxial layer is formed into trapezoidal pixels via etching.

[0088] At operation 1008, an oxide layer is deposited on the pixels, which is then etched to expose the n-type semiconductor layer at the top of the pixel, as well as the temporary substrate or TCO layer.

[0089] At operation 1010, a metal seed layer and metal plating are deposited on the oxide layer and openings and etched to electrically isolate portions of the metal plating. Another oxide layer is deposited on the metal plating, openings are etched to expose portions of the metal plating, and a bonding layer is deposited and fabricated on the openings to provide bonding pads that contact exposed portions of the metal plating.

[0090] At operation 1012, the resulting structure is hybridized by attaching a monolithic structure to the bonding pads.

[0091] At operation 1014, the temporary substrate was removed from the hybridized structure.

[0092] At operation 1016, a periodic nanostructure is patterned on the TCO layer, which may be deposited after removal of the temporary substrate if not already present.

[0093] While only certain features of the system and method have been illustrated and described herein, many modifications and changes will occur to those skilled in the art. It is, therefore, to be understood that the appended claims are intended to cover all such modifications and changes. Method operations may be performed substantially simultaneously or in a different order.EMBODIMENTS

[0094] Various embodiments are listed below. It will be understood that the embodiments listed below may be combined with all aspects and other embodiments in accordance with the scope of the invention.

[0095] Embodiment (a). A light emitting diode comprising: an epitaxial stack on a substrate, the epitaxial stack comprising at least one n-type layer, at least one p-type layer, a first confinement layer, a second confinement layer, and an active region having an active region width, wherein the first confinement layer and the second confinement layer independently have a width less than the active region width; a p- type contact on the epitaxial stack; and an n-type contact adjacent to the at least one n-type layer.

[0096] Embodiment (b). The light emitting diode of embodiment (a), wherein the width of the first confinement layer is in a range of from 1 pm to 50 pm.

[0097] Embodiment (c). The light emitting diode of embodiment (a) to embodiment(b), wherein the width of the second conferment layer is in a range of from 1 pm to 50 pm.

[0098] Embodiment (d). The light emitting diode of embodiment (a) to embodiment(c), wherein the active region width of the second conferment layer is in a range of from 2 pm to 55 pm.

[0099] Embodiment (e). The light emitting diode of embodiment (a) to embodiment(d), wherein the at least one n-type layer comprises aluminum indium gallium phosphorus (AllnGaP).

[0100] Embodiment (f). The light emitting diode of embodiment (a) to embodiment(e), wherein the at least one n-type layer is doped with one or more of silicon (Si) or tellurium (Te).

[0101] Embodiment (g). The light emitting diode of embodiment (a) to embodiment(f), wherein the at least one p-type layer comprises aluminum indium gallium phosphorus (AllnGaP).

[0102] Embodiment (h). The light emitting diode embodiment (a) to embodiment(g), wherein the at least one p-type layer is doped with magnesium (Mg) or carbon (C).

[0103] Embodiment (i). A light emitting diode (LED) array comprising: a plurality of mesas defining pixels having sidewalls, each of the mesas comprising: an epitaxial stack on a substrate, the epitaxial stack comprising a first n-type layer on the substrate, a second n-type layer on the first n-type layer, an n-type confinement layer on the second n-type layer, an active region having an active region width on the n- type confinement layer, a p-type confinement layer on the active region, a second p- type layer on the p-type confinement layer, wherein the n-type confinement layer and the p-type confinement layer independently have a width less than the active region width; a p-type contact on the epitaxial stack; and an n-type contact adjacent to the second n-type layer on the first n-type layer.

[0104] Embodiment (j). The light emitting diode (LED) array of embodiment (i), wherein the width of the first confinement layer is in a range of from 1 pm to 50 pm.

[0105] Embodiment (k). The light emitting diode (LED) array of embodiment (i) to embodiment (j), wherein the width of the second conferment layer is in a range of from 1 pm to 50 pm.

[0106] Embodiment (I). The light emitting diode (LED) array of embodiment (i) to embodiment (k), wherein the active region width of the second conferment layer is in a range of from 2 pm to 55 pm.

[0107] Embodiment (m). The light emitting diode (LED) array of embodiment (i) to embodiment (I), wherein the first n-type layer, the second n-type layer, and the n-typeconfinement layer independently comprise aluminum indium gallium phosphorus (AllnGaP).

[0108] Embodiment (n). The light emitting diode (LED) array of embodiment (i) to embodiment (m), wherein the one or more of the first n-type layer, the second n-type layer, and the n-type confinement layer are doped with one or more of silicon (Si) or tellurium (Te).

[0109] Embodiment (o). The light emitting diode (LED) array of embodiment (i) to embodiment (n), wherein the p-type confinement layer and the second p-type layer independently comprise aluminum indium gallium phosphorus (AllnGaP).

[0110] Embodiment (p). The light emitting diode (LED) array of embodiment (i) to embodiment (o), wherein one or more of the p-type confinement layer and the second p-type layer are doped with magnesium (Mg) or carbon (C).

[0111] Embodiment (q). A display comprising the light emitting diode (LED) array of embodiment (i) to embodiment (p) affixed to a device substrate by anode metallization bumps.

[0112] Embodiment (r). The display of embodiment (q), further comprising a gallium arsenide (GaAs) substrate on which the epitaxial layers were grown.

[0113] Embodiment (s). The display of embodiment (q) to embodiment (r), wherein the pixels emit a single color.

[0114] Embodiment (t). The display of embodiment (q) to embodiment (s), wherein the pixels emit a red color.

[0115] Embodiment (u). The display of claim embodiment (q) to embodiment (t) comprising: light emitting diodes (LEDs) having at least one characteristic dimension of less than or equal to 500 micrometers, the character dimension being selected from the group consisting of: height, width, depth, thickness, and combinations thereof.

[0116] Embodiment (v) A method of manufacturing a light emitting diode (LED) device, the method comprising: growing a plurality of epitaxial layers including at least one n-type layer, an active region having an active region width, and at least one p- type layer on a substrate to form a mesa having sidewalls; treating the sidewalls of the mesa to form an n-type confinement layer and a p-type confinement layer, wherein the n-type confinement layer and the p-type confinement layer independently have a widthless than the active region width; forming a p-contact on the at least one p-type layer; and forming an n-contact adjacent to the at least one n-type layer.

[0117] The use of the terms "a" and "an" and "the" and similar referents in the context of describing the materials and methods discussed herein (especially in the context of the following claims) are to be construed to cover both the singular and the plural, unless otherwise indicated herein or clearly contradicted by context. Recitation of ranges of values herein are merely intended to serve as a shorthand method of referring individually to each separate value falling within the range, unless otherwise indicated herein, and each separate value is incorporated into the specification as if it were individually recited herein. All methods described herein can be performed in any suitable order unless otherwise indicated herein or otherwise clearly contradicted by context. The use of any and all examples, or exemplary language (e.g., "such as") provided herein, is intended merely to better illuminate the materials and methods and does not pose a limitation on the scope unless otherwise claimed. No language in the specification should be construed as indicating any non-claimed element as essential to the practice of the disclosed materials and methods.

[0118] Reference throughout this specification to the terms first, second, third, etc. may be used herein to describe various elements, and these elements should not be limited by these terms. These terms may be used to distinguish one element from another.

[0119] Reference throughout this specification to a layer, region, or substrate as being "on" or extending "onto" another element, means that it may be directly on or extend directly onto the other element or intervening elements may also be present. When an element is referred to as being "directly on" or extending "directly onto" another element, there may be no intervening elements present. Furthermore, when an element is referred to as being "connected" or "coupled" to another element, it may be directly connected or coupled to the other element and / or connected or coupled to the other element via one or more intervening elements. When an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements present between the element and the other element. It will be understood that these terms are intended to encompass different orientations of the element in addition to any orientation depicted in the figures.

[0120] Relative terms such as "below," "above," "upper,", "lower," "horizontal" or "vertical" may be used herein to describe a relationship of one element, layer, or region to another element, layer, or region as illustrated in the figures. It will be understood that these terms are intended to encompass different orientations of the device in addition to the orientation depicted in the figures.

[0121] Reference throughout this specification to "one embodiment," "certain embodiments," "one or more embodiments" or "an embodiment" means that a particular feature, structure, material, or characteristic described in connection with the embodiment is included in at least one embodiment of the disclosure. Thus, the appearances of the phrases such as "in one or more embodiments," "in certain embodiments," "in one embodiment" or "in an embodiment" in various places throughout this specification are not necessarily referring to the same embodiment of the disclosure. In one or more embodiments, the particular features, structures, materials, or characteristics are combined in any suitable manner.

[0122] Although the disclosure herein has been described with reference to particular embodiments, it is to be understood that these embodiments are merely illustrative of the principles and applications of the present disclosure. It will be apparent to those skilled in the art that various modifications and variations can be made to the method and apparatus of the present disclosure without departing from the spirit and scope of the disclosure. Thus, it is intended that the present disclosure include modifications and variations that are within the scope of the appended claims and their equivalents.

Claims

What is claimed is:1 . A light emitting diode comprising: an epitaxial stack on a substrate, the epitaxial stack comprising at least one n-type layer, at least one p-type layer, a first confinement layer, a second confinement layer, and an active region having an active region width, wherein the first confinement layer and the second confinement layer independently have a width less than the active region width; a p-type contact on the epitaxial stack; and an n-type contact adjacent to the at least one n-type layer.

2. The light emitting diode of claim 1 , wherein the width of the first confinement layer is in a range of from 1 pm to 50 pm.

3. The light emitting diode of claim 1 , wherein the width of the second confinement layer is in a range of from 1 pm to 50 pm.

4. The light emitting diode of claim 1 , wherein the active region width of the second confinement layer is in a range of from 2 pm to 55 pm.

5. The light emitting diode of claim 1 , wherein the at least one n-type layer comprises aluminum indium gallium phosphorus (AllnGaP) and is optionally doped with one or more of silicon (Si) or tellurium (Te).

6. The light emitting diode of claim 1 , wherein the at least one p-type layer comprises aluminum indium gallium phosphorus (AllnGaP) and is optionally doped with magnesium (Mg) or carbon (C).

7. A light emitting diode (LED) array comprising: a plurality of mesas defining pixels having sidewalls, each of the mesas comprising: an epitaxial stack on a substrate, the epitaxial stack comprising a first n- type layer on the substrate, a second n-type layer on the first n-type layer, an n- type confinement layer on the second n-type layer, an active region having anactive region width on the n-type confinement layer, a p-type confinement layer on the active region, a second p-type layer on the p-type confinement layer, wherein the n-type confinement layer and the p-type confinement layer independently have a width less than the active region width; a p-type contact on the epitaxial stack; and an n-type contact adjacent to the second n-type layer on the first n-type layer.

8. The light emitting diode (LED) array of claim 7, wherein the width of the n-type confinement layer is in a range of from 1 pm to 50 pm.

9. The light emitting diode (LED) array of claim 7, wherein the width of the p-type confinement layer is in a range of from 1 pm to 50 pm.

10. The light emitting diode (LED) array of claim 7, wherein the active region width of the second confinement layer is in a range of from 2 pm to 55 pm.11 . The light emitting diode (LED) array of claim 7, wherein the first n-type layer, the second n-type layer, and the n-type confinement layer independently comprise aluminum indium gallium phosphorus (AllnGaP).

12. The light emitting diode (LED) array of claim 11 , wherein the one or more of the first n-type layer, the second n-type layer, and the n-type confinement layer are independently doped with one or more of silicon (Si) or tellurium (Te).

13. The light emitting diode (LED) array of claim 7, wherein the p-type confinement layer and the second p-type layer independently comprise aluminum indium gallium phosphorus (AllnGaP).

14. The light emitting diode (LED) array of claim 13, wherein one or more of the p- type confinement layer and the second p-type layer are doped with magnesium (Mg) or carbon (C).

15. A display comprising the light emitting diode (LED) array of claim 7 affixed to a device substrate by anode metallization bumps.

16. The display of claim 15, further comprising a gallium arsenide (GaAs) substrate on which the epitaxial stack is grown.

17. The display of claim 15, wherein the pixels emit a single color.

18. The display of claim 15, wherein the pixels emit a red color.

19. The display of claim 15 comprising: light emitting diodes (LEDs) having at least one characteristic dimension of less than or equal to 500 micrometers, the character dimension being selected from the group consisting of: height, width, depth, thickness, and combinations thereof.

20. A method of manufacturing a light emitting diode (LED) device, the method comprising: growing a plurality of epitaxial layers including at least one n-type layer, an active region having an active region width, and at least one p-type layer on a substrate to form a mesa having sidewalls; treating the sidewalls of the mesa to form an n-type confinement layer and a p-type confinement layer, wherein the n-type confinement layer and the p-type confinement layer independently have a width less than the active region width; forming a p-contact on the at least one p-type layer; and forming an n-contact adjacent to the at least one n-type layer.

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