Photonic integrated circuit chip and silicon photonics integrated platform

Abstract

Disclosed in the present invention are a photonic integrated circuit chip and a silicon photonics integrated platform, aimed at implementing efficient coupling with common single-mode optical fibers by providing a specific waveguide structure on the photonic integrated circuit chip, without introducing a suspended structure, so that the overall structure has high mechanical stability, reliability tests for photonic integrated circuit chips under high temperature and high humidity conditions can be passed, and processes such as reflow soldering and through-silicon vias are feasible.

Description

Photonic integrated circuit chips and silicon photonic integration platforms

[0001] This application claims priority to the Chinese patent application filed with the China Patent Office on September 8, 2023, with application number 202311155520.5 and invention name “Photonic Integrated Circuit Chip and Silicon Photonic Integration Platform”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present invention relates to the field of optical communication technology, and in particular to a photonic integrated circuit chip and a silicon photonic integrated platform. Background Art

[0003] In recent years, photonic integrated circuit chips have effectively reduced the cost and power consumption of optical communication modules and are a key technology for achieving optical interconnection. The mode field diameter of a typical single-mode silicon optical waveguide is on the order of hundreds of nanometers, while the mode field diameter (MFD) of ordinary single-mode optical fibers required for coupling and alignment with photonic integrated circuit chips (such as silicon photonic chips) is 9-10μm. This significant mode field mismatch between the two makes direct coupling with a narrow alignment tolerance and results in significant optical coupling losses. Summary of the Invention

[0004] The object of the present invention is to provide a photonic integrated circuit chip and a silicon photonic integrated platform, so as to improve the optical coupling efficiency between the photonic integrated circuit chip and an external optical fiber.

[0005] The purpose of the present invention is achieved by the following technical solutions:

[0006] According to one aspect of the present invention, there is provided a photonic integrated circuit chip, comprising: a stacked supporting silicon layer, a first silicon oxide layer, and a second silicon oxide layer;

[0007] The photonic integrated circuit chip includes an optical device disposed in the first silicon oxide layer and a device waveguide optically connected to the optical device, and a side of the photonic integrated circuit chip has an external end face coupled to the outside world;

[0008] At least one first metal layer is further provided in the first silicon oxide layer, and in the thickness direction of the supporting silicon, the at least one first metal layer is located between the optical device and the supporting silicon;

[0009] The photonic integrated circuit chip also includes a first waveguide, which is disposed in the first silicon oxide layer or the second silicon oxide layer. The first waveguide is optically coupled to the device waveguide. In a direction perpendicular to the thickness of the supporting silicon, the first waveguide extends from the interior of the photonic integrated circuit chip toward the outer end surface. The first waveguide is configured to have a first mode size on a side away from the outer end surface and a second mode size on a side close to the outer end surface, wherein the first mode size is larger than the second mode size.

[0010] Furthermore, in the thickness direction of the supporting silicon, the distance between the first waveguide and the supporting silicon is greater than half of the mode field diameter of an external optical fiber to be optically coupled with the photonic integrated circuit chip.

[0011] Furthermore, in a direction pointing from the inside of the photonic integrated circuit chip to the outer end surface, a portion of the first waveguide is in an inverted wedge-shaped structure.

[0012] Optionally, the number of the first waveguides is 1 or more;

[0013] When there are multiple first waveguides, the multiple first waveguides are located in the same film layer and placed side by side, and at least one of the multiple first waveguides gradually becomes thinner toward the outer end surface.

[0014] Furthermore, in the case where the first waveguide is arranged in the first silicon oxide layer, the photonic integrated circuit chip also includes a second waveguide, which is located in the second silicon oxide layer, is optically coupled with the first waveguide, and is spaced apart from the first waveguide in the thickness direction; in the thickness direction perpendicular to the supporting silicon, the second waveguide extends from the interior of the photonic integrated circuit chip to the outer end surface.

[0015] Furthermore, in a direction pointing from the inside of the photonic integrated circuit chip to the outer end surface, a portion of the second waveguide is in an inverted wedge-shaped structure.

[0016] Further, in a direction perpendicular to the thickness of the supporting silicon, an extension length of the second waveguide is smaller than an extension length of the first waveguide, and an end portion of the second waveguide close to the outer end surface is flush with an end portion of the first waveguide close to the outer end surface.

[0017] Furthermore, the number of the second waveguides is multiple, and the number of the first waveguides is multiple;

[0018] At a cross-sectional position close to the plane where the outer end surface is located, the combination of the plurality of second waveguides and the plurality of first waveguides is arranged in multiple rows and / or multiple columns.

[0019] Furthermore, at a cross-sectional position close to the plane where the outer end surface is located, between adjacent rows and / or columns, the plurality of second waveguides and the plurality of first waveguides are arranged in a staggered or irregular manner.

[0020] Furthermore, at least one second waveguide among the plurality of second waveguides has a constant cross-sectional width directed from the interior of the photonic integrated circuit chip toward the outer end surface.

[0021] Furthermore, the photonic integrated circuit chip also includes a third waveguide, which is located in the first silicon oxide layer, the third waveguide is optically coupled with the first waveguide and the second waveguide respectively, and the third waveguide is spaced apart from the first waveguide and the second waveguide respectively in the thickness direction; in the thickness direction of the supporting silicon, the third waveguide is located between the first waveguide and the second waveguide; in the thickness direction perpendicular to the supporting silicon, the third waveguide extends from the interior of the photonic integrated circuit chip to the outer end surface.

[0022] Furthermore, the third waveguide and the device waveguide are both located in the first silicon oxide layer.

[0023] Furthermore, in a direction perpendicular to the thickness of the supporting silicon, an extension length of the third waveguide is greater than an extension length of the first waveguide, the third waveguide is optically connected to the device waveguide, and an end portion of the third waveguide close to the outer end surface is flush with an end portion of the first waveguide close to the outer end surface.

[0024] Furthermore, in a cross-sectional direction close to the outer end surface, a plurality of first waveguides and a plurality of second waveguides surround the periphery of the third waveguide.

[0025] Furthermore, the photonic integrated circuit chip also includes a fourth waveguide, which is located in the second silicon oxide layer, and is optically coupled with the first waveguide and the second waveguide respectively. The fourth waveguide is spaced apart from the first waveguide and the second waveguide respectively in the thickness direction; in the thickness direction perpendicular to the supporting silicon, the fourth waveguide extends from the inside of the photonic integrated circuit chip to the outer end surface; in the thickness direction of the supporting silicon, the fourth waveguide is located on the side of the second waveguide facing away from the first waveguide.

[0026] Furthermore, in a direction pointing from the inside of the photonic integrated circuit chip to the outer end surface, a portion of the fourth waveguide is in an inverted wedge-shaped structure.

[0027] Furthermore, in a direction perpendicular to the thickness of the supporting silicon, an extension length of the fourth waveguide is smaller than an extension length of the first waveguide, and an end portion of the fourth waveguide close to the outer end surface is flush with an end portion of the first waveguide close to the outer end surface.

[0028] Furthermore, in the case where the first waveguide is arranged in the second silicon oxide layer, the photonic integrated circuit chip also includes a fifth waveguide, which is located in the second silicon oxide layer, optically coupled with the first waveguide, and spaced apart from the first waveguide in the thickness direction; in the thickness direction perpendicular to the supporting silicon, the fifth waveguide extends from the inside of the photonic integrated circuit chip to the outer end surface; in the thickness direction of the supporting silicon, the fifth waveguide is located on the side of the first waveguide away from the first silicon oxide layer.

[0029] Furthermore, in a direction pointing from the inside of the photonic integrated circuit chip to the outer end surface, a portion of the fifth waveguide has an inverted wedge-shaped structure.

[0030] Furthermore, in a direction perpendicular to the thickness of the supporting silicon, an extension length of the fifth waveguide is smaller than an extension length of the first waveguide, and an end portion of the fifth waveguide close to the outer end surface is flush with an end portion of the first waveguide close to the outer end surface.

[0031] Furthermore, the photonic integrated circuit chip further includes a sixth waveguide, the sixth waveguide being located in the first silicon oxide layer, the sixth waveguide being optically coupled to the first waveguide, and being spaced apart from the first waveguide in a thickness direction;

[0032] In a direction perpendicular to the thickness of the supporting silicon, the sixth waveguide extends from the interior of the photonic integrated circuit chip to the outer end surface.

[0033] Furthermore, in a direction pointing from the inside of the photonic integrated circuit chip to the outer end surface, a portion of the sixth waveguide has an inverted wedge-shaped structure.

[0034] Further, in a direction perpendicular to the thickness of the supporting silicon, an extension length of the sixth waveguide is smaller than an extension length of the first waveguide, and an end portion of the sixth waveguide close to the outer end surface is flush with an end portion of the first waveguide close to the outer end surface.

[0035] Furthermore, at least one second metal layer is provided in the second silicon oxide layer, and the at least one second metal layer is electrically connected to the at least one first metal layer through a metal through-hole.

[0036] Furthermore, the photonic integrated circuit chip further includes a third silicon oxide layer.

[0037] Wherein, in the thickness direction of the supporting silicon, the third silicon oxide layer is arranged between the first silicon oxide layer and the supporting silicon.

[0038] Furthermore, the photonic integrated circuit chip further includes a protective layer, which covers a surface of the second silicon oxide layer on a side away from the first silicon oxide layer; wherein the material of the protective layer is silicon nitride.

[0039] Furthermore, the optical device includes one or a combination of a photodetector, a laser, a modulator and a wavelength division multiplexer.

[0040] According to another aspect of the present invention, there is further provided a silicon photonic integrated platform, comprising any of the aforementioned photonic integrated circuit chips;

[0041] An optical fiber, comprising an optical fiber core and an optical fiber cladding covering the optical fiber core;

[0042] The optical fiber is aligned with the outer end surface of the photonic integrated circuit chip to perform optical coupling.

[0043] Furthermore, a groove is provided at a cross-sectional position of the supporting silicon close to the outer end surface, and the optical fiber is placed in the groove.

[0044] The present invention provides a solution for the optical interconnection between photonic integrated circuit chips and optical fibers. It aims to set a specific waveguide structure on the photonic integrated circuit chip to achieve efficient coupling with ordinary single-mode optical fibers. At the same time, no suspended structure is introduced, so that the overall structure has strong mechanical stability, can pass the high-temperature and high-humidity reliability testing conditions of the photonic integrated circuit chip, and is compatible with processes such as reflow soldering and through-silicon vias.

[0045] Furthermore, the distance between the side coupler structure used for coupling in optical interconnection of photonic integrated circuits and the substrate can be optimized to prevent the light field from leaking into the substrate. The position and critical dimensions of the single-layer waveguide and multi-layer waveguide within the side coupler structure can also be flexibly arranged as needed. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other implementation methods can be obtained based on these drawings without paying any creative work.

[0047] FIG1 shows a schematic structural diagram of a photonic integrated circuit chip provided in the first embodiment of the present application.

[0048] FIG. 2 is a schematic cross-sectional view of the edge coupler structure of the photonic integrated circuit chip provided in FIG. 1 at positions 1 and 2 .

[0049] FIG3 shows a schematic structural diagram of a photonic integrated circuit chip manufactured based on semiconductor on insulator according to an embodiment of the present application.

[0050] FIG4 shows a schematic structural diagram of a photonic integrated circuit chip provided in the second embodiment of the present application.

[0051] FIG5 shows a first example of a cross-sectional schematic diagram of the edge coupler structure of the photonic integrated circuit chip provided in FIG4 at positions 1, 2, and 3. ...

[0052] FIG6 shows a second example of a cross-sectional schematic diagram of the edge coupler structure of the photonic integrated circuit chip provided in FIG4 at positions 1, 2, and 3. ...

[0053] FIG. 7 shows a third example of a cross-sectional schematic diagram of the edge coupler structure of the photonic integrated circuit chip provided in FIG. 4 at positions 1 , 2 , and 3 .

[0054] FIG8 shows a fourth example of a cross-sectional schematic diagram of the edge coupler structure of the photonic integrated circuit chip provided in FIG4 at positions 1, 2, and 3. FIG.

[0055] FIG9 shows a fifth example of a cross-sectional schematic diagram of the edge coupler structure of the photonic integrated circuit chip provided in FIG4 at positions 1 and 2. FIG.

[0056] FIG10 shows a schematic structural diagram of a photonic integrated circuit chip provided in the third embodiment of the present application.

[0057] FIG. 11 is a schematic cross-sectional view of the edge coupler structure of the photonic integrated circuit chip provided in FIG. 10 at positions 1 , 2 , and 3 .

[0058] FIG12 shows a schematic structural diagram of a photonic integrated circuit chip provided in the fourth embodiment of the present application.

[0059] FIG13A is a schematic cross-sectional view showing the edge coupler structure of the photonic integrated circuit chip provided in FIG12 at positions 1, 2, and 3. ...

[0060] FIG13B is a schematic cross-sectional view showing the edge coupler structure of the photonic integrated circuit chip provided in FIG12 at positions 1, 2, and 3. ...

[0061] FIG14 shows a schematic structural diagram of a photonic integrated circuit chip provided in the fifth embodiment of the present application.

[0062] FIG15 shows a schematic structural diagram of a photonic integrated circuit chip provided in the sixth embodiment of the present application.

[0063] FIG16 shows a schematic structural diagram of a photonic integrated circuit chip provided in the seventh embodiment of the present application.

[0064] FIG. 17 shows another cross-sectional view of the edge coupler structure of the photonic integrated circuit chip provided in FIG. 16 at positions 1 , 2 , and 3 .

[0065] FIG18 shows a schematic structural diagram of a photonic integrated circuit chip provided in the eighth embodiment of the present application.

[0066] FIG. 19 shows another cross-sectional view of the edge coupler structure of the photonic integrated circuit chip provided in FIG. 18 at position 1 .

[0067] FIG20 shows a schematic structural diagram of a silicon photonic integration platform provided in an embodiment of the present application.

[0068] FIG21 shows a cross-sectional schematic diagram of the silicon photonic integration platform provided in an embodiment of the present application. DETAILED DESCRIPTION

[0069] The above description is only an overview of the technical solution of the present invention. In order to more clearly understand the technical means of the present invention, it can be implemented in accordance with the contents of the specification. In order to make the above and other purposes, features and advantages of the present invention more obvious and easy to understand, the following preferred embodiments are specifically cited and described in detail with reference to the accompanying drawings.

[0070] In the description of the present invention, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected" and "connected" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, an electrical connection, or mutual communication; it can be directly connected, or indirectly connected through an intermediate medium, or it can be the internal connection of two elements or the interaction relationship between two elements. The meaning of chip in this article may include bare chip. When it comes to method steps, the sequence illustrated in this article represents an exemplary scheme, but does not represent a limitation on the sequence. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0071] As used herein, the term "substrate" can refer to the substrate of a diced wafer or the substrate of an undiced wafer. It should be understood that the term "film" encompasses layers and, unless otherwise specified, should not be interpreted as indicating vertical or horizontal thickness. It should be noted that the thicknesses of the various material layers of the edge coupler structure shown in the figures are merely illustrative and do not represent actual thicknesses.

[0072] In order to make the objects, features and advantages of the present invention more obvious and easy to understand, the present invention is further described in detail below with reference to the accompanying drawings and specific embodiments.

[0073] In common technology, photonic integrated circuit chips utilize silicon waveguides fabricated on the top silicon layer of an SOI (Silicon On Insulator) structure. The silicon oxide layer (BOX layer) between the bottom and top silicon layers typically has a thickness between 0.7μm and 3μm, and the silicon waveguide typically has a thickness between 150nm and 340nm. To ensure effective coupling between the silicon waveguide and the SiN waveguide above, the spacing between the two is typically less than 500nm. Therefore, in common technology, the vertical distance between the SiN waveguide layer and the underlying silicon layer is typically less than 4μm. To ensure efficient coupling between the photonic integrated circuit chip and conventional single-mode optical fiber (where the mode field spot is typically 9-10μm), the mode field diameter of the light spot near the end face of the edge coupler must also be 9-10μm. Consequently, light field leakage into the underlying silicon layer is unavoidable, introducing additional losses.

[0074] Furthermore, in common technologies, to improve the coupling efficiency of edge couplers, the underlying silicon beneath key areas of some edge couplers is partially etched away to form a suspended structure. While this eliminates the loss of light fields leaking into the underlying silicon, the presence of this suspended structure results in low mechanical stability and is prone to collapse in subsequent processes (for example, it is extremely easy to break during wafer dicing and chip packaging). This makes it difficult to pass the reliability testing conditions required for photonic integrated circuit chips, and it is also incompatible with processes such as reflow soldering and through-silicon vias (TSVs) used in photonic integrated circuit chips, resulting in increased manufacturing costs.

[0075] In view of this, one aspect of the present invention provides a photonic integrated circuit chip for resolving the problem of optical field leakage into underlying silicon in a photonic integrated circuit chip. The photonic integrated circuit chip comprises: a stacked supporting silicon, a first silicon oxide layer, and a second silicon oxide layer; an optical device disposed in the first silicon oxide layer and a device waveguide optically connected to the optical device; a side of the photonic integrated circuit chip having an external end face coupled to the outside world; at least one first metal layer disposed in the first silicon oxide layer, and located between the optical device and the supporting silicon in the thickness direction of the supporting silicon; and a first waveguide disposed in the first silicon oxide layer or the second silicon oxide layer, optically coupled to the device waveguide. The first waveguide extends perpendicular to the thickness of the supporting silicon from the interior of the photonic integrated circuit chip to the external end face, and is configured to have a first mode size on a side away from the external end face and a second mode size on a side close to the external end face, wherein the first mode size is larger than the second mode size.

[0076] As can be seen from the above, the present application aims to achieve efficient coupling with ordinary single-mode optical fibers by setting a specific waveguide structure on a photonic integrated circuit chip (PIC chip), while not introducing a suspended structure, so that the overall structure has strong mechanical stability, can pass the high temperature and high humidity reliability test conditions of the photonic integrated circuit chip, and is compatible with processes such as reflow soldering and through-silicon vias.

[0077] Example 1

[0078] FIG1 shows a schematic structural diagram of a photonic integrated circuit chip provided in the first embodiment of the present application, and FIG2 shows a schematic cross-sectional diagram of an edge coupler structure of the photonic integrated circuit chip provided in FIG1 at positions 1 and 2.

[0079] As shown in FIG. 1 and FIG. 2 , the photonic integrated circuit chip 1000 provided in the first embodiment of the present application includes: a supporting silicon 100 , a first silicon oxide layer 110 , and a second silicon oxide layer 120 , which are stacked.

[0080] The photonic integrated circuit chip 1000 includes an optical device 210 disposed in the first silicon oxide layer 110 and a device waveguide 220 optically connected to the optical device 210. The photonic integrated circuit chip 1000 has an external end face coupled to the outside world, perpendicular to the thickness of the supporting silicon 100. Specifically, the side of the photonic integrated circuit chip 1000 is provided with an external end face coupled to the outside world.

[0081] At least one first metal layer 310 is further provided in the first silicon oxide layer 110. In the thickness direction of the supporting silicon 100, the at least one first metal layer 310 is located between the optical device 210 and the supporting silicon 100.

[0082] The photonic integrated circuit chip 1000 also includes a first waveguide 410 disposed within the first silicon oxide layer 110. The first waveguide 410 is optically coupled to the device waveguide 220. The first waveguide 410 extends from the interior of the photonic integrated circuit chip toward the outer end surface in a direction perpendicular to the thickness of the supporting silicon 100. The first waveguide 410 is configured to have a first mode size on a side distal from the outer end surface and a second mode size on a side proximal to the outer end surface. The first mode size is larger than the second mode size.

[0083] Furthermore, in the thickness direction of the supporting silicon 100 , the distance between the first waveguide 410 and the supporting silicon 100 is greater than half of the mode field diameter of an external optical fiber optically coupled to the photonic integrated circuit chip.

[0084] In an embodiment of the present invention, the spacing between the first waveguide 410 and the supporting silicon 100 in the photonic integrated circuit chip 1000 is designed to be greater than half the mode field diameter of the external optical fiber optically coupled thereto, that is, the technical solution provided by the embodiment of the present invention can make the spacing between the first waveguide 410 and the supporting silicon 100 greater than 4.5-5 μm, thereby solving the problem of leakage of the light field on the photonic integrated circuit chip to the supporting silicon (substrate). At the same time, no suspended structure is introduced, so that the overall structure has strong mechanical stability, which is beneficial for the photonic integrated circuit chip to pass reliability tests such as high temperature and high humidity, and is compatible with reflow soldering and through-silicon via processes.

[0085] In this embodiment, the device waveguide 220, optical device 210, and first waveguide 410 in the photonic integrated circuit chip can be fabricated based on a semiconductor-on-insulator (SOI) substrate. The SOI substrate can be, for example, a silicon-on-insulator (SOI). For example, as shown in FIG3 , the SOI substrate can include an insulating layer 602, a semiconductor layer 603 formed on the insulating layer 602, and a substrate layer 601 located below the insulating layer 602. The substrate layer 601 is also called a backing substrate (or backing layer), and the semiconductor layer 603 can be silicon, also called top silicon. The semiconductor layer 603 can be patterned, deposited, doped, and other processes to form a portion of the photonic integrated circuit chip 1000. Specifically, the device waveguide 220 is formed by etching a portion of the semiconductor layer 603. The optical device 210 can include one or a combination of a photodetector, a laser, a modulator, and a wavelength division multiplexer. For example, a photodetector includes a light absorption layer (e.g., a germanium layer). In the thickness direction of the substrate layer 601, the light absorbing layer is arranged on the side of the device waveguide 220 away from the substrate layer 601. The insulating layer 602 is, for example, a buried silicon oxide layer. The optical device 210 includes a portion of the device waveguide 220 and the light absorbing layer.

[0086] 1 to 3 , a device waveguide 220 , an optical device 210 , a first silicon oxide layer 110 , at least one first metal layer 310 within the first silicon oxide layer 110 , and a first waveguide 410 are fabricated on a substrate layer 601 (e.g., the bottom silicon of an SOI structure). After completion, an oxide layer 130 (for example, a SiO2 film layer) can be deposited or bonded on the surface of the first silicon oxide layer 110 on the side away from the substrate layer 601 to flatten the surface of the first silicon oxide layer 110 on the side away from the substrate layer 601, and then the supporting silicon 100 is bonded to the above-mentioned oxide layer on the surface of the first silicon oxide layer 110 on the side away from the substrate layer 601. Then, the structure having both the substrate layer 601 and the supporting silicon 100 is flipped upside down as a whole, so that the supporting silicon 100 is at the bottom and the substrate layer 601 is at the top. Then, the substrate layer 601 is removed to obtain the first silicon oxide layer 110 located above the supporting silicon 100, and at least one first metal layer 310, optical device 210, device waveguide 220 and first waveguide 410 located in the first silicon oxide layer 110. At this time, the distance between the first waveguide 410 and the supporting silicon 100 is far enough. By designing the number or film thickness of at least one first metal layer 310 in the first silicon oxide layer 110, the distance between the first waveguide 410 and the supporting silicon 100 can be easily designed to be larger than half the mode field diameter of the external optical fiber optically coupled to the photonic integrated circuit chip (the mode field diameter of an ordinary single-mode optical fiber is 9-10 μm), so as to prevent the light field of the photonic integrated circuit chip from leaking into the supporting silicon 100.

[0087] For example, in this embodiment, the device waveguide 220 is a silicon waveguide, and the first waveguide 410 is a silicon nitride waveguide or a silicon oxynitride waveguide. Since silicon generally has a higher refractive index, the actual mode size achievable by a silicon waveguide is approximately 2-5 μm. However, since silicon nitride or silicon oxynitride has a lower refractive index than silicon, the silicon nitride waveguide or silicon oxynitride waveguide (first waveguide) can achieve a larger mode size than the silicon waveguide (device waveguide).

[0088] In some embodiments, as shown in FIG. 1 and FIG. 2 , from the inside of the photonic integrated circuit chip 1000 toward the outer end surface, a portion of the first waveguide 410 is in an inverted wedge-shaped structure.

[0089] Optionally, there are one or more first waveguides 410. When there are multiple first waveguides 410, the multiple first waveguides 410 are located in the same film layer and arranged side by side. In this case, the edge coupler structure for mode spot conversion is composed of multiple parallel first waveguides 410, and at least one of the multiple first waveguides 410 gradually tapers toward the outer end face, allowing the light field mode spot to gradually expand from the interior of the photonic integrated circuit chip 1000 toward the outer end face.

[0090] In some embodiments, when the at least one first metal layer 310 includes multiple first metal layers 310, a metal through-hole is further provided between two adjacent first metal layers 310 in the first silicon oxide layer 110 in the thickness direction of the supporting silicon 100, and the multiple first metal layers 310 realize electrical connection between each first metal layer 310 or other devices through the metal through-hole.

[0091] Furthermore, at least one second metal layer 320 is further provided in the second silicon oxide layer 120 , and the at least one second metal layer 320 is electrically connected to the at least one first metal layer 310 through a metal through-hole.

[0092] Example 2

[0093] Figure 4 shows a schematic diagram of the structure of the photonic integrated circuit chip provided in the second embodiment of the present application. Figure 5 shows a first example of a cross-sectional schematic diagram of the edge coupler structure of the photonic integrated circuit chip provided in Figure 4 at positions 1, 2, and 3.

[0094] As shown in Figures 4 and 5, in the second embodiment of the present application, when the first waveguide 410 is arranged in the first silicon oxide layer 110, the photonic integrated circuit chip 1000 further includes a second waveguide 420. The second waveguide 420 is located in the second silicon oxide layer 120. The second waveguide 420 is optically coupled to the first waveguide 410 and is spaced apart from the first waveguide 410 in the thickness direction. In the thickness direction perpendicular to the supporting silicon 100, the second waveguide 420 extends from the interior of the photonic integrated circuit chip 1000 to the outer end surface.

[0095] In Example 2, compared to Example 1, in addition to the single-layer first waveguide 410, a second waveguide 420 is additionally provided, disposed in a separate layer from the first waveguide 410. In the thickness direction of the supporting silicon 100, the second waveguide 420 is spaced from the first waveguide 410 by a distance less than or equal to a predetermined spacing (e.g., 500 nm), enabling optical coupling between the second waveguide 420 and the first waveguide 410. In this case, the photonic integrated circuit chip 1000 comprises multiple waveguides. Because the mode field diameter of a single-layer waveguide is typically sensitive to its own morphology or size, this can result in the optical field spot size at cross-sectional position 1 near the outer end face of the photonic integrated circuit chip being too large or too small, making adjustment difficult. By employing multiple waveguides, where multiple waveguides participate in optical field spot conversion, the sensitivity of the single-layer waveguide's morphology or size to the mode field diameter can be reduced while ensuring coupling efficiency.

[0096] Specifically, the second waveguide 420 is located within the second silicon oxide layer 120. This means that the second waveguide 420 is also supported and coated by the SiO2 film. Light coupled from the first waveguide 410 undergoes mode spot conversion in the second waveguide 420 and then expands into the silicon oxide surrounding the second waveguide 420. The size of the light field mode spot is adjusted by both the first waveguide 410 and the second waveguide 420, ultimately matching the mode field of the external optical fiber.

[0097] Optionally, the number of the second waveguide 420 is one or more.

[0098] Optionally, in a direction from the inside of the photonic integrated circuit chip 1000 to the outer end surface, a portion of the second waveguide 420 is in an inverted wedge-shaped structure.

[0099] Furthermore, in a direction perpendicular to the thickness of the supporting silicon 100 , an extension length of the second waveguide 420 is smaller than an extension length of the first waveguide 410 , and an end portion of the second waveguide 420 close to the outer end surface is flush with an end portion of the first waveguide 410 close to the outer end surface.

[0100] In some embodiments, there are multiple second waveguides 420 and multiple first waveguides 410; at a cross-sectional location near the plane containing the outer end surface, the combination of the multiple second waveguides 420 and the multiple first waveguides 410 is arranged in multiple rows and / or columns. In this embodiment, the first waveguides 410 and the second waveguides 420 are configured to perform spot conversion (e.g., expand the spot size of the light) on light coupled from the device waveguide 220 and transmit it to an external optical fiber, or to perform spot conversion (e.g., shrink the spot size of the light) on light input from an external optical fiber and couple the spot-converted light to the device waveguide 220.

[0101] In some embodiments, at least one second waveguide 420 among the plurality of second waveguides 420 has a constant cross-sectional width extending from the interior of the photonic integrated circuit chip 1000 toward the outer end surface. For example, as shown in FIG5 , two second waveguides 420 have a constant cross-sectional width at a cross-sectional position 2 of the photonic integrated circuit chip 1000 that is away from the outer end surface and at a cross-sectional position 1 of the photonic integrated circuit chip 1000 that is close to the outer end surface.

[0102] Optionally, the second waveguide 420 is a silicon nitride waveguide or a silicon oxynitride waveguide.

[0103] For example, as shown in FIG5 , at cross-sectional location 3, far from the edge of the photonic integrated circuit chip 1000, there is only one first waveguide 410 in the lower layer. This first waveguide 410 has a larger cross-sectional dimension, and the light field is primarily confined within this first waveguide 410. At cross-sectional location 2, far from the edge of the photonic integrated circuit chip 1000, there are two first waveguides 410 and two second waveguides 420. The first waveguide 410 on the left side of the lower layer has a relatively larger cross-sectional dimension, while the other first waveguide 410 has a relatively smaller cross-sectional dimension. The cross-sectional dimensions of the two second waveguides 420 on the upper layer are also relatively small. The light field is primarily confined within the first waveguide 410 on the left side of the lower layer. At cross-sectional location 1, near the outer end face of the photonic integrated circuit chip 1000, the two first waveguides 410 on the lower layer and the two second waveguides 420 on the upper layer are both smaller in dimension. The light field is confined by the two first waveguides 410 on the lower layer, the two second waveguides 420 on the upper layer, and the surrounding silicon oxide. The upper and lower waveguide layers jointly participate in adjusting the light field mode spot size, which reduces the sensitivity of the single-layer waveguide's own morphology or size to the mode field diameter of the single-layer waveguide while ensuring the coupling efficiency.

[0104] The cross-sectional dimensions of the first waveguide 410 located on the left side of the lower layer can vary linearly or nonlinearly as it moves from cross-sectional position 3 to cross-sectional position 1. The cross-sectional dimensions of the first waveguide 410 located on the right side of the lower layer and the two second waveguides 420 located on the upper layer can vary or remain unchanged. The two second waveguides 420 located on the upper layer can have the same or different heights, and the two first waveguides 410 located on the lower layer can have the same or different heights.

[0105] FIG6 shows a second example of a cross-sectional schematic diagram of the edge coupler structure of the photonic integrated circuit chip provided in FIG4 at positions 1, 2, and 3. ...

[0106] As shown in Figure 6, compared to Figure 5, in this example, from cross-sectional position 2 to cross-sectional position 1, the two first waveguides 410 located in the lower layer of the photonic integrated circuit chip gradually taper toward the outer end surface, while the cross-sectional dimensions of the two second waveguides 420 located in the upper layer toward the outer end surface remain unchanged. In this case, the mode spot conversion is simultaneously achieved by the changes in the two first waveguides 410 located in the lower layer.

[0107] FIG. 7 shows a third example of a cross-sectional schematic diagram of the edge coupler structure of the photonic integrated circuit chip provided in FIG. 4 at positions 1 , 2 , and 3 .

[0108] As shown in FIG. 7 , compared to FIG. 5 and FIG. 6 , illustratively, the number of the first waveguides 410 located in the lower layer is greater than two, for example, three, and the number of the second waveguides 420 located in the upper layer is also greater than two, for example, three.

[0109] For example, at cross-sectional position 3 of the photonic integrated circuit chip, away from the outer end face, there is only one first waveguide 410 in the middle of the lower layer. This first waveguide 410 has a larger cross-sectional dimension, and the light field is primarily confined within the first waveguide 410. At cross-sectional position 2 of the photonic integrated circuit chip, away from the outer end face, there are three first waveguides 410 and three second waveguides 420. The first waveguide 410 in the middle of the lower layer has a relatively large cross-sectional dimension, while the other two first waveguides 410 and the three second waveguides 420 in the upper layer have relatively smaller cross-sectional dimensions. The light field is primarily confined within the first waveguide 410 in the middle of the lower layer. At cross-sectional position 1 of the photonic integrated circuit chip, near the outer end face, the three first waveguides 410 in the lower layer and the three second waveguides 420 in the upper layer are all relatively small, and the light field is confined by the three first waveguides 410 in the lower layer, the three second waveguides 420 in the upper layer, and the surrounding silicon oxide.

[0110] FIG8 shows a fourth example of a cross-sectional schematic diagram of the edge coupler structure of the photonic integrated circuit chip provided in FIG3 at positions 1, 2, and 3. ...

[0111] As shown in FIG. 8 , compared to FIG. 5 , FIG. 6 and FIG. 7 , the number of the first waveguides 410 located in the lower layer is two, and the number of the second waveguides 420 located in the upper layer is three.

[0112] For example, at cross-sectional position 3 of the photonic integrated circuit chip, away from the outer end face, there are only two first waveguides 410 in the lower layer. These two first waveguides 410 have larger cross-sectional dimensions, and the light field is primarily confined within the first waveguides 410. At cross-sectional position 2 of the photonic integrated circuit chip, away from the outer end face, there are two first waveguides 410 and three second waveguides 420. The two first waveguides 410 in the lower layer have relatively larger cross-sectional dimensions, while the three second waveguides 420 in the upper layer have relatively smaller cross-sectional dimensions, and the light field is primarily confined within the two first waveguides 410 in the lower layer. At cross-sectional position 1 of the photonic integrated circuit chip, closer to the outer end face, both the two first waveguides 410 in the lower layer and the three second waveguides 420 in the upper layer are smaller in dimensions. The light field is confined by the two first waveguides 410 in the lower layer, the three second waveguides 420 in the upper layer, and the surrounding silicon oxide.

[0113] FIG9 shows a fifth example of a cross-sectional schematic diagram of the edge coupler structure of the photonic integrated circuit chip provided in FIG4 at positions 1 and 2. FIG.

[0114] As shown in FIG. 9 , compared to FIG. 5 , FIG. 6 , FIG. 7 and FIG. 8 , the number of the first waveguide 410 located in the lower layer is one, and the number of the second waveguide 420 located in the upper layer is two.

[0115] For example, at cross-sectional location 2 of the photonic integrated circuit chip, away from the outer end face, there is a first waveguide 410 and two second waveguides 420. The lower first waveguide 410 has a relatively large cross-sectional dimension, while the upper two second waveguides 420 have relatively small cross-sectional dimensions. The light field is primarily confined within the lower first waveguide 410. At cross-sectional location 1 of the photonic integrated circuit chip, closer to the outer end face, both the lower first waveguide 410 and the upper two second waveguides 420 are relatively small. The light field is confined by the lower first waveguide 410, the upper two second waveguides 420, and the surrounding silicon oxide.

[0116] Example 3

[0117] Figure 10 shows a schematic diagram of the structure of the photonic integrated circuit chip provided in the third embodiment of the present application. Figure 11 shows a schematic cross-sectional view of the edge coupler structure of the photonic integrated circuit chip provided in Figure 10 at positions 1, 2, and 3.

[0118] As shown in Figures 10 and 11 , in the third embodiment of the present application, the photonic integrated circuit chip 1000 further includes a third waveguide 430. The third waveguide 430 is located within the first silicon oxide layer 110. The third waveguide 430 is optically connected to the device waveguide 220. The third waveguide 430 is a silicon waveguide and is optically coupled to the first waveguide 410 and the second waveguide 420, respectively. Furthermore, the third waveguide 430 is spaced apart from the first waveguide 410 and the second waveguide 420 in the thickness direction. In the thickness direction of the supporting silicon 100, the third waveguide 430 is located between the first waveguide 410 and the second waveguide 420. In a direction perpendicular to the thickness of the supporting silicon 100, the third waveguide 430 extends from the interior of the photonic integrated circuit chip 1000 to the outer end surface.

[0119] Furthermore, in some embodiments, the third waveguide 430 and the device waveguide 220 are both located in the first silicon oxide layer 110 .

[0120] Furthermore, in a direction perpendicular to the thickness of the supporting silicon 100, the extension length of the third waveguide 430 is greater than the extension length of the first waveguide 410. The third waveguide 430 is optically connected to the device waveguide 220, allowing the light field exiting the device waveguide 220 to be directly transferred to the third waveguide 430, thereby avoiding unnecessary loss of optical energy. Furthermore, the end of the third waveguide 430 near the outer end surface is flush with the end of the first waveguide 410 near the outer end surface.

[0121] Optionally, the number of the third waveguide 430 is 1 or more.

[0122] Furthermore, in the cross-sectional direction close to the outer end surface, the plurality of first waveguides 410 and the plurality of second waveguides 420 surround the periphery of the third waveguide 430 .

[0123] For example, as shown in FIG11 , at cross-sectional position 3 of the photonic integrated circuit chip, which is away from the outer end face, there is only one third waveguide 430 in the middle layer. This third waveguide 430 has a larger cross-sectional size, and the light field is primarily confined within the third waveguide 430. At cross-sectional position 2 of the photonic integrated circuit chip, which is away from the outer end face, there are two first waveguides 410, two second waveguides 420, and one third waveguide 430. The light field is still primarily confined within the third waveguide 430 located in the middle. At cross-sectional position 1 of the photonic integrated circuit chip, which is closer to the outer end face, the two first waveguides 410 in the lower layer, the two second waveguides 420 in the upper layer, and the third waveguide 430 in the middle layer are all smaller in size. The light field is collectively confined by the two first waveguides 410 in the lower layer, the two second waveguides 420 in the upper layer, the third waveguide 430 in the middle layer, and the surrounding silicon oxide.

[0124] Example 4

[0125] FIG12 is a schematic diagram illustrating the structure of a photonic integrated circuit chip provided in a fourth embodiment of the present application. FIG13A is a schematic diagram illustrating the cross-section of the edge coupler structure of the photonic integrated circuit chip provided in FIG12 at positions 1, 2, and 3. FIG13B is a schematic diagram illustrating the cross-section of the edge coupler structure of the photonic integrated circuit chip provided in FIG12 at positions 1, 2, and 3.

[0126] As shown in FIG12 , in the fourth embodiment of the present application, the photonic integrated circuit chip 1000 further includes a fourth waveguide 440. The fourth waveguide 440 is located within the second silicon oxide layer 120 and optically coupled to the first waveguide 410 and the second waveguide 420, respectively. Furthermore, the fourth waveguide 440 is spaced apart from the first waveguide 410 and the second waveguide 420 in the thickness direction. In a direction perpendicular to the thickness of the supporting silicon 100, the fourth waveguide 440 extends from the interior of the photonic integrated circuit chip 1000 toward the outer end surface. In the thickness direction of the supporting silicon 100, the fourth waveguide 440 is located on the side of the second waveguide 420 facing away from the first waveguide 410.

[0127] Optionally, in a direction from the inside of the photonic integrated circuit chip 1000 to the outer end surface, a portion of the fourth waveguide 440 is in an inverted wedge-shaped structure.

[0128] Furthermore, in a direction perpendicular to the thickness of the supporting silicon 100 , an extension length of the fourth waveguide 440 is smaller than an extension length of the first waveguide 410 , and an end of the fourth waveguide 440 close to the outer end surface is flush with an end of the first waveguide 410 close to the outer end surface.

[0129] 13A and 13B , the fourth embodiment of the present application relates to a process in which three layers of silicon nitride waveguides or silicon oxynitride waveguides participate in edge coupling, wherein the first waveguide 410 located at the bottom layer extends from cross-sectional position 1 to cross-sectional position 3.

[0130] For example, as shown in FIG13A , at cross-sectional position 3 of the photonic integrated circuit chip, away from the outer end face, there is only one first waveguide 410 in the lower layer. This first waveguide 410 has a relatively large cross-sectional dimension, and the light field is primarily confined within the first waveguide 410. At cross-sectional position 2 of the photonic integrated circuit chip, away from the outer end face, there are three first waveguides 410, three second waveguides 420, and three fourth waveguides 440. The first waveguide 410 located in the middle of the lower layer has a relatively large cross-sectional dimension, while the three fourth waveguides 440 located in the upper layer and the three second waveguides 420 located in the middle layer have relatively small cross-sectional dimensions. The light field is primarily confined within the first waveguide 410 located in the middle of the lower layer. At cross-sectional position 1 of the photonic integrated circuit chip, the two first waveguides 410 located in the lower layer, the three second waveguides 420 located in the middle layer, and the three fourth waveguides 440 located in the upper layer all have relatively small cross-sectional dimensions. The light field is confined by the three first waveguides 410 at the bottom, the three second waveguides 420 at the middle, the three fourth waveguides 440 at the top, and the surrounding silicon oxide. At this point, light coupled in from outside the photonic integrated circuit chip 1000 is ultimately coupled into the bottom first waveguide 410.

[0131] For example, as shown in FIG13B , at cross-sectional position 3 of the photonic integrated circuit chip, away from the outer end face, there is only one first waveguide 410 in the lower layer. This first waveguide 410 has a relatively large cross-sectional dimension, and the light field is primarily confined within the first waveguide 410. At cross-sectional position 2 of the photonic integrated circuit chip, away from the outer end face, there are two first waveguides 410, one second waveguide 420, and two fourth waveguides 440. The first waveguide 410 located on the left side of the lower layer has a relatively large cross-sectional dimension, while the two fourth waveguides 440 located on the upper layer and the second waveguide 420 located in the middle layer have relatively small cross-sectional dimensions. The light field is primarily confined within the first waveguide 410 on the left side of the lower layer. At position 1, a cross section of the photonic integrated circuit chip near the outer end face, the two first waveguides 410 in the lower layer, the two fourth waveguides 440 in the upper layer, and the second waveguide 420 in the middle layer are all relatively small. The light field is confined by the two first waveguides 410 in the lower layer, the second waveguide 420 in the middle layer, the two fourth waveguides 440 in the upper layer, and the surrounding silicon oxide. At this point, light coupled into the photonic integrated circuit chip 1000 from outside is ultimately coupled into the bottommost first waveguide 410.

[0132] Example 5

[0133] FIG14 shows a schematic structural diagram of a photonic integrated circuit chip provided in the fifth embodiment of the present application.

[0134] As shown in FIG14 , in the fifth embodiment of the present application, the first waveguide 410 is disposed within the second silicon oxide layer 120 . In this case, after the front-end process of the device waveguide 220 of the photonic integrated circuit chip (including fabricating at least one corresponding functional layer on the device waveguide 220 ) is completed, the first waveguide 410 can be fabricated on the side of the device waveguide 220 facing away from the supporting silicon 100 . Since the device waveguide 220 has relatively few back metal layers, the degree of freedom regarding the location of the first waveguide 410 is relatively high.

[0135] Example 6

[0136] FIG15 shows a schematic structural diagram of a photonic integrated circuit chip provided in the sixth embodiment of the present application.

[0137] As shown in Figure 15, in the sixth embodiment of the present application, when the first waveguide 410 is arranged in the second silicon oxide layer 120, the photonic integrated circuit chip 1000 further includes a fifth waveguide 450. The fifth waveguide 450 is located in the second silicon oxide layer 120, and the fifth waveguide 450 is optically coupled with the first waveguide 410 and is spaced apart from the first waveguide 410 in the thickness direction; in the thickness direction perpendicular to the supporting silicon 100, the fifth waveguide 450 extends from the inside of the photonic integrated circuit chip 1000 to the outer end surface; in the thickness direction of the supporting silicon 100, the fifth waveguide 450 is located on the side of the first waveguide 410 away from the first silicon oxide layer 110.

[0138] Optionally, the number of the fifth waveguide 450 is 1 or more.

[0139] Furthermore, in a direction from the inside of the photonic integrated circuit chip 1000 to the outer end surface, a portion of the fifth waveguide 450 is in an inverted wedge-shaped structure.

[0140] Furthermore, in a direction perpendicular to the thickness of the supporting silicon 100 , an extension length of the fifth waveguide 450 is smaller than an extension length of the first waveguide 410 , and an end portion of the fifth waveguide 450 close to the outer end surface is flush with an end portion of the first waveguide 410 close to the outer end surface.

[0141] Example 7

[0142] Figure 16 shows a schematic diagram of the structure of the photonic integrated circuit chip provided by the seventh embodiment of the present application. Figure 17 shows another schematic cross-sectional view of the edge coupler structure of the photonic integrated circuit chip provided in Figure 16 at positions 1, 2, and 3.

[0143] As shown in Figures 16 and 17, in the seventh embodiment of the present application, on the basis of the sixth embodiment, the photonic integrated circuit chip 1000 further includes a sixth waveguide 460, which is located in the first silicon oxide layer 110, and the sixth waveguide 460 is optically coupled with the first waveguide 410, and is spaced apart from the first waveguide 410 in the thickness direction; in the thickness direction perpendicular to the supporting silicon 100, the sixth waveguide 460 extends from the interior of the photonic integrated circuit chip 1000 to the outer end surface.

[0144] Optionally, the number of the sixth waveguide 460 is 1 or more.

[0145] Furthermore, in a direction from the inside of the photonic integrated circuit chip 1000 to the outer end surface, a portion of the sixth waveguide 460 is in an inverted wedge-shaped structure.

[0146] For example, as shown in FIG17 , at the cross-sectional position 3 of the photonic integrated circuit chip away from the outer end face, there is only one first waveguide 410 in the middle layer, the cross-sectional size of the first waveguide 410 is relatively large, and the light field is mainly confined in the first waveguide 410. At the cross-sectional position 2 of the photonic integrated circuit chip away from the outer end face, there is one first waveguide 410, two fifth waveguides 450, and two sixth waveguides 460. Among them, the cross-sectional size of the first waveguide 410 in the middle layer is relatively large, and the two waveguides in the upper layer are relatively large. The cross-sectional dimensions of the fifth waveguide 450 and the lower sixth waveguide 460 are relatively small, and the light field is primarily confined to the middle first waveguide 410. At cross-sectional location 1, near the outer end face of the photonic integrated circuit chip, the two lower sixth waveguides 460, the middle first waveguide 410, and the upper fifth waveguide 450 are all relatively small. The light field is collectively confined by the lower two sixth waveguides 460, the middle first waveguide 410, the upper two fifth waveguides 450, and the surrounding silicon oxide. At this point, light coupled into the photonic integrated circuit chip 1000 from outside is ultimately coupled into the middlemost first waveguide 410.

[0147] Example 8

[0148] Figure 18 shows a schematic diagram of the structure of the photonic integrated circuit chip provided by the eighth embodiment of the present application. Figure 19 shows another schematic cross-sectional view of the edge coupler structure of the photonic integrated circuit chip provided in Figure 18 at position 1.

[0149] As shown in Figures 18 and 19, in the seventh embodiment of the present application, compared to the second embodiment, in order to prevent moisture from entering the upper silicon oxide of the photonic integrated circuit chip during long-term use, thereby causing the performance of the side waveguide to deteriorate, and to prevent the surface of the photonic integrated circuit chip from being easily affected by various dirt during process engineering such as bumps and TSVs, the photonic integrated circuit chip further includes a protective layer 500. The protective layer 500 covers the surface of the second silicon oxide layer 120 away from the first silicon oxide layer 110. The material of the protective layer 500 is silicon nitride.

[0150] Furthermore, the protective layer is also beneficial to improving the scratch resistance of the surface of the photonic integrated circuit chip.

[0151] According to another aspect of the present invention, there is provided a silicon photonic integrated circuit platform, comprising the photonic integrated circuit chip described in any of the aforementioned embodiments; and an optical fiber, wherein the optical fiber comprises an optical fiber core and an optical fiber cladding covering the optical fiber core; wherein the optical fiber is aligned with the outer end surface of the photonic integrated circuit chip for optical coupling.

[0152] FIG20 shows a schematic structural diagram of a silicon photonic integration platform provided in an embodiment of the present application.

[0153] Exemplarily, as shown in FIG20 , after the optical fiber and the photonic integrated circuit chip are coupled and aligned by active alignment, they are fixed to the outer end of the edge coupler structure of the photonic integrated circuit chip by glue.

[0154] FIG21 shows a cross-sectional schematic diagram of the silicon photonic integration platform provided in an embodiment of the present application.

[0155] For example, as shown in FIG21 , in order to limit the positional movement of the optical fiber, a groove 101 is provided at a cross-sectional position of the supporting silicon near the outer end surface. The optical fiber is placed in the groove 101 .

[0156] Exemplarily, the groove 101 is a V-groove, so that the optical fiber core and the optical fiber cladding are exactly placed in the V-groove, and then glue is used to fix the optical fiber.

[0157] It should be noted that the “first”, “second”, “third”, “fourth”, “fifth” and “sixth” in this article are intended to distinguish different objects, rather than to sort the objects or limit the number of objects.

[0158] The embodiments of the present invention provide a solution for the optical interconnection between photonic integrated circuit chips and optical fibers. The solution aims to provide a specific waveguide structure on the photonic integrated circuit chip to achieve efficient coupling with ordinary single-mode optical fibers. At the same time, no suspended structures are introduced, so that the overall structure has strong mechanical stability, can pass the high-temperature and high-humidity reliability testing conditions of the photonic integrated circuit chip, and is compatible with processes such as reflow soldering and through-silicon vias.

[0159] Furthermore, the distance between the side coupler structure used for coupling in optical interconnection of photonic integrated circuits and the substrate can be optimized to prevent the light field from leaking into the substrate. The position and critical dimensions of the single-layer waveguide and multi-layer waveguide within the side coupler structure can also be flexibly arranged as needed.

[0160] The above is only a preferred embodiment of the present invention and is not intended to limit the scope of the present invention. All equivalent changes and modifications of the shape, structure, characteristics and spirit described in the scope of the claims of the present invention should be included in the scope of the claims of the present invention.

Claims

1. A photonic integrated circuit chip, characterized in that: include: A supporting silicon, a first silicon oxide layer and a second silicon oxide layer are stacked; The photonic integrated circuit chip comprises an optical device arranged in the first silicon oxide layer and a device waveguide optically connected to the optical device, and the side of the photonic integrated circuit chip has an external end face coupled to the outside world; At least one first metal layer is also provided in the first silicon oxide layer, and in the thickness direction of the supporting silicon, the at least one first metal layer is located between the optical device and the supporting silicon; The photonic integrated circuit chip also includes a first waveguide, which is arranged in the first silicon oxide layer or the second silicon oxide layer. The first waveguide is optically coupled to the device waveguide. In a thickness direction perpendicular to the supporting silicon, the first waveguide extends from the inside of the photonic integrated circuit chip to the outer end surface. The first waveguide is configured to have a first mode size on a side away from the outer end surface and a second mode size on a side close to the outer end surface, wherein the first mode size is larger than the second mode size.

2. The photonic integrated circuit chip according to claim 1, characterized in that: In the thickness direction of the supporting silicon, the spacing between the first waveguide and the supporting silicon is larger than half of the mode field diameter of an external optical fiber to be optically coupled with the photonic integrated circuit chip.

3. The photonic integrated circuit chip according to claim 2, characterized in that: From the inside of the photonic integrated circuit chip to the direction of the outer end surface, a portion of the first waveguide is in an inverted wedge-shaped structure.

4. The photonic integrated circuit chip according to claim 2, characterized in that: The number of the first waveguides is 1 or more; When there are multiple first waveguides, the multiple first waveguides are located in the same film layer and placed side by side, and at least one of the multiple first waveguides gradually becomes thinner toward the outer end surface.

5. The photonic integrated circuit chip according to claim 2, characterized in that: In the case where the first waveguide is arranged in the first silicon oxide layer, the photonic integrated circuit chip further comprises a second waveguide, the second waveguide is arranged in the second silicon oxide layer, the second waveguide is optically coupled with the first waveguide, and is spaced apart from the first waveguide in a thickness direction; In a direction perpendicular to the thickness of the supporting silicon, the second waveguide extends from the interior of the photonic integrated circuit chip to the outer end surface.

6. The photonic integrated circuit chip according to claim 5, characterized in that: A portion of the second waveguide is in a reverse wedge-shaped structure in a direction pointing from the inside of the photonic integrated circuit chip to the outer end surface.

7. The photonic integrated circuit chip according to claim 5, characterized in that: In a direction perpendicular to the thickness of the supporting silicon, an extension length of the second waveguide is smaller than an extension length of the first waveguide, and an end of the second waveguide close to the outer end surface is flush with an end of the first waveguide close to the outer end surface.

8. The photonic integrated circuit chip as claimed in claim 7, characterized in that: The number of the second waveguides is plural, and the number of the first waveguides is plural; At a cross-sectional position close to the plane where the outer end surface is located, the combination of the plurality of second waveguides and the plurality of first waveguides is arranged in a plurality of rows and / or a plurality of columns.

9. The photonic integrated circuit chip according to claim 8, characterized in that: At a cross-sectional position close to the plane where the outer end surface is located, between adjacent rows and / or columns, the plurality of second waveguides and the plurality of first waveguides are arranged in a staggered or irregular manner.

10. The photonic integrated circuit chip according to claim 7, characterized in that: At least one second waveguide among the plurality of second waveguides has a constant cross-sectional width directed from the inside of the photonic integrated circuit chip to the outer end surface.

11. The photonic integrated circuit chip according to claim 5, characterized in that: The photonic integrated circuit chip further includes a third waveguide, the third waveguide is located in the first silicon oxide layer, the third waveguide is optically coupled with the first waveguide and the second waveguide respectively, and the third waveguide is spaced apart from the first waveguide and the second waveguide respectively in a thickness direction; In the thickness direction of the supporting silicon, the third waveguide is located between the first waveguide and the second waveguide; In a direction perpendicular to the thickness of the supporting silicon, the third waveguide extends from the interior of the photonic integrated circuit chip to the outer end surface.

12. The photonic integrated circuit chip according to claim 11, wherein: The third waveguide and the device waveguide are both located in the first silicon oxide layer.

13. The photonic integrated circuit chip according to claim 11, characterized in that: In a thickness direction perpendicular to the supporting silicon, the extension length of the third waveguide is greater than that of the first waveguide, the third waveguide is optically connected to the device waveguide, and an end of the third waveguide close to the outer end surface is flush with an end of the first waveguide close to the outer end surface.

14. The photonic integrated circuit chip according to claim 13, characterized in that: In a cross-sectional direction close to the outer end surface, a plurality of first waveguides and a plurality of second waveguides surround the periphery of the third waveguide.

15. The photonic integrated circuit chip according to claim 5, characterized in that: The photonic integrated circuit chip further includes a fourth waveguide, the fourth waveguide is located in the second silicon oxide layer, the fourth waveguide is optically coupled with the first waveguide and the second waveguide respectively, and the fourth waveguide is spaced apart from the first waveguide and the second waveguide respectively in a thickness direction; In a direction perpendicular to the thickness of the supporting silicon, the fourth waveguide extends from the interior of the photonic integrated circuit chip to the outer end surface; In a thickness direction of the supporting silicon, the fourth waveguide is located on a side of the second waveguide facing away from the first waveguide.

16. The photonic integrated circuit chip according to claim 15, characterized in that: From the inside of the photonic integrated circuit chip to the direction of the outer end surface, a portion of the fourth waveguide is in an inverted wedge-shaped structure.

17. The photonic integrated circuit chip according to claim 16, characterized in that: In a direction perpendicular to the thickness of the supporting silicon, an extension length of the fourth waveguide is smaller than an extension length of the first waveguide, and an end of the fourth waveguide close to the outer end surface is flush with an end of the first waveguide close to the outer end surface.

18. The photonic integrated circuit chip according to claim 1, characterized in that: In the case where the first waveguide is arranged in the second silicon oxide layer, the photonic integrated circuit chip further comprises a fifth waveguide, the fifth waveguide is arranged in the second silicon oxide layer, the fifth waveguide is optically coupled with the first waveguide, and is spaced apart from the first waveguide in a thickness direction; In a direction perpendicular to the thickness of the supporting silicon, the fifth waveguide extends from the interior of the photonic integrated circuit chip to the outer end surface; In the thickness direction of the supporting silicon, the fifth waveguide is located on a side of the first waveguide away from the first silicon oxide layer.

19. The photonic integrated circuit chip according to claim 18, characterized in that: From the inside of the photonic integrated circuit chip to the direction of the outer end surface, a portion of the fifth waveguide is in an inverted wedge-shaped structure.

20. The photonic integrated circuit chip according to claim 19, characterized in that: In a direction perpendicular to the thickness of the supporting silicon, an extension length of the fifth waveguide is shorter than an extension length of the first waveguide, and an end of the fifth waveguide close to the outer end surface is flush with an end of the first waveguide close to the outer end surface.

21. The photonic integrated circuit chip according to claim 18, characterized in that: The photonic integrated circuit chip further includes a sixth waveguide, the sixth waveguide being located in the first silicon oxide layer, the sixth waveguide being optically coupled to the first waveguide, and being spaced apart from the first waveguide in a thickness direction; In a direction perpendicular to the thickness of the supporting silicon, the sixth waveguide extends from the interior of the photonic integrated circuit chip to the outer end surface.

22. The photonic integrated circuit chip according to claim 21, characterized in that: From the inside of the photonic integrated circuit chip to the direction of the outer end surface, a portion of the sixth waveguide is in an inverted wedge-shaped structure.

23. The photonic integrated circuit chip according to claim 22, characterized in that: In a direction perpendicular to the thickness of the supporting silicon, an extension length of the sixth waveguide is smaller than an extension length of the first waveguide, and an end of the sixth waveguide close to the outer end surface is flush with an end of the first waveguide close to the outer end surface.

24. The photonic integrated circuit chip according to claim 1, characterized in that: At least one second metal layer is also disposed in the second silicon oxide layer, and the at least one second metal layer is electrically connected to the at least one first metal layer through a metal through hole.

25. The photonic integrated circuit chip according to claim 1, characterized in that: The photonic integrated circuit chip further comprises a third silicon oxide layer, Wherein, in the thickness direction of the supporting silicon, the third silicon oxide layer is arranged between the first silicon oxide layer and the supporting silicon.

26. The photonic integrated circuit chip according to claim 1, characterized in that: The photonic integrated circuit chip further comprises a protective layer, wherein the protective layer covers a surface of the second silicon oxide layer on a side away from the first silicon oxide layer; Wherein, the material of the protective layer is silicon nitride.

27. The photonic integrated circuit chip according to claim 1, characterized in that: The optical device includes one or a combination of a photodetector, a laser, a modulator and a wavelength division multiplexer.

28. A silicon photonic integration platform, characterized in that: A photonic integrated circuit chip comprising any one of claims 1 to 27; An optical fiber, comprising an optical fiber core and an optical fiber cladding covering the optical fiber core; Wherein, the optical fiber is aligned with the outer end surface of the photonic integrated circuit chip to perform optical coupling.

29. The silicon photonic integrated platform according to claim 28, characterized in that: A groove is arranged at a cross-sectional position of the supporting silicon close to the outer end surface, and the optical fiber is placed in the groove.

Images