Display chip and display apparatus and preparation method therefor

Abstract

Provided are a display chip and a display apparatus and a preparation method therefor. The display chip comprises: an epitaxial layer, the epitaxial layer comprising a first semiconductor layer, a quantum well light-emitting layer, and a second semiconductor layer which are sequentially stacked and arranged; a first reflective layer, which is located on the side of the second semiconductor layer away from the first semiconductor layer; a first metal binding layer, which is located on the side of the first reflective layer away from an epitaxial structure; a heat dissipation layer, the heat dissipation layer comprising a first heat dissipation layer and / or a second heat dissipation layer. The first heat dissipation layer is located between the epitaxial structure and the first reflective layer, the second heat dissipation layer is located on the side of the first reflective layer away from the epitaxial structure, the second heat dissipation layer is provided with a first opening exposing the first reflective layer, and the first metal binding layer is arranged on the side of the second heat dissipation layer away from the first reflective layer and fills the first opening. The described structure may improve the heat dissipation performance of the display chip.

Description

Display chip, display device and manufacturing method thereof

[0001] This application claims priority to Chinese patent application No. 202311134552.7 filed on September 4, 2023, and the contents of the above-mentioned Chinese patent application disclosure are hereby incorporated by reference in their entirety as a part of this application. Technical Field

[0002] The present disclosure relates to a display chip, a display device and a manufacturing method thereof. Background Art

[0003] Currently, the heat dissipation performance of light-emitting diodes (LEDs) needs to be further improved. This is especially true as technology advances and LEDs become smaller. Display devices such as micro-LEDs, which have been miniaturized, face even more serious heat dissipation issues due to their higher injection current density and high brightness.

[0004] Summary of the Invention

[0005] The present disclosure provides a display chip and a display device and a manufacturing method thereof, which can improve the heat dissipation performance of the display chip.

[0006] An embodiment of the present disclosure provides a display chip, comprising:

[0007] an epitaxial layer, the epitaxial layer comprising a first semiconductor layer, a quantum well light-emitting layer, and a second semiconductor layer stacked in sequence, one of the first semiconductor layer and the second semiconductor layer being an n-type semiconductor layer and the other being a p-type semiconductor layer;

[0008] a first reflective layer, located on a side of the second semiconductor layer facing away from the first semiconductor layer;

[0009] a first metal binding layer, located on a side of the first reflective layer away from the epitaxial structure;

[0010] A heat dissipation layer, wherein the heat dissipation layer includes a first heat dissipation layer and / or a second heat dissipation layer, the first heat dissipation layer is located between the epitaxial structure and the first reflective layer, the second heat dissipation layer is located on a side of the first reflective layer away from the epitaxial structure, the second heat dissipation layer is provided with a first opening exposing the first reflective layer, and the first metal binding layer is provided on a side of the second heat dissipation layer away from the first reflective layer and fills the first opening.

[0011] An embodiment of the present disclosure provides a display device including a chip structure and a second substrate. The chip structure is formed by the aforementioned display chip, and the chip structure is bound to the second substrate via the first metal binding layer.

[0012] The present disclosure provides a method for manufacturing the aforementioned display chip, comprising the following steps:

[0013] providing an epitaxial wafer for forming the epitaxial layer;

[0014] forming the first reflective layer on a side of the second semiconductor layer of the epitaxial wafer facing away from the first semiconductor layer;

[0015] forming the first metal binding layer on the first reflective layer;

[0016] in,

[0017] Firstly, forming a first heat dissipation layer on a side of the second semiconductor layer of the epitaxial wafer facing away from the first semiconductor layer, and then forming the first reflective layer on a side of the first heat dissipation layer facing away from the second semiconductor layer;

[0018] and / or,

[0019] forming a dielectric layer on a side of the first reflective layer facing away from the epitaxial wafer;

[0020] performing patterning on the dielectric layer to form a second opening exposing the first reflective layer;

[0021] Then forming the second heat dissipation layer filling the second opening;

[0022] and then etching away the dielectric layer to form a first opening exposing the first reflective layer;

[0023] Then, the first metal binding layer is formed on a side of the second heat dissipation layer facing away from the first reflective layer, and the first metal binding layer fills the first opening.

[0024] The present disclosure provides a method for manufacturing the aforementioned display device, comprising the following steps:

[0025] According to the above-mentioned method for preparing a display chip, the display chip is prepared;

[0026] The display chip is bound to the second substrate via the first metal binding layer to manufacture the display device.

[0027] The display chip and display device provided by the present disclosure, and their manufacturing methods, employ a method of disposing a first heat dissipation layer between the epitaxial structure and the first reflective layer and / or a second heat dissipation layer having a first opening on the side of the first reflective layer facing away from the epitaxial structure. When the second heat dissipation layer is present, a first metal binding layer is located on the side of the second heat dissipation layer facing away from the first reflective layer and fills the first opening. Thus, by providing the first heat dissipation layer and / or a second heat dissipation layer with a specific structure, the heat dissipation performance of the display chip can be improved, and the chip's luminous brightness and other performance can be enhanced. The present disclosure is particularly applicable to improving the heat dissipation performance of micro-display devices such as Micro-LEDs, and enhancing their luminous brightness and other performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] FIG1 is a schematic diagram of a chip structure in which a dielectric layer is formed on a first reflective layer according to an embodiment of the present disclosure;

[0029] FIG2 is a schematic diagram of a chip structure after the dielectric layer in FIG1 is patterned according to an embodiment of the present disclosure;

[0030] FIG3 is a schematic diagram of a chip structure in which a heat dissipation sub-layer (first heat dissipation layer) is formed on the first reflective layer in FIG2 according to an embodiment of the present disclosure;

[0031] FIG4 is a schematic diagram of a chip structure after removing the dielectric layer in FIG3 according to an embodiment of the present disclosure;

[0032] FIG5 is a schematic structural diagram of a display chip manufactured after forming a first metal binding layer on the first reflective layer and the first heat dissipation layer in FIG4 according to an embodiment of the present disclosure;

[0033] FIG6 is a schematic structural diagram of the display chip in FIG4 after being bound to the second substrate according to an embodiment of the present disclosure;

[0034] FIG7 is a schematic structural diagram of the display chip of FIG6 after the base layer is removed according to an embodiment of the present disclosure;

[0035] FIG8 is a schematic structural diagram of the display chip in FIG7 after being etched into a preset chip structure according to an embodiment of the present disclosure;

[0036] FIG9 is a schematic diagram of the structure of a display device manufactured after sequentially forming various film layers on the surface of the chip structure of FIG8 according to an embodiment of the present disclosure;

[0037] FIG10 is a schematic structural diagram of another embodiment of the present disclosure after the display chip in FIG7 is etched into a preset chip structure;

[0038] FIG11 is a schematic diagram of the structure of a display device manufactured after sequentially forming various film layers on the surface of the chip structure of FIG10 according to an embodiment of the present disclosure;

[0039] FIG12 is a schematic diagram of the structure of a display chip according to another embodiment of the present disclosure;

[0040] FIG13 is a schematic structural diagram of a display device manufactured using the display chip of FIG12 according to an embodiment of the present disclosure;

[0041] FIG14 is a schematic structural diagram of a display device according to another embodiment of the present disclosure. DETAILED DESCRIPTION

[0042] In order to enable those skilled in the art to better understand the scheme of the present invention, the present invention is further described in detail below. The specific embodiments listed below are only for describing the principles and features of the present invention. The examples are only used to explain the present invention and are not intended to limit the scope of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without making creative efforts are within the scope of protection of the present invention.

[0043] An embodiment of the present disclosure provides a display chip, as shown in Figures 1 to 14, which includes: an epitaxial layer, the epitaxial layer including a first semiconductor layer, a quantum well light-emitting layer, and a second semiconductor layer stacked in sequence, one of the first semiconductor layer and the second semiconductor layer being an n-type semiconductor layer and the other being a p-type semiconductor layer; a first reflective layer, located on a side of the second semiconductor layer facing away from the first semiconductor layer; a first metal binding layer, located on a side of the first reflective layer facing away from the epitaxial structure; a heat dissipation layer, the heat dissipation layer including a first heat dissipation layer and / or a second heat dissipation layer, the first heat dissipation layer being located between the epitaxial structure and the first reflective layer, the second heat dissipation layer being located on a side of the first reflective layer facing away from the epitaxial structure, the second heat dissipation layer being provided with a first opening exposing the first reflective layer, and the first metal binding layer being provided on a side of the second heat dissipation layer facing away from the first reflective layer and filling the first opening.

[0044] Exemplarily, as shown in FIG. 1 to FIG. 11 , the display chip includes a first heat dissipation layer and a second heat dissipation layer; or, as shown in FIG. 12 to FIG. 14 , the display chip includes a second heat dissipation layer.

[0045] Specifically, the above-mentioned heat dissipation layer can be formed of a high thermal conductivity (thermal conductivity coefficient) material, and its thermal conductivity can be greater than or equal to 2000W / (m·K). By introducing a high thermal conductivity heat dissipation layer, the heat dissipation performance of the chip can be effectively alleviated, and the brightness and other performance of the display chip (such as Micro-LED) can be improved.

[0046] In some embodiments, the first heat dissipation layer may include diamond material and / or graphene material.

[0047] In some embodiments, the second heat dissipation layer may include diamond material and / or graphene material.

[0048] Specifically, the thermal conductivity of graphene material and diamond material can be approximately 5300 W / (m·K) and 2100 W / (m·K), respectively, which are higher than that of the silicon substrate and the metal film layer (for example, the thermal conductivity of the copper metal film layer and the silver metal film layer are approximately 400 W / (m·K) and 430 W / (m·K) respectively). By using diamond material and / or graphene material to form the above-mentioned heat dissipation layer, the heat dissipation performance of the chip can be further alleviated, and the brightness of the display chip and other performance can be improved.

[0049] In addition, the thickness of the first heat dissipation layer may be 100-300 nm, for example, 100 nm, 130 nm, 150 nm, 180 nm, 200 nm, 230 nm, 250 nm, 280 nm, 300 nm, or a range consisting of any two thereof.

[0050] In addition, the thickness of the second heat dissipation layer may be 10-20 μm, for example, 10 μm, 11 μm, 12 μm, 13 μm, 14 μm, 15 μm, 16 μm, 17 μm, 18 μm, 19 μm, 20 μm, or any two thereof.

[0051] Specifically, the first opening penetrates the second heat dissipation layer to expose the surface of the first reflective layer, and the first metal binding layer fills the first opening and covers the second heat dissipation layer and the first opening (that is, the projection of the first metal binding layer on the first reflective layer covers the projection of the second heat dissipation layer on the first reflective layer and the projection of the first opening on the first reflective layer).

[0052] Specifically, the second heat dissipation layer may include a plurality of heat dissipation sub-layers, and every two adjacent heat dissipation sub-layers are separated by a first opening.

[0053] The distance between the centers of two adjacent heat dissipation sub-layers may be 2-20 μm, for example, 2 μm, 5 μm, 8 μm, 10 μm, 13 μm, 15 μm, 18 μm, 20 μm, or a range consisting of any two thereof.

[0054] In addition, the size of each heat dissipation sublayer may be 1-10 μm, for example, 1 μm, 1 μm, 2 μm, 3 μm, 4 μm, 5 μm, 6 μm, 7 μm, 8 μm, 9 μm, 10 μm, or a range consisting of any two thereof.

[0055] Specifically, the projection of the heat dissipation sublayer on the first reflective layer can be circular, the size of the heat dissipation sublayer is its diameter (that is, the diameter of the projection of the heat dissipation sublayer on the first reflective layer is 1 to 10 μm), and the center of the heat dissipation sublayer is its center of the circle (that is, the distance between the centers of each two adjacent heat dissipation sublayers is the distance between the centers of the projections of the two adjacent heat dissipation sublayers on the first reflective layer).

[0056] In addition, the first metal binding layer is used to bind the display chip to the second substrate (Bonding), that is, the display chip is bound to the second substrate through the first metal binding layer. The second substrate, for example, includes a silicon substrate or a silicon-based complementary metal oxide semiconductor (CMOS) pixel driving circuit.

[0057] Specifically, the first metal binding layer includes a metal, for example, one or more of chromium (Cr), platinum (Pt), nickel (Ni), titanium (Ti), silver (Ag), etc. Exemplarily, the first metal binding layer is a multilayer structure, that is, it includes multiple metal layers, for example, a chromium layer, a platinum layer, a nickel layer, a titanium layer, a nickel layer, and a silver layer stacked in sequence on a side of the first reflective layer facing away from the first semiconductor layer.

[0058] In addition, the first reflective layer is used to enhance the light extraction efficiency of the display chip. The first reflective layer may include silver (Ag), and may specifically be a silver reflective mirror.

[0059] In addition, the thickness of the first reflective layer may be 100-300 nm, for example, 100 nm, 130 nm, 150 nm, 180 nm, 200 nm, 230 nm, 250 nm, 280 nm, 300 nm, or a range consisting of any two thereof.

[0060] The display chip of the embodiment of the present disclosure may be a vertical chip structure, such as a vertical Micro-LED chip structure. By adopting high thermal conductivity materials, the heat dissipation performance of the chip can be improved and the luminous brightness of the chip can be increased.

[0061] In one embodiment, as shown in Figures 1 to 13, the above-mentioned epitaxial layer can be an InGaN-based epitaxial structure, the first semiconductor layer is an n-type semiconductor layer, the second semiconductor layer is a p-type semiconductor layer, and the above-mentioned quantum well light-emitting layer is an InGaN-based quantum well light-emitting layer, specifically an InGaN-based quantum well light-emitting layer with 3 to 6 periods.

[0062] Specifically, the quantum well light-emitting layer includes one or more of a blue light quantum well light-emitting layer, a green light quantum well light-emitting layer or a red light quantum well light-emitting layer, and each of the blue light quantum well light-emitting layer, the green light quantum well light-emitting layer or the red light quantum well light-emitting layer is an InGaN-based quantum well light-emitting layer, specifically 3 to 6 periods of InGaN-based quantum well light-emitting layers.

[0063] Generally, the emission band (wavelength range) of the blue light quantum well layer is 445-465 nm, the emission band of the green light quantum well layer is 515-535 nm, and the emission band of the red light quantum well layer is 615-630 nm.

[0064] In some embodiments, the blue light quantum well layer includes 3 to 6 first repeating units, each of which includes u-In stacked along a first direction. m Ga 1-m N-well layer and u-In q Ga 1-q N barrier layer (i.e. blue light quantum well layer is 3 to 6 periods of u-In m Ga 1-m N / u-In q Ga 1-q N quantum well structure), 0.18≤m≤0.21, 0.01≤q≤0.02, u-In m Ga 1-m The thickness of the N-well layer can be 2.5 to 3 nm, and the u-In q Ga 1-q The thickness of the N barrier layer may be 10-15 nm, for example, 10 nm, 11 nm, 12 nm, 13 nm, 14 nm, 15 nm, or a range consisting of any two thereof.

[0065] In addition, the first repeating unit may further include a fourth u-GaN layer, a fourth u-GaN layer, a u-In layer m Ga 1-m N-well layer and u-In q Ga 1-q N barrier layers are stacked. m Ga 1-m N-well layer and u-In q Ga 1-q The fourth u-GaN layer is deposited before the N barrier layer. This growth mode can effectively alleviate the wavelength shift problem caused by high current injection, further optimizing the performance of the display chip. The thickness of the fourth u-GaN layer can be 2-3nm.

[0066] In some embodiments, the green quantum well light-emitting layer may include 1 to 2 second repeating units and 2 to 3 third repeating units.

[0067] Each second repeating unit includes a stacked arrangement of u-In w Ga 1-w N potential well layer and the first n-GaN barrier layer (ie, the second repeating unit is u-In w Ga 1-w N / n-GaN quantum well structure), 0.24≤w≤0.25, u-In w Ga 1-w The thickness of the N-well layer is 2.5-3 nm, the thickness of the first n-GaN barrier layer is 10-15 nm, and the Hall electron concentration can be 5×10 17~6×10 17 cm -3 .

[0068] In addition, the second repeating unit may further include a fifth u-GaN layer, a fifth u-GaN layer, a u-In layer, w Ga 1-w The N-well layer and the first n-GaN barrier layer are stacked. w Ga 1-w A fifth u-GaN layer is deposited before the N-well layer and the first n-GaN barrier layer. This growth mode effectively alleviates the wavelength shift problem caused by high current injection, further optimizing the performance of the display chip. The thickness of the fifth u-GaN layer can be 2-3 nm.

[0069] Each third repeating unit includes a stacked arrangement of u-In z Ga 1-z N potential well layer and the second n-GaN barrier layer (ie the third repeating unit is u-In z Ga 1-z N / n-GaN quantum well structure), 0.25≤z≤0.28, u-In z Ga 1-z The thickness of the N-well layer is 2.5-3 nm, the thickness of the second n-GaN barrier layer is 10-15 nm, and the Hall electron concentration can be 5×10 17 ~6×10 17 cm -3 .

[0070] In addition, the third repeating unit may further include a sixth u-GaN layer, a sixth u-GaN layer, a u-In layer, z Ga 1-z The N-well layer and the second n-GaN barrier layer are stacked. z Ga 1-z A sixth u-GaN layer is deposited before the formation of the N-well layer and the second n-GaN barrier layer. This growth mode effectively alleviates the wavelength shift problem caused by high current injection, further optimizing the performance of the display chip. The thickness of the sixth u-GaN layer can be 2-3 nm.

[0071] In some embodiments, the red quantum well light emitting layer may include 1 to 6 (e.g., 3 to 6) fourth repeating units, and each fourth repeating unit (i.e., the periodic structure of the red quantum well light emitting layer) includes a seventh u-GaN layer, a u-In layer, and a seventh u-GaN layer stacked in sequence. g Ga 1-g N potential well layer (0.18≤g≤0.21, i.e. In component content is 18% to 21%), u-Inh Ga 1-h N barrier layer (0.01≤h≤0.02, i.e. In component content is 1% to 2%), u-In i Ga 1-i N potential well layer (0.25≤i≤0.28, that is, the In component content is 25% to 28%), the third n-GaN barrier layer, u-In j Ga 1-j N potential well layer (0.35≤j≤0.38, that is, the In component content is 35% to 38%), the fourth n-GaN barrier layer, u-In k Ga 1-k N layer (0.1≤k≤0.25, i.e., the In component content is 10% to 25%).

[0072] The thickness of the seventh u-GaN layer can be 2 to 3 nm, and the thickness of the u-In layer can be 2 to 3 nm. g Ga 1-g The thickness of the N-well layer can be 2.5 to 3 nm, and the u-In h Ga 1-h The thickness of the N barrier layer can be 10 to 15 nm, and the u-In i Ga 1-i The thickness of the N-well layer can be 2.5 to 3 nm, the thickness of the third n-GaN barrier layer can be 10 to 15 nm, and the thickness of the u-In j Ga 1-j The thickness of the N-well layer can be 2.5 to 3 nm, the thickness of the fourth n-GaN barrier layer can be 10 to 15 nm, and the thickness of the u-In k Ga 1-k The thickness of the N layer can be 1 to 2 nm.

[0073] 1 to 13 , the first semiconductor layer (ie, the n-type semiconductor layer) may include n-Al x Ga 1-x N / n-GaN superlattice layer, and n-Al x Ga 1-x n-Al between the N / n-GaN superlattice layer and the quantum well light-emitting layer y Ga 1-y N / n-GaN superlattice layer (lightly doped superlattice structure), n-Al x Ga 1-x The Hall electron concentration of N / n-GaN superlattice is greater than that of n-Al y Ga 1-y The Hall electron concentration in the N / n-GaN superlattice layer. By adopting the above superlattice structure, dislocation extension can be alleviated, further optimizing the performance of the display chip.

[0074] In the embodiments of the present disclosure, unless otherwise specified, the Hall electron concentration is the measured Hall electron concentration, and the Hall hole concentration is the measured Hall hole concentration.

[0075] Specifically, n-Al d Ga 1-d The N / n-GaN superlattice layer includes n-Al d Ga 1-d N layer and the fifth n-GaN layer, namely n-Al d Ga 1-d The N / n-GaN superlattice layer includes at least one fifth repeating unit, and each fifth repeating unit includes n-Al stacked along the first direction. d Ga 1-d N layer and the fifth n-GaN layer, the number of the fifth repeating unit is n-Al d Ga 1-d The period number of the N / n-GaN superlattice layer.

[0076] Wherein, 0.05≤d≤0.1, that is, the Al component content is 5% to 10%, for example, 5%, 6%, 7%, 8%, 9%, 10% or a range consisting of any two thereof.

[0077] In addition, n-Al d Ga 1-d The thickness of the N / N layer may be 2 to 2.5 nm, for example, 2 nm, 2.1 nm, 2.2 nm, 2.3 nm, 2.4 nm, 2.5 nm, or a range consisting of any two thereof.

[0078] In addition, the thickness of the fifth n-GaN layer can be 7-8 nm, for example, 7 μm, 7.1 μm, 7.2 μm, 7.3 μm, 7.4 μm, 7.5 μm, 7.6 μm, 7.7 μm, 7.8 μm, 7.9 μm, 8 μm or a range consisting of any two thereof.

[0079] In addition, n-Al d Ga 1-d The thickness of the N / n-GaN superlattice layer may be 2 to 2.5 μm, for example, 2 μm, 2.1 μm, 2.2 μm, 2.3 μm, 2.4 μm, 2.5 μm, or a range consisting of any two thereof.

[0080] In addition, n-Al d Ga 1-d The Hall electron concentration of the N / n-GaN superlattice layer can be as high as 2×10 18 ~2×10 19 cm -3 , for example 2×10 18 cm-3 , 3×10 18 cm -3 , 4×10 18 cm -3 , 5×10 18 cm -3 , 6×10 18 cm -3 , 7×10 18 cm -3 , 8×10 18 cm -3 , 9×10 18 cm -3 , 1×10 19 cm -3 or a range consisting of any two of them.

[0081] In addition, n-Al e Ga 1-e The Hall electron concentration of the N / n-GaN superlattice layer can be as high as 1×10 17 ~3×10 17 cm -3 , for example 1×10 17 cm -3 , 1.5×10 17 cm -3 , 2×10 17 cm -3 , 2.5×10 17 cm -3 , 3×10 17 cm -3 or a range consisting of any two of them.

[0082] In addition, n-Al e Ga 1-e In the N / n-GaN superlattice layer, 0.01≤e≤0.03, n-Al e Ga 1-e The thickness of the N / n-GaN superlattice layer may be 0.2-0.5 μm, for example, 0.2 μm, 0.3 μm, 0.4 μm, 0.5 μm, or a range consisting of any two thereof.

[0083] Continuing to refer to FIG. 1 to FIG. 13 , the epitaxial layer may further include a second u-GaN layer, a u-In a Ga 1-a N / u-GaN superlattice layer (non-doped superlattice structure), u-In b Ga 1-b N / n-GaN superlattice layer (doped superlattice structure), first semiconductor layer, second u-GaN layer, u-In a Ga 1-aN / u-GaN superlattice layer, u-In b Ga 1-b The N / n-GaN superlattice layer and the quantum well light-emitting layer are stacked in sequence, and the second u-GaN layer is located between the n-Al y Ga 1-y N / n-GaN superlattice layer and u-In a Ga 1-a Between N / u-GaN superlattice layers.

[0084] The second u-GaN layer mainly serves as a non-doped GaN planarization layer, and its thickness can be 15 to 20 nm.

[0085] In addition, u-In a Ga 1-a N / u-GaN superlattice layer including u-In a Ga 1-a N layer and the seventh u-GaN layer, u-In a Ga 1-a The thickness of the N layer can be 2 to 2.5 nm, 0.01≤a≤0.03 (i.e. u-In a Ga 1-a The In component content in the N layer is 1% to 3%), and the thickness of the seventh u-GaN layer can be 5 to 15 nm, for example, 5 nm, 8 nm, 10 nm, 13 nm, 15 nm or a range consisting of any two thereof.

[0086] In addition, u-In a Ga 1-a The number of periods of the N / u-GaN superlattice layer can be 3 to 5. Specifically, u-In a Ga 1-a The N / u-GaN superlattice layer includes at least one sixth repeating unit, each of which includes u-In stacked along the first direction. a Ga 1-a N layer and the seventh u-GaN layer, the number of the sixth repeating unit is u-In a Ga 1-a The period number of the N / u-GaN superlattice layer.

[0087] In addition, u-In b Ga 1-b The N / n-GaN superlattice layer includes u-In crystals staggered along a first direction. b Ga 1-b N layer and the sixth n-GaN layer, u-In b Ga 1-b The thickness of the N layer can be 2 to 2.5 nm, 0.03≤b≤0.08 (i.e. u-In b Ga1-b The In component content in N is 3% to 8%), the thickness of the sixth n-GaN layer can be 5 to 15 nm, for example, 5 nm, 8 nm, 10 nm, 13 nm, 15 nm or a range consisting of any two thereof, and the Hall electron concentration of the sixth n-GaN layer is 5×10 17 ~6×10 17 cm -3 .

[0088] In addition, u-In b Ga 1-b The number of periods of the N / n-GaN superlattice layer is 3 to 5. Specifically, u-In b Ga 1-b The N / n-GaN superlattice layer includes at least one seventh repeating unit, and each seventh repeating unit includes u-In stacked along the first direction. b Ga 1-b N layer and the sixth n-GaN layer, the number of the seventh repeating unit is u-In b Ga 1-b The period number of the N / n-GaN superlattice layer.

[0089] Continuing with Figures 1 to 13, the epitaxial layer also includes a third u-GaN layer disposed between the quantum well light-emitting layer and the second semiconductor layer (p-type semiconductor layer). In specific implementations, after the quantum well light-emitting layer is grown, the third u-GaN layer can be deposited before the second semiconductor layer is grown. The third u-GaN layer serves as a protective layer and can be 20 to 30 nm thick.

[0090] Continuing to refer to Figures 1 to 13, the second semiconductor layer may include an electron blocking layer, a hole supply layer and a p-type ohmic contact layer stacked in sequence on a side of the quantum well light-emitting layer away from the first semiconductor layer, and the third u-GaN layer is located between the electron blocking layer and the quantum well light-emitting layer.

[0091] Specifically, the electron blocking layer may include a p-AlGaN layer and / or a p-AlGaN polarization induction layer. The Al content in the p-AlGaN layer may be 20-25% and the thickness may be 20-60 nm. The Al content in the p-AlGaN polarization induction layer varies gradually along the thickness direction of the p-AlGaN polarization induction layer, specifically, it may linearly vary from 30% to 0. The theoretically calculated hole concentration of the film layer is approximately 2.5×10 18 cm -3 about.

[0092] Specifically, the p-AlGaN layer is formed of p-AlGaN material, which is generally doped with Mg. In this material system, the activation energy of Mg doping is high, making it difficult to achieve a high hole concentration and low resistivity. Therefore, relatively speaking, the use of the above-mentioned p-AlGaN polarization inducing layer can reduce the differential resistance of the device.

[0093] In addition, the hole supply layer may include a first p-GaN layer and / or a p-Al f Ga 1-f N / p-GaN superlattice layer.

[0094] The thickness of the first p-GaN layer may be 100-140 nm, for example, 100 nm, 110 nm, 120 nm, 130 nm, 140 nm, or a range consisting of any two thereof.

[0095] Among them, p-Al f Ga 1-f The N / p-GaN superlattice layer includes p-Al f Ga 1-f N layer and the second p-GaN layer, namely p-Al f Ga 1-f The N / p-GaN superlattice layer includes at least one eighth repeating unit, and each eighth repeating unit includes p-Al stacked along the first direction. f Ga 1-f N layer and the second p-GaN layer. f Ga 1-f The Hall hole concentration of the N / p-GaN superlattice layer can be as high as 1.5×10 18 ~2.5×10 18 cm -3 , 0.15≤f≤0.25 (i.e. p-Al f Ga 1-f The Al content in the N layer is 15% to 25%), and the p-Al f Ga 1-f The thickness of the N layer may be 2 to 2.5 nm, and the thickness of the second p-GaN layer may be 7 to 8 nm.

[0096] In addition, the p-type ohmic contact layer includes 4 to 6 periods of p-In c Ga 1-c N / p-GaN ohmic contact layer, p-In c Ga 1-c The N / p-GaN ohmic contact layer includes p-In c Ga 1-c N layer and the third p-GaN layer, namely p-In c Ga1-c The N / p-GaN ohmic contact layer includes at least one ninth repeating unit, each ninth repeating unit including p-In stacked along the first direction. c Ga 1-c N layer and the third p-GaN layer, the number of the ninth repeating unit is p-In c Ga 1-c The number of periods of the N / p-GaN ohmic contact layer.

[0097] Among them, 0.1≤c≤0.2 (i.e. p-In c Ga 1-c The In component content in the N layer is 10% to 20%), and the p-In c Ga 1-c The thickness of the N layer is 2 to 2.5 nm, and the thickness of the third p-GaN layer is 7 to 8 nm.

[0098] In addition, referring to FIG. 1 to FIG. 13 , the display chip further includes a first transparent conductive layer disposed between the second semiconductor layer and the first reflective layer. The first transparent conductive layer is located between the p-type ohmic contact layer and the first reflective layer.

[0099] The thickness of the first transparent conductive layer can be 20 to 100 nm, for example, 20 nm, 30 nm, 40 nm, 50 nm, 60 nm, 70 nm, 80 nm, 90 nm, 100 nm, or any two thereof. The first transparent conductive layer can include indium tin oxide (ITO), specifically an ITO film layer.

[0100] Continuing to refer to Figures 1 to 13, the above-mentioned display chip also includes a base layer, which includes a first substrate and a buffer layer. The first substrate and the buffer layer are located on the side of the first semiconductor layer away from the second semiconductor layer, and the first substrate, the buffer layer and the first semiconductor layer are stacked in sequence.

[0101] Specifically, the first substrate may include a sapphire substrate, a silicon substrate, a SiC substrate or a GaN homogeneous substrate, wherein the sapphire substrate may include a c-plane sapphire substrate or a patterned sapphire substrate, etc.

[0102] In addition, the buffer layer may include one or more of an AlN buffer layer, a graded AlGaN buffer layer with a graded Al content, and an n-AlGaN buffer layer, wherein the n-AlGaN buffer layer is formed of an n-type doped AlGaN material.

[0103] In addition, the thickness of the buffer layer may be 15 to 25 nm, for example, 15 nm, 18 nm, 20 nm, 23 nm, 25 nm, or a range consisting of any two thereof.

[0104] In addition, the matrix layer may further include a first u-GaN layer, the first u-GaN layer being located between the first semiconductor layer and the buffer layer, specifically between the buffer layer and the n-Al layer. x Ga 1-x Between N / n-GaN superlattice layers.

[0105] In addition, the thickness of the first u-GaN layer can be 3 to 4 μm. According to the X-ray diffraction test results of the first u-GaN layer, the half-peak width of the (0002) plane ω scan rocking curve of the first u-GaN layer is approximately 70 to 85 arcsec, and the half-peak width of the (10-12) plane ω scan rocking curve is 160 to 180 arcsec.

[0106] In some embodiments, as shown in FIG1 to FIG6 and FIG12, the first substrate is a sapphire substrate, the base layer includes a first substrate, an AlN buffer layer and a first u-GaN layer stacked, and the first semiconductor layer (n-Al x Ga 1-x The N / n-GaN superlattice layer is disposed on the first u-GaN layer.

[0107] In some embodiments, the first substrate is a silicon substrate, the base layer includes a first substrate, an AlN buffer layer, a graded AlGaN buffer layer and a first u-GaN layer stacked in layers, and the first semiconductor layer (n-Al x Ga 1-x The N / n-GaN superlattice layer is disposed on the first u-GaN layer.

[0108] Specifically, the Al component in the graded AlGaN buffer layer may show a decreasing trend along the direction from the buffer layer to the first u-GaN layer, and the decreasing trend may be a gradient decrease or a linear gradual decrease (i.e., the graded AlGaN buffer layer may be a linearly graded AlGaN layer, for example, linearly gradient from AlGaN to GaN (i.e., the Al component content therein linearly gradients to 0)).

[0109] In some embodiments, the first substrate is a SiC substrate, the base layer includes a first substrate and an n-AlGaN buffer layer stacked together, the first semiconductor layer (n-Al x Ga 1-x The N / n-GaN superlattice layer is placed on the n-AlGaN buffer layer. Generally speaking, GaN and SiC substrates have a smaller lattice mismatch, allowing for the direct fabrication of vertical display chips.

[0110] In some embodiments, the first substrate is a GaN homogeneous substrate, and the first semiconductor layer (n-Al x Ga 1-x The N / n-GaN superlattice layer is provided on a GaN homogeneous substrate.

[0111] In other embodiments, as shown in FIG14 , the epitaxial layer may be an AlGaInP-based epitaxial structure, specifically an AlGaInP red light epitaxial structure, such as an AlGaInP red light Micro-LED epitaxial structure. The first semiconductor layer is a p-type semiconductor layer, specifically including a p-AlGaInP confinement layer; the second semiconductor layer is an n-type semiconductor layer, specifically including an n-AlGaInP confinement layer; the quantum well light-emitting layer may be an AlGaInP-based multi-quantum well light-emitting layer; and the display chip further includes a GaAs substrate, wherein the GaAs substrate, the second semiconductor layer (n-type semiconductor layer), the quantum well light-emitting layer, and the first semiconductor layer (p-type semiconductor layer) are sequentially stacked.

[0112] An embodiment of the present disclosure also provides a display device, as shown in Figures 8 to 11, 13 and 14, which includes a chip structure and a second substrate. The chip structure is formed by the above-mentioned display chip, and the chip structure is bound to the second substrate through a first metal binding layer.

[0113] Specifically, as shown in Figures 8 to 11, 13 and 14, the chip structure includes a first semiconductor layer, a first metal binding layer, and other film layers located between the first semiconductor layer and the first metal binding layer (such as a second semiconductor layer, a quantum well light-emitting layer, etc., please refer to the above for details and will not be repeated here).

[0114] Continuing with Figures 9, 11, 13, and 14, the display device may further include a third heat dissipation layer disposed on the surface of the chip structure. The third heat dissipation layer includes a first layer portion located on a side of the first semiconductor layer facing away from the second semiconductor layer, and a second layer portion connected to the first layer portion. The second layer portion extends along the sidewalls of the chip structure until it covers the sidewalls of the first metal binding layer. The provision of the third heat dissipation layer can further improve the heat dissipation characteristics of the display device, enhancing its luminous brightness and other performance.

[0115] Specifically, the third heat dissipation layer may include a high thermal conductivity material, the thermal conductivity of which may be greater than or equal to 2000 W / (m·K). In some embodiments, the third heat dissipation layer includes a diamond material and / or a graphene material.

[0116] In addition, the thickness of the third heat dissipation layer may be 50-200 nm, for example, 50 nm, 80 nm, 100 nm, 130 nm, 150 nm, 180 nm, 200 nm, or a range consisting of any two thereof.

[0117] Continuing to refer to Figures 9, 11, 13 and 14, the above-mentioned display device may further include a second reflective layer, a passivation layer and a second transparent conductive layer sequentially arranged on the surface of the chip structure, and a third heat dissipation layer is located on the surface of the second transparent conductive layer (the passivation layer and the second transparent conductive layer are located between the second reflective layer and the third heat dissipation layer).

[0118] The second transparent conductive layer penetrates the passivation layer and the second reflective layer and is connected to the first semiconductor layer (specifically, the n-Al x Ga 1-x N / n-GaN superlattice layer is connected), that is, the second reflective layer is provided with a third opening for allowing the second transparent conductive layer to pass through, and the passivation layer is provided with a fourth opening for allowing the second transparent conductive layer to pass through. The second transparent conductive layer passes through the fourth opening of the passivation layer and the third opening of the second reflective layer respectively to be connected to the first semiconductor layer. Accordingly, the second transparent conductive layer forms a first recessed portion recessed toward the first semiconductor layer at the fourth opening and the third opening (the first recessed portion is connected to the first semiconductor layer after passing through the fourth opening and the third opening), and the third heat dissipation layer also forms a second recessed portion recessed toward the first semiconductor layer at the fourth opening and the third opening.

[0119] Continuing to refer to Figures 9, 11, 13 and 14, the display device also includes a first ohmic contact layer, which is connected to the third heat dissipation layer. The first ohmic contact layer has the same polarity as the first semiconductor layer, that is, when the first semiconductor layer is an n-type semiconductor layer (as shown in Figures 8 to 11 and 13), the first ohmic contact layer is an n-type ohmic contact layer (n-type ohmic contact electrode), and when the first semiconductor layer is a p-type semiconductor layer, the first ohmic contact layer is a p-type ohmic contact layer (as shown in Figure 14).

[0120] Exemplarily, when the first ohmic contact layer is an n-type ohmic contact layer, it may include one or more of titanium (Ti), aluminum (Al), gold (Au), etc. For example, the first ohmic contact layer includes a titanium layer, an aluminum layer, a titanium layer and a gold layer stacked in sequence.

[0121] Continuing to refer to Figures 9, 11, 13 and 14, the display device also includes an isolation layer, which covers the third heat dissipation layer. One end of the first ohmic contact layer is connected to the third heat dissipation layer, and the other end extends along the direction from the second semiconductor layer to the first semiconductor layer until it penetrates the isolation layer, that is, the side of the first ohmic contact layer facing away from the second substrate is basically flush with the side of the isolation layer facing away from the first substrate.

[0122] Specifically, the projection of the isolation layer on the second substrate covers the projections of the chip structure, the second reflective layer, the passivation layer, the second transparent conductive layer and the third heat dissipation layer on the second substrate.

[0123] Specifically, as shown in Figures 9, 11, 13 and 14, the second reflective layer includes a first reflective portion located on a side of the chip structure facing away from the second substrate, and a second reflective portion connected to the first reflective portion and extending along the side wall of the chip structure, that is, the second reflective portion is arranged around the circumference (side wall) of the chip structure and covers the entire side wall of the chip structure, that is, one end of the second extension portion in the first direction is connected to the first reflective portion, and the other end is connected to the second substrate.

[0124] In addition, the passivation layer includes a first passivation portion located on a side of the chip structure facing away from the second substrate, and a second passivation portion connected to the first passivation portion and extending along the surface of the second reflective portion, that is, the second passivation portion is also arranged around the circumference of the chip structure and covers the entire side wall of the chip structure, that is, one end of the second passivation portion in the first direction is connected to the first passivation portion, and the other end is connected to the second substrate.

[0125] In addition, the second transparent conductive layer includes a first transparent conductive portion located on a side of the chip structure facing away from the second substrate, and a second transparent conductive portion connected to the first transparent conductive portion and extending along the surface of the second passivation portion. That is, the second transparent conductive portion is also arranged around the periphery of the chip structure and covers the entire side wall of the chip structure. In other words, one end of the second transparent conductive portion in the first direction is connected to the first transparent conductive portion, and the other end is connected to the second substrate.

[0126] In addition, the third heat dissipation layer includes a first heat dissipation portion located on a side of the chip structure facing away from the second substrate, and a second heat dissipation portion connected to the first heat dissipation portion and extending along the surface of the second transparent conductive portion. That is, the second heat dissipation portion is also arranged around the circumference of the chip structure and covers the entire side wall of the chip structure. In other words, one end of the second heat dissipation portion in the first direction is connected to the first heat dissipation portion, and the other end is connected to the second substrate.

[0127] Specifically, the first transparent conductive part is connected to the first semiconductor layer after penetrating the first reflective part and the first passivation part, that is, the third opening is provided in the first reflective part, the fourth opening is provided in the first passivation part, the first recessed part is provided in the first transparent conductive part, and the second recessed part is provided in the first heat dissipation part.

[0128] For example, as shown in Figures 8, 9, 13 and 14, in the display device, the projection of the composite film layer composed of the first transparent conductive layer, the first reflective layer, the heat dissipation layer (the first heat dissipation layer and / or the second heat dissipation layer) and the first metal binding layer on the second substrate can cover the projection of the epitaxial layer (from the first semiconductor layer to the second semiconductor layer) on the second substrate, the width of the composite film layer can be greater than the width of the epitaxial layer, the projections of each film layer in the composite film layer on the second substrate can basically overlap, and the projections of each film layer in the epitaxial layer on the second substrate can basically overlap.

[0129] For example, as shown in Figures 10 and 11, in the display device, the chip structure can be a trapezoidal structure, that is, the first semiconductor layer, the first metal binding layer, and the film layers between the first semiconductor layer and the first metal binding layer can respectively be trapezoidal structures, and the width of the side away from the second substrate is smaller than the width of the side close to the second substrate.

[0130] Specifically, the second reflective layer may include Ta2O5 and / or SiO2, for example, a Ta2O5 / SiO2 reflective film. By providing the second reflective layer, light extraction efficiency can be enhanced.

[0131] Specifically, the passivation layer may include silicon oxide and / or silicon nitride (SiN x ), the silicon oxide compound may specifically include silicon dioxide (SiO2), for example, the passivation layer may include SiN x film layer and / or SiO2 film layer.

[0132] Specifically, the second transparent conductive layer may include ITO, and may specifically be an ITO film layer.

[0133] In some embodiments, the thickness of the second transparent conductive layer may be 20-100 nm, for example, 20 nm, 30 nm, 40 nm, 50 nm, 60 nm, 70 nm, 80 nm, 90 nm, 100 nm, or a range consisting of any two thereof.

[0134] In a specific implementation, the aforementioned display chip can be used and bonded to a second substrate. The base layer in the display chip is removed, and its sidewalls are etched and repaired to form a chip structure of a preset shape and size. A second reflective layer, a passivation layer, a second transparent conductive layer, and a third heat dissipation layer are then sequentially formed on the surface of the chip structure. An isolation layer covering these film layers and a first ohmic contact layer connected to the third heat dissipation layer are then formed to produce a display device.

[0135] The present disclosure also provides a method for preparing the above-mentioned display chip, comprising the following steps: providing an epitaxial wafer for forming an epitaxial layer; forming a first reflective layer on a side of the second semiconductor layer of the epitaxial wafer facing away from the first semiconductor layer; forming a first metal binding layer on the first reflective layer; wherein, first forming a first heat dissipation layer on a side of the second semiconductor layer of the epitaxial wafer facing away from the first semiconductor layer, and then forming the first reflective layer on a side of the first heat dissipation layer facing away from the second semiconductor layer (as shown in Figures 12 and 13); and / or forming a dielectric layer on a side of the first reflective layer facing away from the epitaxial wafer (as shown in Figure 1); patterning the dielectric layer to form a second opening exposing the first reflective layer (as shown in Figure 2); then forming a second heat dissipation layer filling the second opening (as shown in Figure 3); then etching and removing the dielectric layer to form a first opening exposing the first reflective layer (as shown in Figure 4); then forming a first metal binding layer on a side of the second heat dissipation layer facing away from the first reflective layer, and allowing the first metal binding layer to fill the first opening (as shown in Figure 5), thereby manufacturing the display chip.

[0136] The dielectric layer may specifically include silicon dioxide (SiO 2 ), and its thickness may be 500 nm to 1 μm.

[0137] Specifically, the number of the second openings may be multiple (consistent with the number of the heat dissipation sub-layers), and each second opening penetrates the dielectric layer to expose the surface of the first reflective layer.

[0138] When there are multiple second openings, the distance (pitch) between the centers of each two adjacent second openings can be 2 to 20 μm, for example, 2 μm, 5 μm, 8 μm, 10 μm, 13 μm, 15 μm, 18 μm, 20 μm or a range consisting of any two thereof.

[0139] In addition, the size R of the second opening may be 1 to 10 μm, for example, 1 μm, 1 μm, 2 μm, 3 μm, 4 μm, 5 μm, 6 μm, 7 μm, 8 μm, 9 μm, 10 μm, or a range consisting of any two thereof.

[0140] Specifically, the second opening can be a hole that penetrates the dielectric layer, for example, a circular hole (i.e., the projection of the second opening on the first reflective layer is substantially circular), the size of the second opening is its diameter (i.e., the diameter of the second opening is 1 to 10 μm), and the center of the second opening is its center of the circle (i.e., the distance between the centers of each two adjacent second openings as described above is the distance between the centers of the projections of the two adjacent second openings on the first reflective layer).

[0141] In addition, the epitaxial wafer may include an InGaN-based epitaxial wafer, and the formed epitaxial layer is an InGaN-based epitaxial structure, or the epitaxial wafer may include an AlGaInP-based epitaxial wafer, and the formed epitaxial layer is an AlGaInP-based epitaxial structure.

[0142] In the embodiments of the present disclosure, unless otherwise specified, each film layer may be formed by conventional methods of forming these film layers in the art, such as deposition or growth by magnetron sputtering (Sputter), chemical vapor deposition (CVD) (such as metal organic chemical vapor deposition (MOCVD), microwave plasma chemical vapor deposition (MPCVD)), 3D inkjet printing, etc.

[0143] The following takes InGaN-based epitaxial wafer as an example to further introduce its preparation process.

[0144] As mentioned above, the display chip further includes a base layer, and the preparation process further includes a process of sequentially forming a buffer layer, a first u-GaN layer and other film layers on the first substrate to obtain the base layer.

[0145] Specifically, when the first substrate is a sapphire substrate, an AlN buffer layer is epitaxially grown on the first substrate using a Sputter device, and then a first u-GaN layer is grown using an MOCVD device to obtain a base layer.

[0146] When the first substrate is a silicon substrate, an MOCVD device can be used to epitaxially grow an AlN buffer layer, a graded AlN buffer layer, etc., and then epitaxially grow a first u-GaN layer to obtain a base layer.

[0147] When the first substrate is a SiC substrate, an n-AlGaN buffer layer may be formed on the first substrate using an n-type doped AlGaN material to obtain the base layer.

[0148] In the preparation process of the above-mentioned InGaN-based epitaxial wafer, after the base layer is prepared, MOCVD or other methods can be used to sequentially epitaxially grow n-AlGaN layers on the surface of the base layer (i.e., the side of the first u-GaN layer (or n-AlGaN buffer layer) facing away from the first substrate). x Ga 1-x N / n-GaN superlattice layer and n-Al y Ga 1-y An N / n-GaN superlattice layer is formed to form a first semiconductor layer.

[0149] When the first substrate is a GaN homogeneous substrate, n-Al can be grown directly on the first substrate. x Ga 1-x N / n-GaN superlattice layer and n-Al y Ga 1-yAn N / n-GaN superlattice layer is formed to form a first semiconductor layer.

[0150] Subsequently, in n-Al y Ga 1-y A second u-GaN layer (non-doped GaN planarization layer) is epitaxially grown on the N / n-GaN superlattice layer; u-In is then deposited on the second u-GaN layer. a Ga 1-a N / u-GaN superlattice layer, and then u-In a Ga 1-a u-In grown on N / u-GaN superlattice layer b Ga 1-b N / n-GaN superlattice layer.

[0151] Later, at u-In b Ga 1-b An InGaN-based quantum well light-emitting layer is epitaxially grown on the N / n-GaN superlattice layer.

[0152] Subsequently, a third u-GaN layer is deposited on the quantum well light-emitting layer.

[0153] Subsequently, an electron blocking layer, a hole supply layer (such as depositing a first p-GaN layer), a p-type ohmic contact layer (such as depositing a p-In layer) and a second hole supply layer (such as depositing a first p-GaN layer) are sequentially grown on the third u-GaN layer. c Ga 1-c N / p-GaN ohmic contact layer, etc.).

[0154] Subsequently, a first transparent conductive layer is formed on the p-type ohmic contact layer to produce an InGaN-based epitaxial wafer. Specifically, an ITO film layer can be deposited on the p-type ohmic contact layer and annealed to form the first transparent conductive layer. The annealing process can improve the transmittance of the ITO film layer (first transparent conductive layer) and reduce the material resistance.

[0155] Subsequently, a first reflective layer is formed on the first transparent conductive layer (eg, by depositing an Ag reflective mirror).

[0156] Subsequently, as shown in FIG1 and FIG2, a dielectric layer (such as depositing SiO2 material) is formed on the first reflective layer and patterned to form a second opening exposing the first reflective layer (ie, the second opening penetrates the dielectric layer).

[0157] Subsequently, as shown in FIG3 , a second heat dissipation layer is formed on the patterned dielectric layer. For example, diamond material may be deposited by MPCVD or 3D inkjet printing to form the second heat dissipation layer.

[0158] 4, the dielectric layer is etched away to expose the first reflective layer covered by the patterned dielectric layer. When the dielectric layer is made of SiO2, a BOE solution can be used to etch the dielectric layer until the first reflective layer is exposed.

[0159] Subsequently, as shown in FIG5 , a metal material for forming a first metal binding layer is deposited on the second heat dissipation layer and the first reflective layer not covered by the second heat dissipation layer (i.e., the first reflective layer exposed after removing the dielectric layer) to form a first metal binding layer, thereby manufacturing a display chip.

[0160] In other embodiments, as shown in FIG12 , after forming the first transparent conductive layer, a first heat dissipation layer can be formed on the first transparent conductive layer. For example, graphene material is deposited by CVD, 3D inkjet printing, etc., and annealed by vacuum annealing and / or laser annealing to form the first heat dissipation layer. In combination with vacuum annealing or laser annealing, the material density and electrical conductivity of the first heat dissipation layer can be improved. Subsequently, a first reflective layer, a second heat dissipation layer, and a first metal binding layer can be sequentially formed on the first heat dissipation layer (the formation method is described above and will not be repeated here) to obtain a display chip having a first heat dissipation layer and a second heat dissipation layer.

[0161] The embodiment of the present disclosure further provides a method for preparing the aforementioned display device, comprising the following steps: preparing a display chip according to the aforementioned method for preparing a display chip; and binding the display chip to a second substrate via a first metal binding layer to prepare a display device.

[0162] Specifically, the process of binding the display chip to the second substrate through the first metal binding layer may include: depositing the second metal binding layer on the second substrate, and then binding (connecting) the first metal binding layer of the display chip and the second metal binding layer of the second substrate.

[0163] Specifically, the second metal binding layer includes a metal, for example, one or more of chromium (Cr), platinum (Pt), silver (Ag), indium (In), etc. Exemplarily, the second metal binding layer is a multilayer structure, that is, it includes multiple metal layers, for example, a chromium layer, a platinum layer, a silver layer, an indium layer, etc., which are sequentially stacked on the second substrate.

[0164] Specifically, as mentioned above, the second substrate may include a silicon substrate or a silicon-based complementary metal oxide semiconductor (CMOS) pixel driving circuit.

[0165] In some embodiments, the epitaxial wafer is an InGaN-based epitaxial wafer. As mentioned above, the InGaN-based epitaxial wafer further includes a base layer located on the side of the first semiconductor layer away from the second semiconductor layer. The method for preparing the display device further includes the following steps S101 to S105.

[0166] S101 , bonding the display chip to the second substrate via a first metal bonding layer (as shown in FIG6 ).

[0167] S102 , removing the base layer to expose the first semiconductor layer (as shown in FIG. 7 ).

[0168] In specific implementation, the substrate and the first u-GaN layer and other film layers in the above-mentioned base layer can be removed by conventional methods in the art. For example, when the first substrate in the base layer is a sapphire substrate, the sapphire substrate can be removed by a laser lift-off (LLO) process; when the first substrate in the base layer is a silicon substrate, the silicon substrate can be removed by wet etching; when the first substrate in the base layer is a SiC substrate, it can be removed by laser lift-off or grinding.

[0169] For example, when the first substrate in the base layer is a sapphire substrate, after the display chip is bonded to the second substrate, the sapphire substrate can be removed using a laser lift-off (LLO) process, and the first u-GaN layer can be etched using an inductively coupled plasma etching (ICP-RIE) process until the first semiconductor layer is etched (i.e., the first semiconductor layer is exposed), and the first semiconductor layer is planarized and polished before proceeding to subsequent steps.

[0170] S103 , then, etching the display chip according to preset parameters of the chip structure to form a chip structure (as shown in FIG. 8 and FIG. 10 ).

[0171] In a specific implementation, the display chip can be etched (primarily etching its sidewalls) according to parameters such as a preset pixel size and pixel pitch of the display device. Specifically, an ICP-RIE process can be used for etching to form a chip structure that meets the preset parameters such as the size. For example, a blue chip (the quantum well light-emitting layer of the display chip is a blue quantum well light-emitting layer), a green chip (the quantum well light-emitting layer of the display chip is a green quantum well light-emitting layer), and a red chip (the quantum well light-emitting layer of the display chip is a red quantum well light-emitting layer) can be prepared according to the aforementioned display chip preparation method. Then, according to parameters such as different pixel sizes and pixel pitches, the blue chip, green chip, and red chip are etched to form a blue chip structure (B), a green chip structure (G), and a red chip structure (R), respectively. Then, according to the preparation method of the display device of the embodiment of the present disclosure, the blue chip structure (B), the green chip structure (G), and the red chip structure (R) are bonded to a second substrate to prepare an RGB Micro-LED chip.

[0172] Among them, after the display chip is etched, a sidewall repair process (such as wet etching, etc.) can be used to repair the etched interface (such as the sidewall surface) of the formed chip structure to reduce the defect density, and then proceed to the subsequent step (forming a second reflective layer on the surface of the chip structure).

[0173] S104. Then, a second reflective layer, a passivation layer, a second transparent conductive layer, and a third heat dissipation layer are sequentially formed on the surface of the chip structure, wherein the second transparent conductive layer is connected to the first semiconductor layer after penetrating the passivation layer and the second reflective layer (as shown in FIG. 9 , FIG. 11 , and FIG. 13 ).

[0174] For example, a Ta2O5 / SiO2 reflective film can be deposited on the surface of the chip structure to form a second reflective layer, and SiO2 / SiN can be deposited by plasma enhanced chemical vapor deposition (PECVD) or atomic layer deposition (ALD). x , to form a passivation layer.

[0175] For example, an ITO film layer can be deposited on the surface of the passivation layer and annealed to form a second transparent conductive layer. By combining the annealing process, the transmittance of the ITO film layer (second transparent conductive layer) can be improved and the material resistance can be reduced.

[0176] For example, graphene material can be deposited on the surface of the second transparent conductive layer using methods such as CVD and inkjet printing, and then annealed through processes such as vacuum annealing and / or laser annealing to form the third heat dissipation layer. Combining vacuum annealing or laser annealing can improve the material density and conductivity of the third heat dissipation layer.

[0177] S105 , forming a first ohmic contact layer connected to the third heat dissipation layer to manufacture a display device (as shown in FIG9 , FIG11 and FIG13 ) .

[0178] In some other embodiments, the epitaxial wafer is an AlGaInP-based epitaxial wafer, the AlGaInP-based epitaxial wafer includes a GaAs substrate, and the method for preparing the display device further includes the following steps S201 to S208.

[0179] S201 , etching the AlGaInP-based epitaxial wafer according to preset parameters of the chip structure.

[0180] As mentioned above, the display chip can be etched (mainly its sidewalls are etched, specifically by using ICP-RIE etching process) according to the preset pixel size and pixel pitch parameters of the display device, so as to form a chip structure that meets the preset size and other parameters after passing through subsequent steps S202 to S206.

[0181] S202 , then bonding the first semiconductor layer (p-type semiconductor layer) of the etched AlGaInP-based epitaxial wafer to a transfer substrate.

[0182] The transfer substrate may include a sapphire substrate or a silicon substrate.

[0183] A protective film layer may be provided between the transfer substrate and the first semiconductor layer, and a colloid may be provided between the protective film layer and the transfer substrate.

[0184] S203 , then removing the GaAs substrate (ie, stripping the GaAs substrate) to expose the second semiconductor layer (n-type semiconductor layer).

[0185] S204: A first reflective layer, a first metal bonding layer, and a heat dissipation layer are formed on the side of the second semiconductor layer of the epitaxial wafer facing away from the first semiconductor layer. The heat dissipation layer includes the first heat dissipation layer and / or the second heat dissipation layer, thereby producing a display chip. The detailed process for forming these layers can be found in the previous description and will not be further described here.

[0186] S205 , bonding the display chip to the second substrate through the first metal bonding layer.

[0187] S206 , removing the transfer substrate and exposing the first semiconductor layer to form a chip structure.

[0188] During implementation, the transfer substrate is peeled off, and the colloid and protective film layers are removed to expose the first semiconductor layer. A sidewall repair process (e.g., wet etching) can then be used to repair the etched interface (e.g., sidewall surface) of the resulting chip structure to reduce defect density before proceeding to the subsequent step (forming a second reflective layer on the chip structure surface).

[0189] S207: A second reflective layer, a passivation layer, a second transparent conductive layer, and a third heat dissipation layer are sequentially formed on the surface of the chip structure. The second transparent conductive layer penetrates the passivation layer and the second reflective layer and then connects to the first semiconductor layer. The formation process of these layers is described above and will not be repeated here.

[0190] S208 , forming a first ohmic contact layer connected to the third heat dissipation layer to manufacture a display device (as shown in FIG. 14 ).

[0191] In addition, as mentioned above, the display device may further include an isolation layer, and its preparation process may further include a process of forming the isolation layer. The isolation layer may include SiO2, and may specifically be a SiO2 film layer formed of SiO2.

[0192] In the description of this disclosure, “n-” means n-type doping, such as the aforementioned n-GaN layer, n-Al x Ga 1-xN / n-GaN superlattice layers and the like all represent n-type doped layers, which can use conventional dopants in the art, such as SiH4; "p-" represents p-type doping, such as the aforementioned p-GaN layer, p-AlGaN layer, p-Al f Ga 1-f N / p-GaN superlattice layers, etc., all represent p-type doped layers, which may also use conventional dopants in the art; "u-" indicates undoped, such as the aforementioned u-GaN layer, which represents an undoped gallium nitride film layer. Furthermore, unless otherwise specified, "content" refers to molar content, and the aforementioned "thickness" refers to the thickness direction parallel to the first direction, which is parallel to the direction from the first semiconductor layer to the second semiconductor layer.

[0193] In addition, terms such as "first" and "second" are used only for descriptive purposes, such as distinguishing between components to more clearly illustrate / explain the technical solution, and cannot be understood as indicating or implying the number of technical features indicated or the order with substantial significance.

[0194] In addition, unless otherwise expressly specified or limited, terms such as "disposed," "located on," "connected," and "connected" should be understood in a broad sense. For example, they may refer to fixed connections, detachable connections, or integral connections; they may refer to mechanical connections, electrical connections, or communication connections (network connections); they may refer to direct connections, indirect connections through an intermediate medium, or internal communication between two components. Those skilled in the art will understand the specific meanings of the above terms in the present invention based on the specific circumstances.

[0195] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the above embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A display chip, characterized in that: include: An epitaxial layer, the epitaxial layer comprising a first semiconductor layer, a quantum well light-emitting layer, and a second semiconductor layer stacked in sequence, one of the first semiconductor layer and the second semiconductor layer being an n-type semiconductor layer and the other being a p-type semiconductor layer; a first reflective layer, located on a side of the second semiconductor layer facing away from the first semiconductor layer; A first metal binding layer, located on a side of the first reflective layer away from the epitaxial structure; The heat dissipation layer includes a first heat dissipation layer and / or a second heat dissipation layer, the first heat dissipation layer is located between the epitaxial structure and the first reflective layer, the second heat dissipation layer is located on a side of the first reflective layer away from the epitaxial structure, the second heat dissipation layer is provided with a first opening exposing the first reflective layer, and the first metal binding layer is provided on a side of the second heat dissipation layer away from the first reflective layer and fills the first opening.

2. The display chip according to claim 1, characterized in that: The first heat dissipation layer includes diamond material and / or graphene material; And / or, the thickness of the first heat dissipation layer is 100-300 nm; And / or, the second heat dissipation layer includes diamond material and / or graphene material; And / or, the thickness of the second heat dissipation layer is 10-20 μm; And / or, the second heat dissipation layer includes multiple heat dissipation sub-layers, each two adjacent heat dissipation sub-layers are separated by the first opening, the size of the heat dissipation sub-layers is 1-10 μm, and / or, the distance between the centers of each two adjacent heat dissipation sub-layers is 2-20 μm.

3. The display chip according to claim 1, characterized in that: The epitaxial layer is an InGaN-based epitaxial structure, the first semiconductor layer is an n-type semiconductor layer, and the second semiconductor layer is a p-type semiconductor layer.

4. The display chip according to claim 3, characterized in that: The first semiconductor layer includes n-Al x Ga 1-x N / n-GaN superlattice layer, and located in the n-Al x Ga 1-x The n-Al between the N / n-GaN superlattice layer and the quantum well light emitting layer y Ga 1-y N / n-GaN superlattice layer, the n-Al x Ga 1-x The Hall electron concentration of the N / n-GaN superlattice layer is greater than that of the n-Al y Ga 1-y Hall electron concentration in N / n-GaN superlattice layer.

5. The display chip according to claim 4, characterized in that: The n-Al d Ga 1-d The Hall electron concentration of the N / n-GaN superlattice layer is 2×10 18 ~2×10 19 cm -3 ; And / or, the n-Al d Ga 1-d The N / n-GaN superlattice layer includes n-Al d Ga 1-d N layer and the fifth n-GaN layer, 0.05≤d≤0.1, the n-Al d Ga 1-d The thickness of the N layer is 2 to 2.5 nm, and the thickness of the fifth n-GaN layer is 7 to 8 nm; And / or, the n-Al d Ga 1-d The thickness of the N / n-GaN superlattice layer is 2 to 2.5 μm; And / or, the n-Al e Ga 1-e The Hall electron concentration of the N / n-GaN superlattice layer is 1×10 17 ~3×10 17 cm -3 ; And / or, the n-Al e Ga 1-e In the N / n-GaN superlattice layer, 0.01≤e≤0.03; And / or, the n-Al e Ga 1-e The thickness of the N / n-GaN superlattice layer is 0.2 to 0.5 μm.

6. The display chip according to claim 3, characterized in that: The epitaxial layer also includes a second u-GaN layer, a u-In a Ga 1-a N / u-GaN superlattice layer, u-In b Ga 1-b N / n-GaN superlattice layer, the n-type semiconductor layer, the second u-GaN layer, the u-In a Ga 1-a N / u-GaN superlattice layer, the u-In b Ga 1-b The N / n-GaN superlattice layer and the quantum well light-emitting layer are stacked in sequence; wherein, and / or, the u-In a Ga 1-a N / u-GaN superlattice layer including u-In a Ga 1-a N layer and the seventh u-GaN layer, the u-In a Ga 1-a The thickness of the N layer is 2 to 2.5 nm, 0.01≤a≤0.03, and the thickness of the seventh u-GaN layer is 5 to 15 nm; and / or, the u-In a Ga 1-a The period number of N / u-GaN superlattice layers is 3 to 5; and / or, the u-In b Ga 1-b N / n-GaN superlattice layer including u-In b Ga 1-b N layer and the sixth n-GaN layer, the u-In b Ga 1-b The thickness of the N layer is 2-2.5 nm, 0.03≤b≤0.08, the thickness of the sixth n-GaN layer is 5-15 nm, and the Hall electron concentration of the sixth n-GaN layer is 5×10 17 ~6×10 17 cm -3 ; and / or, the u-In b Ga 1-b The period number of the N / n-GaN superlattice layer is 3 to 5.

7. The display chip according to claim 3, characterized in that: The epitaxial layer further includes a third u-GaN layer disposed between the quantum well light-emitting layer and the second semiconductor layer and / or a first transparent conductive layer disposed between the second semiconductor layer and the first reflective layer.

8. The display chip according to claim 3, characterized in that: The second semiconductor layer includes an electron blocking layer, a hole supply layer and a p-type ohmic contact layer which are sequentially stacked on a side of the quantum well light-emitting layer away from the first semiconductor layer, wherein: The electron blocking layer comprises a p-AlGaN polarization induction layer, and the Al component content in the p-AlGaN polarization induction layer linearly changes from 30% to 0 in the thickness direction of the p-AlGaN polarization induction layer; And / or, the hole supply layer includes a first p-GaN layer and / or a p-Al f Ga 1-f N / p-GaN supercrystals The thickness of the first p-GaN layer is 100-140 nm; the p-Al f Ga 1-f N / p-GaN superlattice layer includes p-Al f Ga 1-f N layer and a second p-GaN layer, the p-Al f Ga 1-f The thickness of the N layer is 2 to 2.5 nm, 0.15 ≤ f ≤ 0.25, and the Hall hole concentration is 1.5 × 10 18 ~2.5×10 18 cm -3 , the thickness of the second p-GaN layer is 7 to 8 nm; And / or, the p-type ohmic contact layer includes 4 to 6 periods of p-In c Ga 1-c N / p-GaN ohmic contact layer, the p-In c Ga 1-c N / p-GaN superlattice layer includes p-In c Ga 1-c N layer and the third p-GaN layer, the p-In c Ga 1-c The thickness of the N layer is 2-2.5 nm, 0.1≤c≤0.2, and the thickness of the third p-GaN layer is 7-8 nm.

9. The display chip according to claim 3, characterized in that: It also includes a base layer, wherein the base layer includes a first substrate located on a side of the first semiconductor layer away from the second semiconductor layer; wherein, The first substrate is a sapphire substrate, the base layer further comprises an AlN buffer layer and a first u-GaN layer located between the first substrate and the first semiconductor layer, and the first semiconductor layer is disposed on the first u-GaN layer; Alternatively, the first substrate is a silicon substrate, the base layer further comprises an AlN buffer layer, a gradient AlGaN buffer layer with a gradient Al component content, and a first u-GaN layer, the first substrate, the AlN buffer layer, the gradient AlGaN buffer layer, and the first u-GaN layer are stacked in sequence, and the first semiconductor layer is arranged on the first u-GaN layer; Alternatively, the first substrate is a SiC substrate, the base layer further includes an n-AlGaN buffer layer, and the first semiconductor layer is disposed on the n-AlGaN buffer layer; Alternatively, the first substrate is a GaN homogeneous substrate, and the first semiconductor layer is disposed on the GaN homogeneous substrate.

10. The display chip according to claim 1 or 3, characterized in that: The quantum well light-emitting layer includes one or more of a blue light quantum well light-emitting layer, a green light quantum well light-emitting layer or a red light quantum well light-emitting layer.

11. The display chip according to claim 10, characterized in that: The blue light quantum well layer includes 3 to 6 first repeating units, each of which includes stacked u-In m Ga 1-m N-well layer and u-In q Ga 1-q N barrier layer, 0.18≤m≤0.21, 0.01≤q≤0.02, the u-In m Ga 1-m The thickness of the N potential well layer is 2.5 to 3 nm. q Ga 1-q The thickness of the N barrier layer is 10 to 15 nm; And / or, the green light quantum well light emitting layer comprises 1 to 2 second repeating units and 2 to 3 third repeating units, wherein the second repeating unit comprises a stacked arrangement of u-In w Ga 1-w N potential well layer and the first n-GaN barrier layer, 0.24≤w≤0.25, the u-In w Ga 1-w The thickness of the N potential well layer is 2.5-3 nm, the thickness of the first n-GaN barrier layer is 10-15 nm; the third repeating unit includes a stacked u-In z Ga 1-z N potential well layer and the second n-GaN barrier layer, 0.25≤z≤0.28, the u-In z Ga 1-z The thickness of the N potential well layer is 2.5 to 3 nm, and the thickness of the second n-GaN barrier layer is 10 to 15 nm; And / or, the red light quantum well light-emitting layer includes 1 to 6 fourth repeating units, each of which includes a seventh u-GaN layer stacked in sequence, a u-In layer with a thickness of 2.5 to 3 nm, g Ga 1-g N potential well layer, u-In with a thickness of 10 to 15 nm h Ga 1-h N barrier layer, u-In with a thickness of 2.5 to 3 nm i Ga 1-i N potential well layer, a third n-GaN barrier layer with a thickness of 10 to 15 nm, and a u-In layer with a thickness of 2.5 to 3 nm j Ga 1-j N potential well layer, a fourth n-GaN barrier layer with a thickness of 10 to 15 nm, and a u-In layer with a thickness of 1 to 2 nm k Ga 1-k N layer, 0.18≤g≤0.21, 0.01≤h≤0.02, 0.25≤i≤0.28, 0.35≤j≤0.38, 0.1≤k≤0.

25.

12. The display chip according to claim 1 or 2, characterized in that: The epitaxial layer is an AlGaInP-based epitaxial structure, the first semiconductor layer is a p-type semiconductor layer, and the second semiconductor layer is an n-type semiconductor layer.

13. A display device, characterized in that: The device comprises a chip structure and a second substrate, wherein the chip structure is formed by the display chip according to any one of claims 1 to 12, and the chip structure is bound to the second substrate through the first metal binding layer.

14. The display device according to claim 13, characterized in that: It also includes a third heat dissipation layer arranged on the surface of the chip structure, the third heat dissipation layer includes a first layer portion located on a side of the first semiconductor layer away from the second semiconductor layer, and a second layer portion connected to the first layer portion, the second layer portion extends along the side wall of the chip structure until it covers the side wall of the first metal binding layer.

15. The display device according to claim 14, characterized in that: The third heat dissipation layer includes diamond material and / or graphene material; And / or, the thickness of the third heat dissipation layer is 50-200 nm.

16. The display device according to claim 14, characterized in that: It also includes a second reflective layer, a passivation layer, and a second transparent conductive layer which are sequentially arranged on the surface of the chip structure, and the third heat dissipation layer is located on the surface of the second transparent conductive layer; The second transparent conductive layer penetrates the passivation layer and the second reflective layer and contacts with the first semi-transparent conductive layer. Conductor layer connection; The display device further includes a first ohmic contact layer, wherein the first ohmic contact layer is connected to the third heat dissipation layer; The display device further includes an isolation layer, which covers the third heat dissipation layer. One end of the first ohmic contact layer is connected to the third heat dissipation layer, and the other end extends from the second semiconductor layer to the first semiconductor layer until penetrating the isolation layer.

17. A method for preparing a display chip according to any one of claims 1 to 12, characterized in that: The following steps are involved: Providing an epitaxial wafer for forming the epitaxial layer; forming the first reflective layer on a side of the second semiconductor layer of the epitaxial wafer away from the first semiconductor layer; forming the first metal binding layer on the first reflective layer; in, Firstly, forming a first heat dissipation layer on a side of the second semiconductor layer of the epitaxial wafer away from the first semiconductor layer, and then forming the first reflective layer on a side of the first heat dissipation layer away from the second semiconductor layer; and / or, forming a dielectric layer on a side of the first reflective layer away from the epitaxial wafer; Performing a patterning process on the dielectric layer to form a second opening exposing the first reflective layer; Then forming the second heat dissipation layer filling the second opening; Then etching and removing the dielectric layer to form a first opening exposing the first reflective layer; Then, the first metal binding layer is formed on a side of the second heat dissipation layer away from the first reflective layer, and the first metal binding layer fills the first opening.

18. The method for preparing a display chip according to claim 17, characterized in that: The dielectric layer includes silicon dioxide.

19. A method for preparing a display device according to any one of claims 13 to 16, characterized in that: The following steps are involved: The display chip is obtained according to the method for preparing the display chip according to claim 17 or 18; The display chip is bonded to the second substrate via the first metal bonding layer to obtain the The display device.

20. The method for manufacturing a display device according to claim 19, characterized in that: The epitaxial wafer is an InGaN-based epitaxial wafer, and the InGaN-based epitaxial wafer further includes a substrate layer located on a side of the first semiconductor layer away from the second semiconductor layer. The method for preparing the display device further includes: Binding the display chip to the second substrate through the first metal binding layer; removing the base layer to expose the first semiconductor layer; Then, etching the display chip according to preset parameters of the chip structure to form the chip structure; Then, forming a second reflective layer, a passivation layer, a second transparent conductive layer and a third heat dissipation layer in sequence on the surface of the chip structure, wherein the second transparent conductive layer penetrates the passivation layer and the second reflective layer and is connected to the first semiconductor layer; Then forming a first ohmic contact layer connected to the third heat dissipation layer; or, The epitaxial wafer is an AlGaInP-based epitaxial wafer, and the AlGaInP-based epitaxial wafer includes a GaAs substrate. The method for preparing the display device further includes: Etching the AlGaInP-based epitaxial wafer according to preset parameters of the chip structure; Then, the first semiconductor layer of the etched AlGaInP-based epitaxial wafer is bound to a transfer substrate; Then, removing the GaAs substrate to expose the second semiconductor layer; Then, forming the first reflective layer, the first metal binding layer and a heat dissipation layer on the side of the second semiconductor layer of the epitaxial wafer away from the first semiconductor layer, wherein the heat dissipation layer includes the first heat dissipation layer and / or the second heat dissipation layer, to obtain the display chip; Binding the display chip to the second substrate through the first metal binding layer; Then removing the transfer substrate and exposing the first semiconductor layer to form the chip structure; Then, forming a second reflective layer, a passivation layer, a second transparent conductive layer and a third heat dissipation layer in sequence on the surface of the chip structure, wherein the second transparent conductive layer penetrates the passivation layer and the second reflective layer and is connected to the first semiconductor layer; A first ohmic contact layer connected to the third heat dissipation layer is then formed.

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