Full-color micro-led chip, display device, and manufacturing method

Abstract

The present disclosure provides a full-color Micro-LED chip, a display device, and a manufacturing method. The full-color Micro-LED chip comprises a functional layer provided on a substrate layer; the functional layer comprises an n-type semiconductor layer and a quantum well layer which are stacked in a second direction; the functional layer comprises at least one unit group; each unit group comprises a first subunit, a second subunit, and a third subunit which are distributed in a first direction; the first direction intersects with the second direction; and the surface of a blue light quantum well layer of the first subunit facing away from the n-type semiconductor layer, the surface of a green light quantum well layer of the second subunit facing away from the n-type semiconductor layer, and the surface of a red light quantum well layer of the third subunit facing away from the n-type semiconductor layer are flush with one another. According to the present disclosure, simultaneous monolithic integration of RGB full-color Micro-LED chips can be achieved, and the advantages of simple manufacturing process and the like are achieved.

Description

A full-color Micro-LED chip and display device and its preparation method

[0001] This application claims priority to Chinese Patent Application No. 202311133201.4 filed on September 4, 2023, and the contents of the above-mentioned Chinese patent application disclosure are hereby incorporated by reference in their entirety as a part of this application. Technical Field

[0002] The present disclosure relates to a full-color Micro-LED chip and display device and a method for manufacturing the same. Background Art

[0003] At present, the main solutions for achieving full-color micro-light-emitting diodes (Micro-LEDs) include InGaN-based blue light (B), green light (G) and red light (R) solutions, InGaN-based blue light, green light and AlGaInP-based red light solutions, and InGaN-based blue light Micro-LED and red and green quantum dot color conversion solutions to achieve full-color display.

[0004] Among them, due to factors such as the different film-forming processes of the blue quantum well layer, green quantum well layer and red quantum well layer, InGaN material needs to independently grow blue, green and red LEDs on a sapphire substrate or a silicon substrate to achieve RGB full color, followed by the Micro-LED chip manufacturing process in sequence, and finally the silicon-based pixel driving circuit bonding (Bonding), or it can be integrated into the silicon-based pixel driving circuit through "mass transfer" to achieve RGB full-color display, and the preparation process is complicated.

[0005] Summary of the Invention

[0006] The present disclosure provides a full-color Micro-LED chip and display device and a preparation method thereof, which can simultaneously form a blue light quantum well layer, a green light quantum well layer and a red light quantum well layer on the same substrate layer, realize the simultaneous monolithic integration of RGB Micro-LED chips, and obtain a full-color Micro-LED chip with advantages such as a simple preparation process.

[0007] The present disclosure provides a full-color Micro-LED chip, including:

[0008] base layer;

[0009] A functional layer is provided on the base layer, the functional layer comprising an n-type semiconductor layer and a quantum well layer stacked along a second direction; the functional layer comprises at least one unit group, each of the unit groups comprising a first subunit, a second subunit and a third subunit distributed along a first direction, the first direction intersecting with the second direction; the quantum well layer of the first subunit comprises a blue quantum well layer; the quantum well layer of the second subunit comprises a blue quantum well layer and a green quantum well layer stacked in sequence on the n-type semiconductor layer along the second direction; the quantum well layer of the third subunit comprises a blue quantum well layer, a green quantum well layer and a red quantum well layer stacked in sequence on the n-type semiconductor layer along the second direction; the blue quantum well layer of the first subunit faces away from the n-type semiconductor layer, the green quantum well layer of the second subunit faces away from the n-type semiconductor layer, and the red quantum well layer of the third subunit faces away from the n-type semiconductor layer are flush with each other.

[0010] An embodiment of the present disclosure provides a full-color Micro-LED display device, including an epitaxial structure, which is formed by the above-mentioned full-color Micro-LED chip, wherein the epitaxial structure includes the functional layer; the epitaxial structure includes chip groups corresponding one-to-one to the unit groups, each chip group includes a first chip structure corresponding to the first sub-unit, a second chip structure corresponding to the second sub-unit, and a third chip structure corresponding to the third sub-unit, and each of the first chip structure, the second chip structure and the third chip structure are separated by an isolation layer.

[0011] The present disclosure provides a method for preparing the full-color Micro-LED chip, comprising the following steps:

[0012] Providing a substrate for forming the base layer, the substrate comprising a layer to be patterned, the layer to be patterned having a first side surface and a second side surface opposite to each other, and a direction from the first side surface to the second side surface is parallel to the second direction;

[0013] Performing patterning on the first side of the layer to be patterned to form at least one mesa group, each mesa group including a first mesa, a second mesa, and a third mesa distributed along the first direction, with the second side of the layer to be patterned as a reference, a height of the first mesa being greater than a height of the second mesa, and a height of the second mesa being greater than a height of the third mesa; wherein the layer to be patterned forms a patterned layer after the patterning process;

[0014] epitaxially growing an n-type semiconductor layer and a quantum well layer on the first side of the patterned layer in sequence, wherein the quantum well layer includes a blue quantum well layer, a green quantum well layer, and a red quantum well layer sequentially grown on the n-type semiconductor layer, and a side of the blue quantum well layer on the first mesa facing away from the n-type semiconductor layer, a side of the green quantum well layer on the second mesa facing away from the n-type semiconductor layer, and a side of the red quantum well layer on the third mesa facing away from the n-type semiconductor layer are flush with each other to form a flush quantum well surface;

[0015] Removing the green quantum well layer and the red quantum well layer on the first mesa, and the red quantum well layer on the second mesa through a first etching process to expose the flush quantum well surface, thereby forming at least one unit group on the base layer, each unit group including the first sub-unit on the first mesa, the second sub-unit on the second mesa, and the third sub-unit on the third mesa;

[0016] After the flush quantum well surface is exposed, a fourth u-GaN layer, an electron blocking layer, a hole supply layer and a p-type ohmic contact layer are sequentially grown on the flush quantum well surface to produce the full-color Micro-LED chip.

[0017] The present disclosure provides a method for preparing a full-color Micro-LED display device, comprising the following steps:

[0018] Providing the above-mentioned full-color Micro-LED chip, or producing a full-color Micro-LED chip according to the above-mentioned method for producing the full-color Micro-LED chip;

[0019] The full-color Micro-LED chip is bound to a pixel driving circuit element to produce a full-color Micro-LED display device.

[0020] The full-color Micro-LED chip and display device provided by the present disclosure and their preparation method simultaneously form at least one group of unit groups on the same substrate layer, each group of unit groups includes a first sub-unit, a second sub-unit and a third sub-unit distributed along a first direction, the quantum well layer of the first sub-unit includes a blue light quantum well layer, the quantum well layer of the second sub-unit includes a blue light quantum well layer and a green light quantum well layer sequentially arranged on the n-type semiconductor layer along the second direction, the quantum well layer of the third sub-unit includes a blue light quantum well layer, a green light quantum well layer and a red light quantum well layer sequentially stacked on the n-type semiconductor layer along the second direction, and the blue light quantum well layer of the first sub-unit is away from the n-type semiconductor layer. The side of the green light quantum well layer of the second sub-unit is away from the n-type semiconductor layer, and the side of the red light quantum well layer of the third sub-unit is away from the n-type semiconductor layer. That is, a flush quantum well surface is formed, thereby forming a blue light quantum well layer, a green light quantum well layer and a red light quantum well layer on the same substrate layer, realizing simultaneous monolithic integration of RGB. LED chips, that is, full-color Micro-LED chips and display devices are obtained. At the same time, the full-color Micro-LED chips and display devices disclosed in the present invention have advantages such as a simple preparation process, which is conducive to practical industrial applications. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] FIG1 is a schematic structural diagram of a substrate after a first groove is formed in an embodiment of the present disclosure;

[0022] FIG2 is a schematic structural diagram of a substrate after a second groove is formed in an embodiment of the present disclosure;

[0023] FIG3 is a schematic structural diagram of a substrate after a dielectric layer is formed on the substrate according to an embodiment of the present disclosure;

[0024] FIG4 is a schematic structural diagram of a buffer layer formed on a substrate according to an embodiment of the present disclosure;

[0025] FIG5 is a schematic structural diagram of a first u-GaN layer formed on a buffer layer according to an embodiment of the present disclosure;

[0026] FIG. 6 shows an embodiment of the present disclosure in which n is sequentially formed on the first u-GaN layer. ++ -Schematic diagram of the structure after the heavily doped GaN layer and the n-AlGaN / n-GaN superlattice layer;

[0027] FIG. 7 shows a diagram of sequentially forming a second u-GaN layer, a u-In layer, and a second u-GaN layer on the n-AlGaN / n-GaN superlattice layer according to an embodiment of the present disclosure. x”' Ga 1-x”' N / u-In y”' Ga 1-y”' Schematic diagram of the structure after the N superlattice layer;

[0028] FIG8 is a diagram of an embodiment of the present disclosure in u-Inx”' Ga 1-x”' N / u-In y”' Ga 1-y”' Schematic diagram of the structure after the quantum well layer is formed on the N superlattice layer;

[0029] FIG9 is a schematic diagram of the structure after etching away the red light quantum well layer on the first mesa and the second mesa according to an embodiment of the present disclosure;

[0030] FIG10 is a schematic diagram of a structure exposing a flush quantum well surface according to an embodiment of the present disclosure;

[0031] FIG11 is a schematic structural diagram of a full-color Micro-LED chip according to an embodiment of the present disclosure;

[0032] FIG12 is a schematic diagram of the structure of a full-color Micro-LED chip and a pixel driving circuit component after being bound together according to an embodiment of the present disclosure;

[0033] FIG13 is a schematic diagram of the structure of a full-color Micro-LED display device after removing the substrate layer during the preparation process of an embodiment of the present disclosure;

[0034] FIG14 is a schematic structural diagram of the n-type semiconductor layer after modification during the preparation of a full-color Micro-LED display device according to an embodiment of the present disclosure;

[0035] FIG15 is a schematic structural diagram of an embodiment of the present disclosure after a first chip structure, a second chip structure, and a third chip structure are formed through a second etching process;

[0036] FIG16 is a schematic structural diagram of a full-color Micro-LED display device according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0037] To help those skilled in the art better understand the solutions of the present disclosure, the present disclosure is further described below. The specific embodiments listed below merely illustrate the principles and features of the present disclosure. These examples are intended solely to illustrate the present disclosure and do not limit its scope. All other implementations derived by those skilled in the art based on the embodiments of the present disclosure without inventive effort are intended to fall within the scope of protection of the present disclosure.

[0038] The present disclosure provides a full-color Micro-LED chip, as shown in Figures 1 to 11. The full-color Micro-LED chip includes: a base layer 1; a functional layer, provided on the base layer 1, the functional layer including an n-type semiconductor layer 21 and a quantum well layer 24 stacked along a second direction; the functional layer includes at least one group of unit groups 200, each unit group 200 including a first sub-unit 201, a second sub-unit 202, and a third sub-unit 203 distributed along a first direction, the first direction intersecting with the second direction; the quantum well layer 24 of the first sub-unit 201 includes a blue light quantum well layer 241; the quantum well layer 24 of the second sub-unit 202 includes a blue light quantum well layer 241 stacked in sequence on the n-type semiconductor layer 21 along the second direction. The quantum well layer 241 and the green quantum well layer 242 (these quantum well layers 24 are arranged on the side of the n-type semiconductor layer 21 facing away from the substrate layer 1); the quantum well layer 24 of the third subunit 203 includes a blue quantum well layer 241, a green quantum well layer 242 and a red quantum well layer 243 stacked in sequence on the n-type semiconductor layer 21 along the second direction (these quantum well layers 24 are arranged on the side of the n-type semiconductor layer 21 facing away from the substrate layer 1); the blue quantum well layer 241 of the first subunit 201, the green quantum well layer 242 of the second subunit 202, and the red quantum well layer 243 of the third subunit 203 facing away from the n-type semiconductor layer 21 are flush.

[0039] That is, the first subunit 201 includes an n-type semiconductor layer 21 and a blue light quantum well layer 241 stacked in sequence on the base layer 1 along the second direction, the second subunit 202 includes an n-type semiconductor layer 21, a blue light quantum well layer 241 and a green light quantum well layer 242 stacked in sequence on the base layer 1 along the second direction, and the third subunit 203 includes an n-type semiconductor layer 21, a blue light quantum well layer 241, a green light quantum well layer 242 and a red light quantum well layer 243 stacked in sequence on the base layer 1 along the second direction.

[0040] Specifically, in the above-mentioned full-color Micro-LED chip, the number of unit groups 200 can be one or more (as shown in Figures 10 and 11, the full-color Micro-LED chip includes two unit groups 200). When there are multiple unit groups 200, these unit groups 200 can be specifically distributed along the first direction, and every two adjacent unit groups 200 are in direct contact (for example, as shown in Figures 10 and 11, the third sub-unit 203 in one unit group 200 can be in direct contact with the first sub-unit 201 in another unit group 200), that is, there is no isolation structure such as a gap or film layer between the two.

[0041] In addition, as shown in Figure 11, in each unit group 200, the second subunit 202 can be between the first subunit 201 and the third subunit 203, and each adjacent two of the first subunit 201, the second subunit 202 and the third subunit 203 are in direct contact, that is, there is no isolation structure such as a gap or film layer between the adjacent two.

[0042] Specifically, referring to Figures 2, 10 and 11, the base layer 1 includes a patterned layer located on the side of the n-type semiconductor layer 21 away from the quantum well layer 24, and the side of the patterned layer facing the n-type semiconductor layer 21 includes a mesa group corresponding one-to-one to the unit group 200, each mesa group includes a first mesa 101, a second mesa 102 and a third mesa 103 distributed along a first direction. Taking the side of the patterned layer away from the n-type semiconductor layer 21 as a reference, the height of the first mesa 101 is greater than the height of the second mesa 102, and the height of the second mesa 102 is greater than the height of the third mesa 103. The first subunit 201 is located on the first mesa 101, the second subunit 202 is located on the second mesa 102, and the third subunit 203 is located on the third mesa 103.

[0043] By arranging the above-mentioned mesas on the patterned layer to achieve a height (thickness) gradient change of the patterned layer (base layer 1), a first subunit 201 is formed on the first mesa 101, a second subunit 202 is formed on the second mesa 102, and a third subunit 203 is formed on the third mesa 103. This is conducive to making the blue light quantum well layer 241 of the first subunit 201 facing away from the n-type semiconductor layer 21, the green light quantum well layer 242 of the second subunit 202 facing away from the n-type semiconductor layer 21, and the red light quantum well layer 243 of the third subunit 203 facing away from the n-type semiconductor layer 21 flush, that is, forming a flush quantum well surface.

[0044] Generally, the height difference ΔH1 between the first mesa 101 and the second mesa 102 can be substantially equal to the thickness of the green quantum well layer 242 , and the height difference ΔH2 between the second mesa 102 and the third mesa 103 can be substantially equal to the thickness of the red quantum well layer 243 , so as to form a flush quantum well surface.

[0045] 10 and 11 , the thickness of the n-type semiconductor layer 21 of each of the first subunit 201 , the second subunit 202 and the third subunit 203 is substantially the same, and the n-type semiconductor layers 21 of each of the two subunits are staggered in the second direction. When manufacturing a full-color Micro-LED chip, the layer to be patterned, which is used to form a patterned layer, can first be patterned to form the above-mentioned mesa group on its surface. Then, an n-type semiconductor layer 21 is epitaxially grown on the surface of the patterned layer having the mesa group formed thereon. The thickness of the n-type semiconductor layer 21 formed on each of the first mesa 101, the second mesa 102, and the third mesa 103 is substantially the same. Since the heights of each of the first mesa 101, the second mesa 102, and the third mesa 103 are different, the heights of the n-type semiconductor layer 21 formed on each of the first mesa 101, the second mesa 102, and the third mesa 103 are different (i.e., the n-type semiconductor layer 21 formed on each of the first mesa 101, the second mesa 102, and the third mesa 103 are staggered in the second direction).

[0046] The height difference ΔH1 between the first mesa 101 and the second mesa 102 may be smaller than the height difference ΔH2 between the second mesa 102 and the third mesa 103 , but the present invention is not limited thereto.

[0047] In some embodiments, the height difference ΔH1 between the first mesa 101 and the second mesa 102 may be 36-54 nm, for example, 36 nm, 38 nm, 40 nm, 43 nm, 45 nm, 48 nm, 50 nm, 52 nm, 54 nm, or any two thereof.

[0048] In some embodiments, the height difference ΔH2 between the second mesa 102 and the third mesa 103 may be 39-60 nm, for example, 39 nm, 43 nm, 45 nm, 48 nm, 50 nm, 53 nm, 55 nm, 58 nm, 60 nm, or any two thereof.

[0049] Generally, the width of the first subunit 201 (also the width of each film layer in the first subunit 201), the width of the second subunit 202 (also the width of each film layer in the second subunit 202), and the width of the third subunit 203 (also the width of each film layer in the third subunit 203) can be 1.9 to 4.1 mm, for example, 1.9 mm, 2.3 mm, 2.5 mm, 2.8 mm, 3 mm, 3.3 mm, 3.5 mm, 3.8 mm, 4.1 mm or a range consisting of any two of them.

[0050] The length of the first subunit 201 (also the length of each film layer in the first subunit 201) and the width of the second subunit 202 can be equal or different; the width of the first mesa 101 is equal to the width of the first subunit 201, the width of the second mesa 102 is equal to the width of the second subunit 202, and the width of the third mesa 103 is equal to the width of the third subunit 203. The width directions of the first subunit 201, the second subunit 202, the third subunit 203, the first mesa 101, the second mesa 102, and the third mesa 103 are parallel to each other and perpendicular to the first direction and the second direction, respectively.

[0051] In addition, the length of the first subunit 201 (also the length of each film layer in the first subunit 201), the length of the second subunit 202 (also the length of each film layer in the second subunit 202), and the length of the third subunit 203 (also the length of each film layer in the third subunit 203) can be 2.5 to 7 mm, for example, 2.5 mm, 3 mm, 3.5 mm, 4 mm, 4.5 mm, 5 mm, 5.5 mm, 6 mm, 6.5 mm, 7 mm or a range consisting of any two of them.

[0052] The length of the first subunit 201 (also the length of each film layer in the first subunit 201) and the length of the second subunit 202 can be equal or different; the length of the first mesa 101 is equal to the length of the first subunit 201, the length of the second mesa 102 is equal to the length of the second subunit 202, and the length of the third mesa 103 is equal to the length of the third subunit 203. The length directions of the first subunit 201, the second subunit 202, the third subunit 203, the first mesa 101, the second mesa 102, and the third mesa 103 are parallel to each other, and are all parallel to the first direction and perpendicular to the second direction.

[0053] Continuing to refer to Figures 3 to 5, 10 and 11, the base layer 1 includes a substrate 11 located on the side of the n-type semiconductor layer 21 away from the quantum well layer 24, a first u-GaN layer (undoped GaN thin film) 14 located between the substrate 11 and the n-type semiconductor layer 21, a dielectric layer 12 and a buffer layer 13 located between the substrate 11 and the first u-GaN. The dielectric layer 12 is arranged on the circumferential side of the buffer layer 13, that is, the dielectric layer 12 is formed with a third groove 130, and the third groove 130 penetrates the dielectric layer 12 in the second direction (that is, the surface of the substrate 11 is exposed through the third groove 130). The buffer layer 13 is filled in the third groove 130, and specifically can fill the third groove 130. The side of the buffer layer 13 facing away from the substrate 11 is basically flush with the side of the dielectric layer 12 facing away from the substrate 11.

[0054] The width of the third groove 130 (ie, the width of the annular pattern formed by the unetched dielectric layer 12 ) may be 5 to 10 μm, for example, 5 μm, 6 μm, 7 μm, 8 μm, 9 μm, 10 μm, or any two thereof.

[0055] The substrate 11 may include a sapphire substrate or a silicon substrate. Generally, when the substrate 11 is a silicon substrate, the base layer 1 further includes a stress regulation layer located between the buffer layer 13 and the first u-GaN layer 14. The stress regulation layer may include an AlGaN layer, wherein the Al component content thereof decreases along the direction from the buffer layer 13 to the first u-GaN layer 14 (parallel to the second direction). The decreasing trend may be a gradient decrease or a linear gradual decrease (i.e., the stress regulation layer may be a linearly graded AlGaN layer, for example, linearly gradient from AlGaN to GaN (i.e., the Al component content thereof linearly gradients to 0)).

[0056] For example, the stress regulating layer includes Al2O3 stacked on the buffer layer 13 (ie, the side of the buffer layer 13 facing away from the substrate 11) in sequence along the second direction. 0.8 Ga 0.2 N layer, Al 0.6 Ga 0.4 N layer and Al 0.3 Ga 0.7 N layer, thereby causing the Al component content in the stress regulation layer to decrease gradually along the direction from the buffer layer 13 to the first u-GaN layer 14.

[0057] Specifically, the dielectric layer 12 may include silicon oxide and / or silicon nitride (SiN x ), the silicon oxide compound may specifically include silicon dioxide (SiO2), for example, the dielectric layer 12 may be SiN x film layer or SiO2 film layer.

[0058] In addition, the thickness of the dielectric layer 12 may be 20-40 nm, for example, 20 nm, 23 nm, 25 nm, 28 nm, 30 nm, 33 nm, 35 nm, 38 nm, 40 nm, or any two thereof.

[0059] In addition, the buffer layer 13 may include aluminum nitride (AlN), which may be specifically an AlN buffer layer. Using AlN material to form the AlN buffer layer can improve the film quality of the first u-GaN layer 14, reduce non-radiative recombination, and improve the luminescence performance of the device.

[0060] In addition, the buffer layer 13 may have a thickness of 20 to 40 nm, for example, 20 nm, 23 nm, 25 nm, 28 nm, 30 nm, 33 nm, 35 nm, 38 nm, 40 nm, or any two thereof.

[0061] In addition, the thickness of the first u-GaN layer 14 may be 2-3 μm, for example, 2 μm, 2.3 μm, 2.5 μm, 2.8 μm, 3 μm, or a range consisting of any two thereof.

[0062] Specifically, the patterned layer may be the substrate 11 (as shown in FIG. 1 to FIG. 11 ); or, the patterned layer is located between the substrate 11 and the n-type semiconductor layer 21 , for example, the patterned layer is the first u-GaN layer 14 formed on the substrate 11 .

[0063] 6 to 11 , the n-type semiconductor layer 21 may include n ++ -GaN heavily doped layer 211 and located at n ++ -GaN heavily doped layer 211 and quantum well layer 24 between the n-AlGaN / n-GaN super lattice layer 212, which is conducive to further optimize the performance of the full-color Micro-LED chip, wherein, by ++ The n-AlGaN / n-GaN superlattice layer 212 is formed between the heavily doped n-GaN layer 211 and the quantum well layer 24, which can further reduce the heavy doping process (i.e., n ++ -The extension of dislocations in the material and the regulation of stress during the formation process of the heavily doped GaN layer 211.

[0064] Specifically, n ++ The Hall electron concentration of the heavily doped GaN layer 211 can be 5×10 18 ~2×10 19 cm -3 , for example 5×10 18 cm -3 , 8×10 18 cm -3 , 1×10 19 cm -3 , 1.3×10 19 cm -3 , 1.5×10 19 cm -3 , 1.8×10 19 cm -3 , 2×10 19 cm -3 or a range consisting of any two of them.

[0065] In addition, n ++The thickness of the heavily doped GaN layer 211 may be 1.5 to 2.5 μm, for example, 1.5 μm, 1.8 μm, 2 μm, 2.3 μm, 2.5 μm, or any two thereof.

[0066] In addition, the Hall electron concentration of the n-AlGaN / n-GaN superlattice layer 212 can be 1×10 18 ~1.5×10 18 cm -3 , for example 1×10 18 cm -3 , 1.1×10 18 cm -3 , 1.2×10 18 cm -3 , 1.3×10 18 cm -3 , 1.4×10 18 cm -3 , 1.5×10 18 cm -3 or a range consisting of any two of them.

[0067] In addition, the period number of the n-AlGaN / n-GaN superlattice layer 212 is 5 to 10 (i.e., it can be ++ An n-AlGaN / n-GaN superlattice layer 212 with 5 to 10 periods is formed between the heavily doped GaN layer 211 and the quantum well layer 24 . The number of periods of the n-AlGaN / n-GaN superlattice layer 212 is, for example, 5, 6, 7, 8, 9 or 10.

[0068] Specifically, the n-AlGaN / n-GaN superlattice layer 212 includes n-AlGaN layers and n-GaN layers alternately arranged along the second direction, that is, the n-AlGaN / n-GaN superlattice layer 212 includes a plurality of repeating units, each repeating unit including an n-AlGaN layer and an n-GaN layer stacked along the second direction, and the number of repeating units is the number of periods of the n-AlGaN / n-GaN superlattice layer 212 (e.g., 5 to 10 periods). The thickness of the n-AlGaN layer can be 2 to 3 nm, for example, 2 nm, 2.3 nm, 2.5 nm, 2.8 nm, 3 nm, or any two thereof, the Al content can be 2 to 8%, for example, 2%, 3%, 4%, 5%, 6%, 7%, 8%, or any two thereof, and the thickness of the n-GaN layer can be 5 to 10 nm, for example, 5 nm, 6 nm, 7 nm, 8 nm, 9 nm, 10 nm, or any two thereof.

[0069] 7 to 11 , the functional layer may further include a second u-GaN layer 22 located between the n-type semiconductor layer 21 and the quantum well layer 24, a u-In layer 23 located between the second u-GaN layer 22 and the quantum well layer 24, and a second u-GaN layer 24 located between the second u-GaN layer 22 and the quantum well layer 24. x”' Ga 1-x”' N / u-In y”' Ga 1-y”' In the N superlattice layer 23 , 0.01≤x′″≤0.1, y′″=0 or 0.005≤y′″≤0.01.

[0070] Among them, u-In x”' Ga 1-x”' N / u-In y”' Ga 1-y”' The number of periods of the N superlattice layer 23 can be 5 to 10 (ie, 5 to 10 periods of u-In can be formed between the second u-GaN layer 22 and the quantum well layer 24). x”' Ga 1-x”' N / u-In y”' Ga 1-y”' N superlattice layer 23), u-In x”' Ga 1-x”' N / u-In y”' Ga 1-y”' The number of periods of the N superlattice layer 23 is, for example, 5, 6, 7, 8, 9, or 10.

[0071] Specifically, u-In x”' Ga 1-x”' N / u-In y”' Ga 1-y”' The N superlattice layer 23 includes u-In crystals arranged in a staggered manner along the second direction. x”' Ga 1-x”' N-layer and u-In y”' Ga 1-y”' N layer, i.e. u-In x”' Ga 1-x”' / u-In y”' Ga 1-y”' The N superlattice layer includes a plurality of repeating units, each of which includes u-In stacked along the second direction. x”' Ga 1-x”' Layer and u-In y”' Ga 1-y”' N layers, the number of repeating units is u-In x”' Ga 1-x”' / u-In y”' Ga 1-y”' N is the number of periods of the superlattice layer (e.g., 5 to 10 periods).

[0072] Among them, u-In x”' Ga 1-x”'The thickness of the N layer can be 2 to 3 nm, for example, 2 μm, 2.3 μm, 2.5 μm, 2.8 μm, 3 μm, or a range consisting of any two thereof, and the In component content is 1 to 10% (i.e., 0.01≤x″≤0.1), for example, 1%, 2%, 3%, 4%, 5%, 6%, 7%, 8%, 9%, 10%, or a range consisting of any two thereof.

[0073] In addition, u-In y”' Ga 1-y”' The thickness of the N layer can be 5 to 10 nm, for example, 5 μm, 6 μm, 7 μm, 8 μm, 9 μm, 10 μm or any two thereof, and the In component content is 0 (ie, y''=0, at which time u-In y”' Ga 1-y”' The N layer is u-GaN layer, u-In x”' Ga 1-x”' N / u-In y”' Ga 1-y”' The N superlattice layer 23 is u-In x”' Ga 1-x”' N / u-GaN superlattice layer) or 0.5-1% (i.e., 0.005≤y″≤0.01, where the In component content is, for example, 0.5%, 0.6%, 0.7%, 0.8%, 0.9%, 1% or a range consisting of any two thereof).

[0074] Specifically, referring to FIG10 and FIG11, in the full-color Micro-LED chip, each of the first subunit 201, the second subunit 202 and the third subunit 203 includes n subunits sequentially stacked along the second direction. ++ -GaN heavily doped layer 211, n-AlGaN / n-GaN superlattice layer 212, second u-GaN layer 22, u-In x”' Ga 1-x”' N / u-In y”' Ga 1-y”' N superlattice layer 23 and quantum well layer 24, wherein n of each of the first subunit 201, the second subunit 202 and the third subunit 203 ++ -GaN heavily doped layer 211 has substantially the same thickness, and the n ++ The heavily doped n-AlGaN layers 211 are staggered in the second direction, the thickness of the n-AlGaN / n-GaN superlattice layers 212 of each two are substantially the same, the thickness of the second u-GaN layers 22 of each two are staggered in the second direction, the thickness of the second u-GaN layers 22 of each two are substantially the same, the second u-GaN layers 22 of each two are staggered in the second direction, and the thickness of the u-In layers 22 of each two are substantially the same. x”' Ga 1-x”'N / u-In y”' Ga 1-y”' The thickness of the N superlattice layer 23 is substantially the same, and the u-In x”' Ga 1-x”' N / u-In y”' Ga 1-y”' The N superlattice layer 23 is staggered in the second direction, and makes the blue light quantum well layer 241 of the first subunit 201 facing away from the n-type semiconductor layer 21, the green light quantum well layer 242 of the second subunit 202 facing away from the n-type semiconductor layer 21, and the red light quantum well layer 243 of the third subunit 203 facing away from the n-type semiconductor layer 21 flush, so as to form a flush quantum well surface.

[0075] Specifically, the blue light quantum well layer 241 (blue light quantum well structure) may include 3 to 5 first repeating units, each of which includes a first potential well layer and a first barrier layer stacked along the second direction, the first potential well layer including u-In x Ga 1-x N layer, 0.18≤x≤0.2, the first barrier layer includes an n-GaN layer (the blue light quantum well structure is u-In x Ga 1-x N / n-GaN) or u-In y Ga 1-y N layer (the blue light quantum well structure is u-In x Ga 1-x N / u-In y Ga 1-y N), 0.01≤y≤0.03.

[0076] Among them, u-In x Ga 1-x The In component content of the N layer is 18-20% (ie, 0.18≤x≤0.2), for example, 18%, 18.5%, 19%, 19.5%, 20% or a range consisting of any two thereof.

[0077] In addition, the thickness of the first potential well layer may be 2-3 nm, for example, 2 μm, 2.3 μm, 2.5 μm, 2.8 μm, 3 μm, or a range consisting of any two thereof.

[0078] In addition, when the first barrier layer is an n-GaN layer, its Hall electron concentration can be 1×10 17 ~5×10 17 cm -3 , for example 1×10 17 cm -3 , 2×10 17 cm -3 , 3×10 17 cm-3 , 4×10 17 cm -3 , 5×10 17 cm -3 Or any two of them; when the first barrier layer is u-In y Ga 1-y In the N layer, the In component content can be 1-3% (ie, 0.01≤y≤0.03), for example, 1%, 1.5%, 2%, 2.5%, 3% or a range consisting of any two thereof.

[0079] In addition, the first barrier layer (n-GaN layer or u-In y Ga 1-y The thickness of the N layer may be 10 to 15 nm, for example, 10 nm, 11 nm, 12 nm, 13 nm, 14 nm, 15 nm, or a range consisting of any two thereof.

[0080] Specifically, the green quantum well layer 242 (green quantum well structure) includes 3 to 5 second repeating units, each of which includes a second potential well layer and a second barrier layer stacked along the second direction. The second potential well layer includes u-In x' Ga 1-x' N layer, 0.25≤x'≤0.28, the second barrier layer includes an n-GaN layer (the green light quantum well structure is u-In x' Ga 1-x' N / n-GaN) or u-In y' Ga 1-y' N layer (the green light quantum well structure is u-In x' Ga 1-x' N / u-In y' Ga 1-y' N), 0.03≤y'≤0.05.

[0081] Among them, the thickness of the second potential well layer can be 2 to 3 nm, for example, 2 μm, 2.3 μm, 2.5 μm, 2.8 μm, 3 μm or a range consisting of any two thereof, and the thickness of the second barrier layer can be 10 to 15 nm, for example, 10 nm, 11 nm, 12 nm, 13 nm, 14 nm, 15 nm or a range consisting of any two thereof.

[0082] In addition, when the second barrier layer is an n-GaN layer, its Hall electron concentration can be 1×10 17 ~5×10 17 cm -3 , for example 1×10 17 cm -3 , 2×10 17 cm -3, 3×10 17 cm -3 , 4×10 17 cm -3 , 5×10 17 cm -3 or a range consisting of any two of them.

[0083] In addition, when the second barrier layer is u-In y Ga 1-y In the N layer, the In component content is 3-5% (ie, 0.03≤y'≤0.05), for example, 3%, 3.5%, 4%, 4.5%, 5% or a range consisting of any two thereof.

[0084] Specifically, the red light quantum well layer 243 (red light quantum well structure) includes 3 to 5 third repeating units, each of which includes a third potential well layer, a third barrier layer and a u-Al layer stacked in sequence along the second direction. z Ga 1-z N layer, 0.1≤z≤0.25, the third potential well layer includes u-In x ”Ga 1-x "N layer, 0.35≤x"≤0.38, the third barrier layer includes n-GaN layer (the red light quantum well structure is u-In x ”Ga 1-x ”N / n-GaN / u-Al z Ga 1-z N) or u-In y ”Ga 1-y "N layer (the red light quantum well structure is u-In x ”Ga 1-x ”N / u-In y ”Ga 1-y ”N / u-Al z Ga 1-z N), 0.05≤y"≤0.08. Among them, through u-Al z Ga 1-z The N layer can confine In more in the quantum well.

[0085] Among them, the thickness of the third potential well layer can be 2 to 3 nm, for example, 2 μm, 2.3 μm, 2.5 μm, 2.8 μm, 3 μm or a range consisting of any two thereof, and the thickness of the third barrier layer can be 10 to 15 nm, for example, 10 nm, 11 nm, 12 nm, 13 nm, 14 nm, 15 nm or a range consisting of any two thereof.

[0086] In addition, when the third barrier layer is an n-GaN layer, its Hall electron concentration can be 1×10 17 ~5×1017 cm -3 , for example 1×10 17 cm -3 , 2×10 17 cm -3 , 3×10 17 cm -3 , 4×10 17 cm -3 , 5×10 17 cm -3 or a range consisting of any two of them.

[0087] In addition, when the third barrier layer is u-In y Ga 1-y In the N layer, the In component content can be 5-8% (i.e., 0.05≤y″≤0.08), for example, 5%, 5.5%, 6%, 6.5%, 7%, 7.5%, 8% or a range consisting of any two thereof.

[0088] In addition, u-Al z Ga 1-z The thickness of the N layer can be 1 to 2 nm, for example, 1 μm, 1.3 μm, 1.5 μm, 1.8 μm, 2 μm or a range consisting of any two thereof, and the Al component content can be 10 to 25% (i.e., 0.1≤z≤0.25), for example, 10%, 13%, 15%, 18%, 20%, 23%, 25% or a range consisting of any two thereof.

[0089] Continuing with Figure 11 , the functional layers of the full-color Micro-LED chip also include a fourth u-GaN layer 31, a p-type semiconductor layer 32, and a p-type ohmic contact layer 33, sequentially located on the side of the quantum well layer 24 facing away from the n-type semiconductor layer 21. The p-type semiconductor layer 32 includes an electron blocking layer 321 and a hole supply layer 322 located between the electron blocking layer 321 and the p-type ohmic contact layer 33. Specifically, the substrate layer 1, n-type semiconductor layer 21, two-dimensional well layer 24, fourth u-GaN layer 31, electron blocking layer 321, hole supply layer 322, and p-type ohmic contact layer 33 are sequentially arranged along the second direction. The projections of the fourth u-GaN layer 31, electron blocking layer 321, hole supply layer 322, and p-type ohmic contact layer 33 on the substrate layer 1 each overlap the projections of the aforementioned multiple unit groups 200 on the substrate layer 1.

[0090] Specifically, the electron blocking layer 321 may include one or more of a p-AlGaN layer, a p-AlGaN / p-GaN superlattice layer, and a p-AlGaN polarization-inducing layer (also called a p-AlGaN graded layer or a polarization-induced p-AlGaN doped layer) in which the Al component content linearly changes in the second direction.

[0091] Among them, the Al component content in the p-AlGaN layer can be 10-25% (that is, the p-AlGaN layer can be formed using a p-AlGaN material with an Al component content of 10-25%), for example, 10%, 13%, 15%, 18%, 20%, 23%, 25% or a range composed of any two thereof.

[0092] In addition, the thickness of the electron blocking layer 321 may be 20 to 60 nm, for example, 20 nm, 25 nm, 30 nm, 35 nm, 40 nm, 45 nm, 50 nm, 55 nm, 60 nm, or any two thereof.

[0093] In addition, the hole supply layer 322 may include one or more of a p-GaN layer, a p-AlGaN / p-GaN superlattice layer, and a p-AlGaN polarization inducing layer having an Al composition linearly graded in the second direction.

[0094] The thickness of the p-GaN layer may be 100-160 nm, for example, 100 nm, 110 nm, 120 nm, 130 nm, 140 nm, 150 nm, 160 nm, or a range consisting of any two thereof.

[0095] Relatively speaking, the above-mentioned electron blocking layer 321 and / or hole supply layer 322 adopts a p-AlGaN polarization induction layer, which can increase the hole concentration and conductivity of the material, increase the quantum well electron-hole recombination rate, reduce the power consumption of the full-color Micro-LED display device formed by the full-color Micro-LED chip, and improve the luminous efficiency.

[0096] For example, the hole supply layer 322 may include a double-layer p-AlGaN polarization inducing layer (ie, the double (two) p-AlGaN polarization inducing layers are stacked (laminated) along the second direction).

[0097] Specifically, in the electron blocking layer 321 or the hole supply layer 322, the p-AlGaN / p-GaN superlattice layer includes p-AlGaN layers and p-GaN layers alternately arranged along the second direction, that is, the p-AlGaN / p-GaN superlattice layer includes a plurality of repeating units, each repeating unit including a p-AlGaN layer and a p-GaN layer stacked along the second direction. The thickness of the p-AlGaN layer may be 2 to 3 nm, such as 2 μm, 2.3 μm, 2.5 μm, 2.8 μm, 3 μm, or any two thereof, and the Al content may be 20 to 25%, such as 20%, 21%, 22%, 23%, 24%, 25%, or any two thereof. The thickness of the p-GaN layer may be 5 to 10 nm, such as 5 μm, 6 μm, 7 μm, 8 μm, 9 μm, 10 μm, or any two thereof.

[0098] For example, when the hole supply layer 322 includes a p-AlGaN / p-GaN superlattice layer, the p-AlGaN / p-GaN superlattice layer may have a period number of 10 to 13 periods (ie, the number of its repeating units is 10 to 13).

[0099] In addition, the p-type ohmic contact layer 33 may include p ++ - One or more of a heavily doped GaN layer, an ITO (indium tin oxide) film layer, a p-InGaN / p-GaN superlattice layer, and a p-AlGaN polarization inducing layer with a linear gradient of Al component content in the second direction.

[0100] Among them, p ++ -GaN heavily doped layers may include Mg, p ++ -GaN heavily doped layer can have a Hall hole concentration of 2×10 20 ~4×10 20 cm -3 , for example 2×10 20 cm -3 , 2.5×10 20 cm -3 , 3×10 20 cm -3 , 3.5×10 20 cm -3 , 4×10 20 cm -3 or a range consisting of any two of them, p ++ The thickness of the heavily doped GaN layer may be 10 to 40 nm, for example, 10 nm, 15 nm, 20 nm, 25 nm, 30 nm, 35 nm, 40 nm, or a range consisting of any two thereof.

[0101] The p-InGaN / p-GaN superlattice layer includes p-InGaN layers and p-GaN layers alternately arranged along the second direction, that is, the p-InGaN / p-GaN superlattice layer includes a plurality of repeating units, each repeating unit includes a p-InGaN layer and a p-GaN layer stacked along the second direction, and the number of repeating units is the number of periods of the p-InGaN / p-GaN superlattice layer (e.g., 3 to 5 periods, that is, the p-type ohmic contact layer may include 3 to 5 periods of p-InGaN / p-GaN superlattice layers). Among them, the thickness of the p-InGaN layer can be 2 to 3 nm, for example, 2 μm, 2.3 μm, 2.5 μm, 2.8 μm, 3 μm or a range consisting of any two thereof, and the In component content can be 5 to 10%, for example, 5%, 6%, 7%, 8%, 9%, 10% or a range consisting of any two thereof; the thickness of the p-GaN layer can be 5 to 10 nm, for example, 5 nm, 6 nm, 7 nm, 8 nm, 9 nm, 10 nm or a range consisting of any two thereof.

[0102] Specifically, in the p-AlGaN polarization inducing layer described above, the Al component content linearly changes from 30% to 0 in the second direction, specifically, it can linearly change from 30% to 0 along the direction from the n-type semiconductor layer 21 (or the base layer 1 ) to the quantum well layer 24 .

[0103] The thickness of the p-AlGaN polarization inducing layer may be 60 to 80 nm, for example, 60 nm, 63 nm, 65 nm, 68 nm, 70 nm, 73 nm, 75 nm, 78 nm, 80 nm, or a range consisting of any two thereof.

[0104] Unless otherwise specified, the thickness described in the embodiments of the present disclosure is the thickness of a single layer. For example, the thickness of the above-mentioned p-AlGaN polarization inducing layer can be 60 to 80 nm, which means that the thickness of one p-AlGaN polarization inducing layer is 60 to 80 nm. Taking the hole supply layer 322 as an example, when the hole supply layer 322 includes a double-layer p-AlGaN polarization inducing layer, its thickness is the sum of the thicknesses of the two p-AlGaN polarization inducing layers, that is, 120 to 160 nm.

[0105] The embodiments of the present disclosure also provide a full-color Micro-LED display device, as shown in Figures 15 and 16. The full-color Micro-LED display device includes an epitaxial structure, which is formed by the above-mentioned full-color Micro-LED chip, wherein the epitaxial structure includes the above-mentioned functional layer, and the epitaxial structure includes chip groups 200' corresponding one-to-one to the unit groups 200. Each chip group 200' includes a first chip structure 201' corresponding to the first sub-unit 201, a second chip structure 202' corresponding to the second sub-unit 202, and a third chip structure 203' corresponding to the third sub-unit 203. Each of the first chip structure 201', the second chip structure 202' and the third chip structure 203' is separated by an isolation layer 9.

[0106] Continuing to refer to Figures 15 and 16, the epitaxial structure also includes a fourth u-GaN layer 31, a p-type semiconductor layer 32 and a p-type ohmic contact layer 33, which are sequentially located on the side of the quantum well layer 24 away from the n-type semiconductor layer 21. The p-type semiconductor layer 32 includes an electron blocking layer 321 and a hole supply layer 322 located between the electron blocking layer 321 and the p-type ohmic contact layer 33. These layers all come from the full-color Micro-LED chip.

[0107] 12 to 16 , the full-color Micro-LED display device further includes a first transparent conductive layer 41 , a reflective layer 42 , a metal binding layer 43 , and a pixel driving circuit element 5 , which are sequentially located on the side of the p-type ohmic contact layer 33 facing away from the p-type semiconductor layer 32 .

[0108] As shown in FIG16 , the isolation layer 9 extends from the n-type semiconductor layer 21 to the metal binding layer 43 and penetrates the n-type semiconductor layer 21 and the metal binding layer 43. Specifically, the isolation layer 9 extends from the n-type semiconductor layer 21 to the metal binding layer 43. ++ -GaN heavily doped layer 211 extends to the metal binding layer 43 and penetrates the n ++ -GaN heavily doped layer 211 and metal binding layer 43, that is, isolation layer 9 terminates at the side of pixel driving circuit element 5 facing the epitaxial structure, and the projections of the first chip structure 201', the second chip structure 202', the third chip structure 203', and isolation layer 9 on the pixel driving circuit element 5 are all covered by the pixel driving circuit element 5.

[0109] Specifically, the first chip structure 201' includes the functional layers in the first subunit 201, that is, the first chip structure includes an n-type semiconductor layer 21 and a quantum well layer 24 stacked along the second direction, and the quantum well layer 24 of the first chip structure 201' includes a blue light quantum well layer 241; the second chip structure 202' includes the functional layers in the second subunit 202, that is, the second chip structure 202' includes an n-type semiconductor layer 21 and a quantum well layer 24 stacked along the second direction, and the quantum well layer 24 of the second chip structure 202' includes a blue light quantum well layer 241 and a green light quantum well layer 242 located on a side of the blue light quantum well layer 241 away from the n-type semiconductor layer 21; the third chip structure 203' includes the functional layers in the third subunit 203 The functional layer, i.e., the third chip structure 203' includes an n-type semiconductor layer 21 and a quantum well layer 24 stacked along the second direction. The quantum well layer 24 of the third chip structure 203' includes a blue quantum well layer 241, a green quantum well layer 242 located on the side of the blue quantum well layer 241 facing away from the n-type semiconductor layer 21, and a red quantum well layer 243 located on the side of the green quantum well layer 242 facing away from the n-type semiconductor layer 21. The side of the blue quantum well layer 241 of the first chip structure 201' facing away from the n-type semiconductor layer 21, the side of the green quantum well layer 242 of the second chip structure 202' facing away from the n-type semiconductor layer 21, and the side of the red quantum well layer 243 of the third chip structure 203' facing away from the n-type semiconductor layer 21 are flush.

[0110] Specifically, the first chip structure 201' includes a metal binding layer 43, a reflective layer 42, a first transparent conductive layer 41, a p-type ohmic contact layer 33, a hole supply layer 322, an electron blocking layer 321, a fourth u-GaN layer 31, a blue light quantum well layer 241, a u-In layer 33, and a plurality of other layers. x”' Ga 1-x”' N / u-In y”' Ga 1-y”' N superlattice layer 23, second u-GaN layer 22, n-AlGaN / n-GaN superlattice layer 212, n ++ -GaN heavily doped layer 211; the second chip structure 202 ' comprises a metal binding layer 43, a reflective layer 42, a first transparent conductive layer 41, a p-type ohmic contact layer 33, a hole supply layer 322, an electron blocking layer 321, a fourth u-GaN layer 31, a green light quantum well layer 242, a blue light quantum well layer 241, a u-In x”' Ga 1-x”' N / u-In y”' Ga 1-y”' N superlattice layer 23, second u-GaN layer 22, n-AlGaN / n-GaN superlattice layer 212, n ++-GaN heavily doped layer 211; the third chip structure 203 ' comprises a metal binding layer 43, a reflective layer 42, a first transparent conductive layer 41, a p-type ohmic contact layer 33, a hole supply layer 322, an electron blocking layer 321, a fourth u-GaN layer 31, a red light quantum well layer 243, a green light quantum well layer 242, a blue light quantum well layer 241, a u-In x”' Ga 1-x”' N / u-In y”' Ga 1-y”' N superlattice layer 23, second u-GaN layer 22, n-AlGaN / n-GaN superlattice layer 212, n ++ -GaN heavily doped layer 211.

[0111] In some embodiments, as shown in FIG16 , the first chip structure 201 ′, the second chip structure 202 ′, and the third chip structure 203 ′ can be respectively trapezoidal, that is, the metal binding layer 43, the reflective layer 42, the first transparent conductive layer 41, the p-type ohmic contact layer 33, the hole supply layer 322, the electron blocking layer 321, the fourth u-GaN layer 31, the quantum well layer 24, the u-In ... u-In layer 33, the hole supply layer 322, the electron blocking layer 321, the fourth u-GaN layer 31, the quantum well layer 24, the u- x”' Ga 1-x”' N / u-In y”' Ga 1-y”' N superlattice layer 23, second u-GaN layer 22, n-AlGaN / n-GaN superlattice layer 212, n ++ The heavily-doped -GaN layers 211 are all trapezoidal in shape, and their lengths in the first direction gradually decrease from the n-type semiconductor layer 21 to the quantum well layer 24 .

[0112] In addition, as shown in FIG. 14 to FIG. 16 , the n-type semiconductor layer 21 of the first chip structure 201 ′ is away from the side of the quantum well layer 24 (ie, n ++ -GaN heavily doped layer 211 away from the quantum well layer 24), the n-type semiconductor layer 21 of the second chip structure 202 'away from the quantum well layer 24 (ie, n ++ -GaN heavily doped layer 211 away from the quantum well layer 24), the n-type semiconductor layer 21 of the third chip structure 203 'away from the quantum well layer 24 (ie, n ++ -The GaN heavily doped layer 211 is flush with a side facing away from the quantum well layer 24 .

[0113] Among them, n of the first chip structure 201 ′ ++ The thickness of the heavily doped GaN layer 211 is less than that of the second chip structure 202 ′. ++ -GaN heavily doped layer 211 thickness, the second chip structure 202 'n ++The thickness of the heavily doped GaN layer 211 is less than that of the third chip structure 203 ′. ++ -Thickness of the heavily doped GaN layer 211 (as shown in FIG. 14 ).

[0114] For the ++ -The film layer between the GaN heavily doped layer 211 and the quantum well layer 24 (such as the n-AlGaN / n-GaN superlattice layer 212, the second u-GaN layer 22, the u-In x”' Ga 1-x”' N / u-In y”' Ga 1-y”' N superlattice layer 23), the thickness of the film layer in each of the first chip structure 201 ′, the second chip structure 202 ′, and the third chip structure 203 ′ is substantially equal, and is also equal to its thickness in the first subunit 201 , the second subunit 202 , and the third subunit 203 .

[0115] In specific implementation, the n in the full-color Micro-LED chip can be polished by chemical polishing process and other methods. ++ -GaN heavily doped layer 211 is modified on the side away from quantum well layer 24 to repair and flatten it (in the full-color Micro-LED chip at this time, the n of the first subunit 201 is ++ -GaN heavily doped layer 211 away from the quantum well layer 24, the second subunit 202 n ++ -GaN heavily doped layer 211 away from the quantum well layer 24 and the n- ... ++ -The side of the heavily doped GaN layer 211 facing away from the quantum well layer 24 is flush); then, a gap 90 can be etched between each of the first subunit 201, the second subunit 202 and the third subunit 203 of the full-color Micro-LED chip through an etching process (as shown in FIG15 ), and then an isolation layer 9 is formed in the gap 90 (as shown in FIG16 ), so that the functional layer of the first subunit 201 forms the functional layer of the first chip structure 201 ', the functional layer of the second subunit 202 forms the functional layer of the second chip structure 202 ', and the functional layer of the third subunit 203 forms the functional layer of the third chip structure 203 '.

[0116] In addition, as shown in FIG16 , in the epitaxial structure, the surface of each of the first chip structure 201 ′, the second chip structure 202 ′ and the third chip structure 203 ′ is sequentially provided with a passivation layer 6 and a second transparent conductive layer 7, and the second transparent conductive layer 7 penetrates the passivation layer 6 and is connected to the n-type semiconductor layer 21 (specifically, the n-type semiconductor layer 21). ++ -GaN heavily doped layer 211).

[0117] Specifically, for each chip structure, the passivation layer 6 on its surface includes a first passivation portion 61 located on the side of the n-type semiconductor layer 21 away from the quantum well layer 24, and a second passivation portion 62 arranged on the side wall of the chip structure. One end of the second passivation portion 62 away from the first passivation portion 61 extends outward along the first direction (along the direction away from the chip structure where it is located) to form a first extension portion 63, that is, the first extension portion 63 and the first passivation portion 61 are respectively located on opposite sides of the second passivation portion 62 in the second direction, and the extension direction of the first extension portion 63 is basically parallel to the first direction.

[0118] Specifically, for each chip structure, the first extension portion 63 of the passivation layer 6 on its surface can directly contact the pixel driving circuit element 5, and the outer edge of the first extension portion 63 in the first direction (that is, the edge on the side away from the second passivation portion 62) does not exceed the outer edge of the pixel driving circuit element 5 in the first direction.

[0119] In addition, for each chip structure, the second transparent conductive layer 7 on its surface includes a first layer portion 71 located on the side of the passivation layer 6 away from the n-type semiconductor layer 21 in the second direction, and a second layer portion 72 arranged on the side wall of the chip structure. One end of the second layer portion 72 away from the first layer portion 71 extends outward along the first direction to form a second extension portion 73, that is, the second extension portion 73 and the first layer portion 71 are respectively located on opposite sides of the second layer portion 72 in the second direction, and the extension direction of the second extension portion 73 is basically parallel to the first direction.

[0120] The second transparent conductive layer 7 further includes a third extension portion 74 connected to the first layer portion 71. The third extension portion 74 penetrates the first passivation portion 61 of the passivation layer 6 to connect to the n-type semiconductor layer 21. The third extension portion 74 can be specifically arranged at a middle position of the first layer portion 71 in the first direction.

[0121] In addition, as shown in FIG16 , for each chip structure, the second transparent conductive layer 7 on its surface is covered by an isolation layer 9 . Taking the side of the pixel driving circuit element 5 facing the chip structure as a reference, the height of the isolation layer 9 is higher than the height of the second transparent conductive layer 7 .

[0122] In addition, as shown in Figure 16, the second extension portion 73 of the second transparent conductive layer 7 is located on the side of the first extension portion 63 of the passivation layer 6 away from the pixel driving circuit element 5, and there may be a gap between the second extension portion 73 of the second transparent conductive layer 7 and the first extension portion 63 of the passivation layer 6, and the gap is filled by the isolation layer 9.

[0123] In addition, the above-mentioned epitaxial structure also includes an n-type ohmic contact electrode 8 connected to the second transparent conductive layer 7. Specifically, the number of n-type ohmic electrodes is multiple, so that the second transparent conductive layer 7 on the surface of each chip structure (i.e., each first chip structure 201', each second chip structure 202', and each third chip structure 203') is connected to an n-type ohmic contact electrode, and the n-type ohmic contact electrodes of each two chip structures can be separated by an isolation layer 9.

[0124] Continuing with reference to FIG16 , for each chip structure, its n-type ohmic contact electrode 8 may be disposed on the second extension portion 73 of the second transparent conductive layer 7 and extend outward in the second direction away from the second extension portion 73 . Specifically, a side of the n-type ohmic contact electrode 8 away from the second extension portion 73 may be substantially flush with a side of the isolation layer 9 away from the pixel driving circuit element 5 .

[0125] The full-color Micro-LED display device provided by the embodiment of the present disclosure is formed using the above-mentioned full-color Micro-LED chip. As mentioned above, the embodiment of the present disclosure can realize the simultaneous monolithic integration of RGB full-color Micro-LED display devices, has advantages such as a simple preparation process, and is conducive to actual industrial applications.

[0126] The disclosed embodiment further provides a method for preparing the full-color Micro-LED chip. As shown in FIG. 1 to FIG. 11 , the method for preparing the full-color Micro-LED chip includes the following steps S1 to S4 .

[0127] S1. Provide a substrate for forming a base layer 1, the substrate including a layer to be patterned, the layer to be patterned having a first side surface and a second side surface relative to each other, and the direction from the first side surface to the second side surface is parallel to the second direction; pattern the first side surface of the layer to be patterned to form at least one group of mesas, each group of mesas including a first mesa 101, a second mesa 102 and a third mesa 103 distributed along the first direction, with the second side surface of the layer to be patterned as a reference, the height of the first mesa 101 is greater than the height of the second mesa 102, and the height of the second mesa 102 is greater than the height of the third mesa 103; wherein, the layer to be patterned is patterned to form a patterned layer.

[0128] In some embodiments, as shown in FIG. 1 to FIG. 5 , the above preparation process may specifically include the following steps S11 to S14 .

[0129] S11 , growing a dielectric layer 12 on the substrate 11 .

[0130] In specific implementation, a plasma enhanced chemical vapor deposition (PECVD) system or an atomic layer deposition (ALD) device can be used to grow SiO2 film or SiN xThe dielectric layer 12 is formed by a thin film layer. As mentioned above, the thickness of the dielectric layer 12 can be 20-40 nm.

[0131] S12 , etching the dielectric layer 12 to form a third groove 130 exposing the substrate 11 (ie, the etching depth is equal to the thickness of the dielectric layer 12 ), and the unetched dielectric layer 12 is arranged around the third groove 130 (as shown in FIG. 3 ).

[0132] In a specific implementation, the dielectric layer 12 can be exposed and developed to expose the area to be etched, and then the dielectric layer 12 can be etched to form the third groove 130. When the dielectric layer 12 is a SiO2 film layer, it can be etched by BOE wet etching to remove the SiO2 film layer in the area to be etched to form the third groove 130; when the dielectric layer 12 is SiN x When etching the film layer, ICP-RIE dry etching can be used to remove the SiN x film layer, forming a third groove 130.

[0133] After etching, the photoresist can be removed with acetone solution, and then the substrate 11 with the dielectric layer 12 formed thereon is cleaned with ethanol and water, and then blown dry with an inert gas (such as nitrogen) before proceeding to subsequent steps.

[0134] S13 , growing a buffer layer 13 in the third groove 130 (as shown in FIG. 4 ).

[0135] In specific implementation, when the above-mentioned substrate 11 is a sapphire substrate 11, a magnetron sputtering coating (PVD) device can be used to deposit an AlN buffer layer; when the above-mentioned substrate 111 is a silicon substrate 11, MOVCD can generally be used to grow the AlN buffer layer at high and low temperatures, or the Al source can be pre-passed first and then the AlN buffer layer can be grown at high and low temperatures (for example, when growing the AlN buffer layer, trimethylaluminum (aluminum source) can be pre-passed into the chamber used to grow the AlN buffer layer, and then trimethylaluminum and ammonia can be introduced at the same time to grow the AlN buffer layer).

[0136] S14 , growing a first u-GaN layer 14 on the dielectric layer 12 and the buffer layer 13 (as shown in FIG5 ).

[0137] Specifically, the first u-GaN layer 14 may be epitaxially grown using a metal organic chemical vapor deposition (MOCVD) system.

[0138] In addition, when the above-mentioned substrate 11 is a silicon substrate 11, the above-mentioned preparation method may also include: after growing the buffer layer 13 on the substrate 11 (before growing the first u-GaN layer 14), first growing a stress regulation layer on the buffer layer 13, and then growing the first u-GaN layer 14 on the stress regulation layer.

[0139] As mentioned above, the stress regulating layer can be an AlGaN layer, and the Al component therein has a decreasing trend in the second direction away from the buffer layer 13. The decreasing trend can be a gradient decrease or a linear gradient decrease (that is, the stress regulating layer can be a linear gradient AlGaN layer). For example, Al can be grown on the buffer layer 13 in sequence. 0.8 Ga 0.2 N layer, Al 0.6 Ga 0.4 N layer, Al 0.3 Ga 0.7 N layer to form a stress regulating layer; or, a linearly graded AlGaN layer is grown, in which the Al component content can be linearly graded to 0 in the second direction away from the buffer layer 13.

[0140] Specifically, the base includes the substrate 11 , and the layer to be patterned may be the substrate 11 before patterning, or the first u-GaN layer 14 formed on the substrate 11 .

[0141] When the layer to be patterned is a substrate 11 that has not been patterned, the substrate 11 is patterned to form the above-mentioned mesa, and then a dielectric layer 12, a buffer layer 13, a first u-GaN layer 14 and other film layers are grown on the side where the mesa is formed (i.e., the first side), thereby forming the above-mentioned base layer 1, and then an n-type semiconductor layer 21 and a quantum well layer 24 and other film layers are grown in sequence on the base layer 1 to produce a full-color Micro-LED chip (as shown in Figures 1 to 11).

[0142] When the layer to be patterned is the first u-GaN layer 14 formed on the substrate 11, the dielectric layer 12, the buffer layer 13 and other film layers between the substrate 11 and the first u-GaN layer 14 are first grown on the substrate 11, and then the first u-GaN layer 14 is grown. The first u-GaN layer 14 is then patterned to form the above-mentioned mesa, thereby forming the base layer 1, and then the n-type semiconductor layer 21 and the quantum well layer 24 and other film layers are sequentially grown on the side of the base layer 1 where the mesa is formed (that is, the first side of the patterned layer) to produce a full-color Micro-LED chip.

[0143] Specifically, the above-mentioned graphic processing process may include the following steps S15 to S16.

[0144] S15 , as shown in FIG1 , etching the layer to be patterned (substrate 11 ) to form a first groove 110 ; the first groove 110 has a sidewall and a bottom wall, and a side of the sidewall facing away from the bottom wall in the second direction is a first terrace 101 .

[0145] The process of etching the layer to be patterned to form the first groove 110 may specifically include: spin coating 1.5 to 3 μm of photoresist on the layer to be patterned, exposing the area to be etched through exposure and development processes, and then etching by inductively coupled plasma etching to form the first groove 110.

[0146] Specifically, the etched pattern (ie, the shape of the projection of the first groove 110 on the substrate 11 ) may be a rectangle with a length of 5 to 14 mm and a width of 1.9 to 4.1 mm. The depth of the first groove 110 may be 36 to 54 nm.

[0147] S16. As shown in Figure 2, a partial area of ​​the bottom wall of the first groove 110 (i.e., the area used to form the third mesa 103) is etched to form a second groove 120; the surface of the unetched area of ​​the bottom wall of the first groove 110 is the second mesa 102, and the bottom surface of the second groove 120 is the third mesa 103.

[0148] Among them, a partial area of ​​the bottom wall of the first groove 110 is etched to form the second groove 120, which can specifically include: after spin-coating 1.5 to 3 μm of photoresist on the layer to be patterned with the first groove 110, exposing the area to be etched through exposure and development processes, and then etching by inductively coupled plasma etching to form the second groove 120.

[0149] The etched pattern (ie, the shape of the second groove 120 ) may be a rectangle with a length of 2.5 to 7 mm and a width of 1.9 to 4.1 mm. The depth of the second groove 120 may be 39 to 60 nm.

[0150] Generally, in the above steps S15 and S16, after etching is completed, the photoresist can be removed using an acetone solution, and then the layer to be patterned is cleaned using ethanol and water, and then blown dry using an inert gas (such as nitrogen) before proceeding to subsequent steps. The water used can be deionized water, but is not limited thereto.

[0151] In the embodiment of the present disclosure, conventional inductively coupled plasma etching equipment (ICP-RIE) in the art may be used to perform inductively coupled plasma etching.

[0152] S2. As shown in Figures 6 to 8, an n-type semiconductor layer 21 and a quantum well layer 24 are epitaxially grown in sequence on the first side of the patterned layer, wherein the quantum well layer 24 includes a blue quantum well layer 241, a green quantum well layer 242, and a red quantum well layer 243 grown in sequence on the n-type semiconductor layer 21. The blue quantum well layer 241 on the first mesa 101 faces away from the n-type semiconductor layer 21, the green quantum well layer 242 on the second mesa 102 faces away from the n-type semiconductor layer 21, and the red quantum well layer 243 on the third mesa 103 faces away from the n-type semiconductor layer 21 are flush with each other to form a flush quantum well surface.

[0153] As mentioned above, the n-type semiconductor layer 21 may include n-type semiconductor layers 21 and 24 that are sequentially stacked along the direction from the substrate 11 to the quantum well layer 24. ++ -GaN heavily doped layer 211 and n-AlGaN / n-GaN superlattice layer 212. In specific implementation, n-GaN layer 144 may be deposited on the side facing away from substrate 11. ++ -GaN heavily doped layer 211, followed by deposition of 5 to 10 periods of n-AlGaN / n-GaN superlattice layer 212, the formation of n-AlGaN / n-GaN superlattice layer 212 can further reduce the heavy doping process (i.e., n ++ -The extension of dislocations in the material and the regulation of stress during the formation process of the heavily doped GaN layer 211.

[0154] Generally, the first u-GaN layer 14 and the n-type semiconductor layer 21 (n ++ The n-AlGaN heavily doped layer 211 and the n-AlGaN / n-GaN superlattice layer 212 are grown in a hydrogen atmosphere, and the quantum well layer 24 is grown in a nitrogen atmosphere, and the growth temperature of the quantum well layer 24 is lower than the growth temperature of these film layers. In a specific implementation, the above-mentioned preparation method may further include: after the growth of the n-type semiconductor layer 21 is completed (specifically, after the growth of the n-AlGaN / n-GaN superlattice layer 212 is completed), in a nitrogen atmosphere, growing a second u-GaN layer 22 on the n-type semiconductor layer 21 (specifically, on the n-AlGaN / n-GaN superlattice layer 212), and then growing a quantum well layer 24 on the second u-GaN layer 22 (as shown in FIG. 7 ).

[0155] The thickness of the second u-GaN layer 22 may be 10 to 20 nm, for example, 10 nm, 11 nm, 12 nm, 13 nm, 14 nm, 15 nm, 16 nm, 17 nm, 18 nm, 19 nm, 20 nm, or any two thereof.

[0156] Specifically, the first u-GaN layer 14, the n-type semiconductor layer 21 (n ++-GaN heavily doped layer 211 and n-AlGaN / n-GaN superlattice layer 212), the growth temperature is about 1040 ~ 1080 ℃, and it is grown in a hydrogen atmosphere. Before growing the quantum well structure (quantum well layer 24), it is necessary to switch the chamber atmosphere, that is, switch hydrogen to nitrogen, and at the same time, it is necessary to lower the film growth temperature. After the growth of the above-mentioned n-AlGaN / n-GaN superlattice layer 212 is completed, by first growing a second u-GaN layer 22 with a thickness of 10 to 20 nm in a nitrogen atmosphere, the film etching in a high-temperature hydrogen atmosphere and the resulting deterioration of the surface flatness of the subsequent quantum well structure can be avoided.

[0157] In addition, as shown in FIG7 and FIG8, 5 to 10 periods of u-In can be grown on the second u-GaN layer 22. x”' Ga 1-x”' N / u-In y”' Ga 1-y”' After N superlattice layer 23, then u-In x”' Ga 1-x”' N / u-In y”' Ga 1-y”' A quantum well layer 24 is grown on the N superlattice layer 23 , wherein 0.01≤x'≤0.1, y'=0 or 0.005≤y'≤0.01, which can block dislocations to regulate stress and achieve lattice transition before the growth of the quantum well layer 24 (RGB quantum well).

[0158] S3. As shown in Figures 9 and 10, the green quantum well layer 242 and the red quantum well layer 243 located on the first mesa 101, and the red quantum well layer 243 located on the second mesa 102 are removed by a first etching process to expose a flush quantum well surface, thereby forming at least one group of unit groups 200 on the base layer 1, each unit group 200 including a first subunit 201 located on the first mesa 101, a second subunit 202 located on the second mesa 102, and a third subunit 203 located on the third mesa 103.

[0159] As mentioned above, the red light quantum well layer 243 includes a third potential well layer and a third barrier layer. After the growth of the quantum well layer 24 is completed (specifically, after the growth of the red light quantum well layer 243 is completed), under the growth conditions of the third barrier layer, a third u-GaN layer is grown on the quantum well layer 24 (specifically, on the side of the red light quantum well layer 243 facing away from the substrate 11), and then the temperature is cooled. The third u-GaN layer is at least partially decomposed during the cooling process, and then the first etching process is performed.

[0160] Specifically, the growth of the aforementioned quantum well layer 24 and other film layers is carried out in a reaction chamber. As previously mentioned, the quantum well layer 24 is grown in a nitrogen atmosphere. After growth is completed, the layer is cooled and removed from the reaction chamber. The quantum well layer 24 is then etched through a first etching process to expose a flush quantum well surface. After the growth of the quantum well layer 24 is completed, a third u-GaN layer is first epitaxially grown on the quantum well layer 24. The layer is then cooled and removed from the reaction chamber under a nitrogen atmosphere. The third u-GaN layer is at least partially etched and decomposed during the cooling process. Thus, the third u-GaN layer acts as a protective layer to protect the quantum well layer 24 from the effects of the cooling process.

[0161] Specifically, the thickness of the third u-GaN layer may be 10-20 nm, for example, 10 nm, 11 nm, 12 nm, 13 nm, 14 nm, 15 nm, 16 nm, 17 nm, 18 nm, 19 nm, 20 nm, or a range consisting of any two thereof.

[0162] Specifically, the first etching process may include the following steps S31 to S32, that is, first etching away the red quantum well layer 243 corresponding to the first mesa 101 and the second mesa 102 in step S31, and then etching away the green quantum well layer 242 corresponding to the first mesa 101 in step S32.

[0163] S31. After coating the surface of the quantum well layer 24 with a 1.5-3 μm photoresist, the area to be etched is exposed through exposure and development processes (i.e., the red quantum well layer 243 corresponding to the first mesa 101 and the red quantum well layer 243 corresponding to the second mesa 102 are exposed), and then the red quantum well layer 243 corresponding to the first mesa 101 and the red quantum well layer 243 corresponding to the second mesa 102 are etched away by inductively coupled plasma etching (i.e., the epitaxial layer is etched using ICP-RIE) to expose the green quantum well layer 242 corresponding to the first mesa 101 and the green quantum well layer 242 corresponding to the second mesa 102 (as shown in FIG. 9 ).

[0164] The etching depth, the height difference ΔH2 between the second mesa 102 and the third mesa 103, and the thickness of the red light quantum well layer 243 are equal, that is, the etching depth is about 39 to 60 nm. After the etching is completed, the photoresist can be removed with an acetone solution, then washed with ethanol and water, and then blown dry with an inert gas (such as nitrogen) before proceeding to the subsequent process (i.e., step S32). The water used can be deionized water, but is not limited thereto.

[0165] S32. After coating 1.5-3 μm photoresist on the quantum well layer 24, the area to be etched is exposed through exposure and development processes (i.e., the green light quantum well layer 242 corresponding to the first mesa 101 is exposed), and then the green light quantum well layer 242 corresponding to the first mesa 101 is etched away by inductively coupled plasma etching (i.e., the epitaxial layer is etched using ICP-RIE) to expose the blue light quantum well layer 241 corresponding to the first mesa 101, thereby exposing a flush quantum well surface (as shown in Figure 10).

[0166] The etching depth, the height difference ΔH1 between the first mesa 101 and the second mesa 102, and the thickness of the green quantum well layer 242 are equal, that is, the etching depth is approximately 36 to 54 nm. After the etching is completed, the photoresist can be removed with an acetone solution, then washed with ethanol and water, and then blown dry with an inert gas (such as nitrogen) before proceeding to the subsequent process (i.e., step S4). The water used can be deionized water, but is not limited thereto.

[0167] S4. After exposing the flush quantum well surface, the fourth u-GaN layer 31, the electron blocking layer 321, the hole supply layer 322 and the p-type ohmic contact layer 33 are sequentially grown on the flush quantum well surface (as shown in FIG11 ) to produce a full-color LED Micro-LED chip.

[0168] Specifically, after the flush quantum well surface is exposed, the prepared full-color Micro-LED chip precursor is placed in a reaction chamber, and a fourth u-GaN layer 31 is grown on the flush quantum well surface under a nitrogen atmosphere. Then, a hydrogen atmosphere is switched and the temperature is increased to grow the electron blocking layer 321. That is, under a hydrogen atmosphere, the electron blocking layer 321 is grown on the fourth u-GaN layer 31, and the growth temperature of the electron blocking layer 321 is higher than the growth temperature of the fourth u-GaN layer 31.

[0169] Specifically, the thickness of the fourth u-GaN layer 31 may be 20 to 30 nm, for example, 20 nm, 21 nm, 22 nm, 23 nm, 24 nm, 25 nm, 26 nm, 27 nm, 28 nm, 29 nm, 30 nm, or a range consisting of any two thereof.

[0170] The embodiment of the present disclosure further provides a method for preparing the above-mentioned full-color Micro-LED display device. As shown in Figures 12 to 16, the method for preparing the full-color Micro-LED display device includes the following steps S5 to S6.

[0171] S5. Provide the aforementioned full-color Micro-LED chip (as shown in FIG11 ), or prepare a full-color Micro-LED chip according to the aforementioned preparation method of the full-color Micro-LED chip (as shown in FIG1 to FIG11 ), which will not be further described here.

[0172] S6. Bind the full-color Micro-LED chip to the pixel driving circuit element 5 to obtain a full-color Micro-LED display device (as shown in Figures 12 to 16).

[0173] In the disclosed embodiments, a full-color Micro-LED chip can be bonded to a pixel driving circuit element 5 using a conventional standard semiconductor process flow in the art to produce a full-color Micro-LED display device. In some specific embodiments, the process of bonding the full-color Micro-LED chip to the pixel driving circuit element 5 may include the following steps S61 to S67.

[0174] S61 , sequentially growing a first transparent conductive layer 41 , a reflective layer 42 and a metal binding layer 43 on the p-type ohmic contact layer 33 (as shown in FIG. 12 ).

[0175] S62, bonding the metal binding layer 43 to the pixel driving circuit element 5 (Bonding), that is, bonding the full-color Micro-LED chip to the pixel driving circuit element 5 through the metal binding layer 43 (as shown in FIG12 ).

[0176] S63, remove the base layer 1, that is, remove the substrate 11, the first u-GaN layer 14, and the film layers between the substrate 11 and the first u-GaN layer 14 (such as the dielectric layer 12 and the buffer layer 13, etc.) to expose the n-type semiconductor layer 21, specifically, expose the n-type semiconductor layer 21. ++ -GaN heavily doped layer 211 (as shown in FIG13 ), the first subunit 201, the second subunit 202 and the third subunit 203 n ++ The heavily doped GaN layer 211 is exposed.

[0177] S64, the side of the n-type semiconductor layer 21 of the full-color Micro-LED chip away from the quantum well layer 24 (specifically, n ++ The heavily doped layer 211 is modified so that the side of the n-type semiconductor layer 21 of the first subunit 201 facing away from the quantum well layer 24, the side of the n-type semiconductor layer 21 of the second subunit 202 facing away from the quantum well layer 24, and the side of the n-type semiconductor layer 21 of the third subunit 203 facing away from the quantum well layer 24 are flush (as shown in FIG14 );

[0178] S65. Through a second etching process, a gap 90 is formed between each adjacent two of the first sub-unit 201, the second sub-unit 202, and the third sub-unit 203 to form a first chip structure 201' corresponding to the first sub-unit 201, a second chip structure 202' corresponding to the second sub-unit 202, and a third chip structure 203' corresponding to the third sub-unit 203 (as shown in FIG15).

[0179] Among them, the gap 90 is from n ++ -GaN heavily doped layer 211 extends to the metal binding layer 43 and penetrates the n ++ The heavily doped GaN layer 211 and the metal binding layer 43 , that is, the gap 90 ends at the side of the pixel driving circuit element 5 facing the metal binding layer 43 .

[0180] Specifically, as shown in FIG11 , in a full-color Micro-LED chip, each adjacent pair of the first subunit 201 , the second subunit 202 , and the third subunit 203 are in direct contact with each other, with no gap or film layer or other isolation structure between them. Through the second etching process, the first subunit 201 , the second subunit 202 , and the third subunit 203 are partially etched, wherein n ++ -GaN heavily doped layer 211, n-AlGaN / n-GaN superlattice layer 212, second u-GaN layer 22, u-In x”' Ga 1-x”' N / u-In y”' Ga 1-y”' The N superlattice layer 23, the blue quantum well layer 241, the fourth u-GaN layer 31, the electron blocking layer 321, the hole supply layer 322, the p-type ohmic contact layer 33, the first transparent conductive layer 41, the reflective layer 42, and the metal binding layer 43 are also partially etched (i.e., n ++ -GaN heavily doped layer 211, metal binding layer 43, and ++ -The film layers between the heavily doped GaN layer 211 and the metal binding layer 43 are partially etched respectively), thereby forming a first chip structure (blue light chip structure B) 201' corresponding to the first sub-unit 201, a second chip structure (green light chip structure G) 202' corresponding to the second sub-unit 202, a third chip structure (red light chip structure R) 203' corresponding to the third sub-unit 203, and a gap 90 between each adjacent two of the first chip structure 201', the second chip structure 202', and the third chip structure 203'.

[0181] S66, forming an isolation layer 9 in the gap 90 so that each adjacent one of the first chip structure 201', the second chip structure 202' and the third chip structure 203' is separated by the isolation layer, and sequentially forming a passivation layer 6 and a second transparent conductive layer 7 on the surface of each of the first chip structure 201', the second chip structure 202' and the third chip structure 203', and making the second transparent conductive layer 7 penetrate the passivation layer 6 and connect to the n-type semiconductor layer 21 (specifically, to the n-type semiconductor layer 21). ++ -GaN heavily doped layer 211).

[0182] S67 , then, forming an n-type ohmic contact electrode 8 connected to the second transparent conductive layer 7 to produce a full-color Micro-LED display device.

[0183] The specific structures of the passivation layer 6 , the second transparent conductive layer 7 , the n-type ohmic contact electrode 8 and the like are mentioned above and will not be described in detail here.

[0184] In the embodiment of the present disclosure, conventional methods in the art can be used to perform the above-mentioned etching, removal, deposition and other processes. For example, the substrate 11 can be removed by laser lift-off process, the first u-GaN layer 14 can be removed by etching by ICP-RIE, and then the n-GaN layer can be repaired by chemical polishing process. ++ -The flatness of the surface of the heavily doped GaN layer 211 is measured, and then the second etching process is performed by ICP-RIE or other methods according to parameters such as the preset pixel size (i.e., the first chip structure 201', the second chip structure 202', and the third chip structure 203') and the spacing between adjacent pixels to form the above-mentioned gap 90. The side walls of these film layers facing the gap 90 are then passivated and repaired, a passivation layer 6 is deposited, and the chip structure is isolated. Then, a second transparent conductive layer 7 and an n-type ohmic contact layer are deposited to produce a full-color Micro-LED display device.

[0185] Unless otherwise specified, the above-mentioned film layers or structures may be made of conventional materials in the art and are not specifically shown.

[0186] Exemplarily, the first transparent conductive layer 41 may include indium tin oxide (ITO), and may specifically be an ITO film layer.

[0187] Exemplarily, the second transparent conductive layer 7 may include indium tin oxide (ITO), and may specifically be an ITO film layer.

[0188] Exemplarily, the reflective layer 42 may include silver (Ag), which may specifically be a silver high reflective layer 42 . During implementation, an electron beam evaporation device may be used to deposit a silver high reflective material to form the reflective layer 4215 .

[0189] In addition, the thickness of the reflective layer 42 may be 80 nm to 200 nm, for example, 80 nm, 100 nm, 120 nm, 140 nm, 150 nm, 160 nm, 180 nm, 200 nm, or a range consisting of any two thereof.

[0190] Illustratively, the metal binding layer 43 includes a metal, such as one or more of nickel (Ni), titanium (Ti), Ag, etc. Illustratively, the metal binding layer 43 may include a nickel layer, a titanium layer, a nickel layer, and a silver layer sequentially stacked on the reflective layer 42 .

[0191] Exemplarily, the pixel driving circuit element 5 may be a silicon-based pixel driving circuit element 5 , and specifically may include a silicon-based complementary metal oxide semiconductor (CMOS) chip.

[0192] Exemplarily, the isolation layer 9 may include SiO 2 , and specifically may be a SiO 2 film layer formed of SiO 2 .

[0193] In the embodiment of the present disclosure, the patterned layer (such as the substrate 11) is patterned to achieve a thickness gradient change of the patterned layer (i.e., to form at least one set of mesa groups, each of which includes a first mesa 101, a second mesa 102, and a third mesa 103 with successively decreasing heights), and then epitaxially grows functional layers such as an n-type semiconductor layer 21 and an RGB quantum well layer 24 thereon, while maintaining the back surface of the blue quantum well layer 241 corresponding to the first mesa 101, the green quantum well layer 242 corresponding to the second mesa 102, and the red quantum well layer 243 corresponding to the third mesa 103. The first chip structure 201', the second chip structure 202', and the third chip structure 203' are formed by etching the first sub-unit 201', the second chip structure 202', and the third chip structure 203', respectively. RGB full-color Micro-LED display devices (i.e., the first chip structure 201', the second chip structure 202', and the third chip structure 203') are respectively formed.

[0194] Therefore, in the embodiment of the present disclosure, through the preparation process of the full-color Micro-LED chip, RGB three-primary color light emission of a single substrate (such as a sapphire substrate or a silicon substrate, etc.) can be achieved (that is, RGB full-color light emission of a single substrate can be achieved). For example, RGB three-primary color light emission of a single substrate InGaN material can be achieved, that is, the preparation of the RGB LED chip structure can be carried out simultaneously, and the RGB Micro-LED chip can be integrated monolithically to obtain a full-color Micro-LED chip and a display device, and it has the advantages of simple preparation process and cost savings.

[0195] In the description of this disclosure, “n-” or “n ++ " indicates n-type doping, as mentioned above ++ -GaN heavily doped layer 211 and n-AlGaN / n-GaN superlattice layer 212 are both n-type doped layers, and conventional dopants in the art may be used, such as SiH4; "p-" or "p ++ " indicates p-type doping, as mentioned above ++ -GaN heavily doped layer, p-AlGaN / p-GaN superlattice layer, etc. all represent p-type doped layers, which can also use conventional dopants in the field; "u-" represents undoped, such as the aforementioned u-GaN layer represents an undoped gallium nitride film layer, etc. In addition, unless otherwise specified, the "content" mentioned refers to the molar content, and the thickness direction of the "thickness" mentioned above is parallel to the second direction. The arrangement along the second direction (such as stacking arrangement along the second direction, sequentially stacking arrangement along the second direction, etc.) can specifically be arranged along the direction from the n-type semiconductor layer 21 (or substrate layer 1) to the quantum well layer 24, or along the direction from the quantum well layer 24 to the n-type semiconductor layer 21 (or substrate layer 1).

[0196] In addition, terms such as "first" and "second" are used only for descriptive purposes, such as distinguishing between components to more clearly illustrate / explain the technical solution, and cannot be understood as indicating or implying the number of technical features indicated or the order with substantial significance.

[0197] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present disclosure, rather than to limit them. Although the present disclosure has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present disclosure.

Claims

1. A full-color Micro-LED chip, comprising: Base layer; A functional layer is provided on the base layer, the functional layer comprises an n-type semiconductor layer and a quantum well layer stacked along a second direction; the functional layer comprises at least one unit group, each of the unit groups comprises a first sub-unit, a second sub-unit and a third sub-unit distributed along a first direction, the first direction intersects with the second direction; The quantum well layer of the first subunit includes a blue light quantum well layer; The quantum well layer of the second subunit comprises a blue light quantum well layer and a green light quantum well layer sequentially stacked on the n-type semiconductor layer along the second direction; The quantum well layer of the third subunit comprises a blue light quantum well layer, a green light quantum well layer and a red light quantum well layer which are sequentially stacked on the n-type semiconductor layer along the second direction; The blue light quantum well layer of the first subunit faces away from the n-type semiconductor layer, the green light quantum well layer of the second subunit faces away from the n-type semiconductor layer, and the red light quantum well layer of the third subunit faces away from the n-type semiconductor layer.

2. The full-color Micro-LED chip according to claim 1, wherein the base layer includes a patterned layer located on a side of the n-type semiconductor layer away from the quantum well layer, and a side of the patterned layer facing the n-type semiconductor layer includes a mesa group corresponding to the unit group one by one, each of the mesa groups includes a first mesa, a second mesa and a third mesa distributed along the first direction, and with the side of the patterned layer away from the n-type semiconductor layer as a reference, a height of the first mesa is greater than a height of the second mesa, a height of the second mesa is greater than a height of the third mesa, the first subunit is located on the first mesa, the second subunit is located on the second mesa, and the third subunit is located on the third mesa.

3. The full-color Micro-LED chip according to claim 2, wherein: The height difference between the first mesa and the second mesa is equal to the thickness of the green light quantum well layer; and / or, the height difference between the first mesa and the second mesa is 36-54 nm; And / or, the height difference between the second mesa and the third mesa is equal to the thickness of the red light quantum well layer; And / or, a height difference between the second mesa and the third mesa is 39-60 nm.

4. The full-color Micro-LED chip according to claim 2 or 3, wherein: The base layer further includes a substrate located on a side of the n-type semiconductor layer away from the quantum well layer, and a first u-GaN layer located between the substrate and the n-type semiconductor layer; wherein, The patterned layer is the substrate, or the first u-GaN layer; And / or, the substrate includes a sapphire substrate or a silicon substrate; And / or, the base layer further includes a dielectric layer and an AlN buffer layer located between the substrate and the first u-GaN, the dielectric layer is arranged around the AlN buffer layer, and the dielectric layer includes silicon oxide compounds and / or silicon nitrogen compounds.

5. The full-color Micro-LED chip according to claim 4, wherein: The substrate is a silicon substrate, the base layer also includes a stress regulation layer located between the AlN buffer layer and the first u-GaN layer, the stress regulation layer includes an AlGaN layer, and the Al component content therein shows a decreasing trend along the direction from the AlN buffer layer to the first u-GaN layer, and the decreasing trend is a gradient decrease or a linear gradual decrease.

6. The full-color Micro-LED chip according to claim 1, wherein: The n-type semiconductor layer includes n ++ -GaN heavily doped layer, and located in the n ++ -n-AlGaN / n-GaN superlattice layer between the GaN heavily doped layer and the quantum well layer; wherein, The ++ -The Hall electron concentration of the heavily doped GaN layer is 5×10 18 ~2×10 19 cm -3 ; and / or, the n ++ -The thickness of the heavily doped GaN layer is 1.5 to 2.5 μm; And / or, the Hall electron concentration of the n-AlGaN / n-GaN superlattice layer is 1×10 18 ~1.5×10 18 cm -3 ; And / or, the n-AlGaN / n-GaN superlattice layer comprises n-AlGaN layers and n-GaN layers staggered along the second direction, the thickness of the n-AlGaN layer is 2-3 nm, the content of Al component is 2-8%, and the thickness of the n-GaN layer is 5-10 nm; And / or, the number of periods of the n-AlGaN / n-GaN superlattice layer is 5-10.

7. The full-color Micro-LED chip according to claim 1, wherein: The functional layer further includes a second u-GaN layer located between the n-type semiconductor layer and the quantum well layer, a u-In layer located between the second u-GaN layer and the quantum well layer x”' Ga 1-x”' N / u-In y”' Ga 1-y”' N superlattice layers, 0.01≤x'≤0.1, y'=0 or 0.005≤y'≤0.01, where The thickness of the second u-GaN layer is 10 to 20 nm; and / or, the u-In x”' Ga 1-x”' N / u-In y”' Ga 1-y”' The N superlattice layer includes a plurality of crystals intersecting along the second direction. Wrongly set u-In x”' Ga 1-x”' N-layer and u-In y”' Ga 1-y”' N-layer, the u-In x”' Ga 1-x”' The thickness of the N layer is 2 to 3 nm. y”' Ga 1-y”' The thickness of the N layer is 5 to 10 nm; and / or, the u-In x”' Ga 1-x”' N / u-In y”' Ga 1-y”' The period number of the N superlattice layer is 5 to 10.

8. The full-color Micro-LED chip according to claim 1, wherein: The blue light quantum well layer includes 3 to 5 first repeating units, each of which includes a first potential well layer and a first barrier layer stacked along the second direction, and the first potential well layer includes u-In x Ga 1-x N layer, 0.18≤x≤0.2, the thickness of the first potential well layer is 2-3nm, the first barrier layer includes an n-GaN layer or a u-In y Ga 1-y N layer, 0.01≤y≤0.03; the thickness of the first barrier layer is 10-15 nm; And / or, the green light quantum well layer includes 3 to 5 second repeating units, each of the second repeating units includes a second potential well layer and a second barrier layer stacked along the second direction, and the second potential well layer includes u-In x' Ga 1-x' N layer, 0.25≤x'≤0.28, the thickness of the second potential well layer is 2-3nm, and the second barrier layer includes an n-GaN layer or a u-In y' Ga 1-y' N layer, 0.03≤y'≤0.05, the thickness of the second barrier layer is 10-15 nm; And / or, the red light quantum well layer includes 3 to 5 third repeating units, each of which includes a third potential well layer, a third barrier layer and a u-Al layer stacked in sequence along the second direction. z Ga 1-z N layer, 0.1≤z≤0.25, the u-Al z Ga 1-z The thickness of the N layer is 1-2 nm, and the third potential well layer includes u-In x” Ga 1-x” N layer, 0.35≤x″≤0.38, the thickness of the third potential well layer is 2-3nm, and the third barrier layer includes an n-GaN layer or a u-In y” Ga 1-y” N layer, 0.05≤y″≤0.08, and the thickness of the third barrier layer is 10-15 nm.

9. The full-color Micro-LED chip according to claim 1, wherein: The functional layer further includes a fourth u-GaN layer, a p-type semiconductor layer and a p-type ohmic contact layer sequentially located on a side of the quantum well layer away from the n-type semiconductor layer, the p-type semiconductor layer includes an electron blocking layer and a hole supply layer located between the electron blocking layer and the p-type ohmic contact layer, wherein: The electron blocking layer includes one or more of a p-AlGaN layer, a p-AlGaN / p-GaN superlattice layer, and a p-AlGaN polarization induction layer with a linear gradient of Al component content in the second direction; The hole supply layer includes one or more of a p-GaN layer, a p-AlGaN / p-GaN superlattice layer, and a p-AlGaN polarization induction layer with a linear gradient of Al component content in the second direction; The p-type ohmic contact layer includes p ++ a heavily-doped GaN layer, an ITO film layer, a p-InGaN / p-GaN superlattice layer, and a p-AlGaN polarization induction layer having a linear gradient of Al content in the second direction; kind or multiple.

10. The full-color Micro-LED chip according to claim 9, wherein: The Al component content in the p-AlGaN layer is 10-25%; And / or, the p-AlGaN / p-GaN superlattice layer comprises a p-AlGaN layer and a p-GaN layer, the Al component content in the p-AlGaN layer is 20-25%, the thickness of the p-AlGaN layer is 2-3 nm, and the thickness of the p-GaN layer is 5-10 nm; And / or, the Al component content in the p-AlGaN polarization inducing layer changes linearly from 30% to 0 in the second direction; And / or, the thickness of the electron blocking layer is 20 to 60 nm; And / or, the thickness of the p-GaN layer is 100 to 160 nm; And / or, the thickness of the p-AlGaN polarization inducing layer is 60 to 80 nm; and / or, the p ++ - the dopant in the heavily doped GaN layer includes Mg; and / or, the p ++ -GaN heavily doped layer has a hole Hall concentration of 2×10 20 ~4×10 20 cm -3 ; and / or, the p ++ -The thickness of the heavily doped GaN layer is 10 to 40 nm; And / or, the p-InGaN / p-GaN superlattice layer includes a p-InGaN layer and a p-GaN layer, the p-InGaN layer has a thickness of 2 to 3 nm, an In component content of 5 to 10%, and the p-GaN layer has a thickness of 5 to 10 nm.

11. A full-color Micro-LED display device, comprising an epitaxial structure, wherein the epitaxial structure is formed by the full-color Micro-LED chip according to any one of claims 1 to 10, wherein: The epitaxial structure includes the functional layer; the epitaxial structure includes chip groups corresponding one by one to the unit groups, each chip group includes a first chip structure corresponding to the first sub-unit, a second chip structure corresponding to the second sub-unit, and a third chip structure corresponding to the third sub-unit, and each of the first chip structure, the second chip structure and the third chip structure are separated by an isolation layer.

12. The full-color Micro-LED display device according to claim 11, wherein: The functional layer further includes a fourth u-GaN layer, a p-type semiconductor layer and a p-type ohmic contact layer, which are sequentially located on the side of the quantum well layer away from the n-type semiconductor layer; the LED chip further includes a first transparent conductive layer, a reflective layer, a metal binding layer, and a pixel driving circuit element, which are sequentially located on the side of the p-type ohmic contact layer away from the p-type semiconductor layer; the isolation layer extends from the n-type semiconductor layer to the metal binding layer and penetrates the n-type semiconductor layer and the metal binding layer; and / or, the first chip structure, the second chip structure and the third chip structure A passivation layer and a second transparent conductive layer are sequentially provided on the surface of each, the second transparent conductive layer penetrates the passivation layer and is connected to the n-type semiconductor layer, and the epitaxial structure further comprises an n-type ohmic contact electrode connected to the second transparent conductive layer; And / or, a side of the n-type semiconductor layer of the first chip structure facing away from the quantum well layer, a side of the n-type semiconductor layer of the second chip structure facing away from the quantum well layer, and a side of the n-type semiconductor layer of the third chip structure facing away from the quantum well layer are flush.

13. A method for preparing a full-color Micro-LED chip according to any one of claims 1 to 9, comprising the following steps: Providing a substrate for forming the base layer, the substrate comprising a layer to be patterned, the layer to be patterned having a first side surface and a second side surface opposite to each other, and a direction from the first side surface to the second side surface is parallel to the second direction; Performing a patterning process on the first side of the layer to be patterned to form at least one set of mesas, each of which includes a first mesas, a second mesas and a third mesas distributed along the first direction, and taking the second side of the layer to be patterned as a reference, the height of the first mesas is greater than the height of the second mesas, and the height of the second mesas is greater than the height of the third mesas; wherein the layer to be patterned forms a patterned layer after the patterning process; An n-type semiconductor layer and a quantum well layer are sequentially epitaxially grown on the first side of the patterned layer, wherein the quantum well layer comprises a blue quantum well layer, a green quantum well layer and a red quantum well layer sequentially grown on the n-type semiconductor layer, and a side of the blue quantum well layer on the first mesa facing away from the n-type semiconductor layer, a side of the green quantum well layer on the second mesa facing away from the n-type semiconductor layer, and a side of the red quantum well layer on the third mesa facing away from the n-type semiconductor layer are flush with each other to form a flush quantum well surface; Removing the green quantum well layer and the red quantum well layer on the first mesa and the red quantum well layer on the second mesa through a first etching process to expose the flush quantum well surface, thereby forming at least one unit group on the base layer, each of the unit groups comprising the first sub-unit on the first mesa, the second sub-unit on the second mesa, and the third sub-unit on the third mesa; After the flush quantum well surface is exposed, a fourth u-GaN layer, an electron blocking layer, a hole supply layer and a p-type ohmic contact layer are sequentially grown on the flush quantum well surface to obtain the full-color Micro-LED chip.

14. The method for preparing a full-color Micro-LED chip according to claim 13, wherein: The graphical processing process includes: Etching the layer to be patterned to form a first groove; the first groove has a side wall and a bottom wall, and a side of the side wall away from the bottom wall in the second direction is the first terrace; A partial area of ​​the bottom wall of the first groove is etched to form a second groove; the surface of the unetched area of ​​the bottom wall of the first groove is the second mesa, and the bottom surface of the second groove is the third mesa.

15. The method for preparing a full-color Micro-LED chip according to claim 14, wherein: The etching of the layer to be patterned to form the first groove specifically includes: after spin coating 1.5-3 μm of photoresist on the layer to be patterned, exposing the area to be etched through exposure and development processes, and then etching through inductively coupled plasma etching to form the first groove; and / or, The etching of a portion of the bottom wall of the first groove to form the second groove specifically includes: spin coating 1.5 to 3 μm of photoresist on the layer to be patterned with the first groove, exposing the area to be etched through exposure and development processes, and then etching through inductively coupled plasma etching to form the second groove.

16. The method for preparing a full-color Micro-LED chip according to claim 13, wherein: The base comprises a substrate, and the preparation method further comprises: Growing a dielectric layer on the substrate; the dielectric layer comprises a silicon oxide compound and / or a silicon nitrogen compound; Etching the dielectric layer to form a third groove exposing the substrate, wherein the dielectric layer not etched is arranged around the third groove; Growing an AlN buffer layer in the third groove; Growing a first u-GaN layer on the dielectric layer and the AlN buffer layer; Wherein, the patterned layer is the substrate or the first u-GaN layer.

17. The method for preparing a full-color Micro-LED chip according to claim 13, wherein: The n-type semiconductor layer is grown in a hydrogen atmosphere, the quantum well layer is grown in a nitrogen atmosphere, and the growth temperature of the quantum well layer is lower than the growth temperature of the n-type semiconductor layer; the preparation method further comprises: after the growth of the n-type semiconductor layer is completed, in a nitrogen atmosphere, growing a second u-GaN layer on the n-type semiconductor layer, and then growing 5 to 10 u-In of the cycle x”' Ga 1-x”' N / u-In y”' Ga 1-y”' N superlattice layer, and then in the u-In x”' Ga 1-x”' N / u-In y”' Ga 1-y”' The quantum well layer is grown on the N superlattice layer; wherein 0.01≤x'≤0.1, y'=0 or 0.005≤y'≤0.01; And / or, the red light quantum well layer includes a third potential well layer and a third potential barrier layer; the preparation method also includes: after the growth of the quantum well layer is completed, under the growth conditions of the third potential barrier layer, a third u-GaN layer is grown on the quantum well layer, and then the temperature is lowered, the third u-GaN layer is at least partially decomposed during the cooling process, and then the first etching process is performed to expose the flush quantum well surface.

18. The method for preparing a full-color Micro-LED chip according to claim 13, wherein: The first etching process comprises: After coating a 1.5-3 μm photoresist on the surface of the quantum well layer, exposing the red light quantum well layer corresponding to the first mesa and the red light quantum well layer corresponding to the second mesa through exposure and development processes, and then etching away the red light quantum well layer corresponding to the first mesa and the red light quantum well layer corresponding to the second mesa through inductively coupled plasma etching to expose the green light quantum well layer corresponding to the first mesa and the green light quantum well layer corresponding to the second mesa; After coating the quantum well layer with 1.5-3 μm photoresist, the green quantum well layer corresponding to the first mesa is exposed through exposure and development processes, and then the green quantum well layer corresponding to the first mesa is etched away through inductively coupled plasma etching to expose the blue quantum well layer corresponding to the first mesa, thereby exposing the flush quantum well surface; And / or, after exposing the flush quantum well surface, growing a fourth u-GaN layer on the flush quantum well surface in a nitrogen atmosphere; and then growing the electron blocking layer on the fourth u-GaN layer in a hydrogen atmosphere, the growth temperature of the electron blocking layer being higher than the growth temperature of the fourth u-GaN layer.

19. A method for preparing a full-color Micro-LED display device, comprising the following steps: Providing a full-color Micro-LED chip as described in any one of claims 1 to 10, or preparing a full-color Micro-LED chip according to the preparation method of a full-color Micro-LED chip as described in any one of claims 13 to 18; The full-color Micro-LED chip is bound to a pixel driving circuit element to produce a full-color Micro-LED display device.

20. The method for preparing a full-color Micro-LED display device according to claim 19, wherein: The step of binding the full-color Micro-LED chip to a pixel driving circuit element to obtain a full-color Micro-LED display device specifically includes: Growing a first transparent conductive layer, a reflective layer and a metal binding layer in sequence on the p-type ohmic contact layer of the full-color Micro-LED chip; Binding the metal binding layer to a pixel driving circuit element; Removing the substrate layer of the full-color Micro-LED chip; Modifying a side of the n-type semiconductor layer of the full-color Micro-LED chip away from the quantum well layer, so that a side of the n-type semiconductor layer of the first subunit away from the quantum well layer, a side of the n-type semiconductor layer of the second subunit away from the quantum well layer, and a side of the n-type semiconductor layer of the third subunit away from the quantum well layer are flush; Through a second etching process, a gap is formed between each adjacent two of the first subunit, the second subunit and the third subunit, wherein the gap extends from the n-type semiconductor layer of the full-color Micro-LED chip to the metal binding layer and penetrates the n-type semiconductor layer and the metal binding layer to form a first chip structure corresponding to the first subunit, a second chip structure corresponding to the second subunit, and a third chip structure corresponding to the third subunit; forming an isolation layer in the gap so that each of the first chip structure, the second chip structure and the third chip structure is separated by the isolation layer, and sequentially forming a passivation layer and a second transparent conductive layer on the surface of each of the first chip structure, the second chip structure and the third chip structure, and making the second transparent conductive layer penetrate the passivation layer and connect to the n-type semiconductor layer; Then, an n-type ohmic contact electrode connected to the second transparent conductive layer is formed to obtain the full-color Micro-LED display device.

Images