Semiconductor element, semiconductor component, and method for producing a semiconductor element or semiconductor component

Abstract

The invention relates to a semiconductor element (1) comprising the following: - a semiconductor chip (2), which has a first contact surface (21) and a second contact surface (22) on a bottom side (2B), wherein the first contact surface (21) and the second contact surface (22) are separated from one another by an intermediate space (27), - a carrier element (4) on which the semiconductor chip (2) is arranged, wherein the bottom side (2B) faces the carrier element (4), and - a connection layer (3), which - is arranged between the carrier element (4) and the semiconductor chip (2) and connects the semiconductor chip (2) to the carrier element (4), - is anisotropically electrically conductive and - horizontally overlaps with the first contact surface (21) and the second contact surface (22) and extends across the intermediate space (27). The invention also relates to a semiconductor component (10) having a plurality of semiconductor chips (2), and to a method for producing a semiconductor element (1) or semiconductor component (10).

Description

[0001] 2023PF00133 August 1, 2024 P2023,0644 WO N - 1 - Description SEMICONDUCTOR COMPONENT, SEMICONDUCTOR COMPONENT, AND METHOD FOR PRODUCING A SEMICONDUCTOR COMPONENT OR SEMICONDUCTOR COMPONENT A semiconductor component having a semiconductor chip, a semiconductor component having a plurality of semiconductor chips, and a method for producing the same are specified. For example, the semiconductor chip or the semiconductor component or the semiconductor component is suitable for emitting electromagnetic radiation with a peak wavelength approximately in the visible to infrared spectral range. The peak wavelength can designate the maximum of the spectral distribution of the emitted radiation. However, it is also possible for the semiconductor chip or the semiconductor component or the semiconductor component to be suitable for detecting electromagnetic radiation.It is also possible for the semiconductor chip to be designed as an integrated electronic circuit. There are various options for electrically contacting semiconductor chips. For example, in so-called horizontal LEDs, both electrical contacts can be arranged on the same side of the LED. However, increasing miniaturization of LEDs is leading to ever smaller distances between the electrical contacts, so that the risk of short circuits increases. This in turn leads to lower LED yield and higher production costs. One problem to be solved here is to specify a semiconductor component with improved reliability 2023PF00133 August 1, 2024 P2023,0644 WO N - 2 -. A further problem to be solved is to specify a semiconductor component with improved reliability.Furthermore, one object to be achieved is to specify a method for producing a semiconductor component or semiconductor device with improved reliability. These objects are achieved, inter alia, by a semiconductor component, a semiconductor device and a method having the features of the independent claims. According to at least one embodiment of a semiconductor component, this comprises a semiconductor chip which has a first contact area and a second contact area on an underside, wherein the first contact area and the second contact area are separated from one another by a gap. In other words, the semiconductor chip can have a horizontal chip design. The gap can, for example, have a width or lateral extent of 10 - 30 µm, wherein deviations within the scope of usual manufacturing tolerances are possible.Furthermore, the semiconductor chip can be an optoelectronic semiconductor chip, for example, a radiation-emitting or radiation-detecting semiconductor chip. The radiation-emitting semiconductor chip can have an active zone suitable for generating radiation. The active zone can be provided to emit electromagnetic radiation with a peak wavelength approximately in the visible to infrared spectral range during operation. Accordingly, the 2023PF00133 August 1, 2024 P2023,0644 WO N - 3 - radiation-detecting semiconductor chip can have an active zone suitable for absorbing radiation. Furthermore, the semiconductor chip can be a switching element having an integrated electronic circuit. For example, the semiconductor chip can have more than two contact surfaces on the underside, each of which is separated from one another by a gap.According to at least one embodiment, the semiconductor component comprises a carrier element on which the semiconductor chip is arranged. In this case, it is possible for the underside of the semiconductor chip to face the carrier element. For example, the first contact surface and the second contact surface can be located between a semiconductor layer sequence of the semiconductor chip, which comprises, for example, the active zone, and the carrier element. According to at least one embodiment, the semiconductor component comprises a connecting layer which is arranged between the carrier element and the semiconductor chip and connects the semiconductor chip to the carrier element. Among other things, the semiconductor chip can be electrically conductively connected to the carrier element by the connecting layer. Preferably, the connecting layer is anisotropically electrically conductive.In the present case, this means, for example, that the connecting layer has a higher electrical conductivity in some regions in directions in which a current flow is to occur than in directions in which the current flow is to be suppressed. For example, the 2023PF00133 August 1, 2024 P2023,0644 WO N - 4 - connecting layer can have a higher electrical conductivity in some regions in a vertical direction, in which the semiconductor chip follows the carrier element, than in lateral directions and in particular in the lateral direction in which the second contact area follows the first contact area. According to at least one embodiment, the connecting layer overlaps horizontally, i.e. in lateral directions running transversely to the vertical direction, with the first contact area and the second contact area and extends across the gap between the first and second contact areas.In other words, the first and second contact surfaces are connected to each other by the connecting layer. However, due to the anisotropic electrical conductivity of the connecting layer, it is possible to prevent a short circuit between the first contact surface and the second contact surface. Structuring or interrupting the connecting layer in the gap can thus be omitted, thus reducing manufacturing costs. The same can apply to a larger number of contact surfaces. In particular, the connecting layer overlaps horizontally with all contact surfaces and extends across the gaps between the contact surfaces.According to at least one embodiment of a semiconductor component, this comprises: ^ a semiconductor chip which has a first contact area and a second contact area on an underside, wherein the first contact area and the second contact area are separated from one another by an intermediate space, 2023PF00133 August 1, 2024 P2023,0644 WO N - 5 - ^ a carrier element on which the semiconductor chip is arranged, wherein the underside faces the carrier element, and ^ a connecting layer which ^ is arranged between the carrier element and the semiconductor chip and connects the semiconductor chip to the carrier element, ^ is anisotropically electrically conductive and ^ horizontally overlaps the first contact area and the second contact area and extends across the intermediate space.The semiconductor chip can have a semiconductor layer sequence with a first and second semiconductor region of different conductivity, wherein the active zone is arranged between the first and second semiconductor regions. The first and second semiconductor regions as well as the active zone can each be formed from one or more semiconductor layers. The semiconductor layers can be layers deposited epitaxially on a growth substrate. The growth substrate can remain in the semiconductor chip or be at least partially detached. The first semiconductor region can be arranged on a side facing the carrier element. The second semiconductor region can be arranged on a side facing away from the carrier element. For example, the first semiconductor region has a p-type conductivity, while the second semiconductor region has an n-type conductivity.However, it is also possible for the first semiconductor region to have n-type conductivity and the second semiconductor region to have p-type conductivity. 2023PF00133 August 1, 2024 P2023,0644 WO N - 6 - Materials based on arsenide, phosphide, or nitride compound semiconductors, for example, are considered for the semiconductor regions or semiconductor layers of the semiconductor layer sequence. "Based on arsenide, phosphide, or nitride compound semiconductors" in the present context means that the semiconductor layers are Al. n Ga m In 1-n-m As, Al n Ga m In 1-n-m P or Al n Ga m In 1- n-mN, where 0 ^ n ^ 1, 0 ^ m ^ 1 and n+m ^ 1 apply. This material does not necessarily have to have a mathematically exact composition according to the above formula. Rather, it can contain one or more dopants as well as additional components that determine the characteristic physical properties of Al n Ga m In 1-n-m As-, Al n Ga m In 1-n- m P or Al n Ga m In 1-n-mN-material do not change significantly. For the sake of simplicity, however, the above formula only includes the essential components of the crystal lattice (Al, Ga, In, As or P or N), even if these may be partially replaced by small amounts of other substances. Furthermore, for a semiconductor chip that is a switching element, silicon, for example, can also be used as a material. For example, the semiconductor chip is a micro-LED (or micro-LED, µLED, µ-LED, uLED, u-LED) or a micro-IC (micro-integrated circuit or µIC). The semiconductor chip is characterized by its particularly small size. For example, the semiconductor chip can have a rectangular footprint and a size of no more than 40 µm x 80 µm, although deviations within the scope of normal manufacturing tolerances are possible.A height or vertical extent of the semiconductor chip, which is determined approximately along the vertical direction, lies, for example, in the range from 1.5 µm to 2023PF00133 August 1, 2024 P2023,0644 WO N - 7 - 10 µm, wherein deviations within the scope of usual manufacturing tolerances are possible. According to at least one embodiment or configuration, the connecting layer comprises an electrically insulating base layer and electrically conductive paths, wherein the electrically conductive paths run through the base layer from a side of the connecting layer facing the carrier element to a side of the connecting layer facing away from the carrier element. For example, the electrically conductive paths run in a vertical direction, wherein manufacturing-related deviations are possible. The electrically conductive paths can be embedded in the base layer and surrounded by it on the circumference.On a side facing the semiconductor chip, the electrically conductive paths can protrude slightly beyond the base layer. According to at least one embodiment or configuration, the connecting layer is pressure-sensitive. For example, even low pressures, approximately the size of finger pressure, are sufficient to mold the connecting layer to the carrier element and the semiconductor chip and to connect them. For example, the base layer can comprise a base material with a modulus of elasticity between 1 and 1000 MPa, in particular between 1 and 100 MPa. According to at least one embodiment or configuration, the semiconductor chip and the carrier element are reversibly connected to one another by means of the connecting layer. This means, for example, that the semiconductor chip can be detached from the carrier element without causing damage. This makes it possible, for example, to check the still 2023PF00133 1.August 2024 P2023,0644 WO N - 8 - testing the functionality of an unfinished semiconductor component facilitates replacement of the semiconductor chip and / or the connecting layer, which is in particular detachably or reversibly attached to the semiconductor chip and carrier element, if the functionality is not met. Furthermore, an adhesive bond can be formed by means of the connecting layer. For example, an adhesive material that has an adhesive strength of between 0.5 and 10 N / 20 mm or between 1 and 3 N / 20 mm (tested according to EN ISO 29862-2019) at room temperature can be used as the base material of the base layer. This adhesive bond can be formed at lower temperatures than conventional adhesive bonds. This makes it possible, for example, to prevent deformation of the carrier element.According to at least one embodiment or configuration, the base material contains at least one of the following materials: silicone, acrylate. According to at least one embodiment or configuration, the electrically conductive paths comprise particles that are solid bodies, i.e., not hollow bodies, made of an electrically conductive material or solid bodies with a coating made of an electrically conductive material. For example, one of the following materials is suitable for the electrically conductive material: Ag, Ni, Cu, Au, Fe, Sn, Zn, Pd, Pt, Fe, Cr, Mo, CNT (carbon nanotubes), TCO (transparent conductive oxide). If the solid bodies are provided with a coating, they can be formed from an electrically insulating material such as glass, polystyrene, or a thermoplastic or thermosetting plastic. For example, the particles are spherical.However, other shapes such as cylinders or polyhedra are also possible. The particles can each have a lateral extent of at most 15 µm, in particular 3 µm ± 1 µm, whereby the lateral extent is determined along a lateral direction. In this case, it is possible for the tolerance to be relatively large, which facilitates manufacturing, and yet electrically conductive paths are still created. Lateral distances between the paths are, for example, two to three times greater than the lateral extent of the particles. The paths can be arranged at equal distances from one another, although deviations within the scope of usual manufacturing tolerances are possible. For example, the paths are arranged at lattice points of a two-dimensional, hexagonal lattice. The connecting layer can be multilayered, so that each electrically conductive path has several interconnected particles arranged one above the other.However, it is also possible for the connecting layer to be formed in a single layer, so that no further particles are arranged on a particle. Furthermore, the number of particles can be limited horizontally to one particle for each electrically conductive path. According to at least one embodiment or configuration, the connecting layer projects laterally beyond the semiconductor chip. In other words, the connecting layer can have greater lateral dimensions than the semiconductor chip. This allows the semiconductor chip to be securely positioned on the connecting layer. However, it is advantageous if the connecting layer has no more than twice the lateral dimensions of the semiconductor chip. In this way, radiation that is to be transmitted through the semiconductor component is only slightly blocked. Furthermore, material consumption and thus material costs can be kept low.According to at least one embodiment or configuration, the carrier element comprises a base element and a first connection surface and a second connection surface, wherein the first connection surface and the second connection surface are arranged on a side of the base element facing the semiconductor chip. The first contact surface can be electrically conductively connected to the first connection surface by the connecting layer. Furthermore, the second contact surface can be electrically conductively connected to the second connection surface by the connecting layer. For example, there are at least ten electrical paths between the first contact surface and the first connection surface and between the second contact surface and the second connection surface. Metals such as Au, Cu or Pd are suitable for the first and second connection surfaces, for example.The carrier element can have more than two connection surfaces, for example, if the semiconductor chip has more than two contact surfaces. In particular, each contact surface can be assigned exactly one connection surface, and vice versa, with the connecting layer being arranged between the contact surface and the connection surface. According to at least one embodiment or configuration, the base element is radiation-permeable. In particular, the base element is permeable to visible radiation. For example, a thermoplastic material such as PET (polyethylene terephthalate) can be used for the base element.According to at least one embodiment of a semiconductor component, the component comprises a plurality of semiconductor chips, each having a first contact surface and a second contact surface on an underside, wherein the first contact surface and the second contact surface are separated from one another by a gap. The properties of the semiconductor chip mentioned in connection with the semiconductor component apply in particular to the semiconductor chips. Furthermore, according to at least one embodiment, the semiconductor component comprises a carrier on which the semiconductor chips are arranged, wherein the underside in each case faces the carrier. Furthermore, according to at least one embodiment, the semiconductor component comprises a plurality of connecting layers, each arranged between the carrier and a semiconductor chip and connecting the semiconductor chip to the carrier. Among other things, the semiconductor chips can each be electrically conductively connected to the carrier by the connecting layers.The properties of the connecting layer mentioned in connection with the semiconductor component apply in particular to the connecting layers. In particular, the connecting layers are each anisotropically electrically conductive. Furthermore, the connecting layers preferably each overlap horizontally with the first contact area and the second contact area of ​​the semiconductor chip to which they are connected and extend across the respective intermediate space. The semiconductor component, which is, for example, a display device, is characterized, among other things, by high resolution, in particular when micro-LEDs are used as semiconductor chips. According to at least one embodiment or configuration, the carrier has, for example, an electrically insulating base body. The base body is, for example, radiation-permeable. In particular, the base body is permeable to visible radiation.This makes it possible for the semiconductor component, which may be a display device, for example, to display information or images when switched on and to be transparent when switched off. The properties of the base element mentioned in connection with the semiconductor component apply in particular to the base body. According to at least one embodiment or configuration, the carrier has an electrically conductive contact structure. The contact structure is arranged in particular on a side of the carrier or base body facing the semiconductor chips. For example, the first contact surface and the second contact surface of the semiconductor chips are each electrically conductively connected to the electrically conductive contact structure by the connecting layer.In this case, at least ten electrical paths can be located between the first contact area and the contact structure, as well as between the second contact area and the contact structure. The electrically conductive contact structure can be an electrically conductive grid. The grid can have at least one linear interruption. The at least one linear interruption divides the electrically conductive grid into separate grid regions, wherein the first contact area and the second contact area of ​​each semiconductor chip are connected to different grid regions. The grid regions have, in particular, different polarities. According to at least one embodiment or configuration of the semiconductor component or semiconductor part, only one semiconductor chip is located on the connecting layer(s).Furthermore, the semiconductor component can have precisely one semiconductor chip. The method described below is suitable for producing a semiconductor component or semiconductor part as described above. Features described in connection with the semiconductor component or semiconductor part can therefore also be used for the method, and vice versa. According to at least one embodiment of a method for producing a semiconductor component or semiconductor part of the type mentioned above, this comprises the following steps: - providing a connection starting layer on a first carrier layer, - structuring the connection starting layer to create a plurality of connection layers, - applying a second carrier layer to a side of the structured connection starting layer facing away from the first carrier layer, 2023PF00133 1.August 2024 P2023,0644 WO N - 14 - - Detaching the first carrier layer from the structured connecting starting layer, wherein the connecting layers remain on the second carrier layer, - Providing a carrier structure, - Applying at least one connecting layer to the carrier structure, wherein the at least one connecting layer adheres to the carrier structure by pressing it, - Detaching the second carrier layer from the at least one connecting layer, - Applying a semiconductor chip to each connecting layer, wherein the semiconductor chip adheres to the connecting layer by pressing it. The connecting starting layer corresponds, in particular with regard to its structural nature and its physical properties, to the connecting layer described in more detail in connection with the semiconductor component.The carrier structure can be provided for producing one or more carrier elements, each for a semiconductor component, or for producing one or more carriers, each for a semiconductor component, and can accordingly have the properties mentioned in connection with the carrier element or carrier. The first carrier layer can contain a plastic material, for example PET. The second carrier layer can also contain a plastic material such as PET. Furthermore, the second carrier layer can have regions of higher adhesion, on which the connecting layers are arranged, and regions of lower adhesion, on which residues of the connecting starting layer are arranged. For example, the regions of higher adhesion can contain PET 2023PF00133 August 1, 2024 P2023,0644 WO N - 15 -, while silicone, fluoropolymer, SiO2, or air, for example, can be considered for the regions of lower adhesion.When the first carrier layer is detached from the structured interconnect layer, the areas of lower adhesion support the retention of the interconnect layer residues on the first carrier layer. Furthermore, the areas of higher adhesion support the retention of the interconnect layers on the second carrier layer. The interconnect layer can be structured by cutting with a tool, such as a blade or a laser. These processes can be performed simply and cost-effectively. The semiconductor component is particularly suitable for display devices such as scoreboards, symbols, and displays, and can be used, for example, in the interior and exterior of vehicles as well as in consumer and industrial applications.1B shows a schematic cross-sectional view and a schematic plan view of a semiconductor component according to a first exemplary embodiment, FIG. 2A shows a schematic cross-sectional view and a schematic plan view of a semiconductor component according to a second exemplary embodiment, FIG. 3 shows a schematic plan view of a semiconductor component according to an exemplary embodiment, FIGS. 4A to 4H show various steps of a method according to a first exemplary embodiment, and FIGS. 4B1 and 4D1 show intermediate steps of the method according to a first variant, and FIGS. 4B2, 4D2, 4B3 and 4D3 show intermediate steps of the method according to a second variant, FIGS. 5A to 5D show various steps of a method according to a second exemplary embodiment, and FIGS. 6A to 6C show a method for checking and reversing an arrangement of a semiconductor chip on a carrier structure.In the exemplary embodiments and figures, identical, similar, or similarly acting elements can each be provided with the same reference numerals. The illustrated elements and their relative sizes to one another are not necessarily to scale; rather, individual elements may be exaggerated for clarity and / or clarity. Figure 1A shows a cross-section of a semiconductor component 1 according to a first exemplary embodiment, taken along the line AA shown in Figure 1B. The semiconductor component 1 comprises a semiconductor chip 2, for example an optoelectronic semiconductor chip, which may be a radiation-emitting semiconductor chip. The radiation-emitting semiconductor chip may be provided to emit radiation with a peak wavelength 2023PF00133 August 1, 2024 P2023,0644 WO N - 17 - in the visible to infrared spectral range.The radiation can exit the semiconductor component 1 at a top side 1A of the semiconductor component 1 or at a top side 2A of the semiconductor chip 2. The semiconductor chip 2 can have a shape that widens towards the top side 2A. It is furthermore possible for the optoelectronic semiconductor chip to be a radiation-detecting semiconductor chip that, for example, detects radiation with a peak wavelength in the visible to infrared spectral range. The semiconductor chip 2 has a semiconductor layer sequence 23 that comprises a first semiconductor region 24 of a first conductivity, for example a p-conductivity, and a second semiconductor region 26 of a second conductivity, for example an n-conductivity. However, it is also possible for the reverse to occur, with the first semiconductor region 24 having an n-conductivity and the second semiconductor region 26 having a p-conductivity.Furthermore, the semiconductor layer sequence 23 comprises an active zone 25, which is suitable, for example, for generating radiation with a peak wavelength in the visible to infrared spectral range. As already mentioned, materials based on arsenide, phosphide, or nitride compound semiconductors are suitable for the semiconductor layer sequence 23. Furthermore, the semiconductor chip 2 has a first contact area 21 and a second contact area 22 on a bottom side 2B opposite the top side 1A, 2A, wherein, for example, the first contact area 21 is provided for electrically contacting the first semiconductor region 24 and the second contact area 22 is provided for electrically contacting the second semiconductor region 26.The two contact surfaces 21, 22 can be located essentially in the same horizontal plane, which is arranged parallel to a plane spanned by a first lateral direction L1 and a second lateral direction L2 running transversely, in particular perpendicularly, to the first lateral direction L1. The semiconductor chip 2 thus has a horizontal chip design. The two contact surfaces 21, 22 are separated from one another by a gap 27, which has, for example, a width or lateral extent b2 of 10 - 30 µm, wherein deviations within the scope of usual manufacturing tolerances are possible. The lateral extent b2 can be determined along the first lateral direction L1. The semiconductor chip 2 can be a micro-LED and can be characterized by particularly small dimensions.For example, the semiconductor chip 2 can have a width or lateral extent b1 of 80 µm along the first lateral direction L1 and a depth or lateral extent t1 of 40 µm along the second lateral direction L2, and a thickness or vertical extent d of 1.5 µm to 10 µm along a vertical direction V, wherein deviations within the scope of usual manufacturing tolerances are possible in each case. The vertical direction V runs transversely, in particular perpendicularly, to the first and second lateral directions L1, L2. Furthermore, the semiconductor component 1 comprises a carrier element 4 on which the semiconductor chip 2 is arranged, wherein the underside 2B of the semiconductor chip 2 faces the carrier element 4. The carrier element 4 comprises a 2023PF00133 1.August 2024 P2023,0644 WO N - 19 - Base element 41 and a first connection area 42 and a second connection area 43, wherein the first connection area 42 and the second connection area 43 are arranged on a side of the base element 41 facing the semiconductor chip 2. The base element 41 can be formed from a thermoplastic material such as PET (polyethylene terephthalate) and can be in particular radiation-permeable, preferably permeable to visible radiation. A connecting layer 3 is arranged between the semiconductor chip 2 and the carrier element 4, which, among other things, electrically connects the semiconductor chip 2 to the carrier element 4.The connecting layer 3 overlaps horizontally, i.e., in lateral directions comprising the lateral directions L1, L2, with the first contact area 21 and the second contact area 22 and extends across the gap 27, so that the two contact areas 21, 22 are connected to one another by the connecting layer 3. Furthermore, the first contact area 21 is electrically connected to the first connection area 42 by the connecting layer 3. Furthermore, the second contact area 22 is electrically connected to the second connection area 43 by the connecting layer 3.The connecting layer 3 is an anisotropically electrically conductive layer which has a multiplicity of electrically conductive paths 32, wherein the electrically conductive paths 32 are aligned substantially vertically, that is to say within the scope of usual manufacturing tolerances, and extend from a side facing the carrier element 4 through an electrically insulating base layer 31 of the connecting layer 3 to a side facing away from the carrier element 4 or facing the semiconductor chip 2.As a result, the connecting layer 3 has a higher electrical conductivity in some regions in the vertical direction V, in which a current flow is intended to occur between the carrier element 4 and the semiconductor chip 2, than in the lateral directions, in particular in the first lateral direction L1, in which the current flow between the first and second contact areas 21, 22 is intended to be suppressed in order to prevent a short circuit. Structuring of the connecting layer 3 in the intermediate space 27, which would be necessary in the case of a metal connection in order to prevent a short circuit, can advantageously be omitted, so that the manufacturing effort is reduced. The paths 32 are in particular arranged regularly. For example, the paths 32 are arranged at lattice points of a two-dimensional, hexagonal lattice.For example, at least ten electrical paths 32 are located between the first contact surface 21 and the first connection surface 42, as well as between the second contact surface 22 and the second connection surface 43. The base layer 31 is formed from a base material containing, for example, silicone or acrylate. Furthermore, the electrically conductive paths 32 can be formed from particles 33, wherein each path 32 has a plurality of interconnected particles 33 arranged one above the other in the vertical direction V. Horizontally, the electrically conductive paths 32 can each be limited to one particle 33. As mentioned above, the particles 33 can be solid bodies made of an electrically conductive material or 2023PF00133 1.August 2024 P2023,0644 WO N - 21 - solid bodies with a coating of an electrically conductive material, wherein materials such as Ag, Ni, Cu, Au, Fe, Sn, Zn, Pd, Pt, Fe, Cr, Mo, CNT (carbon nanotubes), and TCO (transparent conductive oxide) are suitable for the electrically conductive material. If the solid bodies are provided with a coating, they can be formed from an electrically insulating material such as glass, polystyrene, or a thermoplastic or thermosetting plastic. Furthermore, the particles 33 can be spherical. However, other shapes such as cylinders or polyhedra are also conceivable. The particles 33 can each have a lateral extent b3 of at most 15 µm, in particular of 3 µm ± 1 µm, wherein the lateral extent b3 is understood to be the lateral dimension of the particle 33 which assumes a maximum.Lateral distances a between the paths 32 are, for example, two to three times larger than the lateral extent b3 of the particles 33. The connecting layer 3 projects laterally beyond the semiconductor chip 2. For example, the connecting layer 3 has a width or first lateral extent b4 of 120–150 µm and a depth or second lateral extent t4 of 80 µm, although deviations within the range of typical manufacturing tolerances are possible. The connecting layer 3 is sufficiently large to enable, for example, the secure positioning of the semiconductor chip 2 and sufficiently small to provide minimal blocking of radiation intended to be transmitted through the semiconductor component 1. Furthermore, with a sufficiently small connecting layer 3, material consumption and thus material costs can be kept low. 2023PF00133 1.August 2024 P2023,0644 WO N - 22 - The semiconductor chip 2 and the carrier element 4 can be reversibly connected to one another by means of the connecting layer 3, so that it is possible to detach the semiconductor chip 2 from the carrier element 4 without causing damage. This allows the connection to be undone when the not yet completed semiconductor component is checked for functionality if the functionality is not met (cf. Figures 6A to 6C). The connecting layer 3 can be pressure-sensitive, so that even low pressures, approximately the size of a finger pressure, are sufficient to mold the connecting layer 3 onto the carrier element 4 and the semiconductor chip 2 and to connect them (cf. Figures 4E and 4H). For example, the base material of the base layer 31 can have a modulus of elasticity between 1 and 1000 MPa, in particular between 1 and 100 MPa.Furthermore, an adhesive bond is formed, in particular, by means of the connecting layer 3. While, for example, a thermo-compression process associated with higher temperatures is used to produce conventional adhesive bonds, the adhesive bond in the present case can be produced in a lamination process (cf. Figures 4E and 4H), in which no or only insignificant deformation of the carrier element 4 occurs. For example, an adhesive material that has, for example, an adhesive force of between 0.5 and 10 N / 20 mm or between 1 and 3 N / 20 mm (tested according to EN ISO 298622019) at room temperature can be used as the base material of the base layer 31. 2023PF00133 August 1, 2024 P2023,0644 WO N - 23 - Due to the anisotropically electrically conductive connecting layer 3, the semiconductor component 1 is characterized, for example, by high reliability, high transmission, and low material costs.Furthermore, the semiconductor component 1 can have all the features and advantages mentioned in connection with the further exemplary embodiments. Figure 2A shows a cross-section of a semiconductor component 1 according to a second exemplary embodiment, taken along the line AA shown in Figure 2B. While the connecting layer 3 according to the first exemplary embodiment is designed in multiple layers, so that each electrically conductive path 32 has a plurality of particles 33 arranged one above the other, the connecting layer 3 according to the second exemplary embodiment is designed in a single layer, so that no further particles are arranged on a particle 33. The semiconductor component 1 can therefore be designed to be particularly thin. Furthermore, the semiconductor component 1 can have all the features and advantages mentioned in connection with the first exemplary embodiment and in connection with the further exemplary embodiments.Figure 3 shows a schematic plan view of a semiconductor component 10 according to one exemplary embodiment. The semiconductor component 10 comprises a plurality of semiconductor chips 2 in the manner of the semiconductor chip 2 described in connection with the first exemplary embodiment 2023PF00133 August 1, 2024 P2023,0644 WO N - 24 -. This means, among other things, that the semiconductor chips 2 have a horizontal chip design and each have a first contact area 21 and a second contact area 22 on a bottom side 2B, wherein the first contact area 21 and the second contact area 22 are separated from one another by a gap 27 (cf. Figures 1A and 1B). Furthermore, the semiconductor component 10 comprises a carrier 40 on which the semiconductor chips 2 are arranged, wherein the bottom side 2B in each case faces the carrier 40 (analogous to Figure 1A).The carrier 40 comprises an electrically insulating base body 44 and an electrically conductive contact structure 45, which is arranged on a side of the carrier 40 or base body 44 facing the semiconductor chips 2. The base body 44, like the base element 41, can be formed from a thermoplastic material such as PET (polyethylene terephthalate) and can be particularly radiation-permeable, preferably transparent to visible radiation. This makes it possible for the semiconductor component 10, which is, for example, a display device, to display information or images when switched on and to be transparent when switched off. The contact structure 45 is, for example, an electrically conductive grid. Advantageously, the grid 45 also enables the transmission of radiation. 2023PF00133 1.August 2024 P2023,0644 WO N - 25 - The grid 45 has a plurality of first grid lines 46 running parallel to one another and a plurality of second grid lines 47 running parallel to one another, wherein the plurality of first grid lines 46 and the plurality of second grid lines 47 intersect, for example, at a right angle. The grid lines 46, 47 can each be a few micrometers wide. Furthermore, the contact structure 45 has a plurality of linear interruptions 48, which divide the contact structure 45 into separate grid regions 49. The interruptions 48 can run transversely to the first and second grid lines 46, 47. The first contact area 21 and the second contact area 22 of each semiconductor chip 2 are connected to different grid regions 49 having different polarities. The semiconductor chips 2 are regularly arranged on the carrier 40.However, it is also possible for the semiconductor chips 2 to be arranged irregularly. Furthermore, the semiconductor component 10 comprises a plurality of connecting layers 3, each of which is arranged between the carrier 40 and exactly one semiconductor chip 2 and, among other things, electrically connects the semiconductor chip 2 to the carrier 40. The connecting layers 3 are formed in the manner of the connecting layer 3 described in connection with the first exemplary embodiment. Thus, the connecting layers 3 are each anisotropically electrically conductive and each overlap horizontally with the first contact area 21 and the second contact area 22 of the semiconductor chip 2 to which they are connected, and extend across the respective gap 27 (analogous to Fig. 1A). 2023PF00133 1.August 2024 P2023,0644 WO N - 26 - The semiconductor component 10, which is, for example, a display device, is characterized, among other things, by a high resolution, in particular when micro-LEDs are used as semiconductor chips. Furthermore, the semiconductor component 10 can have all the features and advantages mentioned in connection with the further exemplary embodiments. In connection with Figures 4A to 4H, a first exemplary embodiment of a method is described which is suitable for producing a semiconductor component 1 or semiconductor component 10 as described in connection with Figures 1 to 3. The method comprises a step of providing a connection output layer 30 on a first carrier layer 51 (cf. Figure 4A), wherein the connection output layer 30 is detachably arranged on the first carrier layer 51. The first carrier layer 51 can contain a plastic material, for example PET.The connection starting layer 30 corresponds, in particular with regard to its structural nature and its physical properties, to the connection layer 3 explained in more detail in connection with the first exemplary embodiment. To produce the connection starting layer 30, an electrically insulating base material with dispersed particles 33 can be provided, wherein the particles 33 are arranged, for example, by an alternating electric field to form electrically conductive paths 32. 2023PF00133 August 1, 2024 P2023,0644 WO N - 27 - Furthermore, the method comprises a step of structuring the connection starting layer 30 so that a plurality of connection layers 3 are created (cf. Figs. 4B, 4B1, 4B2). This step can include a cutting process carried out by means of a tool 53. The tool 53 can be a blade.The blade can be used to create intersecting cutting lines 54 in the connecting starting layer 30, which run along an edge of a connecting layer 3 to be created (see arrow in Fig. 4B1). Alternatively, the tool 53 can be a laser that cuts into the connecting starting layer 30 along an edge of a connecting layer 3 to be created (see arrow in Fig. 4B2). Furthermore, the method comprises a step of applying a second carrier layer 52 to a side of the structured connecting starting layer 30 facing away from the first carrier layer 51 (see arrow in Fig. 4C). The second carrier layer 52 can contain a plastic material such as PET. The method also comprises a step of detaching or delaminating (see Fig.4D, 4D1, 4D2) of the first carrier layer 51 from the structured connection starting layer 30, wherein residues 34 of the structured connection starting layer 30 remain on the first carrier layer 51 (cf. Fig. 4D1, bottom and Fig. 4D2, bottom), while the connection layers 3 remain adhered to the second carrier layer 52 (cf. Fig. 4D1, top and Fig. 4D2, top). From the residues 34 of the structured connection starting layer 30, further connection layers 3 can be produced in the manner described in connection with Figs. 4A to 4D (cf. Figs. 4B3, 4D3) in order to achieve the highest possible yield and save material costs.Furthermore, the method comprises a step of providing a carrier structure 50, which is intended for producing one or more carrier elements 4 for a respective semiconductor component 1, for example, according to the first or second exemplary embodiment and / or for producing one or more carriers 40 for a respective semiconductor component 10, for example, according to the exemplary embodiment (see Fig. 4E). Accordingly, the carrier structure 50 can have a carrier body 55, from which at least one base element 41 and / or a base body 44 can be produced. The carrier body 55 can accordingly have the above-mentioned properties of the base element 41 or base body 44 (see Figs. 1A, 1B and 3).Furthermore, the carrier structure 50 can comprise a first connection structure 56 for producing at least one first connection surface 42 and / or a first part of a contact structure 45 and a second connection structure 57 for producing at least one second connection surface 43 and / or a part of a second contact structure 45. The connection structures 56, 57 can accordingly have the above-mentioned properties of the connection surfaces 42, 43 and contact structure 45, respectively (cf. Figs. 1A, 1B and 3). Furthermore, the method comprises a step of applying or laminating at least one connecting layer 3 to the carrier structure 50, wherein the at least one connecting layer 3 adheres to the carrier structure 50 by pressing it (cf. arrow in Fig. 4E). Even low pressures, approximately the size of a 2023PF00133 1, are sufficient for this purpose.August 2024 P2023,0644 WO N - 29 - finger pressure to mold the connecting layer 3 onto the carrier structure 50 and connect it to the latter. The at least one connecting layer 3 is arranged such that it connects the first and second connection structures 56, 57 to one another. Furthermore, the method comprises a step of detaching or delaminating the second carrier layer 52 (cf. arrow in Fig. 4F), wherein the at least one connecting layer 3 remains adhered to the carrier structure 50 (cf. Fig. 4G). Finally, the method comprises a step of applying a semiconductor chip 2 to a respective connecting layer 3, wherein the semiconductor chip 2 adheres to the connecting layer 3 by pressing it (cf. Fig. 4H). Even low pressures, approximately the dimension of a finger pressure, are sufficient to mold the connecting layer 3 onto the semiconductor chip 2 and connect it to it.A second embodiment of a method is described in conjunction with Figures 5A to 5D. The method can begin with the steps described in conjunction with Figures 4A and 4B (cf. Figures 5A and 5B). The steps of applying a second carrier layer 52 (Figure 5C) and detaching the first carrier layer 51 (Figure 5D) can then be carried out as described in conjunction with Figures 4C and 4D. However, the second carrier layer 52 comprises regions 52A of higher adhesion, on which the bonding layers 3 are arranged, and regions 52B of lower adhesion, on which the residues 34 of the bonding starting layer 30 are arranged. The areas 52A with higher adhesion can contain PET, while the areas 52B with lower adhesion can contain, for example, silicone, fluoropolymer, SiO2 or air.When the first carrier layer 51 is detached from the structured connecting starting layer 30, the regions 52B of lower adhesion support the residues 34 of the connecting starting layer 30 remaining on the first carrier layer 51. Furthermore, the regions 52A of higher adhesion support the connecting layers 3 remaining on the second carrier layer 52. Subsequently, the steps described in connection with Figures 4E to 4H can be carried out in an analogous manner. Using one of the methods described in connection with Figures 4 and 5, a method for testing a semiconductor component 1 or semiconductor device 10 to be separated from the composite can be carried out in the composite (cf. Figures 6A to 6C).Should the inspection reveal insufficient functionality of a semiconductor chip 2 and / or a connecting layer 3, the insufficient semiconductor chip 2 (cf. Fig. 6B) and, if applicable, the insufficient connecting layer 3 can be detached (cf. Fig. 6C) and replaced using a lifting instrument 58 having a high adhesive force. The simple possibility of reversing or rearranging the process can improve quality and yield. The invention is not limited by the description based on the exemplary embodiments. Rather, the invention encompasses any new feature and any combination of features, which in particular includes any combination of features in the patent claims, even if this feature or combination itself is not explicitly specified in the patent claims or exemplary embodiments.This patent application claims priority from German patent application 102023123960.0, the disclosure of which is hereby incorporated by reference.

[0002] 2023PF00133 August 1, 2024 P2023,0644 WO N - 32 - List of reference symbols 1 Semiconductor component 1A Top side 2 Semiconductor chip 2A Top side 2B Bottom side 3 Connection layer 4 Carrier element 10 Semiconductor component 21 First contact area 22 Second contact area 23 Semiconductor layer sequence 24 First semiconductor region 25 Active zone 26 Second semiconductor region 27 Intermediate space 30 Connection starting layer 31 Base layer 32 Electrically conductive path 33 Particles 34 Residues 40 Carrier 41 Base element 42 First connection area 43 Second connection area 44 Base body 45 Contact structure, grid 46 First grid line 2023PF00133 1.August 2024 P2023,0644 WO N - 33 - 47 second grid line 48 interruption 49 grid area 50 carrier structure 51 first carrier layer 52 second carrier layer 52A area of ​​higher adhesion 52B area of ​​lower adhesion 53 tool, blade, laser 54 cutting line 55 carrier body 56 first connecting structure 57 second connecting structure 58 lifting instrument a distance b1, b2, b3, b4 width, lateral extent d thickness, vertical extent t1, t4 depth, lateral extent L1 first lateral direction L2 second lateral direction V vertical direction.

Claims

2023PF00133 August 1, 2024 P2023,0644 WO N - 34 - Claims 1. Semiconductor component (1) comprising ^ a semiconductor chip (2) which has a first contact area (21) and a second contact area (22) on a bottom side (2B), wherein the first contact area (21) and the second contact area (22) are separated from one another by an intermediate space (27), ^ a carrier element (4) on which the semiconductor chip (2) is arranged, wherein the bottom side (2B) faces the carrier element (4), and ^ a connecting layer (3) which ^ is arranged between the carrier element (4) and the semiconductor chip (2) and connects the semiconductor chip (2) to the carrier element (4), ^ is anisotropically electrically conductive, ^ horizontally overlaps the first contact area (21) and the second contact area (22) and extends across the intermediate space (27), and ^ a plurality of electrically conductive paths (32),wherein: ^ the carrier element (4) has a base element (41) and a first connection surface (42) and a second connection surface (43), and the first connection surface (42) and the second connection surface (43) are arranged on a side of the base element (41) facing the semiconductor chip (2), and the first contact surface (21) is electrically conductively connected to the first connection surface (42) by the connecting layer (3), and the second contact surface (22) is electrically conductively connected to the second connection surface (43) by the connecting layer (3), and, 2023PF00133 August 1, 2024 P2023,0644 WO N - 35 - ^ at least ten electrical paths (32) are located between the first contact area (21) and the first connection area (42) and between the second contact area (22) and the second connection area (43).

2. Semiconductor component (1) according to the preceding claim, wherein the semiconductor chip (2) and the carrier element (4) are reversibly connected to one another by means of the connecting layer (3).

3. Semiconductor component (1) according to one of the preceding claims, wherein an adhesive connection is formed by means of the connecting layer (3). 4.Semiconductor component (1) according to one of the preceding claims, wherein the connecting layer (3) comprises an electrically insulating base layer (31), wherein the electrically conductive paths (32) run through the base layer (31) from a side of the connecting layer (3) facing the carrier element (4) to a side of the connecting layer (3) facing away from the carrier element (4).

5. Semiconductor component (1) according to the preceding claim, wherein a base material of the base layer (31) contains at least one of the following materials: silicone, acrylate.

6. Semiconductor component (1) according to one of the preceding claims, wherein the electrically conductive paths (32) have particles (33) which are solid bodies made of an electrically conductive. 2023PF00133 August 1, 2024 P2023,0644 WO N - 36 - material or solid body with a coating of an electrically conductive material.

7. Semiconductor component (1) according to the preceding claim, wherein one of the following materials is suitable for the electrically conductive material: Ag, Ni, Cu, Au, Fe, Sn, Zn, Pd, Pt, Fe, Cr, Mo, CNT (carbon nanotubes), TCO (transparent conductive oxide).

8. Semiconductor component (1) according to one of the preceding claims, wherein the semiconductor chip (2) is laterally projected over by the connecting layer (3).

9. Semiconductor component (1) according to one of the preceding claims, wherein the semiconductor chip (2) is a micro-LED or a micro-IC.

10. Semiconductor component (1) according to one of the preceding claims, wherein the base element (41) is radiation-transparent. 11.Semiconductor component (10) comprising ^ a plurality of semiconductor chips (2), each having a first contact surface (21) and a second contact surface (22) on an underside (2B), wherein the first contact surface (21) and the second contact surface (22) are separated from one another by an intermediate space (27), ^ a carrier (40) on which the semiconductor chips (2) are arranged, wherein the underside (2B) in each case faces the carrier (40), and ^ a plurality of connecting layers (3), each. 2023PF00133 August 1, 2024 P2023,0644 WO N - 37 - ^ are arranged between the carrier (40) and a semiconductor chip (2) and connect the semiconductor chip (2) to the carrier (40), ^ are anisotropically electrically conductive, ^ horizontally overlap with the first contact surface (21) and the second contact surface (22) and extend across the intermediate space (27), and ^ have a plurality of electrically conductive paths (32), wherein: ^ the carrier (40) has a base body (44) and an electrically conductive contact structure (45), and the contact structure (45) is arranged on a side of the base body (44) facing the semiconductor chips (2), and the first contact surface (21) and the second contact surface (22) are each electrically conductively connected to the electrically conductive contact structure (45) by the connecting layer (3),and ^ there are at least ten electrical paths (32) between the first contact area (21) and the contact structure (45) and between the second contact area (22) and the contact structure (45).

12. Semiconductor component (10) according to the preceding claim, wherein the contact structure (45) has an electrically conductive grid (45) with at least one linear interruption (48), wherein the at least one linear interruption (48) divides the electrically conductive grid (45) into separate grid regions (49), and wherein the first contact area (21) and the second contact area (22) of each semiconductor chip (2) are connected to different grid regions (49).

13. Semiconductor component (1) or semiconductor component (10) according to one of the preceding claims, wherein on the, 2023PF00133 August 1, 2024 P2023,0644 WO N - 38 - or the connecting layer(s) (3) each have only one semiconductor chip (2).

14. A method for producing a semiconductor component (1) or semiconductor device (10) according to one of the preceding claims, comprising: - providing a connection starting layer (30) on a first carrier layer (51), - structuring the connection starting layer (30) so that a plurality of connection layers (3) are formed, - applying a second carrier layer (52) on a side of the structured connection starting layer (30) facing away from the first carrier layer (51), - detaching the first carrier layer (51) from the structured connection starting layer (30), wherein the connection layers (3) remain on the second carrier layer (52), - providing a carrier structure (50), - applying at least one connection layer (3) to the carrier structure (50),wherein the at least one connecting layer (3) adheres to the carrier structure (50) by pressing it on, - detaching the second carrier layer (52) from the at least one connecting layer (3), - applying a semiconductor chip (2) to each connecting layer (3), wherein the semiconductor chip (2 adheres to the connecting layer (3) by pressing it on.

15. Method according to the preceding claim, wherein the second carrier layer (52) has regions (52A) of higher adhesion, on which the connecting layers (3) are arranged, and regions (52B) of lower adhesion, on which residues, 2023PF00133 August 1, 2024 P2023,0644 WO N - 39 - (34) of the connection output layer (30).

16. The method according to one of the two preceding claims, wherein the structuring of the connection output layer (30) is carried out by cutting with a blade or a laser.

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